Interleaving method and device, de-interleaving method and device, equipment and storage medium
By using a pre-stored interleaving table for Polar code interleaving and deinterleaving, the problem of high computational complexity in existing technologies is solved, enabling fast interleaving and deinterleaving, reducing system time consumption and alleviating memory burden.
Patent Information
- Application Number
- CN202510990667.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-17
- Publication Date
- 2025-10-31
AI Technical Summary
The existing Polar code interleaving/deinterleaving process has high computational complexity, involving a large number of arithmetic operations and logical judgments, resulting in low computational efficiency.
By pre-storing the interleaving pre-store table, the information bit sequence is byte-expanded and loaded into the interleaver's register. The pre-store table is then used for full sequence interleaving and bit extraction, avoiding real-time calculation of the interleaving index.
It reduces computational complexity, decreases time consumption, optimizes memory resources, improves versatility, and enables fast interleaving and deinterleaving.
Smart Images
Figure CN120880465A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of wireless communication technology, and in particular to an interleaving method, a deinterleaving method, an apparatus, a device, and a storage medium. Background Technology
[0002] In communication systems, Polar codes are currently the only channel coding scheme rigorously proven to reach the Shannon limit. They utilize channel polarization theory to divide the channel into noise-free and noisy channels, with information bits transmitted only in the noise-free channel to achieve optimal error correction performance. Information bit interleaving is the core element of Polar codes in enhancing their resistance to burst errors.
[0003] In existing schemes, the interleaving / deinterleaving of Polar codes requires real-time calculation of the interleaving index based on parameters such as code length and information bit position.
[0004] This process involves a large number of arithmetic operations and logical judgments, resulting in high computational complexity. Summary of the Invention
[0005] To address one of the aforementioned technical deficiencies, this application provides an interleaving method, a deinterleaving method, an apparatus, a device, and a storage medium.
[0006] A first aspect of this application provides an interleaving method, the method comprising:
[0007] The information bit sequence to be interleaved is extended by bytes to obtain the information byte sequence;
[0008] The sequence of information bytes is loaded into the three registers of the interleaver, and full-sequence interleaving is performed according to the pre-stored interleaving pre-table to obtain the full-sequence interleaving result;
[0009] Bit extraction is performed on the full sequence interleaving result to obtain the final interleaving result;
[0010] Among them, the interleaving pre-store table includes 6;
[0011] Among them, the first and second interleaving pre-store tables correspond to bytes 0-63, the third and fourth interleaving pre-store tables correspond to bytes 64-127, and the fifth and sixth interleaving pre-store tables correspond to bytes 128-163.
[0012] Optionally, the information bit sequence to be interleaved is byte-extended to obtain an information byte sequence, including:
[0013] Expand the bit sequence of information to be interleaved into a byte type;
[0014] Add a padding to the beginning of the information bit sequence to be interleaved. Subtract 1 from the number of bytes to obtain the information byte sequence;
[0015] in, K1 is the maximum decoding length, and K1 is the total number of bits in the information bit sequence to be interleaved.
[0016] Optionally, full sequence interleaving is performed based on a pre-stored interleaving pre-table to obtain the full sequence interleaving result, including:
[0017] The contents loaded in the first register and the second register are concatenated and interleaved according to the pre-stored interleaving pre-table to obtain the first intermediate interleaving result;
[0018] The first intermediate interleaving result and the content loaded in the third register are concatenated, and interleaving is performed according to the pre-stored interleaving pre-store table to obtain the full sequence interleaving result.
[0019] Optionally, bit extraction is performed on the full sequence interleaving result to obtain the final interleaving result, including:
[0020] Extract bytes that are not less than 0 from the full sequence interleaving result;
[0021] The lowest bit of the extracted bytes is used to form the final interleaving result.
[0022] A second aspect of this application provides a deinterleaving method, the method comprising:
[0023] The interleaving result to be deinterleaved is extended by bytes to obtain the interleaving result byte sequence; wherein, the interleaving result to be deinterleaved is obtained by the method described in the first aspect above;
[0024] The interleaving result byte sequence is loaded into the three registers of the interleaver, and full sequence interleaving is performed according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result;
[0025] The least significant bit of each byte in the full sequence deinterleaving result is used to form the final deinterleaving result;
[0026] If K2 < 128, then the deinterleaving pre-store table is the first deinterleaving pre-store table. If K2 ≥ 128, then there are 6 deinterleaving pre-store tables. The second and third deinterleaving pre-store tables correspond to bytes 0-63, the fourth and fifth deinterleaving pre-store tables correspond to bytes 64-127, and the sixth and seventh deinterleaving pre-store tables correspond to bytes 128-163.
[0027] K2 is the total number of bits in the interleaving result to be deinterleaved.
[0028] Optionally, full sequence interleaving is performed based on a pre-stored deinterleaving pre-table to obtain a full sequence deinterleaving result, including:
[0029] The contents loaded in the fourth and fifth registers are concatenated and interleaved according to the pre-stored deinterleaving pre-stored table to obtain the second intermediate interleaving result;
[0030] The second intermediate interleaving result and the content loaded in the sixth register are concatenated, and interleaving is performed according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result.
[0031] A third aspect of this application provides an interlacing device, the device comprising:
[0032] The first processing module is used to perform byte expansion on the information bit sequence to be interleaved to obtain an information byte sequence.
[0033] The second processing module is used to load the information byte sequence into the three registers of the interleaver, perform full sequence interleaving according to the pre-stored interleaving pre-store table, and obtain the full sequence interleaving result;
[0034] The third processing module is used to extract bits from the full sequence interleaving result to obtain the final interleaving result.
[0035] Among them, the interleaving pre-store table includes 6;
[0036] Among them, the first and second interleaving pre-store tables correspond to bytes 0-63, the third and fourth interleaving pre-store tables correspond to bytes 64-127, and the fifth and sixth interleaving pre-store tables correspond to bytes 128-163.
[0037] In a fourth aspect, this application provides a de-intertwining apparatus, the apparatus comprising:
[0038] The fourth processing module is used to perform byte expansion on the interleaving result to be deinterleaved, so as to obtain the interleaving result byte sequence; wherein, the interleaving result to be deinterleaved is obtained by the method described in the first aspect above;
[0039] The fifth processing module is used to load the interleaved result byte sequence into the three registers of the interleaver, perform full sequence interleaving according to the pre-stored deinterleaving pre-stored table, and obtain the full sequence deinterleaving result;
[0040] The sixth processing module is used to form the final deinterleaving result from the least significant bit of each byte in the full sequence deinterleaving result;
[0041] If K2 < 128, then the deinterleaving pre-store table is the first deinterleaving pre-store table. If K2 ≥ 128, then there are 6 deinterleaving pre-store tables. The second and third deinterleaving pre-store tables correspond to bytes 0-63, the fourth and fifth deinterleaving pre-store tables correspond to bytes 64-127, and the sixth and seventh deinterleaving pre-store tables correspond to bytes 128-163.
[0042] K2 is the total number of bits in the interleaving result to be deinterleaved.
[0043] A fifth aspect of this application provides an electronic device, comprising:
[0044] Memory;
[0045] Processor; and
[0046] Computer programs;
[0047] The computer program is stored in the memory and configured to be executed by the processor to implement the method as described in the first or second aspect above.
[0048] A sixth aspect of this application provides a computer-readable storage medium having a computer program stored thereon; the computer program is executed by a processor to implement the method as described in the first or second aspect above.
[0049] This application provides an interleaving method, deinterleaving method, apparatus, device, and storage medium. The method includes: byte-expanding an information bit sequence to be interleaved to obtain an information byte sequence; loading the information byte sequence into three registers of an interleaver; performing full-sequence interleaving according to a pre-stored interleaving pre-table to obtain a full-sequence interleaving result; and bit-sampling the full-sequence interleaving result to obtain a final interleaving result. The interleaving pre-table includes six tables: the first and second interleaving pre-tables correspond to bytes 0-63, the third and fourth interleaving pre-tables correspond to bytes 64-127, and the fifth and sixth interleaving pre-tables correspond to bytes 128-163. The interleaving method provided in this application loads the information byte sequence into the three registers of the interleaver and performs full-sequence interleaving according to the pre-stored interleaving pre-tables, thereby transforming real-time calculation of the interleaving index into table lookup index retrieval, eliminating real-time loop iteration and computational delays, and achieving fast interleaving. Attached Figure Description
[0050] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0051] Figure 1 A flowchart illustrating an interleaving method provided in an embodiment of this application;
[0052] Figure 2 This is a schematic diagram of a deinterleaving method provided in an embodiment of this application;
[0053] Figure 3This is a schematic diagram of the structure of an interlacing device provided in an embodiment of this application;
[0054] Figure 4 This is a schematic diagram of the structure of a de-interlacing device provided in an embodiment of this application;
[0055] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;
[0056] Figure 6 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application. Detailed Implementation
[0057] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.
[0058] In implementing this application, the inventors discovered that in existing solutions, Polar code interleaving / deinterleaving requires real-time calculation of the interleaving index based on parameters such as code length and information bit position. This process involves a large number of arithmetic operations and logical judgments, resulting in high computational complexity.
[0059] To address the aforementioned problems, this application provides an interleaving method, deinterleaving method, apparatus, device, and storage medium. The method includes: byte-expanding the information bit sequence to be interleaved to obtain an information byte sequence; loading the information byte sequence into three registers of an interleaver; performing full-sequence interleaving according to a pre-stored interleaving pre-table to obtain a full-sequence interleaving result; and bit extraction from the full-sequence interleaving result to obtain the final interleaving result. The interleaving pre-table includes six tables: the first and second interleaving pre-tables correspond to bytes 0-63, the third and fourth interleaving pre-tables correspond to bytes 64-127, and the fifth and sixth interleaving pre-tables correspond to bytes 128-163. The interleaving method provided in this application loads the information byte sequence into the three registers of the interleaver and performs full-sequence interleaving according to the pre-stored interleaving pre-tables, thereby transforming real-time calculation of the interleaving index into index lookup from a table, eliminating real-time loop iteration and computational delays, and achieving fast interleaving.
[0060] See Figure 1 This embodiment provides an interleaving method, which includes:
[0061] 101. Perform byte expansion on the information bit sequence to be interleaved to obtain the information byte sequence.
[0062] Step 101 is implemented as follows:
[0063] 101-1 expands the sequence of information bits to be interleaved into a byte type.
[0064] 101-2, Pad the beginning of the information bit sequence to be interleaved. Subtract 1 from each byte type to obtain the information byte sequence.
[0065] in, K1 is the maximum decoding length, and K1 is the total number of bits in the information bit sequence to be interleaved.
[0066] For example, in step 101, the information bit sequence to be interleaved is expanded into a byte type according to the total number of bits K1, and padding is added to the front of the bit sequence. A -1 corresponds to a byte of 0xff.
[0067] Step 101 can be used to perform bit extension padding -1, resulting in an information byte sequence of length 164 bytes.
[0068] 102. Load the information byte sequence into the three registers of the interleaver, perform full sequence interleaving according to the pre-stored interleaving pre-table, and obtain the full sequence interleaving result.
[0069] In step 102, the 164-byte information byte sequence obtained in step 101 is first loaded into the three registers of the interleaver, and then full sequence interleaving is performed according to the pre-stored interleaving pre-table to obtain the full sequence interleaving result.
[0070] 1. Implementation method for loading the information byte sequence into the three registers of the interleaver.
[0071] For example, the three registers are the first register (e.g., T0), the second register (e.g., T1), and the third register (e.g., T2).
[0072] The 164-byte information byte sequence is loaded into the three T0 to T2 registers of the interleaver, as shown in Table 1.
[0073] Table 1
[0074]
[0075]
[0076] 2. Interleaving Pre-store Table
[0077] The interleaving pre-store table consists of six tables. The first and second interleaving pre-store tables correspond to bytes 0-63, the third and fourth interleaving pre-store tables correspond to bytes 64-127, and the fifth and sixth interleaving pre-store tables correspond to bytes 128-163.
[0078] The interleaving prediction table is obtained based on the interleaving pattern table shown in Table 2.
[0079] Table 2
[0080]
[0081] Where m is the position index.
[0082] According to the 3GPP protocol, the principle of polar encoding information bit interleaving.
[0083] If the input sequence is The output sequence after interleaving is
[0084] c ′ k =c Π(k) k = 0, 1, ..., K1-1
[0085] The calculation process for the interlacing patternΠ(k) is as follows:
[0086]
[0087] in, From Table 2,
[0088] Therefore, based on Table 2 and the above interleaving process, we can obtain the first interleaving pre-store table corresponding to bytes 0-63 during the first interleaving (as shown in Table 3), the third interleaving pre-store table corresponding to bytes 64-127 during the first interleaving (as shown in Table 4), and the fifth interleaving pre-store table corresponding to bytes 128-163 during the first interleaving (as shown in Table 5).
[0089] Table 3
[0090]
[0091] Table 4
[0092]
[0093]
[0094] Table 5
[0095]
[0096] Since the interleaving distance of the interleaver is 128 bytes, the dark gray background in Tables 3, 4, and 5 exceeds the interleaving distance of the interleaver. Therefore, 64 is subtracted from the dark gray background values in Tables 3, 4, and 5. Based on Table 2, the second interleaving pre-store table corresponding to bytes 0-63 during the second interleaving is obtained (as shown in Table 6), the fourth interleaving pre-store table corresponding to bytes 64-127 during the second interleaving is obtained (as shown in Table 7), and the sixth interleaving pre-store table corresponding to bytes 128-163 during the second interleaving is obtained (as shown in Table 8).
[0097] Table 6
[0098]
[0099] Table 7
[0100]
[0101] Table 8
[0102]
[0103] After obtaining the first interleaving pre-stored table shown in Table 3, the second interleaving pre-stored table shown in Table 6, the third interleaving pre-stored table shown in Table 4, the fourth interleaving pre-stored table shown in Table 7, the fifth interleaving pre-stored table shown in Table 5, and the sixth interleaving pre-stored table shown in Table 8, the first interleaving pre-stored table, the second interleaving pre-stored table, the third interleaving pre-stored table, the fourth interleaving pre-stored table, the fifth interleaving pre-stored table, and the sixth interleaving pre-stored table will be stored so that they can be looked up during subsequent interleaving.
[0104] 3. The process of performing full sequence interleaving based on the pre-stored interleaving pre-table to obtain the full sequence interleaving result is as follows:
[0105] (1) The implementation method of splicing the contents loaded in the first register and the second register, interleaving according to the pre-stored interleaving pre-stored table, and obtaining the first intermediate interleaving result.
[0106] For example, the contents loaded in the first register (e.g., T0) and the contents loaded in the second register (e.g., T1) are concatenated. The contents loaded in the first register (e.g., T0) are used as the lower 64 bits of the concatenated contents, and the contents loaded in the second register (e.g., T1) are used as the higher 64 bits of the concatenated contents. By looking up the first interleaving pre-store table shown in Table 3, the third interleaving pre-store table shown in Table 4, and the fifth interleaving pre-store table shown in Table 5, the first intermediate interleaving result T0` (i.e. the first interleaving result) is obtained.
[0107] (2) The first intermediate interleaving result and the content loaded in the third register are concatenated and interleaved according to the pre-stored interleaving pre-stored table to obtain the full sequence interleaving result.
[0108] For example, the first intermediate interleaving result (T0`) and the content loaded in the third register (such as T2) are concatenated. The first intermediate interleaving result (T0`) is used as the lower 64 bits of the concatenated result, and the content loaded in the third register (such as T2) is used as the higher 64 bits of the concatenated result. The full sequence interleaving result (i.e. the second interleaving result) is obtained by looking up the second interleaving pre-store table shown in Table 6, the fourth interleaving pre-store table shown in Table 7, and the sixth interleaving pre-store table shown in Table 8.
[0109] In other words, during interleaving, T1 and T0 are concatenated and interleaved once to obtain T0', and then T2 is concatenated with the result of the first interleaving T0' for a second interleaving, resulting in a 64-byte interleaved result. Each 64-byte output result requires two interleavings.
[0110] 103. Bit extraction is performed on the full sequence interleaving result to obtain the final interleaving result.
[0111] In step 103, bytes not less than 0 are extracted from the full sequence interleaving result, and the least significant bit of the extracted bytes is used to form the final interleaving result.
[0112] In other words, in step 103, the byte filled with -1 needs to be removed, and then the lowest bit of each byte is extracted to obtain the interleaved output.
[0113] For example, each time a byte is loaded, it is compared with 0. If the data is greater than or equal to 0, the byte is extracted and output to the storage space; if the data is less than 0, the data is offset by one byte and the loading continues. The above steps are repeated until the processing is complete. The least significant bit of each byte in the storage space is used to form the final interleaved result.
[0114] The interleaving method provided in this embodiment utilizes a pre-generated interleaving pre-stored table to pre-calculate and store the interleaving indexes for different scenarios offline as a static table. At runtime, the indexes are retrieved directly by looking up the table, avoiding real-time calculations. This solves the following problems:
[0115] 1) Reduce computational complexity: Transform dynamic calculations into simple table lookup operations, requiring only address mapping logic in hardware implementation.
[0116] 2) Reduce time consumption: Eliminate the loop iteration and computation delay of real-time algorithms to achieve fast interleaving.
[0117] 3) Optimize memory resources: Static tables can be stored in read-only memory (ROM), eliminating the need for dynamic memory allocation and reducing runtime memory usage.
[0118] 4) Improve versatility: Adapt to multiple scenarios through a unified table lookup interface, reducing code and hardware logic redundancy.
[0119] The interleaving method provided in this embodiment accelerates the interleaving process in the Polar encoding and decoding process based on the interleaving pre-store table, thereby reducing system time consumption and alleviating memory burden.
[0120] This embodiment provides an interleaving method. The method involves byte-expanding the information bit sequence to be interleaved to obtain an information byte sequence; loading the information byte sequence into three registers of the interleaver; performing full-sequence interleaving according to a pre-stored interleaving pre-table to obtain a full-sequence interleaving result; and then extracting bits from the full-sequence interleaving result to obtain the final interleaving result. The interleaving pre-table includes six tables: the first and second tables correspond to bytes 0-63, the third and fourth tables correspond to bytes 64-127, and the fifth and sixth tables correspond to bytes 128-163. This interleaving method loads the information byte sequence into the three registers of the interleaver and performs full-sequence interleaving according to the pre-stored interleaving pre-table, thereby transforming real-time calculation of the interleaving index into index lookup, eliminating real-time loop iteration and computational delays, and achieving fast interleaving.
[0121] See Figure 2 This embodiment provides a de-intertwining method, which includes:
[0122] 201. Perform byte expansion on the interleaving result to be deinterleaved to obtain the byte sequence of the interleaving result.
[0123] Among them, the interlacing result of the uninterlaced part is obtained through Figure 1 The interleaving method shown in the embodiment is obtained.
[0124] For example, the interleaving result to be deinterleaved can be expanded to a byte type to obtain the interleaved result byte sequence.
[0125] 202. Load the interleaved result byte sequence into the three registers of the interleaver, and perform full sequence interleaving according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result.
[0126] In step 202, the K2-length interleaving result byte sequence obtained in step 201 is first loaded into the three registers of the interleaver, and then the full sequence interleaving is performed according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result.
[0127] 1. Implementation method for loading the interleaved byte sequence into the three registers of the interleaver.
[0128] For example, the three registers are the fourth register (e.g., T3), the fifth register (e.g., T4), and the sixth register (e.g., T5).
[0129] The K2-length interleaving result byte sequence is loaded into the three T3 to T5 registers of the interleaver, as shown in Table 9.
[0130] Table 9
[0131]
[0132]
[0133] 2. Deinterleaving pre-stored table
[0134] If K2 < 128, then there is one deinterleaving pre-store table, such as the first deinterleaving pre-store table.
[0135] If K2 ≥ 128, then there are 6 deinterleaving pre-tables. The second and third deinterleaving pre-tables correspond to bytes 0-63, the fourth and fifth deinterleaving pre-tables correspond to bytes 64-127, and the sixth and seventh deinterleaving pre-tables correspond to bytes 128-163.
[0136] K2 is the total number of bits in the interleaving result to be deinterleaved, and also the length of the byte sequence of the interleaving result.
[0137] Deinterleaving is the reverse process of interleaving, so Table 2 needs to be rearranged in reverse order to obtain Table 10, the deinterleaving pattern.
[0138] The deinterleaving prediction table is obtained based on the deinterleaving pattern table shown in Table 10.
[0139] Table 10
[0140]
[0141] Where m is the position index. This represents the maximum decoding length.
[0142] According to the 3GPP protocol, the principle of polar encoding information bit interleaving.
[0143] If the input sequence is The output sequence after interleaving is
[0144] c ′ k =c ∏(k) k = 0, 1, ..., K1-1
[0145] The calculation process for the interlacing patternΠ(k) is as follows:
[0146]
[0147] in, From Table 10,
[0148] Therefore, based on Table 10 and the above interleaving process, the K2Byte length of the interleaving result byte sequence is interleaved to obtain the deinterleaving pre-store table.
[0149] The deinterleaving pre-store table is divided into two types based on whether the value of K2 is greater than the interleaving distance.
[0150] If K2 < 128, then there is one deinterleaving pre-stored table, such as the first deinterleaving pre-stored table. The K2 values with the largest m values extracted from table 10 are called temporary tables, and then their corresponding m values are subtracted... Obtain the required deinterleaving table (i.e., the first deinterleaving pre-stored table).
[0151] Taking K2=39 as an example, first extract the 39 largest values of m from Table 10 to obtain a temporary table, that is... The values are shown in the temporary table in Table 11.
[0152] Table 11
[0153]
[0154]
[0155] Subtract the values in Table 11 The required deinterleaving table (i.e., the first deinterleaving pre-stored table) is obtained, as shown in Table 12.
[0156] Table 12
[0157]
[0158] After obtaining the first uninterruption pre-stored table shown in Table 12, the first uninterruption pre-stored table will be stored so that it can be looked up during subsequent interruption.
[0159] If K2≥128, then based on Table 10 and the above interleaving process, if K2≥163, we can obtain the second deinterleaving pre-stored table corresponding to bytes 0-63 during the first deinterleaving (as shown in Table 13), the fourth deinterleaving pre-stored table corresponding to bytes 64-127 during the first deinterleaving (as shown in Table 14), and the sixth interleaving pre-stored table corresponding to bytes 128-163 during the first deinterleaving (as shown in Table 15).
[0160] Table 13
[0161]
[0162] Table 14
[0163]
[0164]
[0165] Table 15
[0166]
[0167] Since the interleaving distance of the interleaver is 128 bytes, the dark gray portions in Tables 13, 14, and 15 exceed the interleaving distance of the interleaver. Therefore, 64 is subtracted from the dark gray portions in Tables 13, 14, and 15. Based on Table 10, the third deinterleaving pre-stored table corresponding to bytes 0-63 during the second deinterleaving (as shown in Table 16), the fifth deinterleaving pre-stored table corresponding to bytes 64-127 during the second deinterleaving (as shown in Table 17), and the seventh deinterleaving pre-stored table corresponding to bytes 128-163 during the second deinterleaving (as shown in Table 18) are obtained.
[0168] Table 16
[0169]
[0170] Table 17
[0171]
[0172]
[0173] Table 18
[0174]
[0175] After obtaining the first deinterleaving pre-stored table shown in Table 12, or the second deinterleaving pre-stored table shown in Table 13, the third deinterleaving pre-stored table shown in Table 16, the fourth deinterleaving pre-stored table shown in Table 14, the fifth deinterleaving pre-stored table shown in Table 17, the sixth deinterleaving pre-stored table shown in Table 15, and the seventh deinterleaving pre-stored table shown in Table 18, the first deinterleaving pre-stored table, the second deinterleaving pre-stored table, the third deinterleaving pre-stored table, the fourth deinterleaving pre-stored table, the fifth deinterleaving pre-stored table, the sixth deinterleaving pre-stored table, and the seventh deinterleaving pre-stored table will be stored so that they can be looked up during subsequent deinterleaving.
[0176] 3. The process of performing full sequence interleaving based on the pre-stored deinterleaving pre-table to obtain the full sequence deinterleaving result is as follows:
[0177] If K2 < 128, it will only be stored in two registers (such as the fourth register and the fifth register). The contents loaded in the fourth register and the fifth register will be concatenated and interleaved according to the pre-stored first deinterleaving pre-stored table.
[0178] For example, the contents loaded in the fourth register (e.g., T3) and the contents loaded in the fifth register (e.g., T4) are concatenated, with the contents loaded in the fourth register (e.g., T3) serving as the lower 64 bits of the concatenated contents and the contents loaded in the fifth register (e.g., T4) serving as the higher 64 bits of the concatenated contents. By referring to the first interleaving pre-store table shown in Table 3, the third interleaving pre-store table shown in Table 4, and the first deinterleaving pre-store table shown in Table 12, the full sequence deinterleaving result is obtained.
[0179] If K2 ≥ 128, then:
[0180] (1) The contents loaded in the fourth and fifth registers are concatenated and interleaved according to the pre-stored deinterleaving pre-stored table to obtain the second intermediate interleaving result.
[0181] For example, the contents loaded in the fourth register (e.g., T3) and the contents loaded in the fifth register (e.g., T4) are concatenated, with the contents loaded in the fourth register (e.g., T3) serving as the lower 64 bits of the concatenated result and the contents loaded in the fifth register (e.g., T4) serving as the higher 64 bits. By referring to the second deinterleaving pre-store table shown in Table 13, the fourth deinterleaving pre-store table shown in Table 14, and the sixth deinterleaving pre-store table shown in Table 15, the second intermediate interleaving result T3` (i.e., the first deinterleaving result) is obtained.
[0182] (2) The second intermediate interleaving result and the content loaded in the sixth register are concatenated and interleaved according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result.
[0183] For example, the second intermediate interleaving result (T3`) and the content loaded in the sixth register (such as T5) are concatenated. The second intermediate interleaving result (T3`) is used as the lower 64 bits of the concatenated result, and the content loaded in the sixth register (such as T5) is used as the higher 64 bits of the concatenated result. The full sequence deinterleaving result (i.e. the second deinterleaving result) is obtained by looking up the third deinterleaving pre-store table shown in Table 16, the fifth deinterleaving pre-store table shown in Table 17, and the seventh deinterleaving pre-store table shown in Table 18.
[0184] In other words, during interleaving, T4 and T3 are concatenated and de-interleaved once to obtain T3', and then T5 is concatenated with the result of the first de-interleaving, T3', for a second de-interleaving, resulting in a 64-byte de-interleaved result. Each 64-byte output result requires two de-interleaving operations.
[0185] 203, the least significant bit of each byte in the full sequence deinterleaving result is used to form the final deinterleaving result.
[0186] For example, in step 203, the lowest bit of each byte is extracted to obtain the final deinterleaving result.
[0187] The deinterleaving method provided in this embodiment utilizes a pre-generated deinterleaving pre-stored table to pre-calculate and store the deinterleaving indexes for different scenarios offline as a static table. At runtime, the indexes are retrieved directly by looking up the table, avoiding real-time calculation. This solves the following problems:
[0188] 1) Reduce computational complexity: Transform dynamic calculations into simple table lookup operations, requiring only address mapping logic in hardware implementation.
[0189] 2) Reduce time consumption: Eliminate the loop iteration and computation delay of real-time algorithms to achieve fast deinterleaving.
[0190] 3) Optimize memory resources: Static tables can be stored in read-only memory (ROM), eliminating the need for dynamic memory allocation and reducing runtime memory usage.
[0191] 4) Improve versatility: Adapt to multiple scenarios through a unified table lookup interface, reducing code and hardware logic redundancy.
[0192] The deinterleaving method provided in this embodiment accelerates the deinterleaving process in the Polar encoding and decoding process based on the deinterleaving pre-stored table, thereby reducing system time consumption and alleviating memory burden.
[0193] This application provides a deinterleaving method that loads the byte sequence of the interleaving result into three registers of the interleaver, performs full-sequence interleaving according to a pre-stored deinterleaving pre-table, and obtains the full-sequence deinterleaving result. This transforms the real-time calculation of the deinterleaving index into a lookup table to obtain the index, eliminating real-time loop iteration and computation delay, and achieving fast deinterleaving.
[0194] Based on the same inventive concept of the interlacing method, this embodiment provides an interlacing device, see [link to relevant documentation]. Figure 3 The device includes:
[0195] The first processing module 301 is used to perform byte expansion on the information bit sequence to be interleaved to obtain an information byte sequence.
[0196] The second processing module 302 is used to load the information byte sequence into the three registers of the interleaver, perform full sequence interleaving according to the pre-stored interleaving pre-store table, and obtain the full sequence interleaving result.
[0197] The third processing module 303 is used to extract bits from the full sequence interleaving result to obtain the final interleaving result.
[0198] The interleaving pre-stored table includes 6 tables.
[0199] Among them, the first and second interleaving pre-store tables correspond to bytes 0-63, the third and fourth interleaving pre-store tables correspond to bytes 64-127, and the fifth and sixth interleaving pre-store tables correspond to bytes 128-163.
[0200] The first processing module 301 is used to expand the information bit sequence to be interleaved into a byte type.
[0201] Add a padding to the beginning of the information bit sequence to be interleaved. Subtract 1 from each byte type to obtain the information byte sequence.
[0202] in, K1 is the maximum decoding length, and K1 is the total number of bits in the information bit sequence to be interleaved.
[0203] The second processing module is used to concatenate the contents loaded in the first register and the second register, and perform interleaving according to the pre-stored interleaving pre-stored table to obtain the first intermediate interleaving result.
[0204] The first intermediate interleaving result and the content loaded in the third register are concatenated, and interleaving is performed according to the pre-stored interleaving pre-store table to obtain the full sequence interleaving result.
[0205] The third processing module is used to extract bytes that are not less than 0 from the full sequence interleaving result.
[0206] The lowest bit of the extracted bytes is used to form the final interleaving result.
[0207] The apparatus provided in this embodiment loads the information byte sequence into three registers of the interleaver, performs full-sequence interleaving according to the pre-stored interleaving pre-table, and transforms the real-time calculation of the interleaving index into a table lookup index, eliminating real-time loop iteration and computation delay, and achieving fast interleaving.
[0208] Based on the same inventive concept as the deinterlacing method, this embodiment provides a deinterlacing device, see [link to relevant documentation]. Figure 4 The device includes:
[0209] The fourth processing module 401 is used to perform byte expansion on the interleaving result to be deinterleaved, obtaining the interleaving result byte sequence. The interleaving result to be deinterleaved is obtained through... Figure 1 The interleaving method provided in the illustrated embodiment is used to obtain the result.
[0210] The fifth processing module 402 is used to load the interleaving result byte sequence into the three registers of the interleaver, perform full sequence interleaving according to the pre-stored deinterleaving pre-stored table, and obtain the full sequence deinterleaving result.
[0211] The sixth processing module 403 is used to form the final deinterleaving result from the least significant bit of each byte in the full sequence deinterleaving result.
[0212] If K2 < 128, then the deinterleaving pre-store table is the first deinterleaving pre-store table. If K2 ≥ 128, then there are 6 deinterleaving pre-store tables. The second and third deinterleaving pre-store tables correspond to bytes 0-63, the fourth and fifth deinterleaving pre-store tables correspond to bytes 64-127, and the sixth and seventh deinterleaving pre-store tables correspond to bytes 128-163.
[0213] K2 is the total number of bits in the interleaving result to be deinterleaved.
[0214] The fifth processing module is used to concatenate the contents loaded in the fourth and fifth registers, and perform interleaving according to the pre-stored deinterleaving pre-stored table to obtain the second intermediate interleaving result.
[0215] The second intermediate interleaving result and the content loaded in the sixth register are concatenated, and interleaving is performed according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result.
[0216] The apparatus provided in this embodiment loads the interleaving result byte sequence into three registers of the interleaver, performs full-sequence interleaving according to the pre-stored deinterleaving pre-table, obtains the full-sequence deinterleaving result, and then transforms the real-time calculation of the deinterleaving index into a table lookup index, eliminating real-time loop iteration and computation delay, and achieving fast deinterleaving.
[0217] Based on the same inventive concept of the interleaving method, this embodiment provides an electronic device, which is as follows: Figure 5 As shown, it includes: memory 501, processor 502, and computer program.
[0218] The computer program is stored in memory 501 and configured to be executed by processor 502 to implement the above-described interleaving method.
[0219] Specifically,
[0220] The information bit sequence to be interleaved is extended by bytes to obtain the information byte sequence.
[0221] The sequence of information bytes is loaded into the three registers of the interleaver, and full-sequence interleaving is performed according to the pre-stored interleaving pre-table to obtain the full-sequence interleaving result.
[0222] Bit extraction is performed on the full sequence interleaving result to obtain the final interleaving result.
[0223] The interleaving pre-stored table includes 6 tables.
[0224] Among them, the first and second interleaving pre-store tables correspond to bytes 0-63, the third and fourth interleaving pre-store tables correspond to bytes 64-127, and the fifth and sixth interleaving pre-store tables correspond to bytes 128-163.
[0225] The process involves byte-expansion of the information bit sequence to be interleaved, resulting in an information byte sequence, including:
[0226] Expand the bit sequence of information to be interleaved into a byte type.
[0227] Add a padding to the beginning of the information bit sequence to be interleaved. Subtract 1 from each byte type to obtain the information byte sequence.
[0228] in, K1 is the maximum decoding length, and K1 is the total number of bits in the information bit sequence to be interleaved.
[0229] The process involves performing full sequence interleaving based on a pre-stored interleaving table to obtain the full sequence interleaving result, including:
[0230] The contents loaded in the first register and the second register are concatenated and interleaved according to the pre-stored interleaving pre-table to obtain the first intermediate interleaving result.
[0231] The first intermediate interleaving result and the content loaded in the third register are concatenated, and interleaving is performed according to the pre-stored interleaving pre-store table to obtain the full sequence interleaving result.
[0232] The process involves bit extraction from the full sequence interleaving result to obtain the final interleaving result, including:
[0233] Extract bytes that are not less than 0 from the full sequence interleaving result.
[0234] The lowest bit of the extracted bytes is used to form the final interleaving result.
[0235] The electronic device provided in this embodiment has a computer program executed by a processor to load the sequence of information bytes into the three registers of the interleaver, and perform full-sequence interleaving according to the pre-stored interleaving pre-table. This transforms the real-time calculation of the interleaving index into a lookup table to obtain the index, eliminating real-time loop iteration and computation delay, and achieving fast interleaving.
[0236] Based on the same inventive concept of the deinterleaving method, this embodiment provides an electronic device, which is as follows: Figure 6 As shown, it includes: a memory 601, a processor 602, and a computer program.
[0237] The computer program is stored in memory 601 and configured to be executed by processor 602 to implement the above-described deinterleaving method.
[0238] Specifically,
[0239] The interleaving result to be deinterleaved is byte-extended to obtain the interleaving result byte sequence. The interleaving result to be deinterleaved is obtained using the method described in the first aspect above.
[0240] The interleaving result byte sequence is loaded into the three registers of the interleaver, and full sequence interleaving is performed according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result.
[0241] The lowest bit of each byte in the full sequence deinterleaving result is used to form the final deinterleaving result.
[0242] If K2 < 128, then the deinterleaving pre-store table is the first deinterleaving pre-store table. If K2 ≥ 128, then there are 6 deinterleaving pre-store tables. The second and third deinterleaving pre-store tables correspond to bytes 0-63, the fourth and fifth deinterleaving pre-store tables correspond to bytes 64-127, and the sixth and seventh deinterleaving pre-store tables correspond to bytes 128-163.
[0243] K2 is the total number of bits in the interleaving result to be deinterleaved.
[0244] Specifically, full sequence interleaving is performed based on a pre-stored deinterleaving pre-table to obtain the full sequence deinterleaving result, including:
[0245] The contents loaded in the fourth and fifth registers are concatenated and interleaved according to the pre-stored deinterleaving pre-table to obtain the second intermediate interleaving result.
[0246] The second intermediate interleaving result and the content loaded in the sixth register are concatenated, and interleaving is performed according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result.
[0247] The electronic device provided in this embodiment has a computer program executed by a processor to load the interleaving result byte sequence into the three registers of the interleaver, perform full sequence interleaving according to the pre-stored deinterleaving pre-stored table, obtain the full sequence deinterleaving result, and then change the real-time calculation of the deinterleaving index to the lookup table to obtain the index, eliminating the real-time loop iteration and operation delay, and realizing fast deinterleaving.
[0248] Based on the same inventive concept as the interleaving method, this embodiment provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the above-described interleaving method.
[0249] Specifically,
[0250] The information bit sequence to be interleaved is extended by bytes to obtain the information byte sequence.
[0251] The sequence of information bytes is loaded into the three registers of the interleaver, and full-sequence interleaving is performed according to the pre-stored interleaving pre-table to obtain the full-sequence interleaving result.
[0252] Bit extraction is performed on the full sequence interleaving result to obtain the final interleaving result.
[0253] The interleaving pre-stored table includes 6 tables.
[0254] Among them, the first and second interleaving pre-store tables correspond to bytes 0-63, the third and fourth interleaving pre-store tables correspond to bytes 64-127, and the fifth and sixth interleaving pre-store tables correspond to bytes 128-163.
[0255] The process involves byte-expansion of the information bit sequence to be interleaved, resulting in an information byte sequence, including:
[0256] Expand the bit sequence of information to be interleaved into a byte type.
[0257] Add a padding to the beginning of the information bit sequence to be interleaved. Subtract 1 from each byte type to obtain the information byte sequence.
[0258] in, K1 is the maximum decoding length, and K1 is the total number of bits in the information bit sequence to be interleaved.
[0259] The process involves performing full sequence interleaving based on a pre-stored interleaving table to obtain the full sequence interleaving result, including:
[0260] The contents loaded in the first register and the second register are concatenated and interleaved according to the pre-stored interleaving pre-table to obtain the first intermediate interleaving result.
[0261] The first intermediate interleaving result and the content loaded in the third register are concatenated, and interleaving is performed according to the pre-stored interleaving pre-store table to obtain the full sequence interleaving result.
[0262] The process involves bit extraction from the full sequence interleaving result to obtain the final interleaving result, including:
[0263] Extract bytes that are not less than 0 from the full sequence interleaving result.
[0264] The lowest bit of the extracted bytes is used to form the final interleaving result.
[0265] The computer-readable storage medium provided in this embodiment has a computer program thereon that is executed by a processor to load a sequence of information bytes into three registers of an interleaver, perform full-sequence interleaving according to a pre-stored interleaving pre-table, and thus transform the real-time calculation of the interleaving index into a lookup table to obtain the index, eliminating real-time loop iteration and computational delay, and achieving fast interleaving.
[0266] Based on the same inventive concept as the deinterleaving method, this embodiment provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the above-described deinterleaving method.
[0267] Specifically,
[0268] The interleaving result to be deinterleaved is byte-extended to obtain the interleaving result byte sequence. The interleaving result to be deinterleaved is obtained using the method described in the first aspect above.
[0269] The interleaving result byte sequence is loaded into the three registers of the interleaver, and full sequence interleaving is performed according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result.
[0270] The lowest bit of each byte in the full sequence deinterleaving result is used to form the final deinterleaving result.
[0271] If K2 < 128, then the deinterleaving pre-store table is the first deinterleaving pre-store table. If K2 ≥ 128, then there are 6 deinterleaving pre-store tables. The second and third deinterleaving pre-store tables correspond to bytes 0-63, the fourth and fifth deinterleaving pre-store tables correspond to bytes 64-127, and the sixth and seventh deinterleaving pre-store tables correspond to bytes 128-163.
[0272] K2 is the total number of bits in the interleaving result to be deinterleaved.
[0273] Specifically, full sequence interleaving is performed based on a pre-stored deinterleaving pre-table to obtain the full sequence deinterleaving result, including:
[0274] The contents loaded in the fourth and fifth registers are concatenated and interleaved according to the pre-stored deinterleaving pre-table to obtain the second intermediate interleaving result.
[0275] The second intermediate interleaving result and the content loaded in the sixth register are concatenated, and interleaving is performed according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result.
[0276] The computer-readable storage medium provided in this embodiment has a computer program thereon that is executed by a processor to load the interleaving result byte sequence into the three registers of the interleaver, perform full-sequence interleaving according to the pre-stored deinterleaving pre-stored table, obtain the full-sequence deinterleaving result, and then change the real-time calculation of the deinterleaving index to a table lookup index, eliminating real-time loop iteration and operation delay, and realizing fast deinterleaving.
[0277] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.
[0278] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0279] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0280] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0281] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0282] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0283] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. An interlacing method, characterized in that, The method includes: The information bit sequence to be interleaved is extended by bytes to obtain the information byte sequence; The information byte sequence is loaded into the three registers of the interleaver, and full sequence interleaving is performed according to the pre-stored interleaving pre-store table to obtain the full sequence interleaving result; Bit extraction is performed on the full sequence interleaving result to obtain the final interleaving result; Among them, the interleaving pre-store table includes 6; Among them, the first and second interleaving pre-store tables correspond to bytes 0-63, the third and fourth interleaving pre-store tables correspond to bytes 64-127, and the fifth and sixth interleaving pre-store tables correspond to bytes 128-163.
2. The method according to claim 1, characterized in that, The step of byte-expanding the information bit sequence to be interleaved to obtain an information byte sequence includes: Expand the bit sequence of information to be interleaved into a byte type; Add a padding to the beginning of the information bit sequence to be interleaved. Subtract 1 from the number of bytes to obtain the information byte sequence; in, K1 is the maximum decoding length, and K1 is the total number of bits in the information bit sequence to be interleaved.
3. The method according to claim 1, characterized in that, The step of performing full sequence interleaving based on a pre-stored interleaving pre-table to obtain the full sequence interleaving result includes: The contents loaded in the first register and the second register are concatenated and interleaved according to the pre-stored interleaving pre-table to obtain the first intermediate interleaving result; The first intermediate interleaving result and the content loaded in the third register are concatenated, and interleaving is performed according to the pre-stored interleaving pre-store table to obtain the full sequence interleaving result.
4. The method according to claim 2, characterized in that, The bit extraction from the full sequence interleaving result to obtain the final interleaving result includes: Extract bytes that are not less than 0 from the full sequence interleaving result; The lowest bit of the extracted bytes is used to form the final interleaving result.
5. A method for de-intertwining, characterized in that, The method includes: The interleaving result to be deinterleaved is extended by bytes to obtain an interleaving result byte sequence; wherein the interleaving result to be deinterleaved is obtained by the method described in any one of claims 1-4; The interleaving result byte sequence is loaded into the three registers of the interleaver, and full sequence interleaving is performed according to the pre-stored deinterleaving pre-store table to obtain the full sequence deinterleaving result; The least significant bit of each byte in the full sequence deinterleaving result is used to form the final deinterleaving result; If K2 < 128, then the deinterleaving pre-store table is the first deinterleaving pre-store table. If K2 ≥ 128, then there are 6 deinterleaving pre-store tables. The second and third deinterleaving pre-store tables correspond to bytes 0-63, the fourth and fifth deinterleaving pre-store tables correspond to bytes 64-127, and the sixth and seventh deinterleaving pre-store tables correspond to bytes 128-163. K2 is the total number of bits in the interleaving result to be deinterleaved.
6. The method according to claim 5, characterized in that, The step of performing full sequence interleaving based on a pre-stored deinterleaving pre-table to obtain a full sequence deinterleaving result includes: The contents loaded in the fourth and fifth registers are concatenated and interleaved according to the pre-stored deinterleaving pre-stored table to obtain the second intermediate interleaving result; The second intermediate interleaving result and the content loaded in the sixth register are concatenated, and interleaving is performed according to the pre-stored deinterleaving pre-stored table to obtain the full sequence deinterleaving result.
7. An interlacing device, characterized in that, The device includes: The first processing module is used to perform byte expansion on the information bit sequence to be interleaved to obtain an information byte sequence. The second processing module is used to load the information byte sequence into the three registers of the interleaver, perform full sequence interleaving according to the pre-stored interleaving pre-store table, and obtain the full sequence interleaving result; The third processing module is used to extract bits from the full sequence interleaving result to obtain the final interleaving result. Among them, the interleaving pre-store table includes 6; Among them, the first and second interleaving pre-store tables correspond to bytes 0-63, the third and fourth interleaving pre-store tables correspond to bytes 64-127, and the fifth and sixth interleaving pre-store tables correspond to bytes 128-163.
8. A de-interlacing device, characterized in that, The device includes: The fourth processing module is used to perform byte expansion on the interleaving result to be deinterleaved, to obtain an interleaving result byte sequence; wherein the interleaving result to be deinterleaved is obtained by the method described in any one of claims 1-4; The fifth processing module is used to load the interleaving result byte sequence into the three registers of the interleaver, perform full sequence interleaving according to the pre-stored deinterleaving pre-stored table, and obtain the full sequence deinterleaving result; The sixth processing module is used to form the final deinterleaving result from the least significant bit of each byte in the full sequence deinterleaving result; If K2 < 128, then the deinterleaving pre-store table is the first deinterleaving pre-store table. If K2 ≥ 128, then there are 6 deinterleaving pre-store tables. The second and third deinterleaving pre-store tables correspond to bytes 0-63, the fourth and fifth deinterleaving pre-store tables correspond to bytes 64-127, and the sixth and seventh deinterleaving pre-store tables correspond to bytes 128-163. K2 is the total number of bits in the interleaving result to be deinterleaved.
9. An electronic device, characterized in that, include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the method as described in any one of claims 1-4, or to implement the method as described in claim 5 or 6.
10. A computer-readable storage medium, characterized in that, It stores a computer program thereon; the computer program is executed by a processor to implement the method as described in any one of claims 1-4, or to implement the method as described in claim 5 or 6.