Single-rail flash memory array with group pair structure

Abstract

The application provides a group pair structure single-tube flash memory array. In the group pair structure single-tube flash memory array, a substrate comprises a plurality of active regions and isolation structures, one active region comprises a plurality of first segments extending along a first direction and a plurality of second segments extending along a second direction, the first segments and the second segments are alternately arranged in the extension direction of the active region and are both inclined relative to the extension direction of the active region; one group pair storage unit is arranged on one first segment and one second segment respectively, and a plurality of group pair storage units on the same active region form a column; one group pair storage unit comprises two storage tubes with connected sources; a plurality of bit lines extend along the extension direction of the active region, two bit lines form a group, the drain of one storage tube of the group pair storage unit is connected with one bit line in the group and the drain of the other storage tube is connected with the other bit line in the group. In this way, the width of the active region can be reduced, and further miniaturization of the flash memory array is facilitated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a single-tube flash memory array with a group pair structure. BACKGROUND

[0002] Flash memory is a kind of nonvolatile semiconductor memory chip, which can keep the stored data information even in the case of power failure. Flash memory has the advantages of small size, low power consumption and not easy to be physically damaged, and has been widely used.

[0003] With the development of semiconductor chip technology, memory gradually develops towards miniaturization, and the industry needs to continuously research the problem of miniaturized memory array. SUMMARY

[0004] The present application provides a single-tube flash memory array with a group pair structure, which can reduce the width of the active area and expand the space of the isolation structure between the active areas, providing convenience for further miniaturization of the single-tube flash memory array with a group pair structure.

[0005] In order to achieve the above purpose, the single-tube flash memory array with a group pair structure provided by the present application comprises: a substrate comprising a plurality of active areas and an isolation structure separating the plurality of active areas, one of the active areas comprising a plurality of first segments extending along a first direction and a plurality of second segments extending along a second direction, the first segments and the second segments being arranged alternately and continuously extending with each other in the extension direction of the active area, the first direction and the second direction being inclined relative to the extension direction of the active area, the included angle between the first direction and the second direction being greater than 0 degrees and less than 180 degrees; a plurality of the active areas are arranged in parallel in the substrate; a plurality of group pair storage units, one of the first segments and one of the second segments are respectively provided with one of the group pair storage units, a plurality of the group pair storage units on the same active area form a column, and a plurality of the group pair storage units corresponding to different positions of the active areas form a row; one of the group pair storage units comprises two storage tubes with connected sources; a plurality of bit lines are located on the substrate and extend along the extension direction of the active area, two of the bit lines form a group, and a column of the group pair storage units is connected to a group of the bit lines, the drain of one of the storage tubes of the group pair storage unit is connected to one of the bit lines of the corresponding group, and the drain of the other storage tube is connected to the other bit line of the corresponding group.

[0006] Optionally, the drain of the storage tube is connected with the corresponding bit line through a contact hole on the drain, the distance between the two contact holes on the drains of the two storage tubes of the same group of storage cell pairs in the width direction of the active region and the sum of the widths of the two contact holes are a first width, the width of the active region is a second width, and the second width is less than the first width.

[0007] Optionally, the first segment extends linearly or in an arc in the first direction, and the second segment extends linearly or in an arc in the second direction.

[0008] Optionally, the lengths of the first segment and the second segment in the extension direction of the active region are equal.

[0009] Optionally, the single-tube flash memory array of the group pair structure further comprises: a plurality of word lines on the substrate, two word lines form a group, and a group of word lines is connected to a row of the group pair storage cell pairs, the gate of one storage tube of the group pair storage cell is connected to one of the corresponding group of word lines, and the gate of the other storage tube is connected to the other of the corresponding group of word lines.

[0010] Optionally, one of the two bit lines in the same group can serve as the source line of the other.

[0011] Optionally, when data writing or data reading is performed on one of the two storage tubes in the same group pair storage cell, the other serves as a selection tube.

[0012] Optionally, a plurality of the group pair storage cells are arranged on the same well region of the substrate.

[0013] Optionally, the two storage tubes of the same group pair storage cell share the same source region, and one storage tube of the group pair storage cell and one storage tube of another group pair storage cell in the same column and adjacent to each other share the drain region.

[0014] Optionally, the storage tubes in the plurality of group pair storage cells are all N-type storage tubes or all P-type storage tubes.

[0015] The application provides a single-tube flash memory array with a group pair structure. The substrate comprises a plurality of active regions and isolation structures separating the plurality of active regions. One active region comprises a plurality of first segments extending along a first direction and a plurality of second segments extending along a second direction. The first segments and the second segments are alternately arranged and continuously extend with each other in the extension direction of the active region. The first direction and the second direction are both inclined relative to the extension direction of the active region. The included angle between the first direction and the second direction is greater than 0 degrees and less than 180 degrees. The plurality of active regions are arranged in parallel in the substrate. One group pair storage unit is arranged on one first segment and one second segment respectively. The plurality of group pair storage units on the same active region form a column, and the plurality of group pair storage units corresponding to the positions of different active regions form a row. One group pair storage unit comprises two storage tubes with connected sources. A plurality of bit lines are arranged on the substrate and extend along the extension direction of the active region. Two bit lines form a group. One column of group pair storage units is connected to one group of bit lines. The drain of one storage tube of the group pair storage unit is connected to one bit line in the corresponding group, and the drain of the other storage tube is connected to the other bit line in the corresponding group. Thus, on the basis of realizing the connection between the group pair storage unit and the corresponding group of bit lines, the width of the active region can be reduced, the space of the isolation structure between the active regions is expanded, and the further miniaturization of the single-tube flash memory array with the group pair structure is facilitated, which is beneficial to reducing the area of the flash memory array or improving the integration of the flash memory array. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A layout schematic diagram of an existing single-tube flash memory array with a group pair structure.

[0017] Figure 2 A layout schematic diagram of a single-tube flash memory array with a group pair structure provided by an embodiment of the application.

[0018] Figure 3 An architecture diagram of a group pair storage unit provided by an embodiment of the application.

[0019] Figure 4 A schematic diagram of an active region provided by an embodiment of the application.

[0020] Figure 5 A partial SEM diagram of a single-tube flash memory array with a group pair structure provided by another embodiment of the application.

[0021] Label explanation: 101-active region; 101a-first segment; 101b-second segment; 102-isolation structure; 103-group pair storage unit; 104-bit line; 105-word line; 106-contact hole. DETAILED DESCRIPTION

[0022] Figure 1 A layout schematic diagram of an existing single-tube flash memory array with a group pair structure. As shown in FIG. 1, the substrate comprises a plurality of active regions 101 and isolation structures 102 separating the plurality of active regions 101. One active region 101 comprises a plurality of first segments 101a extending along a first direction and a plurality of second segments 101b extending along a second direction. The first segments 101a and the second segments 101b are alternately arranged and continuously extend with each other in the extension direction of the active region 101. The first direction and the second direction are both inclined relative to the extension direction of the active region 101. The included angle between the first direction and the second direction is greater than 0 degrees and less than 180 degrees. The plurality of active regions 101 are arranged in parallel in the substrate. One group pair storage unit 103 is arranged on one first segment 101a and one second segment 101b respectively. The plurality of group pair storage units 103 on the same active region 101 form a column, and the plurality of group pair storage units 103 corresponding to the positions of different active regions 101 form a row. One group pair storage unit 103 comprises two storage tubes with connected sources. A plurality of bit lines 104 are arranged on the substrate and extend along the extension direction of the active region 101. Two bit lines 104 form a group. One column of group pair storage units 103 is connected to one group of bit lines 104. The drain of one storage tube of the group pair storage unit 103 is connected to one bit line 104 in the corresponding group, and the drain of the other storage tube is connected to the other bit line 104 in the corresponding group. Thus, on the basis of realizing the connection between the group pair storage unit 103 and the corresponding group of bit lines 104, the width of the active region 101 can be reduced, the space of the isolation structure 102 between the active regions 101 is expanded, and the further miniaturization of the single-tube flash memory array with the group pair structure is facilitated, which is beneficial to reducing the area of the flash memory array or improving the integration of the flash memory array.Figure 1 As shown in the figure, in the group pair structure single-tube flash memory array, a plurality of group pair storage units 103 are arranged on the active region 101, the drains of the two storage tubes of the group pair storage unit 103 are connected with a corresponding group of bit lines 104 through the contact holes 106, wherein the active region 101 is in a straight strip shape, the width of the active region 101 is W2, the sum of the distance between the two contact holes 106 on the drains of the two storage tubes of the group pair storage unit 103 and the width of the two contact holes 106 is W1, in order to realize the connection of the group pair storage unit 103 and the corresponding group of bit lines 104, the width W2 of the active region 101 needs to be greater than or equal to W1. In this way, the width of the active region 101 will be limited by the width of the two contact holes 106 and the isolation distance between the two bit lines 104, and the active region 101 will occupy the space of the isolation structure 102, which is not conducive to the further miniaturization of the active region 101.

[0023] Therefore, the present application provides a group pair structure single-tube flash memory array, wherein an active region includes a plurality of first segments extending along a first direction and a plurality of second segments extending along a second direction, the first segments and the second segments are arranged alternately and continuously in the extension direction of the active region, the first direction and the second direction are both inclined relative to the extension direction of the active region, the included angle between the first direction and the second direction is greater than 0 degrees and less than 180 degrees, one group pair storage unit is arranged on one first segment and one second segment respectively, the drain of one storage tube of the group pair storage unit is connected with one of the corresponding group of bit lines, and the drain of the other storage tube is connected with the other of the corresponding group of bit lines. In this way, on the basis of realizing the connection of the group pair storage unit and the corresponding group of bit lines, the width of the active region can be reduced, the space of the isolation structure between the active regions can be expanded, and the further miniaturization of the group pair structure single-tube flash memory array is facilitated.

[0024] The group pair structure single-tube flash memory array provided by the present application will be further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be clearer according to the following description. It should be noted that the drawings are all in a very simplified form and all use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application.

[0025] Figure 2 The layout schematic diagram of the group pair structure single-tube flash memory array provided by an embodiment of the present application. Figure 3 The architecture diagram of one group pair storage unit provided by an embodiment of the present application. Figure 4 The schematic diagram of the active region provided by an embodiment of the present application.

[0026] As Figure 2 , Figure 3 and Figure 4As shown, the single-tube flash memory array of the group pair structure provided by the embodiment includes a substrate, a plurality of group pair storage units 103, and a plurality of bit lines 104. The substrate includes a plurality of active regions 101 and isolation structures 102 separating the plurality of active regions 101, one of the active regions 101 includes a plurality of first segments 101a extending along a first direction X1 and a plurality of second segments 101b extending along a second direction X2, the first segments 101a and the second segments 101b are alternately arranged and continuously extend with each other in an extension direction X3 of the active region 101, the first direction X1 and the second direction X2 are both inclined relative to the extension direction X3 of the active region, and an included angle between the first direction X1 and the second direction X2 is greater than 0 degrees and less than 180 degrees; the plurality of active regions 101 are arranged and extend in parallel in the substrate; one of the group pair storage units 103 is arranged on one of the first segments 101a and one of the second segments 101b, respectively, a plurality of the group pair storage units 103 on the same active region 101 form a column, and a plurality of the group pair storage units 103 corresponding to positions of different active regions 101 form a row; one of the group pair storage units 103 includes two storage tubes with connected sources, i.e., a first storage tube T1 and a second storage tube T2; the plurality of bit lines 104 are located on the substrate and extend along the extension direction X3 of the active region 101, two of the bit lines 104 form a group, and one column of the group pair storage units 103 is connected to one group of the bit lines 104, and a drain of one of the storage tubes of the group pair storage unit 103 is connected to one of the bit lines 104 of the corresponding group, and a drain of the other storage tube is connected to the other bit line 104 of the corresponding group.

[0027] In the embodiment, as shown in Figure 2 and Figure 4 As shown, the first segments 101a of the active regions 101 can extend linearly in the first direction X1, the second segments 101b of the active regions 101 can extend linearly in the second direction X2, and the active regions 101 generally extend in the X3 direction.

[0028] Figure 5 A partial SEM diagram of the single-tube flash memory array of the group pair structure provided by another embodiment of the application is shown. In the other embodiment, as shown in Figure 5 As shown, the first segments and the second segments of the active regions 101 can both extend in an arc in a set direction. In some other embodiments, one of the first segments and the second segments of the active regions 101 can extend linearly and the other can extend in an arc.

[0029] In an embodiment, as shown in Figure 4As shown, the length of the first segment 101a in the extension direction X3 of the active region 101 is L1, and the length of the second segment 101b in the extension direction X3 of the active region 101 is L2. L1 and L2 can be equal, which facilitates the arrangement of bit lines 104, but is not limited thereto.

[0030] For example, such as Figure 4 As shown, the first direction X1 and the second direction X2 can point to both sides of the extension direction X3 of the active region 101. The angle between the first direction X1 and X3 and the angle between the second direction X2 and X3 can be equal, but are not limited to this. It should be noted that, referring to... Figure 4 The first segment 101a can be understood as extending along the first direction X1 in a positive or negative direction, the second segment 101b can be understood as extending along the second direction X2 in a positive or negative direction, and the active region 101 can be understood as extending along the third direction X3 in a positive or negative direction.

[0031] In this embodiment, the two storage tubes in the paired storage unit 103 are each independent minimum storage units, that is, each minimum storage unit contains one storage tube.

[0032] In one embodiment of this application, both memory transistors in the paired memory cell 103 can be charge-trap type memory transistors. This results in a lower vertical height of the memory transistors, which facilitates continuous miniaturization with the iteration of process technology and can be applied to 3D memory technology. In another embodiment of this application, both memory transistors in the paired memory cell 103 can be floating-gate type memory transistors, but this is not a limitation.

[0033] In this embodiment, the two memory transistors in the paired memory cell 103 have the same structure and size, meaning they are identical memory transistors. The only difference is that the bit lines connecting the drains of the two memory transistors are different. This embodiment's paired single-transistor flash memory array contains only a single device, has a symmetrical structure, and a simple layout. Furthermore, the two memory transistors in the same paired memory cell 103 have identical dimensions and manufacturing processes, facilitating the acquisition (fabrication) of the paired single-transistor flash memory array and helping to reduce manufacturing costs.

[0034] In this embodiment, multiple pairs of storage cells 103 can be disposed on the same well region on the substrate. For ease of understanding, in Figure 3 In the diagram, each memory cell shows a substrate end, and each substrate end is connected to a VPwell connection line. However, as shown... Figure 2 As shown, in the actual layout of a single-tube flash array with a pair structure, the substrate is the well connection line VPwell, and applying voltage to the well connection line VPwell is equivalent to applying voltage to the well region in the substrate.

[0035] In this embodiment, the well region can be P-type, and both of the two storage tubes of the group pair of storage units 103 can be N-type storage tubes. In another embodiment, the well region can be N-type, and both of the two storage tubes of the group pair of storage units 103 can be P-type storage tubes.

[0036] As shown in Figure 2 , the two storage tubes of the same group pair of storage units 103 can share the same source region, and there is no need to set a contact hole in the middle of the two storage tubes of the same group pair of storage units 103; one storage tube of one group pair of storage units 103 and one storage tube of another group pair of storage units 103 in the same column and adjacent to each other share the drain region. In this way, the active area can be effectively utilized, which helps to improve the storage density.

[0037] As shown in Figure 2 , a plurality of bit lines 104 (BL) are located on the substrate and extend along the extension direction X3 of the active region 101, two bit lines 104 form a group, and one group of bit lines 104 is connected to a column of group pairs of storage units 103, and the drain of one storage tube of the group pair of storage units 103 is connected to one of the bit lines 104 in the corresponding group, and the drain of the other storage tube is connected to the other bit line in the corresponding group.

[0038] For example, the bit lines BL m-2 and BL m-1 form a group, and this group of bit lines is connected to the first column of group pairs of storage units 103; the bit lines BL m and BL m+1 form a group, and this group of bit lines is connected to the second column of group pairs of storage units 103; the bit lines BL m+2 and BL m+3 form a group, and this group of bit lines is connected to the third column of group pairs of storage units 103.

[0039] In this embodiment, as shown in Figure 2 , the setting position relationship of the corresponding bit lines and the contact holes 106 of the two group pairs of storage units 103 adjacent to each other in the same row can be the same.

[0040] Referring to Figure 2 and Figure 4As shown, the drain of the storage tube in the group pair storage unit 103 is connected with the corresponding bit line 104 through a contact hole 106 on the drain, the interval of the two contact holes 106 on the drains of the two storage tubes of the same group pair storage unit 103 in the active region width direction and the sum of the widths of the two contact holes 106 are the first width W1, the width of the active region 101 is the second width W2, the second width W2 is less than the first width W1, the interval of the two contact holes 106 on the drains of the two storage tubes of one group pair storage unit 103 in the active region width direction is related to the interval between the two bit lines of the same group. That is, the active region 101 of the present application is curvedly extended in the extension direction X3, so that the width of the active region 101 can be reduced, and the connection of the group pair storage unit 103 and the corresponding group of bit lines 104 can also be realized.

[0041] In the embodiment, only one contact hole 106 can be arranged on the shared drain region of the two group pair storage units 103 in the same column and adjacent to each other, which is most conducive to the miniaturization of the flash memory array, but is not limited thereto.

[0042] Reference Figure 2 As shown, the group pair structure single-tube flash memory array further comprises a plurality of word lines 105 (WL) located on the substrate and crossing the plurality of active regions 101, wherein two word lines 105 form a group, and a row of group pair storage units 103 are connected with a group of word lines 105, and the gate of one storage tube of the group pair storage unit 103 is connected with one of the word lines 105 of the corresponding group, and the gate of the other storage tube is connected with the other word line 105 of the corresponding group.

[0043] For example, Figure 2 As shown, the word lines WL n-1 and WL n form a group, and the word lines WL n+1 and WL n+2 form a group, and one word line 105 is connected with the gates of a row of storage tubes.

[0044] In the embodiment, the drains of the two storage tubes in the same group pair storage unit 103 are respectively connected with the two bit lines 104 of the same group, and the two storage tubes are both minimum storage units and can independently store data (binary data), thereby realizing 1T storage density.

[0045] When data write and data read are performed on one of the two storage tubes in the same group pair storage unit 103, the other one is a selection tube, i.e. the two storage tubes in the same group pair storage unit 103 can be selection tubes for each other. The two bit lines corresponding to the group pair storage unit 103 can be source lines for each other. Compared with the structure that a selection tube needs to be specially set in a 2T storage array and one bit line and one fixed source line are simultaneously set in the conventional technology, the structure is helpful to reduce the power consumption of the flash memory array when data write and data read operations are performed, simplify the peripheral high-voltage auxiliary circuit of the flash memory array, save the physical space of the group pair storage unit 103, and improve the storage density of the storage unit array. Moreover, the length of the bit line metal wire can be reduced, for example, the length of the bit line metal wire can be reduced by about 50%, which is helpful to improve the IR Drop of the storage array line resistance.

[0046] When data write operation is performed, the voltages of the two bit lines 104 in the same group can be independently applied. When the two bit lines 104 in the same group apply voltages of the same size, the storage tubes connected with the two bit lines 104 have no channel current, which is helpful to further reduce the power consumption during data write operation.

[0047] The application provides a single-tube flash memory array with a group pair structure, a substrate includes a plurality of active regions 101 and isolation structures 102 separating the plurality of active regions 101, one active region 101 includes a plurality of first segments 101a extending along a first direction X1 and a plurality of second segments 101b extending along a second direction X2, the first segments 101a and the second segments 101b are alternately arranged and continuously extend with each other in an extension direction X3 of the active region 101, the first direction X1 and the second direction X2 are both inclined relative to the extension direction X3 of the active region 101, an included angle between the first direction X1 and the second direction X2 is greater than 0 degree and less than 180 degrees, the plurality of active regions 101 are arranged in parallel in the substrate, one group pair storage unit 103 is arranged on one first segment 101a and one second segment 101b respectively, a plurality of group pair storage units 103 on the same active region 101 form a column, a plurality of group pair storage units 103 corresponding to positions of different active regions 101 form a row, one group pair storage unit 103 includes two storage tubes located on the same active region 101, adjacent to each other and connected at a source, a plurality of bit lines 104 are located on the substrate and extend along the extension direction X3 of the active region 101, two bit lines 104 form a group, one column of group pair storage units 103 is connected to one group of bit lines 104, a drain of one storage tube of the group pair storage unit 103 is connected to one bit line 104 in the corresponding group, and a drain of the other storage tube is connected to another bit line 104 in the corresponding group. In this way, on the basis of realizing the connection between the group pair storage unit 103 and the corresponding group of bit lines 104, the width of the active region 101 can be reduced, the space of the isolation structure 102 between the active regions 101 is expanded, and the further miniaturization of the single-tube flash memory array with the group pair structure is facilitated, that is, the area of the flash memory array is reduced, or the integration of the flash memory array is improved.

[0048] In the embodiments of the present application, the terms "first", "second" and the like are only used for description convenience and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that the specific features, structures, materials or characteristics related to the embodiments or examples are included in at least one embodiment or example of the present application. The exemplary representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0049] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, shall fall within the protection scope of the technical solutions of the present application.

Claims

1. A single-tube flash memory array of a group pair structure, characterized by, The application relates to a memory device, comprising: a substrate, which comprises a plurality of active regions and isolation structures separating the plurality of active regions, one of the active regions comprises a plurality of first segments extending along a first direction and a plurality of second segments extending along a second direction, the first segments and the second segments are alternately arranged and continuously extend with each other in the extending direction of the active region, the first direction and the second direction are both inclined relative to the extending direction of the active region, the included angle between the first direction and the second direction is greater than 0 degrees and less than 180 degrees, and the plurality of active regions are arranged in parallel in the substrate; a plurality of group pair storage units, one of the first segments and one of the second segments are respectively provided with one of the group pair storage units, the plurality of group pair storage units on the same active region form a column, and the plurality of group pair storage units corresponding to the positions of different active regions form a row; one of the group pair storage units comprises two storage tubes with connected sources; and a plurality of bit lines, which are located on the substrate and extend along the extending direction of the active region, two of the bit lines form a group, one column of the group pair storage units is connected to one group of the bit lines, the drain of one of the storage tubes of the group pair storage unit is connected to one of the bit lines in the corresponding group, and the drain of the other storage tube is connected to the other bit line in the corresponding group.

2. The array of single-level cells in a pair structure of claim 1, wherein, The drain of the storage tube is connected to the corresponding bit line through a contact hole located on the drain, the interval between the two contact holes on the drains of the two storage tubes of the same group pair storage unit in the active region width direction and the sum of the widths of the two contact holes are a first width, and the width of the active region is a second width, the second width is less than the first width.

3. The array of claim 1 wherein, The first segments extend linearly or in an arc in the first direction, and the second segments extend linearly or in an arc in the second direction.

4. The array of claim 1 wherein, The lengths of the first segments and the second segments in the extending direction of the active region are equal.

5. The array of claim 1 wherein, Further comprising: a plurality of word lines, which are located on the substrate, two of the word lines form a group, one row of the group pair storage units is connected to one group of the word lines, the gate of one of the storage tubes of the group pair storage unit is connected to one of the word lines in the corresponding group, and the gate of the other storage tube is connected to the other word line in the corresponding group.

6. The array of claim 1 wherein, One of the two bit lines in the same group can serve as the source line of the other bit line.

7. The array of claim 1 wherein, When data writing or data reading is performed on one of the two storage tubes in the same group pair storage unit, the other storage tube serves as a selection tube.

8. The array of claim 1 wherein, The plurality of group pair storage units are arranged on the same well region of the substrate.

9. The array of claim 1 wherein, The two storage tubes of the same group pair storage unit share the same source region, and one of the storage tubes of one group pair storage unit and one of the storage tubes of another group pair storage unit in the same column and adjacent to the one group pair storage unit share the drain region.

10. The array of claim 1 wherein, The storage tubes in the plurality of group pair storage units are all N-type storage tubes or all P-type storage tubes.

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