Semiconductor device, manufacturing method thereof and electronic equipment
By forming staggered first and second common bit lines in semiconductor devices, the problem of increased parasitic capacitance after device size reduction is solved, enabling the fabrication of semiconductor devices with smaller area and lower capacitance, and simplifying the process flow.
Patent Information
- Application Number
- CN202410533365.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-29
- Publication Date
- 2025-10-31
AI Technical Summary
With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the impact of minute differences on device performance is increasing. How to manufacture more devices on a limited substrate and reduce parasitic capacitance has become a challenge.
By forming a multilayer stacked structure on a substrate and using lateral etching of different depths to form interlaced first and second common bit lines, the parasitic capacitance between the common bit lines is reduced. The manufacturing method includes forming a stacked structure of multiple sacrificial layers and insulating layers on a substrate, etching to form trenches, forming first and second grooves with different lateral extension depths in the trenches, and finally forming a conductive layer in the grooves to form interlaced common bit lines.
This enables semiconductor devices to operate normally with smaller storage capacitors, reducing footprint and simplifying manufacturing processes.
Smart Images
Figure CN120881997A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.
[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.
[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, wherein the parasitic capacitance between the common bit lines of the semiconductor device is small.
[0006] This application provides a method for manufacturing a semiconductor device, the method comprising:
[0007] A stacked structure consisting of multiple first sacrificial layers, multiple second sacrificial layers and multiple insulating layers is formed on a substrate, wherein there is a second sacrificial layer between two adjacent first sacrificial layers, a first sacrificial layer between two adjacent second sacrificial layers, and an insulating layer between the first sacrificial layer and the second sacrificial layer.
[0008] The stacked structure is etched along the direction toward the substrate to form a trench through the stacked structure;
[0009] The first sacrificial layer is laterally etched within the trench to form a first groove located on both sides of the trench.
[0010] A first common bit line is formed within the first groove;
[0011] The second sacrificial layer is laterally etched within the trench to form a second groove located on both sides of the trench;
[0012] A second common bit line is formed within the second groove;
[0013] Wherein, the lateral extension depth of the first groove in the first sacrificial layer is different from the lateral extension depth of the second groove in the second sacrificial layer; the orthographic projection of the first common bit line on the substrate and the orthographic projection of the second common bit line on the substrate do not completely overlap.
[0014] In some embodiments, the first common bit line is formed in the first groove before the second groove is formed.
[0015] In some embodiments, the lateral extension depth of the first groove within the first sacrificial layer is greater than the lateral extension depth of the second groove within the second sacrificial layer;
[0016] The formation of the first common bit line within the first groove includes:
[0017] A first conductive layer is deposited on the inner wall of the trench to fill the first groove;
[0018] The first conductive layer on the inner wall of the trench and part of the first conductive layer in the first groove are removed by etching, while the first conductive layer at the bottom of the first groove is retained, resulting in a plurality of first common bit lines located at the bottom of the first groove and spaced apart in a direction perpendicular to the substrate.
[0019] In some embodiments, the manufacturing method further includes: after forming the first common bit line, and before lateral etching the second sacrificial layer within the trench,
[0020] A protective layer covering the first common bit line is formed on the surface of the first common bit line.
[0021] In some embodiments, forming a protective layer covering the first common bit line on the surface of the first common bit line includes:
[0022] A protective layer is deposited on the inner wall of the trench to fill the first groove;
[0023] Remove the protective layer on the inner wall of the trench to expose the second sacrificial layer, and the first common bit line is covered by the remaining protective layer.
[0024] In some embodiments, forming a second common bit line within the second groove includes:
[0025] A second conductive layer is deposited on the inner wall of the trench to fill the second groove;
[0026] The second conductive layer on the inner wall of the trench is removed by etching, while the second conductive layer in the second groove is retained, resulting in a plurality of second common bit lines located in the second groove and spaced apart in a direction perpendicular to the substrate.
[0027] In some embodiments, the manufacturing method further includes: after forming the first common bit line and the second common bit line,
[0028] An isolation layer is filled in the trench to separate two adjacent first common bit lines located on the same horizontal plane parallel to the substrate, and to separate two adjacent second common bit lines located on the same horizontal plane parallel to the substrate.
[0029] In some embodiments, under the same etching conditions, the etching rates of the first sacrificial layer, the second sacrificial layer, and the insulating layer are all different.
[0030] In some embodiments, the insulating layer is a single-layer structure or a multi-layer structure.
[0031] This application embodiment also provides a semiconductor device, the semiconductor device comprising:
[0032] Multiple memory cells are distributed across different layers, stacked along a direction perpendicular to the substrate, and periodically distributed.
[0033] Multiple bit lines are distributed in different layers, stacked and spaced apart along a direction perpendicular to the substrate; each bit line is connected to multiple memory cells located in the same layer;
[0034] Multiple first common bit lines are stacked and spaced apart along a direction perpendicular to the substrate; the first common bit lines extend along a column direction parallel to the substrate and are connected to the bit lines of one of the two adjacent layers.
[0035] Multiple second common bit lines are stacked and spaced apart along a direction perpendicular to the substrate; the second common bit lines extend along the column direction and are connected to bit lines in another layer located in two adjacent layers;
[0036] The first common bit line and the second common bit line are alternately distributed in a direction perpendicular to the substrate, and the orthographic projection of the first common bit line on the substrate and the orthographic projection of the second common bit line on the substrate do not completely overlap.
[0037] In some embodiments, the orthographic projection of the first common bit line on the substrate and the orthographic projection of the second common bit line on the substrate do not overlap.
[0038] In some embodiments, an insulating layer is provided between adjacent first common bit lines and second common bit lines in a direction perpendicular to the substrate, the insulating layer being a single-layer structure or a multi-layer structure.
[0039] In some embodiments, the semiconductor device further includes a plurality of first sacrificial layers, a plurality of second sacrificial layers, and a plurality of insulating layers stacked on the substrate; a second sacrificial layer is provided between two adjacent first sacrificial layers, a first sacrificial layer is provided between two adjacent second sacrificial layers, and the insulating layer is provided between the first sacrificial layer and the second sacrificial layer;
[0040] The first common bit line is located in the first sacrificial layer, and the second common bit line is located in the second sacrificial layer.
[0041] In some embodiments, the memory cell includes a transistor, the transistor including a semiconductor layer, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode; the semiconductor layer extends in a direction perpendicular to the substrate and at least partially surrounds the gate electrode;
[0042] The bit line extends along a row direction parallel to the substrate and is connected to the transistor;
[0043] The semiconductor device further includes multiple word lines extending along a direction perpendicular to the substrate, the word lines penetrating multiple layers of the memory cells.
[0044] This application also provides an electronic device, including a semiconductor device manufactured by the manufacturing method described above, or including a semiconductor device as described above.
[0045] The semiconductor device and manufacturing method of the present application embodiment are configured such that the orthographic projection of the first common bit line on the substrate and the orthographic projection of the second common bit line on the substrate do not completely overlap, so that the first common bit line and the second common bit line are staggered in the direction perpendicular to the substrate. This can increase the distance between the first common bit line and the second common bit line in the direction perpendicular to the substrate, thereby reducing the parasitic capacitance between the first common bit line and the second common bit line.
[0046] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description
[0047] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0048] Figure 1 This is a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of this application;
[0049] Figure 2 A schematic longitudinal cross-section of a semiconductor device manufacturing method provided in an exemplary embodiment of this application after forming a stacked structure with a hard mask in a direction perpendicular to the substrate;
[0050] Figure 3A A schematic longitudinal cross-section of a semiconductor device manufacturing method provided in an exemplary embodiment of this application, after trench formation, in a direction perpendicular to the substrate;
[0051] Figure 3B for Figure 3A The diagram shows a cross-sectional view of the structure parallel to the substrate.
[0052] Figure 4 A schematic longitudinal section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after forming a first groove, in a direction perpendicular to the substrate;
[0053] Figure 5 A schematic longitudinal cross-section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a first conductive layer, in a direction perpendicular to the substrate;
[0054] Figure 6 A schematic longitudinal section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a first common bit line, in a direction perpendicular to the substrate;
[0055] Figure 7 A schematic longitudinal cross-section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a protective layer, in a direction perpendicular to the substrate;
[0056] Figure 8 A schematic longitudinal section of a semiconductor device manufacturing method provided in an exemplary embodiment of this application, after removing the protective layer on the inner wall of a trench, in a direction perpendicular to the substrate;
[0057] Figure 9 A schematic longitudinal section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a second groove, in a direction perpendicular to the substrate;
[0058] Figure 10 A schematic longitudinal cross-section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a second conductive layer, in a direction perpendicular to the substrate;
[0059] Figure 11 A schematic longitudinal section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a second common bit line, in a direction perpendicular to the substrate;
[0060] Figure 12This is a schematic diagram of a longitudinal section of a semiconductor device obtained in an exemplary embodiment of this application, in a direction perpendicular to the substrate.
[0061] Figure 13 This is a schematic diagram of a longitudinal section of a semiconductor device in a direction perpendicular to the substrate, which is an exemplary embodiment of this application.
[0062] The meanings of the symbols in the attached diagram are as follows:
[0063] 10-Substrate; 11-Insulating layer; 12-First sacrificial layer; 13-Second sacrificial layer; 14-First conductive layer; 15-Protective layer; 16-Second conductive layer; 17-Isolation layer; 20-Trench; 21-First groove; 22-Second groove; HM-Hard mask; CBL1-First common bit line; CBL2-Second common bit line. Detailed Implementation
[0064] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.
[0065] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values shown in the drawings.
[0066] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the width-to-length ratio of the semiconductor pillars, the thickness of each film layer, and the spacing can be adjusted according to actual needs.
[0067] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.
[0068] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.
[0069] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0070] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.
[0071] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.
[0072] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0073] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.
[0074] In this application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced with "semiconductor film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".
[0075] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.
[0076] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functions or circuits are already distributed. The device involved in the inventive construction of the embodiments of this application is disposed on the main surface of the support structure.
[0077] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.
[0078] This application provides a method for manufacturing a semiconductor device. Figure 1 This is a process flow diagram of a semiconductor device manufacturing method according to an embodiment of this application. Figure 1 As shown, the manufacturing method includes:
[0079] A stacked structure consisting of multiple first sacrificial layers, multiple second sacrificial layers and multiple insulating layers is formed on a substrate, wherein there is a second sacrificial layer between two adjacent first sacrificial layers, a first sacrificial layer between two adjacent second sacrificial layers, and an insulating layer between the first sacrificial layer and the second sacrificial layer.
[0080] The stacked structure is etched along the direction toward the substrate to form trenches that penetrate the stacked structure;
[0081] The first sacrificial layer is etched laterally within the trench to form the first groove located on both sides of the trench.
[0082] A first common position line is formed within the first groove;
[0083] The second sacrificial layer is etched laterally within the trench to form a second groove located on both sides of the trench.
[0084] A second common bit line is formed within the second groove;
[0085] The lateral extension depth of the first groove in the first sacrificial layer is different from that of the second groove in the second sacrificial layer; the orthographic projection of the first common bit line on the substrate and the orthographic projection of the second common bit line on the substrate do not completely overlap.
[0086] The manufacturing method of this application embodiment arranges the first common bit line and the second common bit line alternately in a direction perpendicular to the substrate. The parasitic capacitance between the common bit lines is small, which can ensure that the semiconductor device can work normally with a smaller storage capacitance, thereby reducing the occupied area, and the manufacturing process is simple.
[0087] In some embodiments, the first common bit line is formed in the first groove before the second groove is formed.
[0088] In some embodiments, the lateral extension depth of the first groove within the first sacrificial layer is greater than the lateral extension depth of the second groove within the second sacrificial layer;
[0089] The formation of the first common bit line within the first groove includes:
[0090] A first conductive layer is deposited on the inner wall of the trench to fill the first groove;
[0091] The first conductive layer on the inner wall of the trench and part of the first conductive layer in the first groove are removed by etching, while the first conductive layer at the bottom of the first groove is retained, resulting in a plurality of first common bit lines located at the bottom of the first groove and spaced apart in a direction perpendicular to the substrate.
[0092] In some embodiments, the manufacturing method further includes: after forming the first common bit line, and before lateral etching the second sacrificial layer within the trench,
[0093] A protective layer covering the first common bit line is formed on the surface of the first common bit line.
[0094] In some embodiments, forming a protective layer covering the first common bit line on the surface of the first common bit line includes:
[0095] A protective layer is deposited on the inner wall of the trench to fill the first groove;
[0096] Remove the protective layer on the inner wall of the trench to expose the second sacrificial layer, and the first common bit line is covered by the remaining protective layer.
[0097] In some embodiments, forming a second common bit line within the second groove includes:
[0098] A second conductive layer is deposited on the inner wall of the trench to fill the second groove;
[0099] The second conductive layer on the inner wall of the trench is removed by etching, while the second conductive layer in the second groove is retained, resulting in a plurality of second common bit lines located in the second groove and spaced apart in a direction perpendicular to the substrate.
[0100] In some embodiments, the manufacturing method further includes: after forming the first common bit line and the second common bit line,
[0101] An isolation layer is filled in the trench to separate two adjacent first common bit lines located on the same horizontal plane parallel to the substrate, and to separate two adjacent second common bit lines located on the same horizontal plane parallel to the substrate.
[0102] In some embodiments, under the same etching conditions, the etching rates of the first sacrificial layer, the second sacrificial layer, and the insulating layer are all different.
[0103] In some embodiments, the insulating layer is a single-layer structure or a multi-layer structure. That is, the insulating layer can be a single-layer structure formed of an insulating material, or a multi-layer structure composed of multiple film layers formed of various different materials.
[0104] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.
[0105] Figure 2 A schematic longitudinal cross-section of a semiconductor device manufacturing method provided in an exemplary embodiment of this application after forming a stacked structure with a hard mask in a direction perpendicular to the substrate; Figure 3A A schematic longitudinal cross-section of a semiconductor device manufacturing method provided in an exemplary embodiment of this application, after trench formation, in a direction perpendicular to the substrate; Figure 3B for Figure 3A The diagram shows a cross-sectional view of the structure parallel to the substrate. Figure 4 A schematic longitudinal section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after forming a first groove, in a direction perpendicular to the substrate; Figure 5 A schematic longitudinal cross-section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a first conductive layer, in a direction perpendicular to the substrate; Figure 6 A schematic longitudinal section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a first common bit line, in a direction perpendicular to the substrate; Figure 7A schematic longitudinal cross-section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a protective layer, in a direction perpendicular to the substrate; Figure 8 A schematic longitudinal section of a semiconductor device manufacturing method provided in an exemplary embodiment of this application, after removing the protective layer on the inner wall of a trench, in a direction perpendicular to the substrate; Figure 9 A schematic longitudinal section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a second groove, in a direction perpendicular to the substrate; Figure 10 A schematic longitudinal cross-section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a second conductive layer, in a direction perpendicular to the substrate; Figure 11 A schematic longitudinal section of a semiconductor device manufacturing method provided for an exemplary embodiment of this application, after the formation of a second common bit line, in a direction perpendicular to the substrate; Figure 12 This is a schematic diagram of a longitudinal section of a semiconductor device obtained in an exemplary embodiment of this application, in the direction perpendicular to the substrate.
[0106] like Figures 2 to 12 As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.
[0107] S10: Sequentially deposit an insulating layer 11, a first sacrificial layer 12, another insulating layer 11, and a second sacrificial layer 13 on the substrate 10 to obtain a composite film layer composed of the insulating layer 11, the first sacrificial layer 12, the insulating layer 11, and the second sacrificial layer 13; continue depositing the composite film layer on the substrate 10 to obtain a stacked structure composed of multiple first sacrificial layers 12, multiple second sacrificial layers 13, and multiple insulating layers 11; form a hard mask HM on the surface of the stacked structure, such as... Figure 2 As shown.
[0108] exist Figure 2 In the middle, there is a second sacrificial layer 13 between two adjacent first sacrificial layers 12, a first sacrificial layer 12 between two adjacent second sacrificial layers 13, and an insulating layer 11 between the first sacrificial layer 12 and the second sacrificial layer 13.
[0109] Under the same etching conditions, the etching rates of the first sacrificial layer 12, the second sacrificial layer 13, and the insulating layer 11 are all different. For example, the materials of the first sacrificial layer 12, the second sacrificial layer 13, and the insulating layer 11 can be low-K dielectric materials, that is, dielectric materials with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon oxide (SiO2) or other silicon-containing films; they can also be polycrystalline silicon, aluminum oxide (e.g., Al2O3), etc. Exemplarily, the material of the first sacrificial layer 12 is silicon nitride, the material of the second sacrificial layer 13 is polycrystalline silicon, and the material of the insulating layer 11 is silicon oxide. In this embodiment, the insulating layer 11 is a single-layer structure formed of silicon oxide. In other embodiments, the insulating layer 11 can also be a multilayer structure composed of multiple films formed of various different materials.
[0110] For example only. Figure 2 The stacked structure shown includes two first sacrificial layers 12 and two second sacrificial layers 13. In other embodiments, the stacked structure may include more or fewer first sacrificial layers 12 and second sacrificial layers 13.
[0111] S20: Etch the stacked structure along the direction toward the substrate 10 to form a trench 20 penetrating the stacked structure, such as... Figure 3A and Figure 3B As shown. Among them, Figure 3B The cross-section shown passes through the insulating layer 11.
[0112] In some embodiments, the trench 20 may be formed by dry etching. The trench 20 may extend in a direction perpendicular to the substrate 10 and in a column direction parallel to the substrate 10.
[0113] In the description of this application, both the row direction and the column direction are horizontal directions parallel to the substrate, and the row direction intersects the column direction; for example, the row direction and the column direction are perpendicular to each other. Exemplarily, the row direction can be as follows: Figure 3B The column direction can be as shown in the X direction, where the column direction is as follows: Figure 3B Y direction shown.
[0114] S30: The first sacrificial layer 12 is laterally etched within the trench 20 to form the first grooves 21 located on both sides of the trench 20, such as... Figure 4 As shown.
[0115] The first groove 21 extends to a lateral depth H within the first sacrificial layer 12. In the description of this application, "lateral extension depth" refers to the extension length in a row direction parallel to the substrate.
[0116] The first groove 21 extends along the column direction. Exemplarily, the first groove 21 can be formed using wet etching.
[0117] S40: A first common bit line CBL1 (Common Bit Line 1) is formed within the first groove 21.
[0118] For example, step S40 may include:
[0119] S41: A first conductive layer 14 is deposited on the inner wall of the trench 20 to fill the first groove 21, such as... Figure 5 As shown;
[0120] S42: Etch away the first conductive layer 14 on the inner wall of the trench 20 and part of the first conductive layer 14 in the first groove 21, retaining the first conductive layer 14 at the bottom of the first groove 21, to obtain multiple first common bit lines CBL1 located at the bottom of the first groove 21 and spaced apart in a direction perpendicular to the substrate 10, such as... Figure 6 As shown.
[0121] For example, the first conductive layer can be deposited using an atomic layer deposition (ALD) process.
[0122] For example, the material of the first conductive layer can be selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The first conductive layer can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).
[0123] For example, a wet etching process can be used to remove part of the first conductive layer 14, and the etching amount of the first conductive layer in the first groove 21 can be determined according to the expected width of the first common bit line CBL1.
[0124] S50: A protective layer 15 is formed on the surface of the first common bit line CBL1 to cover the first common bit line CBL1.
[0125] For example, step S50 may include:
[0126] S51: A protective layer 15 is deposited on the inner wall of the trench 20 to fill the remaining space of the first groove 21, such as... Figure 7 As shown;
[0127] S52: Remove the protective layer 15 from the inner wall of the trench 20, exposing the second sacrificial layer 13. The first common bit line CBL1 is covered by the remaining protective layer 15, as shown. Figure 8 As shown.
[0128] The protective layer serves to protect the first common bit line CBL1 from etching damage in subsequent processes and from contact with the subsequently deposited conductive layer. The protective layer can be made of a low-K dielectric material, i.e., a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon oxide (SiO2) or other silicon-containing films. The material of the protective layer can be the same as or different from the material of the insulating layer; for example, both can be silicon oxide.
[0129] For example, the protective layer can be deposited using an ALD process.
[0130] For example, a wet etching process can be used to remove part of the protective layer.
[0131] S60: The second sacrificial layer 13 is laterally etched within the trench 20 to form second grooves 22 located on both sides of the trench 20, such as... Figure 9 As shown.
[0132] The second groove 22 extends laterally to a depth of h within the second sacrificial layer 13. For example... Figure 9 As shown, the lateral extension depth H of the first groove 21 in the first sacrificial layer 12 is greater than the lateral extension depth h of the second groove 22 in the second sacrificial layer 13.
[0133] The second groove 22 extends along the column direction. For example, the second groove 22 can be formed using wet etching.
[0134] S70: A second common bit line CBL2 (Common Bit Line 2) is formed within the second groove 22.
[0135] For example, step S70 may include:
[0136] S71: A second conductive layer 16 is deposited on the inner wall of the trench 20 to fill the second groove 22, such as... Figure 10 As shown;
[0137] S72: Etch away the second conductive layer 16 on the inner wall of the trench 20, retaining the second conductive layer 16 in the second groove 22, to obtain multiple second common bit lines CBL2 located in the second groove 22 and spaced apart in a direction perpendicular to the substrate 10, such as... Figure 11 As shown.
[0138] For example, the second conductive layer can be deposited using an ALD process.
[0139] For example, the material of the second conductive layer can be selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The material of the second conductive layer can be the same as or different from the material of the first conductive layer. The second conductive layer can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).
[0140] S80: Fill the trench 20 with an isolation layer 17, such as Figure 12 As shown.
[0141] The function of the isolation layer is to separate two adjacent first common bit lines CBL1 located on the same horizontal plane parallel to the substrate 10, and to separate two adjacent second common bit lines CBL2 located on the same horizontal plane parallel to the substrate 10.
[0142] In the embodiments of this application, as long as the lateral extension depth of the first groove 21 in the first sacrificial layer 12 is different from the lateral extension depth of the second groove 22 in the second sacrificial layer 13, the orthogonal projection of the first common bit line CBL1 on the substrate 10 and the orthogonal projection of the second common bit line CBL2 on the substrate 10 will not completely overlap.
[0143] In this embodiment, the lateral extension depth H of the first groove 21 in the first sacrificial layer 12 is greater than the lateral extension depth h of the second groove 22 in the second sacrificial layer 13. In other embodiments, the lateral extension depth H of the first groove 21 in the first sacrificial layer 12 may be less than the lateral extension depth h of the second groove 22 in the second sacrificial layer 13.
[0144] Moreover, the second groove and the second common bit line CBL2 can be formed first, and then the first groove and the first common bit line CBL1 can be formed.
[0145] This application also provides a semiconductor device. This semiconductor device can be obtained by the manufacturing method described above.
[0146] like Figure 12 As shown, the semiconductor device includes: multiple memory cells (not shown in the figure), multiple bit lines (not shown in the figure), multiple first common bit lines CBL1 and multiple second common bit lines CBL2;
[0147] Multiple memory cells are distributed in different layers, stacked along a direction perpendicular to the substrate 10, and periodically distributed;
[0148] Multiple bit lines are distributed in different layers, stacked and spaced apart along a direction perpendicular to the substrate 10; each bit line is connected to multiple memory cells located in the same layer;
[0149] Multiple first common bit lines CBL1 are stacked and spaced apart along a direction perpendicular to the substrate 10; the first common bit lines CBL1 extend along a column direction parallel to the substrate 10 and are connected to the bit lines of one of the two adjacent layers.
[0150] Multiple second common bit lines CBL2 are stacked and spaced apart along a direction perpendicular to the substrate 10; the second common bit lines CBL2 extend along the column direction and are connected to the bit lines of another layer located in two adjacent layers;
[0151] The first common bit line CBL1 and the second common bit line CBL2 are alternately distributed in a direction perpendicular to the substrate 10, and the orthogonal projection of the first common bit line CBL1 on the substrate 10 and the orthogonal projection of the second common bit line CBL2 on the substrate 10 do not completely overlap.
[0152] In some embodiments, such as Figure 12 As shown, the orthographic projection of the first common bit line CBL1 on the substrate 10 and the orthographic projection of the second common bit line CBL2 on the substrate 10 do not overlap.
[0153] Figure 13 This is a schematic longitudinal cross-sectional view of another semiconductor device in a direction perpendicular to the substrate, which is an exemplary embodiment of this application. Figure 13 As shown, the orthographic projection of the first common bit line CBL1 on the substrate 10 and the orthographic projection of the second common bit line CBL2 on the substrate 10 have a partially overlapping area.
[0154] In some embodiments, such as Figure 12 and Figure 13 As shown, an insulating layer 11 is provided between the first common bit line CBL1 and the second common bit line CBL2, which are adjacent in a direction perpendicular to the substrate 10. The insulating layer 11 is a single-layer structure or a multi-layer structure.
[0155] In some embodiments, such as Figure 12 and Figure 13 As shown, the semiconductor device further includes a plurality of first sacrificial layers 12, a plurality of second sacrificial layers 13 and a plurality of insulating layers 11 stacked on the substrate 10; there is a second sacrificial layer 13 between two adjacent first sacrificial layers 12, a first sacrificial layer 12 between two adjacent second sacrificial layers 13, and an insulating layer 11 between the first sacrificial layer 12 and the second sacrificial layer 13.
[0156] The first common bit line CBL1 is located in the first sacrificial layer 12, and the second common bit line CBL2 is located in the second sacrificial layer 13.
[0157] In some embodiments, the memory cell includes a transistor, the transistor including a semiconductor layer, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode; the semiconductor layer extends in a direction perpendicular to the substrate 10 and at least partially surrounds the gate electrode;
[0158] The bit line extends along a row direction parallel to the substrate 10 and is connected to the transistor;
[0159] The semiconductor device also includes multiple word lines extending along a direction perpendicular to the substrate 10, the word lines penetrating multiple layers of the memory cells.
[0160] In this application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized, but only its function is emphasized.
[0161] For example, the material of the semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.
[0162] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.
[0163] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.
[0164] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.
[0165] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.
[0166] For example, the material of the bit line can be selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).
[0167] In some embodiments, the electrode material of the gate electrode can be any one or more of the following different types of materials:
[0168] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.
[0169] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.
[0170] Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.
[0171] In some embodiments, the gate insulating layer may comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.
[0172] Low-K materials, such as silicon oxide.
[0173] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.
[0174] In some embodiments, the semiconductor device can be a 3D memory, such as a 3D DRAM. The 3D memory can be a 1T1C or 2T1C structure, or a 1T0C or 2T0C structure (containing read transistors and write transistors).
[0175] This application also provides an electronic device, including a semiconductor device manufactured by the manufacturing method described above, or including a semiconductor device as described above.
[0176] In some embodiments, the electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0177] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure consisting of multiple first sacrificial layers, multiple second sacrificial layers and multiple insulating layers is formed on a substrate, wherein there is a second sacrificial layer between two adjacent first sacrificial layers, a first sacrificial layer between two adjacent second sacrificial layers, and an insulating layer between the first sacrificial layer and the second sacrificial layer. The stacked structure is etched along the direction toward the substrate to form a trench through the stacked structure; The first sacrificial layer is laterally etched within the trench to form a first groove located on both sides of the trench. A first common bit line is formed within the first groove; The second sacrificial layer is laterally etched within the trench to form a second groove located on both sides of the trench; A second common bit line is formed within the second groove; Wherein, the lateral extension depth of the first groove in the first sacrificial layer is different from the lateral extension depth of the second groove in the second sacrificial layer; the orthographic projection of the first common bit line on the substrate and the orthographic projection of the second common bit line on the substrate do not completely overlap.
2. The manufacturing method according to claim 1, characterized in that, Before forming the second groove, the first common bit line is formed within the first groove.
3. The manufacturing method according to claim 2, characterized in that, The lateral extension depth of the first groove within the first sacrificial layer is greater than the lateral extension depth of the second groove within the second sacrificial layer; The formation of the first common bit line within the first groove includes: A first conductive layer is deposited on the inner wall of the trench to fill the first groove; The first conductive layer on the inner wall of the trench and part of the first conductive layer in the first groove are removed by etching, while the first conductive layer at the bottom of the first groove is retained, resulting in a plurality of first common bit lines located at the bottom of the first groove and spaced apart in a direction perpendicular to the substrate.
4. The manufacturing method according to claim 3, characterized in that, Also includes: After the first common bit line is formed, and before the second sacrificial layer is laterally etched within the trench, A protective layer covering the first common bit line is formed on the surface of the first common bit line.
5. The manufacturing method according to claim 4, characterized in that, The step of forming a protective layer covering the first common bit line on the surface of the first common bit line includes: A protective layer is deposited on the inner wall of the trench to fill the first groove; Remove the protective layer on the inner wall of the trench to expose the second sacrificial layer, and the first common bit line is covered by the remaining protective layer.
6. The manufacturing method according to claim 4, characterized in that, The formation of the second common bit line within the second groove includes: A second conductive layer is deposited on the inner wall of the trench to fill the second groove; The second conductive layer on the inner wall of the trench is removed by etching, while the second conductive layer in the second groove is retained, resulting in a plurality of second common bit lines located in the second groove and spaced apart in a direction perpendicular to the substrate.
7. The manufacturing method according to any one of claims 1 to 6, characterized in that, Also includes: After the first common bit line and the second common bit line are formed An isolation layer is filled in the trench to separate two adjacent first common bit lines located on the same horizontal plane parallel to the substrate, and to separate two adjacent second common bit lines located on the same horizontal plane parallel to the substrate.
8. The manufacturing method according to any one of claims 1 to 6, characterized in that, Under the same etching conditions, the etching rates of the first sacrificial layer, the second sacrificial layer, and the insulating layer are all different.
9. The manufacturing method according to any one of claims 1 to 6, characterized in that, The insulating layer can be a single-layer structure or a multi-layer structure.
10. A semiconductor device, characterized in that, include: Multiple memory cells are distributed across different layers, stacked along a direction perpendicular to the substrate, and periodically distributed. Multiple bit lines are distributed in different layers, stacked and spaced apart along a direction perpendicular to the substrate; each bit line is connected to multiple memory cells located in the same layer; Multiple first common bit lines are stacked and spaced apart along a direction perpendicular to the substrate; the first common bit lines extend along a column direction parallel to the substrate and are connected to the bit lines of one of the two adjacent layers. Multiple second common bit lines are stacked and spaced apart along a direction perpendicular to the substrate; the second common bit lines extend along the column direction and are connected to bit lines in another layer located in two adjacent layers; The first common bit line and the second common bit line are alternately distributed in a direction perpendicular to the substrate, and the orthographic projection of the first common bit line on the substrate and the orthographic projection of the second common bit line on the substrate do not completely overlap.
11. The semiconductor device according to claim 10, characterized in that, The orthographic projection of the first common bit line onto the substrate and the orthographic projection of the second common bit line onto the substrate do not overlap.
12. The semiconductor device according to claim 10 or 11, characterized in that, An insulating layer is provided between adjacent first common bit lines and second common bit lines in a direction perpendicular to the substrate. The insulating layer may be a single-layer structure or a multi-layer structure.
13. The semiconductor device according to claim 10 or 11, characterized in that, It also includes a plurality of first sacrificial layers, a plurality of second sacrificial layers and a plurality of insulating layers stacked on the substrate; there is a second sacrificial layer between two adjacent first sacrificial layers, a first sacrificial layer between two adjacent second sacrificial layers, and the insulating layer between the first sacrificial layer and the second sacrificial layer; The first common bit line is located in the first sacrificial layer, and the second common bit line is located in the second sacrificial layer.
14. The semiconductor device according to claim 10 or 11, characterized in that, The memory cell includes a transistor, the transistor including a semiconductor layer, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode; The semiconductor layer extends along a direction perpendicular to the substrate and at least partially surrounds the gate electrode; The bit line extends along a row direction parallel to the substrate and is connected to the transistor; The semiconductor device further includes multiple word lines extending along a direction perpendicular to the substrate, the word lines penetrating multiple layers of the memory cells.
15. An electronic device, characterized in that, It includes semiconductor devices manufactured by the manufacturing method according to any one of claims 1 to 9, or semiconductor devices according to any one of claims 10 to 14.