Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. The semiconductor memory device includes: a gate stack structure including interlayer insulating layers and conductive patterns alternately stacked on a substrate in a vertical direction; a plurality of channel structures penetrating the gate stack structure, one end of each of the plurality of channel structures protruding beyond a boundary of the gate stack structure; and a source layer formed on the gate stack structure. A protruding end of each of the plurality of channel structures extends into the source layer. A protruding end portion of each of the plurality of channel structures has a flat cross-section.

Description

[0001] This application is a divisional application of the original invention patent application No. 202210034893.6 (filed on January 13, 2022, entitled "Semiconductor Memory Device and Method for Manufacturing the Same"). Technical Field

[0002] This disclosure generally relates to electronic devices, and more specifically, to a semiconductor memory device having a vertical channel structure and a method for manufacturing the same. Background Technology

[0003] The recent paradigm shift in computing environments has led to ubiquitous computing environments where computing systems can be used anytime, anywhere. This has spurred the increasing use of portable electronic devices such as mobile phones, digital cameras, and laptops. These portable electronic devices typically include memory systems that utilize semiconductor memory devices, i.e., data storage devices. Data storage devices serve as either the main memory or auxiliary memory devices in portable electronic devices.

[0004] Because they lack mechanical drive components, data storage devices using semiconductor memory offer excellent stability and durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, solid-state drives (SSDs), and so on.

[0005] Semiconductor memory devices are generally classified into volatile memory devices and non-volatile memory devices.

[0006] Non-volatile memory devices have relatively slow write and read speeds, but retain stored data even when power is interrupted. Therefore, non-volatile memory devices are used to store data that must be retained regardless of power supply. Examples of non-volatile memory include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is classified into NOR flash memory and NAND flash memory. Summary of the Invention

[0007] According to one aspect of this disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a gate stack structure including an interlayer insulating layer and a conductive pattern alternately stacked on a substrate in a vertical direction; a plurality of channel structures penetrating the gate stack structure, each of the plurality of channel structures having an end protruding beyond a boundary of the gate stack structure; and a source layer formed on the gate stack structure, wherein the protruding end of each of the plurality of channel structures extends into the source layer, and wherein the protruding end of each of the plurality of channel structures has a flat cross-section.

[0008] According to another aspect of this disclosure, a method for manufacturing a semiconductor memory device is provided, the method comprising the steps of: forming a memory cell array on a first substrate, wherein the memory cell array includes: a gate stack structure having interlayer insulating layers and conductive patterns alternately stacked in a vertical direction; a plurality of channel structures penetrating the gate stack structure, each of the plurality of channel structures having an end extending into the first substrate; and a memory layer extending from between the plurality of channel structures and the gate stack structure to the end of each of the plurality of channel structures and the first substrate; removing the first substrate to expose the memory layer; forming a first source layer on top of the entire structure including the memory layer; performing an etching process to expose the memory layer, the channel structures and the first source layer and leveling the memory layer, the channel structures and the first source layer to the same height; and forming a second source layer on the memory layer, the channel structures and the first source layer.

[0009] According to another aspect of this disclosure, a method for manufacturing a semiconductor memory device is provided, the method comprising the steps of: forming a memory cell array on a first substrate, wherein the memory cell array includes: a gate stack structure having interlayer insulating layers and conductive patterns alternately stacked in a vertical direction; a plurality of channel structures penetrating the gate stack structure, each of the plurality of channel structures having an end extending into the first substrate; and a memory layer extending from between the plurality of channel structures and the gate stack structure to the end of each of the plurality of channel structures and the first substrate; forming a bit line connected to the memory cell array; removing the first substrate to expose the memory layer; forming a first source layer on top of the entire structure including the memory layer; etching the first source layer, the memory layer, and the end of each of the plurality of channel structures by performing a chemical mechanical planarization (CMP) process; and forming a second source layer on top of the entire structure including the planarized first source layer, the memory layer, and the end of each of the plurality of channel structures. Attached Figure Description

[0010] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0011] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between those two elements, or there may be one or more intermediate elements. Similar reference numerals always indicate similar elements.

[0012] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 The circuit diagram shown is for a memory cell array.

[0014] Figure 3 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 4 It is shown Figure 1 The diagram shows a cross-sectional view of the memory cell array.

[0016] Figures 5A to 5F , Figure 6 , Figure 7 and Figures 8A to 8D This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 9 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0018] Figure 10 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0019] The specific structural or functional descriptions disclosed herein are merely illustrative in order to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0020] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement the technical spirit of the present disclosure.

[0021] The embodiments provide a semiconductor memory device and a method for manufacturing the semiconductor memory device that can suppress pattern defects in a process of connecting a channel layer and a source layer having a vertical channel structure to each other.

[0022] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0023] Reference Figure 1 The semiconductor memory device 10 may include peripheral circuitry PC and memory cell array 20.

[0024] The peripheral circuit PC can be configured to control programming operations that store data in the memory cell array 20, reading operations that output data stored in the memory cell array 20, and erasing operations that erase data stored in the memory cell array 20.

[0025] In an implementation, the peripheral circuit PC may include a voltage generator 31, a line decoder 33, a control circuit 35, and a page buffer group 37.

[0026] The memory cell array 20 may include multiple memory blocks. The memory cell array 20 is connected to the row decoder 33 via word line WL and to the page buffer group 37 via bit line BL.

[0027] Control circuit 35 can control voltage generator 31, line decoder 33 and page buffer group 37 in response to command CMD and address ADD.

[0028] Voltage generator 31 can generate various operating voltages (e.g., erase voltage, ground voltage, programming voltage, verification voltage, pass voltage, and read voltage) for programming, reading, and erasing operations based on control circuit 35.

[0029] The row decoder 33 can select a memory block based on the control circuit 35. The row decoder 33 can apply an operating voltage to the word line WL connected to the selected memory block.

[0030] Page buffer group 37 can be connected to memory cell array 20 via bit line BL. During programming operations, page buffer group 37 can temporarily store data received from input / output circuitry (not shown) based on control circuitry 35. During read or verification operations, page buffer group 37 can sense the voltage or current of bit line BL based on control circuitry 35. Page buffer group 37 can select bit line BL based on control circuitry 35.

[0031] Structurally, the memory cell array 20 may overlap with a portion of the peripheral circuit PC.

[0032] Figure 2 It is shown Figure 1The circuit diagram shown is for a memory cell array.

[0033] Reference Figure 2 The memory cell array 20 may include multiple cell strings CS1 and CS2 connected between the source line SL and multiple bit lines BL. The multiple cell strings CS1 and CS2 may be connected together to multiple word lines WL1 to WLn.

[0034] Each of the multiple cell strings CS1 and CS2 may include at least one source selection transistor SST connected to the source line SL, at least one drain selection transistor DST connected to the bit line BL, and multiple memory cells MC1 to MCn connected in series between the source selection transistor SST and the drain selection transistor DST.

[0035] The gates of multiple memory cells MC1 to MCn can be connected to multiple word lines WL1 to WLn stacked and spaced apart from each other. Two or more drain select lines DSL1 and DSL2 can be spaced apart from each other at the same height.

[0036] The gate of the source-select transistor SST can be connected to the source-select line SSL. The gate of the drain-select transistor DST can be connected to the drain-select line corresponding to the gate of the drain-select transistor DST.

[0037] The source line SL can be connected to the source of the source select transistor SST. The drain of the drain select transistor DST can be connected to the bit line corresponding to the drain of the drain select transistor DST.

[0038] Multiple unit strings CS1 and CS2 can be divided into string groups connected to two or more drain select lines DSL1 and DSL2 respectively. Unit strings connected to the same word line and the same bit line can be independently controlled by different drain select lines. In addition, unit strings connected to the same drain select line can be independently controlled by different bit lines.

[0039] In this implementation, two or more drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL2. Multiple unit strings CS1 and CS2 may include a first unit string CS1 connected to a first unit string group of the first drain select line DSL1 and a second unit string CS2 connected to a second unit string group of the second drain select line DSL2.

[0040] Figure 3 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0041] Reference Figure 3 The semiconductor memory device 10 may include peripheral circuitry disposed on a substrate SBU and a gate stack structure GST overlapping with the peripheral circuitry PC.

[0042] Each gate stack-up structure (GST) may include a source select line (SSL), multiple word lines (WL1 to WLn), and two or more drain select lines (DSL1 and DSL2) isolated from each other at the same height by an isolation structure (DSM).

[0043] The source select line SSL and multiple word lines WL1 to WLn can extend in a first direction X and a second direction Y and can be formed into a flat plate shape parallel to the top surface of the substrate SUB. The first direction X can be the direction facing the X-axis in the XYZ coordinate system, and the second direction Y can be the direction facing the Y-axis in the XYZ coordinate system.

[0044] Multiple word lines WL1 to WLn can be stacked on a third direction Z to be spaced apart from each other. The third direction Z can be the direction in which the Z-axis faces in the XYZ coordinate system. Multiple word lines WL1 to WLn can be set between two or more drain select lines DSL1 and DSL2 and source select line SSL.

[0045] The gate stack structure GST can be isolated from each other through slit SI. The isolation structure DSM can be formed to be shorter than slit SI in the third direction Z and can overlap with multiple word lines WL1 to WLn.

[0046] Each of the isolation structure DSM and the slit SI can extend in a linear shape, a zigzag shape, or a wavy shape. The width of each of the isolation structure DSM and the slit SI can be varied according to different design rules.

[0047] According to the implementation, the source select line SSL can be set closer to the peripheral circuit PC than two or more drain select lines DSL1 and DSL2.

[0048] The semiconductor memory device 10 may include a source line SL disposed between a gate stack structure GST and a peripheral circuit PC, and multiple bit lines BL spaced further away from the peripheral circuit PC than the source line SL. The gate stack structure GST may be disposed between the multiple bit lines BL and the source line SL.

[0049] Figure 4 It is shown Figure 1 The diagram shows a cross-sectional view of the memory cell array.

[0050] Reference Figure 4 In a memory cell array, the lower structure U and the upper structure T can be attached to each other, and the serial structure STL_S can be placed on top of the upper structure T.

[0051] The upper structure T may include a gate stack structure GST isolated by a slit SI, a channel structure CH penetrating the gate stack structure GST, a memory layer ML extending along the sidewalls of each channel structure CH, and a bit line 41 and a first connection structure C1 disposed below the gate stack structure GST.

[0052] A gate stack structure (GST) may include interlayer insulating layers (ILDs) and conductive patterns CP1 to CPn alternately stacked in a vertical direction. Each of the conductive patterns CP1 to CPn may include various conductive materials, including doped silicon layers, metal layers, metal silicide layers, and barrier layers. Each of the conductive patterns CP1 to CPn may include two or more types of conductive materials. For example, each of the conductive patterns CP1 to CPn may include tungsten and a titanium nitride (TiN) layer surrounding the surface of the tungsten. Tungsten is a low-resistance metal and reduces the resistance of the conductive patterns CP1 to CPn. The titanium nitride (TiN) layer acts as a barrier layer and prevents direct contact between the tungsten and the interlayer insulating layer (ILD).

[0053] The first conductive pattern CP1, adjacent to bit line 41 among conductive patterns CP1 to CPn, can be used as a drain select line DSL. In another embodiment, two or more conductive patterns adjacent to and continuously stacked with bit line 41 can be used as drain select lines. The nth conductive pattern CPn, adjacent to the first source layer SL1 and the second source layer SL2 among conductive patterns CP1 to CPn, can be used as a source select line SSL. In another embodiment, two or more conductive patterns adjacent to and continuously stacked with the first source layer SL1 and the second source layer SL2 can be used as source select lines. Conductive patterns (e.g., CP2 to CPn-1) that are vertically adjacent to each other and disposed between the drain select line and the source select line can be used as referenced above. Figure 2 The word lines described are WL1 to WLn.

[0054] The channel structure CH can penetrate the gate stack structure GST in the vertical direction, and one end of the channel structure CH can be formed to protrude further than the gate stack structure GST. The channel structure CH can be formed as a hollow type. The channel structure CH may include a core insulating layer 11 filling its central region, a doped semiconductor layer 13 located at the lower end of the core insulating layer 11, and a channel layer 15 surrounding the surfaces of the core insulating layer 11 and the doped semiconductor layer 13. The channel layer 15 can be used as the channel region of the corresponding cell string. The channel layer 15 can be formed of a semiconductor material. In an embodiment, the channel layer 15 may include a silicon layer. The channel structure CH can be formed to protrude further than the interlayer insulating layer ILD disposed at the uppermost part of the gate stack structure GST. The protruding end (i.e., the core insulating layer 11 and the channel layer 15 of the channel structure CH) can be formed to penetrate the first source layer SL1 and directly connect to the second source layer SL2. The core insulating layer 11 and the channel layer 15 protruding further than the gate stack structure GST can extend to the same height.

[0055] The memory layer ML can be formed as a surface surrounding the channel structure CH. The memory layer ML may include a tunnel insulating layer TI surrounding the channel layer of the channel structure CH, a data storage layer DS surrounding the tunnel insulating layer TI, and a barrier insulating layer BI surrounding the data storage layer DS. The memory layer ML can be formed to have the same length as the channel structure CH in the vertical direction. The memory layer ML can be formed to protrude further than the interlayer insulating layer ILD disposed at the top of the gate stack structure GST. The protruding end of the memory layer ML can be formed to penetrate the first source layer SL1 and directly connect to the second source layer SL2. The core insulating layer 11, the channel layer 15, and the memory layer ML, which protrude further than the gate stack structure GST, can extend to the same height. The memory layer ML can be defined as a component included in the channel structure CH. In other words, the core insulating layer 11, the channel layer 15, and the memory layer ML, which protrude further than the gate stack structure GST, can have a flat end at the top of the channel structure CH.

[0056] Bit line 41 may be disposed below the gate stack structure GST. Bit line 41 may be connected to the channel structure CH via contact plugs 31 that penetrate multiple insulating layers 21, 25 and 27. Bit line 41 may be spaced from the substrate SUB via a first insulating structure 51 and a second insulating structure 81.

[0057] The first connection structure 1st_CS may include a first insulating structure 51 and a first connection structure C1 formed in the first insulating structure 51. The first connection structure C1 may include various conductive patterns 63, 65 and 67. The first insulating structure 51 may include two or more insulating layers 51A to 51D stacked between the bit line 41 and the second insulating structure 81.

[0058] The lower structure U may include a CMOS circuit structure CMOS having multiple transistors TR and a component isolation layer ISO formed on a substrate SUB, and may include a second connection structure 2nd_CS formed on the CMOS circuit structure CMOS. The component isolation layer ISO may include an insulating material buried in the substrate SUB.

[0059] The second connection structure 2nd_CS may include a second insulating structure 81 formed on the substrate SUB and a second connection structure C2 formed in the second insulating structure 81. Each second connection structure C2 may include various conductive patterns 83, 85, 87, 89 and 91 buried in the second insulating structure 81. The second insulating structure 81 may include two or more insulating layers 81A to 81D stacked sequentially.

[0060] The upper structure T and the lower structure U may have a structure in which the upper structure T is adhered to the lower structure U by a bonding process. For example, the exposed conductive pattern 67 of the first connecting structure 1st_CS of the upper structure T and the exposed conductive pattern 91 of the second connecting structure 2nd_CS of the lower structure U may be arranged to face each other and adhere to each other. The conductive pattern 67 and the conductive pattern 91 may be defined as bonding metals.

[0061] The serial line structure STL_S may be disposed on the upper structure T. The serial line structure STL_S may be disposed on top of the gate stack structure GST. The serial line structure STL_S may include a first source layer SL1 and a second source layer SL2 that contact a channel structure CH that protrudes further than the gate stack structure GST, an insulating layer 93 disposed on top of the second source layer SL2, an upper line 99, and at least one contact plug CT that penetrates the insulating layer 93 to connect the second source layer SL2 to the upper line 99.

[0062] The contact plug CT may include a contact conductive layer 95 and a diffusion barrier 97 surrounding the sidewalls of the contact conductive layer 95. Each contact plug CT electrically connects a conductive layer 95 and an upper wire 99 to each other.

[0063] The first source layer SL1 and the second source layer SL2, the contact plug CT, and the upper line 99 can be used as Figure 2 The source line SL is shown.

[0064] Figures 5A to 5F , Figure 6 , Figure 7 and Figures 8A to 8D This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0065] Figures 5A to 5F This is a cross-sectional view showing the process of forming a memory cell array, a first linear array, and a first interconnection structure on a first substrate.

[0066] Reference Figure 5A The first material layer 111 and the second material layer 113 can be alternately stacked on the first substrate 101.

[0067] The first substrate 101 may be formed of a material with an etching rate different from that of the first material layer 111 and the second material layer 113. For example, the substrate 101 may include silicon.

[0068] In an embodiment, the first material layer 111 may be a reference layer. Figure 4 The interlayer insulating layer (ILD) described is formed of an insulating material. The second material layer 113 may be formed of a material with an etch rate different from that of the first material layer 111. For example, the first material layer 111 may comprise silicon oxide, and the second material layer 113 may comprise silicon nitride. The following figures illustrate an embodiment where the first material layer 111 is formed of an insulating material and the second material layer 113 is formed as a sacrificial layer, but this disclosure is not limited thereto. The properties of the first material layer 111 and the second material layer 113 may be varied. For example, the first material layer 111 may be formed of a material used for reference above. Figure 4 The interlayer insulation layer (ILD) described is formed of insulating material, and the second material layer 113 may be made of the material used for the above reference. Figure 4 The conductive material forming the described conductive patterns CP1 to CPn.

[0069] Reference Figure 5B A first mask pattern 121 with a first opening 125 can be formed on the stacked structure of the first material layer 111 and the second material layer 113. Subsequently, a channel hole 115 penetrating the first material layer 111 and the second material layer 113 can be formed through the first opening 125 of the first mask pattern 121. The channel hole 115 can extend to a certain depth in the substrate 101. Depending on the etching material used to form the channel hole 115, the channel hole 115 can be formed in various shapes.

[0070] In one embodiment, a first etching material can be used to form the channel hole 115. The etching rate of the first material layer 111 and the second material layer 113 relative to the first etching material can be faster than the etching rate of the first substrate 101 relative to the first etching material. As a result, the width of the end of the channel hole 115 extending into the first substrate 101 can be formed to be narrower than the width of the end of the channel hole 115 penetrating the first material layer 111 and the second material layer 113.

[0071] Reference Figure 5C A memory layer 137 and a channel structure 147 may be formed in the channel hole 115. The sidewalls and ends of the channel structure 147 extending into the first substrate 101 may be surrounded by the memory layer 137.

[0072] The process of forming the memory layer 137 may include sequentially stacking a barrier insulating layer 135, a data storage layer 133, and a tunnel insulating layer 131 on the surfaces of each via 115. The barrier insulating layer 135, the data storage layer 133, and the tunnel insulating layer 131 may include those described above. Figure 4 The barrier insulating layer BI, data storage layer DS, and tunnel insulating layer TI are made of the same material. The memory layer 137 may be formed in a pad shape, and the central region of each channel hole 115 may be defined by the memory layer 137.

[0073] Subsequently, a channel structure 147 can be formed by forming a channel layer 141 on the surface of the memory layer 137. The channel layer 141 may include a semiconductor layer serving as a channel region. For example, the channel layer 141 may include silicon.

[0074] In one embodiment, the channel layer 141 may be formed in a pad shape, and the central region of each channel hole 115 may include a portion not filled by the channel layer 141. When the channel layer 141 is formed in a pad shape, the process of forming the channel structure 147 may include a process of filling the central region of each channel hole on the channel layer 141 with a core insulating layer 143, a process of defining a recessed region at a portion of the central region of each channel hole 115 by etching a portion of the core insulating layer 143, and a process of filling the recessed region with a doped semiconductor layer 145. The core insulating layer 143 may include an oxide, and the doped semiconductor layer 145 may include a conductive dopant. The conductive dopant may include an n-type dopant for a junction. The conductive dopant may include an anti-doped p-type dopant.

[0075] In another embodiment, the channel layer 141 may be formed to fill the central region of each channel via 115, and the core insulating layer 143 and the doped semiconductor layer 145 may be omitted. When the core insulating layer 143 and the doped semiconductor layer 145 are omitted, the process of forming the channel structure 147 may further include a process of doping a conductive dopant into the channel layer 141.

[0076] Reference Figure 5D , can Figure 5C After the first mask pattern 121 shown is removed, a first insulating layer 151 is formed.

[0077] Subsequently, a slit 153 can be formed. The slit 153 can penetrate the first insulating layer 151 and the laminated structure of the first material layer 111 and the second material layer 113. The slit 153 can correspond to... Figure 4 The slit SI is shown. Subsequently, a horizontal space 155 can be defined by selectively removing the second material layer 113 exposed through the slit 153. The horizontal space 155 can be defined between first material layers 111 that are adjacent to each other in the vertical direction.

[0078] Reference Figure 5E The third material layer 157 is used to fill the slits 153 respectively. Figure 5D The horizontal space 155 is shown. The third material layer 157 can be referenced above. Figure 4 The conductive patterns CP1 to CPn are described. A third material layer 157 may fill the horizontal space 155 to surround the channel structure 147 and the memory layer 137.

[0079] As described above, a gate stack structure 150 can be formed on the first substrate 101 by replacing the second material layer 113, which serves as a sacrificial layer, with a third material layer 157 serving as a conductive pattern. The gate stack structure 150 may include a structure in which a first material layer 111, serving as an interlayer insulating layer, and a third material layer 157, serving as a conductive pattern, are alternately stacked. The gate stack structure 150 can be penetrated by a channel structure 147, and the channel structure 147 can extend into the first substrate 101. A memory layer 137 may surround the channel structure 147, thereby providing barriers between the channel structure 147 and the gate stack structure 150, and between the channel structure 147 and the first substrate 101.

[0080] Based on the above reference Figures 5A to 5E The described process can be used to form the above reference on the first substrate 101. Figure 3 The description describes a memory block having multiple cell strings CS1 and CS2. Each cell string may include a drain-select transistor DST connected in series and memory cells MC1 to MCn. (Refer to above) Figure 3 The described drain-select transistor DST and memory cells MC1 to MCn define the intersection of the channel structure 147 and the third material layer 157 as follows: Figure 5E The conductive pattern shown can be connected in series via the channel structure 147.

[0081] Subsequently, a sidewall insulating layer 161 may be formed to cover the sidewalls of the gate stack structure 150. Subsequently, a second insulating layer 163 may be formed to fill the slit 153 and extend to cover the sidewall insulating layer 161 and the first insulating layer 151.

[0082] Reference Figure 5F A third insulating layer 171 may be formed on the second insulating layer 163. Subsequently, a contact plug 173 may be formed, thereby penetrating the third insulating layer 171 or penetrating both the third insulating layer 171 and the second insulating layer 163. The contact plug 173 may extend to contact the channel structure 147.

[0083] Subsequently, a first linear array 175 may be formed. The first linear array 175 may be bit lines connected to contact plugs 173. Subsequently, a first insulating structure 181 covering the first linear array 175 may be formed. The first insulating structure 181 may include two or more insulating layers 181A to 181D. First connection structures 185, 189, 191, and 193 may be embedded in the first insulating structure 181. The first connection structures 185, 189, 191, and 193 may be electrically connected to each other via contact plugs (not shown).

[0084] The first connection structures 185, 189, 191 and 193 may include a first bonding metal 193 having a surface exposed to the outside of the first insulating structure 181.

[0085] Figure 6 This is a cross-sectional view showing the process of forming a CMOS circuit and a second connection structure on a second substrate.

[0086] Reference Figure 6 It may include a process for forming multiple transistors 200 that constitute a complementary metal-oxide-semiconductor (CMOS) circuit.

[0087] The second substrate 201 may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth process.

[0088] Each transistor 200 may be formed in an active region of the second substrate 201 separated by an isolation layer 203. Each transistor 200 may include a gate insulating layer 207 and a gate electrode 209 stacked on the corresponding active region, and junctions 205a and 205b formed in the active regions on both sides of the gate electrode 209. Junctions 205a and 205b may include conductivity type dopants for implementing the corresponding transistors. Junctions 205a and 205b may include at least one of n-type dopants and p-type dopants.

[0089] After forming a plurality of transistors 200, a second connection structure 220 and a second insulating structure 211 may be formed. The second connection structure 220 may be connected to the transistors 200 constituting a CMOS circuit, and the second insulating structure 211 may cover the second connection structure 220 and the transistors 200.

[0090] The second insulating structure 211 may include two or more insulating layers 211A to 211D. The second connection structure 220 may be embedded in the second insulating structure 211. Each second connection structure 220 may include multiple conductive patterns 213, 215, 217, 219, 221, and 223. The second insulating structure 211 and the second connection structure 220 are not limited to the examples shown in the figures, but may be varied.

[0091] The conductive patterns 213, 215, 217, 219, 221 and 223 included in the respective second connection structures 220 may include a second bonding metal 223 having a surface exposed to the outside.

[0092] Figure 7 It is a cross-sectional view showing the process that allows the first connecting structure and the second connecting structure to adhere to each other.

[0093] Reference Figure 7 The first substrate 101 and the second substrate 201 can be aligned such that the first bonding metal 193 on the first substrate 101 and the second bonding metal 223 on the second substrate 201 can contact each other. The first bonding metal 193 and the second bonding metal 223 can include various metals, including, for example, copper.

[0094] Subsequently, the first bonding metal 193 and the second bonding metal 223 can adhere to each other. For this purpose, the first bonding metal 193 and the second bonding metal 223 can be cured after heat is applied to them. However, this disclosure is not limited thereto, and various processes for joining the first bonding metal 193 and the second bonding metal 223 to each other can be introduced.

[0095] Figures 8A to 8D This is a cross-sectional view showing the process of forming a string line connected to multiple cell strings on the gate stack structure 150.

[0096] Reference Figure 8A It can remove Figure 7 The first substrate 101 is shown. When the first substrate 101 is removed, the memory layer 137 can be used as an etch stop layer. Therefore, the channel layer 141, which protrudes further than the gate stack structure 150, can be protected by the memory layer 137.

[0097] Subsequently, boron can be implanted into the channel layer 14, which serves as the channel for the source selection transistor, by performing an ion implantation process. Therefore, the threshold voltage of the source selection transistor can be adjusted.

[0098] Reference Figure 8B A first source layer 301 can be formed on the gate stack 150 to cover the memory layer 137 that protrudes further than the gate stack 150. The first source layer 301 can be formed as a polysilicon layer doped with N-type impurities.

[0099] Subsequently, an etching process can be performed to expose the core insulating layer 143. Chemical mechanical planarization (CMP) is preferably used to perform the etching process. In the etching process exposing the core insulating layer 143, the ends of the memory layer 137 can be etched to have a uniform height. As a result of performing the etching process using CMP, the upper surfaces of the first source layer 301, the memory layer 137, the channel layer 141, and the core insulating layer 143 can have a uniform height.

[0100] Reference Figure 8C A second source layer 302 may be formed on top of the first source layer 301, the memory layer 137, the channel layer 141, and the core insulating layer 143. The second source layer 302 may be formed as a polysilicon layer doped with N-type impurities. The second source layer 302 may be in direct contact with the channel layer 141 and connected to the channel layer 141.

[0101] Subsequently, a heat treatment process is used to diffuse impurities from the first source layer 301 and the second source layer 302 into the channel layer 141. The heat treatment process can be performed using a laser. Localized heat treatment can be applied to the area where the second source layer 302 and the channel layer 141 are in contact with each other using a laser-based heat treatment process.

[0102] Reference Figure 8D An interlayer insulating layer 305 covering the second source layer 302 can be formed. Subsequently, at least one contact plug 315 penetrating the interlayer insulating layer 305 can be formed. The contact plug 315 can contact the second source layer 302. The contact plug 315 may include a diffusion barrier 311 formed on the sidewall of the contact hole and a contact conductive layer 313 filling the contact hole.

[0103] Subsequently, an upper line 317 connecting to the contact plug 315 is formed on the interlayer insulating layer 350. The first source layer 301, the second source layer 302, the contact plug 315, and the upper line 317 can be defined as follows: Figure 2 The source line SL is shown.

[0104] Figure 9 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0105] Reference Figure 9 The memory system 1100 may include a semiconductor memory device 1120 and a memory controller 1110.

[0106] Semiconductor memory device 1120 may be a multi-chip package configured with multiple flash memory chips. Semiconductor memory device 1120 may be a reference... Figures 1 to 4 The semiconductor memory device described.

[0107] The storage controller 1110 controls the semiconductor memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory of the CPU 1112, which performs overall control operations on data exchange with the storage controller 1110. The host interface 1113 may include a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 detects and corrects errors included in data read from the semiconductor memory device 1120, and the memory interface 1115 interfaces with the semiconductor memory device 1120. Additionally, the storage controller 1110 may include a read-only memory (ROM) storing code data, etc., for interfacing with the host.

[0108] The memory system 1100 configured as described above can be a memory card or a solid-state drive (SSD), wherein the semiconductor memory device 1120 is combined with the controller 1110. For example, when the memory system 1100 is an SSD, the storage controller 1110 can communicate with an external source (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronic Devices (IDE) protocol.

[0109] Figure 10 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0110] Reference Figure 10 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210, which are electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for supplying operating voltage to the computing system 1200, and may also include an application chipset, a graphics processor, mobile DRAM, etc.

[0111] According to this disclosure, horn formation can be prevented in the etching process of the vertical channel structure used to expose the channel layer during the process of connecting the channel layer and source layer of the vertical channel structure to each other, thus suppressing pattern defects in the semiconductor memory device.

[0112] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the exemplary embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0113] In the above embodiments, all steps may be performed selectively, or some steps may be omitted. In various embodiments, the steps may not be performed in the described order, but may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0114] Furthermore, exemplary embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is for illustrative purposes only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

[0115] Cross-reference to related applications

[0116] This application claims priority to Korean Patent Application No. 10-2021-0088742, filed on July 6, 2021, with the Korean Intellectual Property Office, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A gate stack structure comprising alternating layers of interlayer insulating layers and conductive patterns; Multiple channel structures that penetrate the gate stack structure, each of the multiple channel structures having an end that protrudes further than the gate stack structure; as well as The source layer includes a first source layer and a second source layer that are sequentially stacked on top of the gate stack and in contact with each other. Each of the plurality of channel structures includes: Channel layer; and A memory layer surrounds the sidewalls of the channel layer. In this embodiment, the protruding end of each of the plurality of channel structures extends into the source layer. In this embodiment, the protruding end of each of the plurality of channel structures penetrates the first source layer, and the memory layer of each of the plurality of channel structures contacts the first source layer.

2. The semiconductor memory device according to claim 1, wherein, The channel layer of each of the plurality of channel structures contacts the second source layer.

3. The semiconductor memory device according to claim 2, wherein, The memory layer includes: A tunnel insulation layer that surrounds the sidewalls of the trench layer; A data storage layer surrounds the sidewalls of the tunnel insulation layer; and A barrier insulating layer surrounds the sidewalls of the data storage layer. In each of the plurality of channel structures, the barrier insulating layer contacts the first source layer.

4. The semiconductor memory device according to claim 1, wherein, The upper surface of the protruding end of each of the plurality of channel structures is located at substantially the same height as the interface between the first source layer and the second source layer.

5. The semiconductor memory device according to claim 2, wherein, The upper end of the channel layer is in contact with the source layer.

6. The semiconductor memory device of claim 1, further comprising an upper line disposed above the source layer.

7. The semiconductor memory device of claim 1, further comprising a bit line connected to the lower end of each of the plurality of channel structures, the bit line being disposed between the substrate and the gate stack structure.

8. The semiconductor memory device of claim 7, further comprising: A conductive connecting line is disposed in the lower layer of the bit line; An insulating structure surrounding the conductive connection line; as well as A conductive connection structure that penetrates the insulating structure and connects the conductive connection line to a complementary metal-oxide-semiconductor (CMOS) circuit.

9. The semiconductor memory device according to claim 1, wherein, Each of the plurality of channel structures has a substantially flat upper surface.

10. A semiconductor memory device, the semiconductor memory device comprising: Peripheral circuits; A gate stack structure that overlaps with the peripheral circuitry and includes alternately stacked interlayer insulating layers and conductive patterns; Multiple channel structures that penetrate the gate stack structure, each of the multiple channel structures having an end that protrudes further than the gate stack structure; The source layer includes a first source layer and a second source layer that are sequentially stacked on top of the gate stack and in contact with each other; as well as A first connection structure and a second connection structure are interconnected in the bonding structure between the peripheral circuit and the gate stack structure. In this embodiment, the protruding end of each of the plurality of channel structures extends into the source layer, and The sidewall of the protruding end of each of the plurality of channel structures contacts the first source layer, and the upper surface of the protruding end of each of the plurality of channel structures contacts the second source layer.

11. The semiconductor memory device of claim 10, wherein, The peripheral circuitry includes a voltage generator, a line decoder, control logic, or a page buffer group.

12. The semiconductor memory device according to claim 10, wherein, Each of the plurality of channel structures includes: Core insulation layer; A channel layer, which surrounds the sidewalls of the core insulation layer; and A memory layer surrounds the sidewalls of the channel layer, and The upper ends of the core insulating layer, the upper ends of the channel layer, and the upper ends of the memory layer protrude upwards and have the same height.

13. A semiconductor memory device, the semiconductor memory device comprising: A gate stack structure comprising alternating layers of interlayer insulating layers and conductive patterns; Multiple channel structures that penetrate the gate stack structure, each of the multiple channel structures having an end that protrudes further than the gate stack structure; as well as The source layer includes a first source layer and a second source layer that are sequentially stacked on top of the gate stack and in contact with each other. In this embodiment, the protruding end of each of the plurality of channel structures extends into the source layer, and The upper surface of the protruding end of each of the plurality of channel structures is located at substantially the same height as the interface between the first source layer and the second source layer.

14. The semiconductor memory device according to claim 13, wherein, Each of the plurality of channel structures includes: Core insulation layer; A channel layer, which surrounds the sidewalls of the core insulation layer; and A memory layer surrounds the sidewalls of the channel layer, and The upper ends of the core insulating layer, the upper ends of the channel layer, and the upper ends of the memory layer protrude upwards and have the same height.

15. The semiconductor memory device according to claim 13, wherein, The upper end of the channel layer is in contact with the source layer.

16. The semiconductor memory device of claim 13, further comprising an upper line disposed above the source layer.

17. The semiconductor memory device of claim 13, further comprising a bit line connected to the lower end of each of the plurality of channel structures, the bit line being disposed between the substrate and the gate stack structure.

18. The semiconductor memory device of claim 17, further comprising: A conductive connecting line is disposed in the lower layer of the bit line; An insulating structure surrounding the conductive connection line; as well as A conductive connection structure that penetrates the insulating structure and connects the conductive connection line to a complementary metal-oxide-semiconductor (CMOS) circuit.

19. The semiconductor memory device according to claim 13, wherein, Each of the plurality of channel structures has a substantially flat upper surface.

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