Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof, and the method comprises the steps: providing a substrate, forming a first conductive region and a second conductive region in the substrate, and enabling the surfaces of the substrate, the first conductive region and the second conductive region to be provided with metal interconnection dielectric layers; etching the metal interconnection dielectric layer to form a first through hole, wherein the first through hole exposes the first conductive region; forming a functional device layer on the surfaces of the metal interconnection dielectric layer and the first through hole; the functional device layer is used as a mask, the metal interconnection dielectric layer and the functional device layer are etched to form a second through hole, and the second through hole exposes the second conductive region; and filling the first through hole and the second through hole with a metal material so as to form a functional device in the first through hole and form a metal interconnection line in the second through hole. Through the improved forming method provided by the scheme of the invention, device damage can be reduced, and device performance can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for forming the same. Background Technology

[0002] MIM capacitors (Metal Insulator Metal Capacitors, also known as plate capacitors or MIM Tube capacitors) utilize different layers of metal and the dielectric material between them to form a capacitor. By using metal as the two electrodes, they effectively reduce parasitic capacitance and contact resistance between the capacitor electrodes. Therefore, MIM capacitors are gradually replacing traditional capacitors and are widely used.

[0003] However, the traditional manufacturing process of MIM capacitors has defects that affect the device performance and industrial applications of MIM capacitors. Summary of the Invention

[0004] The technical problem solved by this disclosure is to provide an improved semiconductor device and a method for forming the same.

[0005] To address the aforementioned technical problems, this disclosure provides a method for forming a semiconductor device, comprising: providing a substrate, wherein a first conductive region and a second conductive region are formed within the substrate, and a metal interconnect dielectric layer is provided on the surfaces of the substrate, the first conductive region, and the second conductive region; etching the metal interconnect dielectric layer to form a first via, the first via exposing the first conductive region; forming a functional device layer on the surfaces of the metal interconnect dielectric layer and the first via; using the functional device layer as a mask, etching the metal interconnect dielectric layer and the functional device layer to form a second via, the second via exposing the second conductive region; and filling the first via and the second via with a metal material to form a functional device in the first via and a metal interconnect in the second via.

[0006] Optionally, forming a functional device layer on the surface of the metal interconnect dielectric layer and the first via includes: forming the functional device layer on the surface of the metal interconnect dielectric layer and the first via using an atomic layer deposition process.

[0007] Optionally, the functional device layer includes a conductive layer and a device dielectric layer. Forming the functional device layer on the surface of the metal interconnect dielectric layer and the first via includes: forming a conductive layer on the surface of the metal interconnect dielectric layer and the first via; and forming a device dielectric layer on the surface of the conductive layer.

[0008] Optionally, the material of the conductive layer includes TiN.

[0009] Optionally, the material of the dielectric layer of the device includes a high dielectric constant material.

[0010] Optionally, before filling the first and second through holes with metal material, the forming method includes forming a metal barrier layer on the surface of the first and second through holes.

[0011] Optionally, the material of the metal barrier layer includes TaN.

[0012] Optionally, the forming method further includes: removing the functional device layer on the surface of the metal interconnect dielectric layer using a chemical mechanical polishing process.

[0013] Optionally, the forming method further includes: oxidizing at least the portion of the functional device layer exposed on the surface of the metal interconnect dielectric layer.

[0014] Optionally, the process parameters of the oxidation treatment satisfy one or more of the following: the process time is selected from 2 seconds to 6 seconds; the process temperature is less than 400°C; and the gas is selected from N2O and NO2.

[0015] To address the aforementioned technical problems, this disclosure also provides a semiconductor device, comprising: a substrate having a first conductive region and a second conductive region formed therein, and a metal interconnect dielectric layer on the surfaces of the substrate, the first conductive region, and the second conductive region; a functional device formed on the metal interconnect dielectric layer, one end of which is electrically connected to the first conductive region and the other end of which is exposed on the surface of the metal interconnect dielectric layer; and a metal interconnect formed on the metal interconnect dielectric layer, one end of which is electrically connected to the second conductive region and the other end of which is exposed on the surface of the metal interconnect dielectric layer.

[0016] Optionally, the functional device includes a MIM capacitor.

[0017] Optionally, a first through-hole is formed in the metal interconnect dielectric layer to form the functional device. The functional device includes: a lower electrode plate formed by a conductive layer located on the surface of the first through-hole, the lower electrode plate being electrically connected to the first conductive region; a device dielectric layer located on the surface of the conductive layer; an upper electrode plate formed by a metal material filled in the first through-hole, the device dielectric layer being sandwiched between the upper electrode plate and the lower electrode plate; and a metal barrier layer located between the upper electrode plate and the device dielectric layer.

[0018] Compared with the prior art, the technical solutions of the embodiments of this disclosure have the following beneficial effects:

[0019] Compared to traditional fabrication processes where subsequent steps can damage the functional devices fabricated in previous steps, thus affecting device performance, this implementation scheme improves certain steps in both the preceding and following processes to reduce damage to the functional devices and enhance device performance. Specifically, after forming the functional device layer but before fabricating the functional devices, the functional device layer is used as a mask for etching the second via. By introducing a portion of the subsequent process before all steps in the preceding process are completed, damage to the functional devices formed in the preceding process is avoided during the etching step in the subsequent process, thus improving the surface morphology of the functional devices. Furthermore, metal material is simultaneously filled into the first and second vias, fabricating the functional devices and metal interconnects together. By integrating the metal filling steps of the preceding and following processes into a single step, the number of process steps is reduced, increasing throughput, while avoiding the impact of the following process on the preceding process and reducing device damage.

[0020] Taking a MIM capacitor as an example, after forming the material layer for forming the lower electrode and the material layer for forming the device dielectric layer on the first via and the substrate surface, the remaining steps of the previous process are not continued. Instead, these two layers are used as a mask to etch the second via. Metal material is simultaneously filled into the first and second vias, thus fabricating the MIM capacitor and metal interconnects. The substrate surface is then polished to remove excess material layers. Therefore, only one polishing is performed during the fabrication process, reducing process steps and increasing production capacity, while also reducing surface damage to the MIM capacitor and improving device performance. Furthermore, even if, during subsequent fabrication, the upper metal interconnect falls onto the device dielectric layer due to OVL deviation, the probability of the upper metal interconnect touching the lower electrode is greatly reduced because the HK damage to the device dielectric layer is minimal.

[0021] The method for forming a semiconductor device provided in this application further includes: oxidizing at least the portion of the functional device layer exposed on the surface of the metal interconnect dielectric layer. After removing the functional device layer from the surface of the metal interconnect dielectric layer using a CMP process and before continuing the fabrication of the upper layer structure, the exposed portion of the functional device layer, especially the top of the conductive layer, is oxidized to form an oxide region on the top of the conductive layer. The oxide region can provide electrical isolation, preventing leakage paths even if the CMP process causes HK damage to the top of the functional device, or preventing short circuits even if subsequent OVL deviations cause upper metal interconnect lines to fall onto the device dielectric layer or even the conductive layer. This further improves device performance. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the fabrication process of a semiconductor device in the prior art;

[0023] Figure 2This is a flowchart of a method for forming a semiconductor device according to an embodiment of this disclosure;

[0024] Figures 3 to 8 This is a schematic diagram of the cross-sectional structure of the device corresponding to each step in the method for forming the semiconductor device according to the embodiments of this disclosure;

[0025] Figure 9 This is a schematic cross-sectional view of a semiconductor device in a variation of an embodiment of this disclosure;

[0026] Explanation of reference numerals in the attached figures:

[0027] 100, 300 - Semiconductor devices; 101, 301 - Substrate; 3011 - First conductive region; 3012 - Second conductive region; 302 - Metal interconnect dielectric layer; 3021 - High dielectric constant layer; 3022 - Low dielectric constant layer; 303 - First via; 304 - Functional device layer; 3041 - Conductive layer; 1042, 3042 - Device dielectric layer; 305 - Second via; 306 - Metal barrier layer; 107, 307 - Metal interconnects; 108, 308 - MIM capacitors; 1081, 3081 - Lower electrode; 1082, 3082 - Upper electrode; 3083 - Oxidation region; 109, 309 - Peripheral logic region; A1, A2 - Metal contacts. Detailed Implementation

[0028] As mentioned in the background section, the existing fabrication process for MIM capacitors has defects, which affect the device performance and industrial applications of MIM capacitors.

[0029] Specifically, semiconductor devices are typically fabricated through multiple processes, with each process (also called a single step) comprising one or more technological steps. Existing technologies typically implement the processes used to fabricate different devices or structures strictly independently and asynchronously, with different steps used to fabricate different devices or structures.

[0030] For example, refer to Figure 1 The fabrication process of a conventional semiconductor device 100 integrating a MIM capacitor 108 includes: firstly, performing a previous process, such as deposition, etching, and polishing, to fabricate the MIM capacitor 108 on a substrate 101, as shown below. Figure 1 As shown in views (a) and (b); then, subsequent processes are performed on the substrate 101 on which the MIM capacitor 108 is formed, forming structures such as metal interconnects 107 through etching, deposition, and polishing, thus completing the fabrication of the current layer, as shown in view (a) and (b); Figure 1As shown in view (c), the previous process can fabricate a complete MIM capacitor 108, that is, the lower electrode 1081, the device dielectric layer 1042, and the upper electrode 1082 are sequentially formed on the substrate through the previous process. The subsequent process is used to form the metal interconnects of the peripheral logic region 109. Next, the upper structure can be fabricated, for example, forming a metal interconnect 107 above the upper electrode 1082 of the MIM capacitor 108 to electrically connect the metal contact A1, and continuing to form a metal interconnect 107 above the metal interconnect 107 of the peripheral logic region 109 to electrically connect the metal contact A2, as shown. Figure 1 The (d) view is shown.

[0031] like Figure 1 As shown in the fabrication process, in existing processes, when fabricating the current layer, a complete MIM capacitor structure is first formed, and then the metal interconnects of the peripheral logic region are formed. Since a polishing process is required when forming the metal interconnects in the subsequent process, the surface of the MIM capacitor already fabricated in the previous process is inevitably subjected to secondary polishing, especially causing surface damage (also known as HK damage) on the dielectric layer of the MIM capacitor, resulting in defects.

[0032] Furthermore, the alignment window for MIM capacitor via-to-via technology is relatively small, making it difficult for upper-layer metal interconnects to accurately align with the upper electrode. Once an overlay (overlay measurement) deviation occurs, the upper-layer metal interconnect will fall onto the device dielectric layer, such as... Figure 1 As shown in view (d). Based on the foregoing analysis, the MIM capacitor has defects due to secondary polishing, especially severe surface damage to the device dielectric layer. The upper metal interconnects falling on the device dielectric layer may accidentally touch the lower plate of the MIM capacitor, causing a short circuit and device failure.

[0033] To address at least one of the aforementioned technical problems, embodiments of this application provide a method for forming a semiconductor device. After forming a material layer for forming a lower electrode and a material layer for forming a device dielectric layer on the surface of a first via and a substrate, the remaining steps of the previous process are not continued. Instead, these two layers are used as a mask to etch a second via. Metal material is simultaneously filled into the first and second vias, thereby simultaneously fabricating a MIM capacitor and metal interconnects. The substrate surface is then polished to remove excess material layers. Thus, only one polishing step is performed during the fabrication process, reducing process steps and increasing throughput, while also reducing surface damage to the MIM capacitor and improving device performance. Furthermore, even if, during subsequent fabrication, the upper metal interconnect falls onto the device dielectric layer due to OVL deviation, the probability of the upper metal interconnect touching the lower electrode is greatly reduced because the device dielectric layer suffers minimal HK damage.

[0034] To make the above-mentioned objectives, features and beneficial effects of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0035] Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of this disclosure.

[0036] refer to Figure 2 The method for forming a semiconductor device may include steps S11 to S19:

[0037] Step S11: Provide a substrate, wherein a first conductive region and a second conductive region are formed in the substrate, and the surfaces of the substrate, the first conductive region and the second conductive region have a metal interconnect dielectric layer;

[0038] Step S13: Etch the metal interconnect dielectric layer to form a first via, the first via exposing the first conductive region;

[0039] Step S15: A functional device layer is formed on the surface of the metal interconnect dielectric layer and the first via.

[0040] Step S17: Using the functional device layer as a mask, the metal interconnect dielectric layer and the functional device layer are etched to form a second via, the second via exposing the second conductive region;

[0041] Step S19: Fill the first through hole and the second through hole with metal material to form a functional device in the first through hole and a metal interconnect in the second through hole.

[0042] As a non-limiting embodiment, the semiconductor device formation method described in this embodiment can be applied to the fabrication process of functional devices, such as MIM capacitors. Using this embodiment, it is possible to form devices such as… Figure 8 The semiconductor device 300 shown integrates a MIM capacitor 308. The semiconductor device 300 can be applied to circuit boards with high capacitance requirements. By collecting overflow capacitance through the MIM capacitor 308, the circuit board can achieve a better large capacitance effect.

[0043] More specifically, the substrate may be, for example, a silicon substrate, or a semiconductor substrate made of other silicon-containing materials.

[0044] In some embodiments, reference Figure 3 The substrate 301 provided in step S11 can be made of a material with a low dielectric constant. For example, the substrate 301 can be formed using a material with a dielectric constant between 1 and 2. The substrate 301 can be etched and deposited to form a first conductive region 3011 and a second conductive region 3012.

[0045] Furthermore, a metal interconnect dielectric layer 302 is formed on the surface of the substrate 301 on which the first conductive region 3011 and the second conductive region 3012 are formed. The metal interconnect dielectric layer 302 can be a silicon oxide layer (e.g., SiO2), fluorine-doped silicon oxide (F-SiO2), a low-k dielectric material (Low-K), an ultra-low-k dielectric material (Ultra Low-K, ULK), a silicon nitride layer (e.g., Si3N4), silicon carbide (SiC), nitrogen-doped silicon carbide (NDC), aluminum nitride (AlN), and combinations thereof.

[0046] Figure 3 An exemplary example is provided using a combination of a high-dielectric-constant layer 3021 and a low-dielectric-constant layer 3022 formed thereon as the metal interconnect dielectric layer 302. The high-dielectric-constant layer 3021 can be formed using a material with a dielectric constant greater than 5, and the low-dielectric-constant layer 3022 can be formed using a material with a dielectric constant of approximately 1-2. For instance, a high-dielectric-constant material film and a low-dielectric-constant material film can be sequentially deposited on the surface of the substrate 301 using a chemical vapor deposition (CVD) process with tetraethoxysilane (TEOS, chemical formula Si(OC2H5)4) as a precursor to form the high-dielectric-constant layer 3021 and the low-dielectric-constant layer 3022.

[0047] The first conductive region 3011 and the second conductive region 3012 can be set independently, that is, they are electrically isolated from each other. Alternatively, the first conductive region 3011 and the second conductive region 3012 can also be electrically connected through a metal interconnect.

[0048] The first conductive region 3011 and the second conductive region 3012 can be made of metallic materials. For example, the metallic materials can be copper (Cu) or aluminum (Al).

[0049] In some embodiments, reference Figure 4 In step S13, an etching process can be used to process the metal interconnect dielectric layer 302 to form a first via 303 that at least partially exposes the first conductive region 3011.

[0050] In some embodiments, reference Figure 5 Step S15 may specifically include: forming a functional device layer 304 on the surface of the metal interconnect dielectric layer 302 and the first via 303 using an atomic layer deposition (ALD) process. The ALD process has a better sidewall deposition rate, which is beneficial to improving the fabrication efficiency.

[0051] Furthermore, the functional device layer 304 may include a conductive layer 3041 and a device dielectric layer 3042. The conductive layer 3041 can be used to form the lower electrode 3081 of the MIM capacitor 308 (e.g., Figure 8 (As shown). The device dielectric layer 3042 can be used to form the "I" structure in the MIM capacitor 308.

[0052] For example, step S15 may specifically include: forming a conductive layer 3041 on the surface of the metal interconnect dielectric layer 302 and the first via 303; and forming a device dielectric layer 3042 on the surface of the conductive layer 3041. The conductive layer 3041 and the device dielectric layer 3042 may be formed sequentially using an ALD process.

[0053] In some embodiments, the material of the conductive layer 3041 may include titanium nitride (TiN).

[0054] In some embodiments, the material of the device dielectric layer 3042 may include a high dielectric constant material.

[0055] Compare Figure 6 and Figure 1 In this embodiment, after etching the first via 303, only the conductive layer 3041 and the device dielectric layer 3042 for forming the lower electrode 3081 are grown. Then, S17 is executed to etch the second via 305 using the functional device layer 304 as a hard mask. For example, refer to... Figure 6 Wet etching or dry etching processes can be used to etch the functional device layer 304 and the metal interconnect dielectric layer 302 to form a second via 305 that at least partially exposes the second conductive region 3012.

[0056] In some embodiments, combined with Figure 7 After step S17 and before step S19, the method for forming the semiconductor device described in this embodiment may further include the step of forming a metal barrier layer 306 on the surface of the first via 303 and the second via 305. The metal barrier layer 306 helps to prevent the metal material filling the via from overflowing. For example, the material of the metal barrier layer 306 may include tantalum nitride (TaN).

[0057] Compare Figure 7 and Figure 1 Traditionally manufactured MIM capacitors 108 do not have a metal barrier layer, but in this embodiment, both the first via 303 and the second via 305 are covered with a metal barrier layer 306. Using this embodiment, the metal material subsequently filled in the second via 305 and the metal material filled in the first via 303 can be reliably confined within their respective vias by the metal barrier layer 306, which is beneficial for improving device performance.

[0058] In some embodiments, in step S19, a thin-film deposition process can be used to fill the first via 303 and the second via 305 with a metallic material. The metallic material can be, for example, copper (Cu).

[0059] Furthermore, after step S19, the following step can also be performed: chemical-mechanical polishing (CMP) can be used to remove the functional device layer 304 from the surface of the metal interconnect dielectric layer 302, resulting in... Figure 8 The semiconductor device 300 is shown. Therefore, only one grinding process is performed during the formation of the semiconductor device 300, which reduces process steps and increases production capacity, while also reducing surface damage to the MIM capacitor 308 and improving device performance. Even if, during subsequent fabrication, the upper metal interconnect falls onto the device dielectric layer 3042 due to OVL deviation, the probability of the upper metal interconnect touching the lower electrode 3081 is greatly reduced because the HK damage to the device dielectric layer 3042 is minimal.

[0060] Continue to refer to Figure 8 The semiconductor device 300 may include functional devices and peripheral logic regions 309 in the lateral direction, performing... Figure 2 The metal interconnect 307 prepared by the steps shown is used to form at least a portion of the metal interconnect structure of the peripheral logic region 309. The functional device can be, for example, a MIM capacitor 308, one end of which is electrically connected to the first conductive region 3011, and the other end exposed on the surface of the metal interconnect dielectric layer 302. One end of the metal interconnect 307 is electrically connected to the second conductive region 3012, and the other end is exposed on the surface of the metal interconnect dielectric layer 302.

[0061] Furthermore, the device dielectric layer 3042 of the MIM capacitor 308 is sandwiched between the upper electrode 3082 and the lower electrode 3081, and a metal barrier layer 306 is also provided between the upper electrode 3082 and the device dielectric layer 3042. Thus, the metal material used to form the upper electrode 3082 is reliably confined within the first through-hole 303, preventing metal material overflow from affecting the device performance of the MIM capacitor 308.

[0062] Therefore, this implementation scheme improves certain steps in the preceding and following processes, reducing damage to the functional device and enhancing device performance. Specifically, after forming the functional device layer 304 and before fabricating the functional device, the functional device layer 304 is used as a mask for etching the second via 305. By introducing a portion of the following process before all steps in the preceding process are completed, damage to the functional device formed in the preceding process is avoided during the etching step in the following process, thus improving the surface morphology of the functional device. Furthermore, metal material is simultaneously filled into the first via 303 and the second via 305, and the functional device and metal interconnect 307 are fabricated together. By integrating the metal filling step of the preceding process and the metal filling step of the following process into the same step, the number of process steps is reduced, the throughput is increased, and the impact of the following process on the preceding process is avoided, thus reducing device damage.

[0063] In a variation of the above embodiment, after obtaining as follows Figure 8 Following the semiconductor device 300 shown, the method for forming the semiconductor device described in this variation may further include the step of: at least oxidizing the portion of the functional device layer 304 exposed on the surface of the metal interconnect dielectric layer 302.

[0064] refer to Figure 8 After the CMP process, the conductive layer 3041, the device dielectric layer 3042, and the metal material filling the first via 303 in step S19 are all at least partially exposed on the surface of the metal interconnect dielectric layer 302. In the example where the functional device is a MIM capacitor 308, after the CMP process, the lower electrode 3081, the device dielectric layer 3042, and the upper electrode 3082 of the MIM capacitor 308 are all at least partially exposed on the surface of the metal interconnect dielectric layer 302.

[0065] Through oxidation treatment, the portion of the functional device layer 304 exposed on the surface of the metal interconnect dielectric layer 302 can be converted into oxide, such as... Figure 9 As shown. For example, after a CMP process, the functional device layer 304 is directly exposed on the surface of the metal interconnect dielectric layer 302. After oxidation, the portion of the functional device layer 304, particularly the conductive layer 3041 near the top, retained after CMP is transformed into an oxide region 3083. As... Figure 9 As shown, in the longitudinal direction, the conductive layer 3041 is no longer directly exposed to the surface of the metal interconnect dielectric layer 302, and the two are isolated by the oxide region 3083.

[0066] Therefore, even if the CMP process causes HK damage to the top of the MIM capacitor 308, no leakage path will be created. Even if subsequent OVL deviation causes the upper metal interconnect to fall onto the device dielectric layer 3042 or even the lower electrode 3081, the presence of the oxide region 3083 prevents the upper metal interconnect from directly contacting the conductive layer 3041 used to form the lower electrode 3081, thus preventing a short circuit.

[0067] The process parameters for oxidation treatment can meet one or more of the following: process time is selected from 2 to 6 seconds; process temperature is less than 400℃; and the gas is selected from nitrous oxide (N2O) and nitrogen dioxide (NO2).

[0068] For example, an N2O processing step can be added after CMP to convert the portion of the lower electrode 3081 near the surface of the metal interconnect dielectric layer 302 from TiN to TiON with a high dielectric constant.

[0069] In some embodiments, the oxidation depth of the conductive layer 3041 should not be too deep to avoid affecting device performance, such as the resistive performance of the MIM capacitor 308. Generally, the wear degree of the device dielectric layer 3042 during CMP is greater than the wear degree of the metal material filling the first via 303 (i.e., the upper electrode 3082) and the conductive layer 3041 (i.e., the lower electrode 3081). In this embodiment, by reasonably setting the process parameters of the oxidation treatment, it is ensured that the depth of the oxidation treatment of the conductive layer 3041 is not less than the wear depth of the device dielectric layer 3042 during CPM.

[0070] Further reference Figure 9 An upper structure is then fabricated above the metal interconnect dielectric layer 302. This upper structure may include a metal contact A1, electrically connected to the upper plate 3082 of the MIM capacitor 308 via a metal interconnect 307. The metal contact A1 is used to connect to an external power supply or to electrically connect to a peripheral logic region 309. The upper structure may also include a metal contact A2, electrically connected to a second conductive region 3012 via a metal interconnect 307.

[0071] In one variation, the first conductive region 3011 and the second conductive region 3012 may be electrically connected. The lower electrode 3081 is powered via the peripheral logic region 309.

[0072] In this embodiment, "high dielectric constant" and "low dielectric constant" are relative dielectric constants. A low dielectric constant typically refers to a dielectric constant below 3.0. A high dielectric constant typically refers to a dielectric constant greater than 3.9.

[0073] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, wherein a first conductive region and a second conductive region are formed therein, and the surfaces of the substrate, the first conductive region and the second conductive region have a metal interconnect dielectric layer. The metal interconnect dielectric layer is etched to form a first via, the first via exposing the first conductive region; A functional device layer is formed on the surface of the metal interconnect dielectric layer and the first via. Using the functional device layer as a mask, the metal interconnect dielectric layer and the functional device layer are etched to form a second via, the second via exposing the second conductive region; Metal material is filled into the first and second through holes to form a functional device in the first through hole and a metal interconnect in the second through hole.

2. The forming method according to claim 1, characterized in that, Forming a functional device layer on the surface of the metal interconnect dielectric layer and the first via includes: The functional device layer is formed on the surface of the metal interconnect dielectric layer and the first via using an atomic layer deposition process.

3. The forming method according to claim 1 or 2, characterized in that, The functional device layer includes a conductive layer and a device dielectric layer. Forming the functional device layer on the surface of the metal interconnect dielectric layer and the first via includes: A conductive layer is formed on the surface of the metal interconnect dielectric layer and the first via. A device dielectric layer is formed on the surface of the conductive layer.

4. The forming method according to claim 3, characterized in that, The conductive layer is made of TiN, and / or the dielectric layer of the device is made of a high dielectric constant material.

5. The forming method according to claim 1, characterized in that, Before filling the first and second through holes with metallic material, the process includes: A metal barrier layer is formed on the surface of the first and second through holes.

6. The forming method according to claim 5, characterized in that, The material of the metal barrier layer includes TaN.

7. The forming method according to claim 1, characterized in that, Also includes: The functional device layer on the surface of the metal interconnect dielectric layer is removed using a chemical mechanical polishing process.

8. The forming method according to claim 1 or 7, characterized in that, Also includes: At least the portion of the functional device layer exposed on the surface of the metal interconnect dielectric layer is subjected to oxidation treatment.

9. The forming method according to claim 8, characterized in that, The process parameters for the oxidation treatment satisfy one or more of the following: The process time is selected from 2 seconds to 6 seconds; Process temperature less than 400℃; The gases are selected from N2O and NO2.

10. A semiconductor device, characterized in that, include: A substrate having a first conductive region and a second conductive region formed therein, and a metal interconnect dielectric layer having a surface of the substrate, the first conductive region and the second conductive region; A functional device is formed on the metal interconnect dielectric layer, with one end of the functional device electrically connected to the first conductive region and the other end exposed on the surface of the metal interconnect dielectric layer; A metal interconnect is formed on the metal interconnect dielectric layer, one end of which is electrically connected to the second conductive region and the other end is exposed on the surface of the metal interconnect dielectric layer.

11. The semiconductor device according to claim 10, characterized in that, The functional device includes a MIM capacitor.

12. The semiconductor device according to claim 10 or 11, characterized in that, A first via is formed within the metal interconnect dielectric layer to form the functional device, the functional device comprising: The lower electrode plate is formed of a conductive layer located on the surface of the first through hole, and the lower electrode plate is electrically connected to the first conductive area; The device dielectric layer is located on the surface of the conductive layer; The upper electrode plate is formed of a metal material filling the first through hole, and the device dielectric layer is sandwiched between the upper electrode plate and the lower electrode plate; A metal barrier layer is located between the upper electrode and the device dielectric layer.

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