Semiconductor device and forming method thereof
By forming an insulating region on top of the conductive layer during the fabrication of MIM capacitors, the short-circuit problems caused by device dielectric layer damage and upper metal interconnect misalignment in traditional MIM capacitor fabrication processes are solved, thereby improving the electrical isolation and performance of the device.
Patent Information
- Application Number
- CN202511082313.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-01
- Publication Date
- 2025-10-31
AI Technical Summary
The traditional manufacturing process of MIM capacitors has defects that affect device performance and industrial applications. In particular, the subsequent polishing process can cause damage to the dielectric layer of the device and misalignment of the upper metal interconnects, leading to short circuits.
After the functional device is fabricated, the exposed portion of the conductive layer is oxidized to form an insulating region, which electrically isolates the conductive layer from the metal interconnects in subsequent processes to prevent leakage and short circuits.
By forming an insulating region on top of the conductive layer, damage to the device from subsequent processes is reduced, the electrical isolation effect of the device is improved, leakage and short circuits are prevented, and the device performance is enhanced.
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Figure CN120882014A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for forming the same. Background Technology
[0002] MIM capacitors (Metal Insulator Metal Capacitors, also known as plate capacitors or MIM tube capacitors) utilize different layers of metal and a dielectric material between them to form a capacitor. Compared to traditional capacitors, MIM capacitors use metal as the two electrodes, thus greatly reducing parasitic capacitance and contact resistance between the capacitor electrodes. Therefore, MIM capacitors have gradually replaced traditional capacitors and are widely used.
[0003] However, the traditional manufacturing process of MIM capacitors has defects that affect the device performance and industrial applications of MIM capacitors. Summary of the Invention
[0004] The technical problem solved by this disclosure is to provide an improved semiconductor device and a method for forming the same.
[0005] To address the aforementioned technical problems, this disclosure provides a method for forming a semiconductor device, comprising: providing a substrate, wherein a first conductive region is formed within the substrate, and the surfaces of the substrate and the first conductive region have a first metal interconnect dielectric layer; fabricating a functional device on the first conductive region, the functional device including a conductive layer electrically connected to the first conductive region, the conductive layer being exposed on the surface of the first metal interconnect dielectric layer; oxidizing a portion of the conductive layer exposed on the surface of the first metal interconnect dielectric layer to form an insulating region; and fabricating a first metal interconnect on the functional device, the first metal interconnect being electrically isolated from the conductive layer by the insulating region.
[0006] Optionally, fabricating a functional device on the first conductive region includes: etching the first metal interconnect dielectric layer to form a first via, the first via exposing the first conductive region; sequentially forming a conductive layer and a device dielectric layer on the surfaces of the first metal interconnect dielectric layer and the first via; filling the first via with a metal material to form the functional device within the first via; wherein the second conductive region formed by the metal material is electrically connected to the first metal interconnect.
[0007] Optionally, after filling the first through-hole with metal material, the forming method further includes: removing the conductive layer and device dielectric layer on the surface of the first metal interconnect dielectric layer using a chemical mechanical polishing process.
[0008] Optionally, the material of the conductive layer includes TiN.
[0009] Optionally, the material of the dielectric layer of the device includes a high dielectric constant material.
[0010] Optionally, the process parameters of the oxidation treatment satisfy one or more of the following: the process time is selected from 2 seconds to 6 seconds; the process temperature is less than 400°C; and the gas is selected from N2O and NO2.
[0011] Optionally, fabricating the first metal interconnect on the functional device includes: forming a second metal interconnect dielectric layer on the surface of the first metal interconnect dielectric layer and the functional device; etching the second metal interconnect dielectric layer to form a second via, the second via at least partially exposing the functional device; and filling the second via with a metal material to form the first metal interconnect within the second via.
[0012] Optionally, the functional device further includes a second conductive region exposed on the surface of the first metal interconnect dielectric layer, wherein the second via simultaneously exposes the insulating region and the second conductive region.
[0013] Optionally, the substrate further comprises a third conductive region, the surface of which has the first metal interconnect dielectric layer. After the functional device is fabricated and before the first metal interconnect is fabricated, the formation method further comprises: etching the first metal interconnect dielectric layer to form a third via, the third via exposing the third conductive region; filling the third via with metal material to form a second metal interconnect within the third via; and polishing the first metal interconnect dielectric layer using a chemical mechanical polishing process.
[0014] Optionally, the functional device further includes a device dielectric layer exposed on the surface of the first metal interconnect dielectric layer, wherein the oxidation depth of the conductive layer in the oxidation process is greater than the wear depth of the device dielectric layer in the chemical mechanical polishing process.
[0015] To address the aforementioned technical problems, this disclosure also provides a semiconductor device, comprising: a substrate having a first conductive region formed therein, and a first metal interconnect dielectric layer on the surfaces of the substrate and the first conductive region; a functional device formed on the first metal interconnect dielectric layer, the functional device including a conductive layer, one end of the conductive layer being electrically connected to the first conductive region, and an insulating region between the other end of the conductive layer and the surface of the first metal interconnect dielectric layer; and a first metal interconnect located above the functional device, the first metal interconnect being electrically isolated from the conductive layer by the insulating region.
[0016] Optionally, a first via is formed in the first metal interconnect dielectric layer to form the functional device, and the conductive layer is formed on the surface of the first via. The functional device further includes: a device dielectric layer located on the surface of the conductive layer; and a second conductive region formed by a metal material filling the first via and electrically connected to the first metal interconnect. The device dielectric layer is sandwiched between the conductive layer and the second conductive region.
[0017] Optionally, the first metal interconnect at least partially covers the device dielectric layer and / or the insulating region.
[0018] Optionally, the semiconductor device further includes: a second metal interconnect dielectric layer located on the surface of the first metal interconnect dielectric layer and the functional device, wherein the first metal interconnect line is formed on the second metal interconnect dielectric layer.
[0019] Optionally, the semiconductor device further includes: a second metal interconnect formed on the first metal interconnect dielectric layer, the first metal interconnect dielectric layer further having a third conductive region, one end of the second metal interconnect electrically connected to the third conductive region and the other end exposed on the surface of the first metal interconnect dielectric layer.
[0020] Optionally, the functional device includes a MIM capacitor.
[0021] Compared with the prior art, the technical solutions of the embodiments of this disclosure have the following beneficial effects:
[0022] In this embodiment, after the functional device is fabricated and before the fabrication of other structures, the exposed portion of the functional device, especially the top of the conductive layer, is oxidized to form an insulating region on top of the conductive layer. This insulating region provides electrical isolation, preventing leakage even if subsequent processes such as CMP cause HK damage to the top of the functional device. Furthermore, even if subsequent OVL deviations cause the upper metal interconnect (i.e., the first metal interconnect) to fall onto the conductive layer, a short circuit will not occur. This further improves device performance.
[0023] Taking a MIM capacitor as an example, after sequentially fabricating the conductive layer (equivalent to the lower electrode), the device dielectric layer, and the second conductive region (equivalent to the upper electrode) of the MIM capacitor, before proceeding with subsequent processes such as the fabrication of the first metal interconnect, the semiconductor device surface is first oxidized to partially oxidize the conductive layer, transforming the portion of the conductive layer exposed on the surface of the first metal interconnect dielectric layer into an insulating region. Therefore, even if the OVL deviation occurs during the subsequent fabrication of the upper structure (such as the first metal interconnect), causing the first metal interconnect to fall onto the device dielectric layer or even the conductive layer, the leakage path between the first metal interconnect and the lower electrode can be reliably blocked by the insulating region. Furthermore, this blocking effect is unaffected by the degree of HK damage at the top of the MIM capacitor. This HK damage may be caused by the final CMP process in the fabrication of the MIM capacitor, or it may be caused by the CMP process during the subsequent fabrication of the third conductive region. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of the fabrication process of a semiconductor device in the prior art;
[0025] Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of this disclosure;
[0026] Figures 3 to 14 This is a schematic diagram of the cross-sectional structure of the device corresponding to each step in the method for forming the semiconductor device according to the embodiments of this disclosure;
[0027] Figures 15 to 18 This is a schematic diagram of the cross-sectional structure of a semiconductor device corresponding to some steps in a variation of the method for forming a semiconductor device according to an embodiment of this disclosure;
[0028] Figures 19 to 22 This is a schematic diagram of the device cross-sectional structure corresponding to some steps in the method for forming a semiconductor device in another variation of the present disclosure;
[0029] Explanation of reference numerals in the attached figures:
[0030] 100, 300 - Semiconductor device; 101, 301 - Substrate; 3011 - First conductive region; 3012 - Third conductive region; 302 - First metal interconnect dielectric layer; 3021 - High dielectric constant layer; 3022 - Low dielectric constant layer; 303 - First via; 304 - Functional device layer; 3041 - Conductive layer; 1042, 3042 - Device dielectric layer; 3043 - Second conductive region; 305 - Second via; 306 - Metal barrier layer ; 107 - Metal interconnect; 3071 - First metal interconnect; 3072 - Second metal interconnect; 3073 - Third metal interconnect; 108, 308 - MIM capacitor; 1081, 3081 - Lower electrode; 1082, 3082 - Upper electrode; 3083 - Insulating region; 109, 309 - Peripheral logic region; 310 - Third via; 311 - Second metal interconnect dielectric layer; 312 - Photoresist layer; A1, A2 - Metal contacts. Detailed Implementation
[0031] As mentioned in the background section, the existing fabrication process for MIM capacitors has defects, which affect the device performance and industrial applications of MIM capacitors.
[0032] Specifically, semiconductor devices are typically fabricated through multiple processes, with each process (also called a single step) comprising one or more technological steps. Existing technologies typically implement the processes used to fabricate different devices or structures strictly independently and asynchronously, with different steps used to fabricate different devices or structures.
[0033] For example, refer to Figure 1 The fabrication process of a conventional semiconductor device 100 integrating a MIM capacitor 108 includes: firstly, performing a previous process, such as deposition, etching, and polishing, to fabricate the MIM capacitor 108 on a substrate 101, as shown below. Figure 1 As shown in views (a) and (b); then, subsequent processes are performed on the substrate 101 on which the MIM capacitor 108 is formed, forming structures such as metal interconnects 107 through etching, deposition, and polishing, thus completing the fabrication of the current layer, as shown in view (a) and (b); Figure 1 As shown in view (c), the previous process can fabricate a complete MIM capacitor 108, that is, the lower electrode 1081, the device dielectric layer 1042, and the upper electrode 1082 are sequentially formed on the substrate through the previous process. The subsequent process is used to form the metal interconnects of the peripheral logic region 109. Next, the upper structure can be fabricated, for example, forming a metal interconnect 107 above the upper electrode 1082 of the MIM capacitor 108 to electrically connect the metal contact A1, and continuing to form a metal interconnect 107 above the metal interconnect 107 of the peripheral logic region 109 to electrically connect the metal contact A2, as shown. Figure 1 The (d) view is shown.
[0034] like Figure 1 As shown in the fabrication process, in existing processes, when fabricating the current layer, a complete MIM capacitor structure is first formed, and then the metal interconnects of the peripheral logic region are formed. Since a polishing process is required when forming the metal interconnects in the subsequent process, the surface of the MIM capacitor already fabricated in the previous process is inevitably subjected to secondary polishing, especially causing surface damage (also known as HK damage) on the dielectric layer of the MIM capacitor, resulting in defects.
[0035] Furthermore, the alignment window for MIM capacitor via-to-via technology is relatively small, making it difficult for upper-layer metal interconnects to accurately align with the upper electrode. Once an overlay (overlay measurement) deviation occurs, the upper-layer metal interconnect will fall onto the device dielectric layer, such as... Figure 1 As shown in view (d). Based on the foregoing analysis, the MIM capacitor has defects due to secondary polishing, especially severe surface damage to the device dielectric layer. The upper metal interconnects falling on the device dielectric layer may accidentally touch the lower plate of the MIM capacitor, causing a short circuit and device failure.
[0036] To address at least one of the aforementioned technical problems, embodiments of this application provide a method for forming a semiconductor device. After the functional device is fabricated but before proceeding with the fabrication of other structures, the exposed portion of the functional device, particularly the top of the conductive layer, is oxidized to form an insulating region on top of the conductive layer. This insulating region provides electrical isolation, preventing leakage even if subsequent processes such as CMP cause HK damage to the top of the functional device. Furthermore, even if subsequent OVL deviation causes the upper metal interconnect (i.e., the first metal interconnect) to fall onto the conductive layer, a short circuit will not occur. Thus, device performance is further improved.
[0037] To make the above-mentioned objectives, features and beneficial effects of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.
[0038] Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of this disclosure.
[0039] refer to Figure 2 The method for forming a semiconductor device may include steps S11 to S17:
[0040] Step S11: Provide a substrate, wherein a first conductive region is formed in the substrate, and the surfaces of the substrate and the first conductive region have a first metal interconnect dielectric layer;
[0041] Step S13: A functional device is fabricated on the first conductive region. The functional device includes a conductive layer electrically connected to the first conductive region, and the conductive layer is exposed on the surface of the first metal interconnect dielectric layer.
[0042] Step S15: Oxidize the portion of the conductive layer exposed on the surface of the first metal interconnect dielectric layer to form an insulating region;
[0043] Step S17: A first metal interconnect is fabricated on the functional device, and the first metal interconnect is electrically isolated from the conductive layer by the insulating region.
[0044] As a non-limiting embodiment, the semiconductor device formation method described in this embodiment can be applied to the fabrication process of functional devices, such as MIM capacitors. Using this embodiment, it is possible to form devices such as… Figure 14 The semiconductor device 300 shown integrates a MIM capacitor 308. The semiconductor device 300 can be applied to circuit boards with high capacitance requirements. By collecting overflow capacitance through the MIM capacitor 308, the circuit board can achieve a better large capacitance effect.
[0045] More specifically, the substrate may be, for example, a silicon substrate, or a semiconductor substrate made of other silicon-containing materials.
[0046] In some embodiments, reference Figure 3 The substrate 301 provided in step S11 can be made of a material with a low dielectric constant. For example, the substrate 301 can be formed using a material with a dielectric constant between 1 and 2. The substrate 301 can be etched and deposited to form the first conductive region 3011.
[0047] Furthermore, the substrate 301 may also have a third conductive region 3012. The third conductive region 3012 and the first conductive region 3011 can be prepared in the same process.
[0048] The first conductive region 3011 and the third conductive region 3012 can be set independently, that is, they are electrically isolated from each other. Alternatively, the first conductive region 3011 and the third conductive region 3012 can also be electrically connected through a metal interconnect.
[0049] The first conductive region 3011 and the third conductive region 3012 can be made of metallic materials. For example, the metallic materials can be copper (Cu) or aluminum (Al).
[0050] Furthermore, a first metal interconnect dielectric layer 302 is formed on the surface of the substrate 301 where the first conductive region 3011 and the third conductive region 3012 are formed. The first metal interconnect dielectric layer 302 may be a silicon oxide layer (e.g., SiO2), fluorine-doped silicon oxide (F-SiO2), a low-dielectric-constant material (Low-K), an ultra-low-dielectric-constant material (Ultra Low-K, ULK), a silicon nitride layer (e.g., Si3N4), silicon carbide (SiC), nitrogen-doped silicon carbide (NDC), aluminum nitride (AlN), and combinations thereof.
[0051] Figure 3 An exemplary example is provided using a combination of a high-dielectric-constant layer 3021 and a low-dielectric-constant layer 3022 formed thereon as the first metal interconnect dielectric layer 302. The high-dielectric-constant layer 3021 can be formed using a material with a dielectric constant greater than 5, and the low-dielectric-constant layer 3022 can be formed using a material with a dielectric constant of approximately 1-2. For instance, a high-dielectric-constant material film and a low-dielectric-constant material film can be sequentially deposited on the surface of the substrate 301 using a chemical vapor deposition (CVD) process with tetraethoxysilane (TEOS, chemical formula Si(OC2H5)4) as a precursor to form the high-dielectric-constant layer 3021 and the low-dielectric-constant layer 3022.
[0052] In some embodiments, the fabrication process of the functional device in step S13 can be as follows: Figures 4 to 6 As shown.
[0053] Specifically, refer to Figure 4 The first metal interconnect dielectric layer 302 is etched to form a first via 303, which exposes a first conductive region 3011. An etching process can be used to process the first metal interconnect dielectric layer 302 to form the first via 303, which at least partially exposes the first conductive region 3011.
[0054] Further, refer to Figure 5 A functional device layer 304 is formed on the surface of the first metal interconnect dielectric layer 302 and the first via 303. Atomic layer deposition (ALD) can be used to form the functional device layer 304 on the surface of the first metal interconnect dielectric layer 302 and the first via 303. ALD has a higher sidewall deposition rate, which is beneficial for improving fabrication efficiency.
[0055] The functional device layer 304 may include a conductive layer 3041 and a device dielectric layer 3042. The conductive layer 3041 may be used to form the lower electrode 3081 of the MIM capacitor 308 (e.g., Figure 6(As shown). The device dielectric layer 3042 can be used to form the "I" structure in the MIM capacitor 308.
[0056] For example, a conductive layer 3041 can be formed first on the surface of the first metal interconnect dielectric layer 302 and the first via 303, and then a device dielectric layer 3042 can be formed on the surface of the conductive layer 3041. The conductive layer 3041 and the device dielectric layer 3042 can be formed sequentially using an ALD process.
[0057] The material of the conductive layer 3041 may include titanium nitride (TiN).
[0058] The material of the device dielectric layer 3042 may include a high dielectric constant material.
[0059] Further, refer to Figure 6 A metallic material is filled into the first via 303 to form a functional device within the via 303. A thin-film deposition process can be used to fill the metallic material into the first via 303. The metallic material can be, for example, copper (Cu).
[0060] The first through-hole 303, filled with metallic material, is adapted to form a second conductive region 3043. In an example where the functional device is a MIM capacitor 308, the second conductive region 3043 can be used to form the upper electrode 3082 of the MIM capacitor 308.
[0061] In some embodiments, after step S13, the following step may be performed: removing the functional device layer 304 on the surface of the first metal interconnect dielectric layer 302 using a chemical-mechanical polishing (CMP) process. Specifically, the device dielectric layer 3042 and the conductive layer 3041 on the surface of the first metal interconnect dielectric layer 302 may be removed using a CMP process to obtain the following: Figure 7 The structure shown. Up to this point, after... Figures 4 to 7 The steps can be followed to prepare a functional device with a complete structure, such as the MIM capacitor 308.
[0062] In some embodiments, after CMP processing, the conductive layer 3041, the device dielectric layer 3042, and the second conductive region 3043 of the functional device are at least partially exposed on the surface of the first metal interconnect dielectric layer 302. In an example where the functional device is a MIM capacitor 308, after CMP processing, the lower electrode 3081, the device dielectric layer 3042, and the upper electrode 3082 of the MIM capacitor 308 are at least partially exposed on the surface of the first metal interconnect dielectric layer 302.
[0063] In some embodiments, after step S13, other structures may be prepared in the current layer.
[0064] Specifically, refer to Figure 8 The first metal interconnect dielectric layer 302 can be etched to form a third via 310, which exposes a third conductive region 3012. Dry etching or wet etching processes can be used to process the first metal interconnect dielectric layer 302 to form the third via 310, which at least partially exposes the third conductive region 3012.
[0065] Further, refer to Figure 9 A metal material is filled into the third via 310 to form a second metal interconnect 3072 within the third via 310. The metal material can be filled into the third via 310 using a thin-film deposition process. The metal material can be, for example, copper (Cu).
[0066] In some embodiments, continue to refer to Figure 9 A metal barrier layer 306 can be formed on the surface of the third via 310 first, and then a metal material can be filled into the third via 310 to form the second metal interconnect 3072. The metal barrier layer 306 helps prevent the metal material filling the via from overflowing. For example, the material of the metal barrier layer 306 may include tantalum nitride (TaN).
[0067] Furthermore, after the second metal interconnect 3072 is prepared, the first metal interconnect dielectric layer 302 can be polished using a CMP process to obtain the desired result. Figure 9 The semiconductor device 300 shown has a flat surface.
[0068] Continue to refer to Figure 9 The semiconductor device 300 may include functional devices and a peripheral logic region 309 in the lateral direction. A second metal interconnect 3072 is used to form at least a portion of the metal interconnect structure of the peripheral logic region 309. The functional device may be, for example, a MIM capacitor 308, one end of which is electrically connected to a first conductive region 3011, and the other end is exposed on the surface of the first metal interconnect dielectric layer 302. One end of the second metal interconnect 3072 is electrically connected to a third conductive region 3012, and the other end is exposed on the surface of the first metal interconnect dielectric layer 302.
[0069] In some embodiments, the oxidation process in step S15 can be performed after the functional device is fabricated and before the second metal interconnect 3072 is fabricated. Alternatively, it can be performed after all current layer structures have been fabricated, for example, after the fabrication of the functional device is completed. Figure 9 The semiconductor device 300 shown is then subjected to the S15 oxidation process.
[0070] refer to Figure 10Through the oxidation process in step S15, the portion of the functional device layer 304 exposed on the surface of the first metal interconnect dielectric layer 302 can be converted into oxide. For example, after a CMP process, the functional device layer 304 is directly exposed on the surface of the first metal interconnect dielectric layer 302. After the oxidation process, the portion of the functional device layer 304, especially the conductive layer 3041 near the top, remaining after CMP is converted into an insulating region 3083. Figure 8 In the longitudinal direction of the view, the conductive layer 3041 is no longer directly exposed to the surface of the first metal interconnect dielectric layer 302, and the two are isolated by the insulating region 3083.
[0071] The process parameters for oxidation treatment can meet one or more of the following: process time is selected from 2 to 6 seconds; process temperature is less than 400℃; and the gas is selected from nitrous oxide (N2O) and nitrogen dioxide (NO2).
[0072] For example, an N2O processing step can be added after CMP to convert the portion of the lower electrode 3081 near the surface of the first metal interconnect dielectric layer 302 from TiN to TiON with a high dielectric constant.
[0073] In some embodiments, the oxidation depth of the conductive layer 3041 should not be too deep to avoid affecting device performance, such as the resistive performance of the MIM capacitor 308. Generally, the wear degree of the device dielectric layer 3042 during CMP is greater than the wear degree of the second conductive region 3043 (i.e., the upper electrode 3082) and the conductive layer 3041 (i.e., the lower electrode 3081). In this embodiment, by reasonably setting the process parameters of the oxidation treatment, it is ensured that the depth of the oxidation treatment of the conductive layer 3041 is not less than the wear depth of the device dielectric layer 3042 during CMP.
[0074] The wear depth of the CMP process on the device dielectric layer 3042 can refer to the degree of wear caused to the device dielectric layer 3042 by a single CMP process. For example, the wear depth of the top of the device dielectric layer 3042 by the CMP process performed in the last step of fabricating the functional device in step S13.
[0075] Alternatively, the wear depth of the CMP on the device dielectric layer 3042 can refer to the cumulative depth caused by multiple CMP processes. For example, in step S13, a CMP process is performed at the end to remove excess functional device layer 304 from the surface of the first metal interconnect dielectric layer 302. Subsequently, a CMP process is also performed at the end of the fabrication of the second metal interconnect 3072 to remove excess metal material from the surface of the first metal interconnect dielectric layer 302. Both of these CMP processes will cause wear on the top of the device dielectric layer 3042. In this example, the depth of the insulating region 3083 is greater than the total wear depth of the device dielectric layer 3042 after two CMP processes.
[0076] Therefore, even if the CMP process causes HK damage to the top of the MIM capacitor 308, no leakage path will be created. Even if subsequent OVL deviation causes the upper metal interconnect (i.e., the first metal interconnect 3071) to fall onto the device dielectric layer 3042 or even the lower electrode 3081, the presence of the insulating region 3083 prevents the first metal interconnect 3071 from directly contacting the conductive layer 3041 used to form the lower electrode 3081, thus preventing a short circuit.
[0077] In some embodiments, the process of fabricating the first metal interconnect 3071 in step S17 can be as follows: Figures 11 to 13 As shown.
[0078] Specifically, refer to Figure 11 A second metal interconnect dielectric layer 311 is formed on the surface of the first metal interconnect dielectric layer 302 and the functional device. This can be achieved by... Figure 10 The surface of the semiconductor device 300 shown is sequentially deposited with a high dielectric constant layer 3021 and a low dielectric constant layer 3022 to obtain the following: Figure 11 The second metal interconnect dielectric layer 311 is shown. In some embodiments, the material of the second metal interconnect dielectric layer 311 may be the same as that of the first metal interconnect dielectric layer 302, or the two may be formed using different materials.
[0079] Further, refer to Figure 12 The second metal interconnect dielectric layer 311 is etched to form a second via 305, which at least partially exposes the functional device. Ideally, the second via 305 is aligned with the second conductive region 3043, meaning that the second via 305 exposes only a portion of the surface of the second conductive region 3043. However, in actual processes, the second via 305 may undergo lateral displacement during processes such as etching, resulting in the second via 305 simultaneously exposing both the second conductive region 3043 and the insulating region 3083.
[0080] The second via 305 exposing the insulating region 3083 can specifically include two scenarios: Scenario 1, along the longitudinal direction shown in the figure, the projection of the second via 305 covers the insulating region 3083, the device dielectric layer 3042, and the second conductive region 3043, that is, the second via 305 directly exposes the top surface of the insulating region 3083; Scenario 2, along the longitudinal direction shown in the figure, the projection of the second via 305 only covers the second conductive region 3043 and the device dielectric layer 3042, but the device dielectric layer 3042 is worn in the previous CMP process, causing the insulating region 3083 to be exposed from the side, in other words, the second via 305 exposes the side surface of the insulating region 3083.
[0081] Further, refer to Figure 13Metal material is filled into the second through-hole 305 to form a first metal interconnect 3071 within the second through-hole 305. Similar to the preparation process of the second metal interconnect 3072, a metal barrier layer (not shown) can be formed on the surface of the second through-hole 305 before filling it with metal material to prevent the metal material from overflowing from the second through-hole 305.
[0082] The second conductive region 3043 is electrically connected to the first metal interconnect 3071. In the example where the functional device is a MIM capacitor, the upper plate 3082 is electrically connected to the first metal interconnect 3071.
[0083] Compare Figure 13 and Figure 1 When the second via 305 shifts laterally, without the insulating region 3083, both the second conductive region 3043 and the conductive layer 3041 would be exposed, causing a short circuit between the upper electrode 3082 and the lower electrode 3081 via the first metal interconnect 3071. This embodiment transforms the area of the conductive layer 3041 near the surface into the insulating region 3083, electrically isolating the first metal interconnect 3071 and the conductive layer 3041 from the insulating region 3083. Therefore, even if the first metal interconnect 3071 simultaneously covers both the conductive region 3041 and the insulating region 3082, a short circuit in the functional device will not occur.
[0084] In some embodiments, reference Figure 14 The third metal interconnect 3073 can be fabricated in the second metal interconnect dielectric layer 311 at the position corresponding to the second metal interconnect 3072. The third metal interconnect 3073 and the first metal interconnect 3071 can be completed in the same process or fabricated sequentially. Furthermore, a metal barrier layer (not shown) can also be provided around the third metal interconnect 3073 to prevent the metal material forming the third metal interconnect 3073 from overflowing.
[0085] Furthermore, an upper structure is fabricated above the second metal interconnect dielectric layer 311. The upper structure may include a metal contact A1, electrically connected to the upper plate 3082 of the MIM capacitor 308 via a first metal interconnect 3071. The metal contact A1 is used to connect to an external power supply or to electrically connect to a peripheral logic region 309. The upper structure may also include a metal contact A2, electrically connected to a third conductive region 3012 via a third metal interconnect 3073 and a second metal interconnect 3072.
[0086] Therefore, by adopting this embodiment, after the functional device is fabricated and before the fabrication of other structures, the exposed portion of the functional device, especially the top of the conductive layer 3041, is oxidized to form an insulating region 3082 on the top of the conductive layer 3041. The insulating region 3082 can provide electrical isolation, so even if subsequent processes such as CMP cause HK damage to the top of the functional device, no leakage path will occur. Alternatively, even if subsequent OVL deviation causes the upper metal interconnect (i.e., the first metal interconnect 3071) to fall onto the conductive layer 3041, a short circuit will not occur. As a result, the device performance is further improved.
[0087] In one variation, the first conductive region 3011 and the third conductive region 3012 may be electrically connected. The lower electrode 3081 is powered via the peripheral logic region 309.
[0088] In one variation, after preparing the following... Figure 5 After establishing the structure shown, instead of filling the first via 303 with metal material, the first metal interconnect dielectric layer 302 and the functional device layer 304 are etched using the functional device layer 304 as a mask to form the third via 310. The third via 310 exposes the third conductive region 3012, as shown. Figure 15 As shown.
[0089] Compare Figure 15 and Figure 1 In this variation, after etching the first via 303, only the conductive layer 3041 and the device dielectric layer 3042 for forming the lower electrode 3081 are grown. Then, the third via 310 is etched using the functional device layer 304 as a hard mask. For example, wet etching or dry etching processes can be used to etch the functional device layer 304 and the first metal interconnect dielectric layer 302 to form the third via 310, which at least partially exposes the third conductive region 3012.
[0090] Further, refer to Figure 16 A metal barrier layer 306 is formed on the surface of the first through-hole 303 and the third through-hole 310. (Comparison) Figure 16 and Figure 1 In conventionally manufactured MIM capacitors 108, no metal barrier layer is provided. However, in this variation, a metal barrier layer 306 is covered on the surfaces of both the first via 303 and the third via 310. Using this embodiment, the metal material subsequently filled in the third via 310 and the metal material filled in the first via 303 can be reliably confined within their respective vias by the metal barrier layer 306, which is beneficial for improving device performance.
[0091] Further, refer to Figure 17A thin-film deposition process can be used to fill the first via 303 and the third via 310 with a metallic material. The metallic material can be, for example, copper (Cu). Thus, a functional device and a second metal interconnect 3072 are simultaneously fabricated.
[0092] Furthermore, the surface of the first metal interconnect dielectric layer 302 is oxidized to transform the portion of the conductive layer 3041 near the top into an insulating region 3083. Then, the upper structure is fabricated to obtain the desired result. Figure 18 The semiconductor device 300 shown is compared. Figure 14 and Figure 18 , Figure 18 The semiconductor device 300 shown is compared to Figure 14 The semiconductor device 300 shown has an additional metal barrier layer 306 between the upper electrode 3082 and the device dielectric layer 3042, which is beneficial to further improve the device performance.
[0093] Based on the above, this modified example improves some steps in the preceding and following processes, reducing damage to the functional device and improving device performance. Specifically, after forming the functional device layer 304 and before fabricating the functional device, the functional device layer 304 is used as a mask for etching the third via 310. By introducing some steps of the following process before all steps of the preceding process are completed, damage to the functional device formed in the preceding process is avoided during the etching step in the following process, thus improving the surface morphology of the functional device. Furthermore, metal material is simultaneously filled into the first via 303 and the third via 310 to fabricate the functional device and the second metal interconnect 3072. By integrating the metal filling step of the preceding process and the metal filling step of the following process into the same step, the number of process steps is reduced, the throughput is increased, and the impact of the following process on the preceding process is avoided, thus reducing device damage.
[0094] Furthermore, by adopting the scheme of this variation to reduce the degree of HK damage on the top of the functional device, the degree of oxidation of the conductive layer 3041 during subsequent oxidation treatment can be reduced accordingly, thereby further reducing the impact on the resistive performance of the functional device. For example, the reaction time can be shortened, or other process parameters can be adjusted to regulate the size of the area where the conductive layer 3041 is transformed into the insulating region 3083 (i.e., the depth in the longitudinal direction shown in the figure).
[0095] In another variation, after preparing the following... Figure 3 After the structure shown, the first metal interconnect dielectric layer 302 can be etched to simultaneously form the first via 303 and the third via 310, as shown. Figure 19As shown. For example, photoresist can be coated on the surface of the first metal interconnect dielectric layer 302 to form a photoresist layer; the pattern on the mask is transferred to the photoresist layer by an exposure process. In this example, the pattern on the mask includes at least two windows, one of which exposes the area on the surface of the first metal interconnect dielectric layer 302 corresponding to the first via 303, and the other exposes the area corresponding to the third via 310; the unexposed photoresist is removed by a development process. At this time, the surface of the first metal interconnect dielectric layer 302 is covered with photoresist except for the area corresponding to the first via 303 and the area corresponding to the third via 310; the surface of the first metal interconnect dielectric layer 302 is etched by an etching process to form the first via 303 and the third via 310. For example, wet etching or dry etching processes can be used to etch the first metal interconnect dielectric layer 302 to form the first via 303 that at least partially exposes the first conductive region 3011 and the third via 310 that at least partially exposes the third conductive region 3012.
[0096] Compare Figure 19 and Figure 1 In this embodiment, after the first metal interconnect dielectric layer 302 is prepared, the first via 303 and the third via 310 are formed simultaneously in the same step of the same process. Then, different materials are filled into the two vias respectively by performing subsequent steps to form different functional devices or structures.
[0097] Further, refer to Figure 20 Conductive layer 3041 and device dielectric layer 3042 are sequentially formed on the surfaces of the first metal interconnect dielectric layer 302, the first via 303 and the third via 310.
[0098] Further, refer to Figure 21 A patterned photoresist layer 312 can be formed on the first metal interconnect dielectric layer 302, the patterned photoresist layer 312 filling the first via 303 and exposing the third via 310. This can be reused. Figures 3 to 14 In the illustrated embodiment, the photomask used to form the second metal interconnect 3072 is exposed and developed to obtain... Figure 21 The patterned photoresist layer 312 is shown.
[0099] Further, refer to Figure 22 Using a patterned photoresist layer 312 as a mask, an etching process is employed to process the functional device layer 304 on the surface of the third via 310, thereby removing the functional device layer 304 from the surface of the third via 310. By covering the first via 303 with the patterned photoresist layer 312, damage to the functional device layer 304 within the first via 303 is avoided during the etching process targeting the third via 310, ensuring device performance.
[0100] The conductive layer 3041 and the device dielectric layer 3042 within the third via 310 can be removed by acid etching. For example, the etching process may include a wet etching process, wherein the etching solution used in the wet etching process may include one or more of ammonia, potassium hydroxide aqueous solution, and hydrofluoric acid.
[0101] Furthermore, the patterned photoresist layer 312 is removed to obtain, as shown below. Figure 15 The device structure shown. Thus, by simultaneously forming the first through-hole 303 and the third through-hole 310, the functional device layer 304 is formed only in the first through-hole 303 and not in the third through-hole 310.
[0102] Further, you can refer to Figures 15 to 18 The fabrication process shown continues to produce functional devices, second metal interconnect 3072, first metal interconnect 3071, third metal interconnect 3073, and metal contacts A1 and A2.
[0103] Based on the above, this modified example improves some steps in the preceding and following processes, reducing damage to the functional device and enhancing device performance. Specifically, in the same step of the same process, both the first via 303 and the third via 310 are formed. Subsequently, corresponding materials are filled into the two vias to form the functional device and the second metal interconnect 3072, respectively. By integrating the etching steps of the preceding and following processes, damage to the functional device formed in the preceding process is avoided during the etching step in the following process, thus improving the surface morphology of the functional device. Furthermore, metal material is simultaneously filled into the first via 303 and the third via 310 to fabricate the functional device and the second metal interconnect 3072 together. By integrating the metal filling steps of the preceding and following processes into the same step, the number of process steps is reduced, production capacity is increased, and the impact of the following process on the preceding process is avoided, thus reducing device damage.
[0104] In this embodiment, "high dielectric constant" and "low dielectric constant" are relative dielectric constants. A low dielectric constant typically refers to a dielectric constant below 3.0. A high dielectric constant typically refers to a dielectric constant greater than 3.9.
[0105] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, wherein a first conductive region is formed therein, and the surfaces of the substrate and the first conductive region have a first metal interconnect dielectric layer. A functional device is fabricated on the first conductive region, the functional device including a conductive layer electrically connected to the first conductive region, the conductive layer being exposed on the surface of the first metal interconnect dielectric layer; The portion of the conductive layer exposed on the surface of the first metal interconnect dielectric layer is oxidized to form an insulating region; A first metal interconnect is fabricated on the functional device, and the first metal interconnect is electrically isolated from the conductive layer by the insulating region.
2. The forming method according to claim 1, characterized in that, The functional device fabricated on the first conductive region includes: The first metal interconnect dielectric layer is etched to form a first via, the first via exposing the first conductive region; A conductive layer and a device dielectric layer are sequentially formed on the surface of the first metal interconnect dielectric layer and the first via. The first through hole is filled with a metallic material to form the functional device within the first through hole; The second conductive region formed by the metal material is electrically connected to the first metal interconnect.
3. The forming method according to claim 2, characterized in that, After filling the first through hole with metallic material, the process further includes: The conductive layer and device dielectric layer on the surface of the first metal interconnect dielectric layer are removed by chemical mechanical polishing.
4. The forming method according to claim 2, characterized in that, The conductive layer is made of TiN, and / or the dielectric layer of the device is made of a high dielectric constant material.
5. The forming method according to claim 1, characterized in that, The process parameters for the oxidation treatment satisfy one or more of the following: The process time is selected from 2 seconds to 6 seconds; Process temperature less than 400℃; The gases are selected from N2O and NO2.
6. The forming method according to claim 1, characterized in that, The fabrication of the first metal interconnect on the functional device includes: A second metal interconnect dielectric layer is formed on the surface of the first metal interconnect dielectric layer and the surface of the functional device; The second metal interconnect dielectric layer is etched to form a second via, the second via at least partially exposing the functional device; The second through-hole is filled with a metallic material to form the first metallic interconnect within the second through-hole.
7. The forming method according to claim 6, characterized in that, The functional device further includes a second conductive region exposed on the surface of the first metal interconnect dielectric layer, and the second via simultaneously exposes the insulating region and the second conductive region.
8. The forming method according to claim 1, characterized in that, The substrate further comprises a third conductive region, the surface of which has the first metal interconnect dielectric layer. After the functional device is fabricated but before the first metal interconnect is fabricated, the substrate further comprises: The first metal interconnect dielectric layer is etched to form a third via, the third via exposing the third conductive region; The third through hole is filled with metal material to form a second metal interconnect line within the third through hole; The first metal interconnect dielectric layer was polished using a chemical mechanical polishing process.
9. The forming method according to claim 3 or 8, characterized in that, The functional device further includes a device dielectric layer exposed on the surface of the first metal interconnect dielectric layer, wherein the oxidation depth of the conductive layer in the oxidation process is greater than the wear depth of the device dielectric layer in the chemical mechanical polishing process.
10. A semiconductor device, characterized in that, include: A substrate having a first conductive region formed therein, and the surfaces of the substrate and the first conductive region having a first metal interconnect dielectric layer; A functional device is formed on the first metal interconnect dielectric layer. The functional device includes a conductive layer, one end of which is electrically connected to the first conductive region, and the other end of which has an insulating region between itself and the surface of the first metal interconnect dielectric layer. A first metal interconnect is located above the functional device, and the first metal interconnect is electrically isolated from the conductive layer by the insulating region.
11. The semiconductor device according to claim 10, characterized in that, A first via is formed within the first metal interconnect dielectric layer to form the functional device, the conductive layer is formed on the surface of the first via, and the functional device further includes: The device dielectric layer is located on the surface of the conductive layer; The second conductive region is formed by a metal material filling the first through-hole and is electrically connected to the first metal interconnect, and the device dielectric layer is sandwiched between the conductive layer and the second conductive region.
12. The semiconductor device according to claim 11, characterized in that, The first metal interconnect at least partially covers the device dielectric layer and / or the insulating region.
13. The semiconductor device according to claim 10, characterized in that, Also includes: A second metal interconnect dielectric layer is located on the surface of the first metal interconnect dielectric layer and the functional device, and the first metal interconnect line is formed on the second metal interconnect dielectric layer.
14. The semiconductor device according to claim 10, characterized in that, Also includes: A second metal interconnect is formed on the first metal interconnect dielectric layer, the first metal interconnect dielectric layer also having a third conductive region, one end of the second metal interconnect being electrically connected to the third conductive region, and the other end being exposed on the surface of the first metal interconnect dielectric layer.
15. The semiconductor device according to claim 10, characterized in that, The functional device includes a MIM capacitor.