A power device and a method of manufacturing the same
By employing a layered passivation structure and field plate design in power devices, the compatibility issues between the drift region and the gate are resolved, achieving a high concentration of two-dimensional electron gas and low leakage current, thereby improving the performance and reliability of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INNOSCIENCE (SUZHOU) SEMICON CO LTD
- Filing Date
- 2025-06-20
- Publication Date
- 2026-07-14
AI Technical Summary
In existing power devices, the passivation structure covering the drift region and the gate cannot simultaneously meet the requirements of a high concentration of two-dimensional electron gas in the drift region and a reduction in leakage current at the gate.
A layered passivation structure is adopted, wherein the first passivation structure covers the gate structure and includes an opening to expose the surface of the barrier layer for doping with electronegative atoms, and the second passivation structure further enhances the two-dimensional electron gas concentration and mobility in the drift region, while a field plate is set for electric field modulation.
This technology achieves improved two-dimensional electron gas concentration in the drift region and enhanced dynamic performance of the device while reducing gate leakage current, thereby increasing the breakdown voltage and integration density of the device.
Smart Images
Figure CN120882038B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a power device and its fabrication method. Background Technology
[0002] In existing power devices, the passivation structure covering the drift region and the gate is the same film layer, which cannot simultaneously meet the requirements of a high concentration of two-dimensional electron gas in the drift region and the need to reduce leakage current at the gate. Summary of the Invention
[0003] This invention provides a power device and its fabrication method, which can reduce gate leakage current while increasing the concentration of two-dimensional electron gas in the drift region and the dynamic performance of the device.
[0004] According to one aspect of the present invention, a power device is provided, comprising:
[0005] Substrate;
[0006] The channel layer is located on one side of the substrate;
[0007] Barrier layer, located on the side of the channel layer away from the substrate;
[0008] The gate structure is located on the side of the barrier layer away from the channel layer, and the gate structure covers part of the barrier layer.
[0009] The source is located on the surface of the barrier layer away from the channel layer; the drain is located on the surface of the barrier layer away from the channel layer; the distance between the source and the gate structure is smaller than the distance between the gate structure and the drain.
[0010] A first passivation structure is located on the side of the gate structure away from the substrate, and the first passivation structure covers the gate structure and part of the barrier layer; the first passivation structure includes an opening that exposes the surface of the barrier layer away from the substrate; the opening includes at least a first opening located on the side of the gate structure adjacent to the drain, and the surface of the barrier layer exposed by the opening away from the substrate is doped with electronegative atoms, the electronegativity of which is greater than or equal to that of oxygen atoms.
[0011] The second passivation structure is located on the side of the first passivation structure away from the substrate; the second passivation structure covers the surface of the first passivation structure and the barrier layer exposed by the opening away from the substrate.
[0012] Based on the above embodiments, optionally, the edge of the first opening away from the gate structure is located between the gate structure and the drain; or, the vertical projection of the edge of the first opening away from the gate structure on the substrate is located within the vertical projection of the drain on the substrate; or, the edge of the first opening away from the gate structure is located on the side of the drain away from the gate structure.
[0013] Based on the above embodiments, optionally, the power device further includes:
[0014] The field plate is located on the side of the second passivation structure away from the substrate; the vertical projection of the field plate onto the gate structure covers part of the gate structure and extends between the gate structure and the drain.
[0015] Based on the above embodiments, optionally, the vertical projection of the field plate on the substrate and the vertical projection of the first opening on the substrate do not overlap.
[0016] Based on the above embodiments, optionally, the distance between the vertical projection of the edge of the field plate adjacent to the first opening onto the substrate and the vertical projection of the edge of the field plate adjacent to the first opening onto the substrate is greater than or equal to 50 nm.
[0017] Based on the above embodiments, optionally, the distance between the vertical projection of the edge of the field plate adjacent to the first opening onto the substrate and the vertical projection of the edge of the field plate adjacent to the first opening onto the substrate is 50nm-200nm.
[0018] Based on the above embodiments, optionally, the first passivation structure includes a first strain layer and a first passivation layer; the first strain layer is located on the side of the gate structure away from the substrate, and the first strain layer covers the side of the gate structure, the surface of the gate structure away from the substrate, and part of the surface of the barrier layer away from the substrate; the first passivation layer is located on the side of the first strain layer away from the substrate; the first passivation layer covers the first strain layer.
[0019] The second passivation structure includes a second strain layer and a second passivation layer. The second strain layer is located on the side of the first passivation layer away from the substrate. The second strain layer covers the surface of the first passivation layer away from the substrate and the surface of the barrier layer with the opening exposed away from the substrate. The second passivation layer is located on the side of the second strain layer away from the substrate and covers the second strain layer.
[0020] Based on the above embodiments, optionally, the material of the first strain layer includes aluminum nitride, and the material of the second strain layer includes aluminum nitride.
[0021] Based on the above embodiments, optionally, the materials of the first passivation layer and the second passivation layer include at least one of silicon nitride, silicon oxide, and silicon oxynitride.
[0022] Based on the above embodiments, optionally, the electronegative atom includes at least one of oxygen atom and fluorine atom.
[0023] Based on the above embodiments, optionally, the gate structure includes a doped nitride semiconductor layer and a gate; the doped nitride semiconductor layer is located on the side of the barrier layer away from the substrate; the gate is located on the side of the doped nitride semiconductor layer away from the substrate, and the gate covers a portion of the doped nitride semiconductor layer.
[0024] According to another aspect of the present invention, a method for fabricating a power device is provided, comprising:
[0025] A trench layer is formed on one side of the substrate;
[0026] A barrier layer is formed on the side of the channel layer away from the substrate;
[0027] A gate structure is formed on the side of the barrier layer away from the substrate; the gate structure covers part of the barrier layer;
[0028] A first passivation substructure is formed on the side of the gate structure away from the substrate; the first passivation substructure covers the gate structure and the barrier layer;
[0029] The first passivation substructure is etched to form an opening, thus forming a first passivation structure; the opening exposes the surface of the barrier layer away from the substrate; the opening includes at least the first opening.
[0030] Electronegative atoms are doped on the surface of the barrier layer exposed by the opening, away from the substrate. The electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.
[0031] A second passivation structure is formed on the side of the first passivation structure away from the substrate; the second passivation structure covers the surface of the first passivation structure and the barrier layer with the opening exposed away from the substrate.
[0032] The source and drain are formed on the surface of the barrier layer away from the channel layer; the distance between the source and the gate structure is smaller than the distance between the gate structure and the drain; the first opening is located on the side of the gate structure adjacent to the drain.
[0033] Based on the above embodiments, optionally, electronegative atoms are doped on the surface of the barrier layer exposed at the opening away from the substrate, including:
[0034] Electronegative atoms are doped onto the surface of the barrier layer, which is exposed at an opening, away from the substrate, using a plasma surface treatment process.
[0035] Based on the above embodiments, optionally, the plasma surface treatment process includes placing the surface of the barrier layer with the opening exposed away from the substrate in a plasma atmosphere of oxygen and / or fluorine.
[0036] Based on the above embodiments, optionally, a gate structure is formed on the side of the barrier layer away from the substrate, including:
[0037] A doped nitride semiconductor layer is formed on the side of the barrier layer away from the substrate; the doped nitride semiconductor layer covers part of the barrier layer;
[0038] A gate is formed on the side of the doped nitride semiconductor layer away from the substrate; the gate covers a portion of the doped nitride semiconductor layer.
[0039] Based on the above embodiments, optionally, a first passivation structure is formed on the side of the gate structure away from the substrate, including:
[0040] A first strainor layer is formed on the side of the gate away from the substrate; the first strainor layer covers the side of the gate, the surface of the gate away from the substrate, the surface of the partially doped nitride semiconductor layer away from the substrate, and the surface of the barrier layer not covered by the gate structure away from the substrate.
[0041] A first passivation sublayer is formed on the side of the first strain sublayer away from the substrate; the first passivation sublayer covers the first strain sublayer;
[0042] The first strain layer and the first passivation layer are etched to form an opening, and the first strain layer and the first passivation layer are formed; the first passivation structure includes the first strain layer and the first passivation layer; the first strain layer covers the side of the gate, the surface of the gate away from the substrate, the surface of the partially doped nitride semiconductor layer away from the substrate, and the surface of the partially barrier layer away from the substrate; the first passivation layer covers the first strain layer.
[0043] Based on the above embodiments, optionally, a second passivation structure is formed on the side of the first passivation structure away from the substrate, including:
[0044] A second strain layer is formed on the side of the first passivation layer away from the substrate; the second strain layer covers the surface of the first passivation layer away from the substrate and the surface of the barrier layer with exposed openings away from the substrate;
[0045] A second passivation layer is formed on the side of the second strain layer away from the substrate; the second passivation layer covers the second strain layer.
[0046] Based on the above embodiments, optionally, after forming the second passivation structure on the side of the first passivation structure away from the substrate, the method further includes:
[0047] A field plate is formed on the side of the second passivation structure away from the substrate; the vertical projection of the field plate onto the gate structure covers part of the gate structure and extends between the gate structure and the drain.
[0048] In the power device provided by the embodiments of the present invention, a first passivation structure is located on the side of the gate structure away from the substrate. The first passivation structure covers the gate structure and part of the barrier layer. The first passivation structure provides passivation protection for the gate structure, preventing leakage current. Furthermore, the first passivation structure covers the entire gate structure, preventing damage to the gate structure when electronegative atoms are doped at the first opening, further preventing leakage current. The first passivation structure includes an opening that exposes the surface of the barrier layer away from the substrate. The exposed surface of the barrier layer away from the substrate is doped with electronegative atoms. Due to the strong electronegativity of these atoms, the surface states of the barrier layer in the drift region can be improved, increasing the concentration of two-dimensional electron gas in the drift region, thereby improving the performance of the power device. A second passivation structure is located on the side of the first passivation structure away from the substrate. The second passivation structure covers the first passivation structure and the exposed surface of the barrier layer away from the substrate. The first passivation structure can further enhance the stress on the device, increasing the concentration and mobility of two-dimensional electron gas in the drift region, and improving the dynamic performance of the device.
[0049] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0051] Figure 1 This is a schematic diagram of the structure of a power device provided in an embodiment of the present invention.
[0052] Figure 2 This is a schematic diagram of the structure of a power device provided in an embodiment of the present invention.
[0053] Figure 3 This is a schematic diagram of another power device provided in an embodiment of the present invention.
[0054] Figure 4 This is a flowchart of a method for fabricating a power device according to an embodiment of the present invention.
[0055] Figures 5-9 This is a schematic diagram of the intermediate structure of a power device provided in an embodiment of the present invention. Detailed Implementation
[0056] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0057] It should be noted that the terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0058] This invention provides a power device. Figure 1 This is a schematic diagram of the structure of a power device provided in an embodiment of the present invention, for reference. Figure 1 The power device includes: a substrate 10; a channel layer 20 located on one side of the substrate 10; a barrier layer 30 located on the side of the channel layer 20 away from the substrate 10; a gate structure 40 located on the side of the barrier layer 30 away from the channel layer 20, and the gate structure 40 partially covers the barrier layer 30; a source 80 located on the surface of the barrier layer 30 away from the channel layer 20; a drain 90 located on the surface of the barrier layer 30 away from the channel layer 20; the distance D1 between the source 80 and the gate structure 40 is smaller than the distance D2 between the gate structure 40 and the drain 90; and a first passivation structure 50 located on the side of the gate structure 40. On the side away from the substrate 10, a first passivation structure 50 covers the gate structure 40 and a portion of the barrier layer 30; the first passivation structure 50 includes an opening that exposes the surface of the barrier layer 30 away from the substrate 10; the opening includes at least a first opening K1 located on the side of the gate structure 40 adjacent to the drain 90; the surface of the barrier layer 30 exposed by the opening is doped with electronegative atoms, the electronegativity of which is greater than or equal to that of oxygen atoms; a second passivation structure 60 is located on the side of the first passivation structure 50 away from the substrate 10; the second passivation structure 60 covers the first passivation structure 50 and the surface of the barrier layer 30 exposed by the opening away from the substrate 10.
[0059] The substrate 10 can be a silicon substrate or a silicon carbide substrate; the channel layer 20 can be made of gallium nitride; and the barrier layer 30 can be made of AlGaN. The gate structure 40 may include a doped nitride semiconductor layer 41 and a gate 42. The first passivation structure 50 may include a first strain layer 51 and a first passivation layer 52, covering the gate structure 40 and the surface of the barrier layer 30 not covered by the gate structure 40 away from the substrate 10. The first passivation structure 50 is relatively thick and completely surrounds the gate structure 40, providing better passivation protection and thus reducing gate leakage. Furthermore, the first passivation structure 50 has an opening, for example, the opening can be located at... Figure 1 The first opening K1 located between the gate structure 40 and the drain 90 is experimentally examined. It was found that when electronegative atoms are doped onto the surface of the barrier layer 30 away from the substrate 10 at the first opening K1, the electronegativity of the doped atoms is greater than or equal to that of oxygen atoms, meaning these doped electronegative atoms have strong oxidizing properties. During the doping process of these electronegative atoms onto the surface of the barrier layer 30, oxidation and interface improvement are achieved, which can improve the surface states of the barrier layer 30 in the drift region, increase the concentration of the two-dimensional electron gas in the drift region, and thus improve the performance of the power device. This application uses a first passivation structure 50 and a second passivation structure 60 to achieve separate modulation of the gate structure 40 and the drift region. Furthermore, the first passivation structure 50 can passivate and protect the gate structure 40, preventing leakage current in the gate structure 40. Furthermore, the first passivation structure 50 covers the entire gate structure 40, thus preventing damage to the gate structure 40 region from the highly oxidizing plasma, such as oxygen or fluorine gas, corresponding to the electronegative atoms, when the surface of the barrier layer 30 at the first opening K1 away from the substrate 10 is doped with strongly oxidizing electronegative atoms, further preventing leakage current in the gate structure 40. The second passivation structure 60 may include a second stress layer 61 and a second passivation layer 62. The second passivation structure 60 can further enhance the stress in the drift region, increase the two-dimensional electron gas concentration and mobility in the drift region, and improve the dynamic performance of the device.
[0060] In power devices, since the drain 90 is generally set with a large voltage, the distance D2 between the drain 90 and the gate structure 40 needs to be relatively large to facilitate the subsequent design of structures such as the field plate 70, reduce the electric field concentration phenomenon of the device, and improve the breakdown voltage of the device. However, at the same time, in order to achieve miniaturization and integration of the device, the distance between the source 80 and the gate structure 40 needs to be set relatively small. Therefore, the distance D1 between the source 80 and the gate structure 40 is set smaller than the distance D2 between the gate structure 40 and the drain 90. While ensuring the miniaturization and integration of the device, the breakdown voltage of the device can be improved.
[0061] The opening includes at least a first opening K1, located on the side of the gate structure 40 adjacent to the drain 90; the opening may also include a second opening, located on the side of the gate structure 40 adjacent to the source 80. Since the distance D1 between the source 80 and the gate structure 40 is smaller than the distance D2 between the gate structure 40 and the drain 90, the first opening K1 is located on the side of the gate structure 40 adjacent to the drain 90, resulting in a larger distance D2 between the gate structure 40 and the drain 90. This simplifies the etching process and simultaneously increases the two-dimensional electron gas concentration in the drift region.
[0062] In the power device provided by the embodiment of the present invention, the first passivation structure 50 is located on the side of the gate structure 40 away from the substrate 10, and the first passivation structure 50 covers the gate structure 40 and part of the barrier layer 30. The first passivation structure 50 can passivate and protect the gate structure 40, preventing leakage. Furthermore, the first passivation structure 50 covers the entire gate structure 40, preventing damage to the gate structure 40 when electronegative atoms are doped at the first opening K1, further preventing leakage. The first passivation structure 50 includes an opening that exposes the surface of the barrier layer 30 away from the substrate 10. The exposed surface of the barrier layer 30 away from the substrate 10 is doped with electronegative atoms. Since the electronegativity of these atoms is relatively strong, it can improve the surface states of the barrier layer 30 in the drift region, increase the concentration of the two-dimensional electron gas in the drift region, and thus improve the performance of the power device. The second passivation structure 60 is located on the side of the first passivation structure 50 away from the substrate 10; the second passivation structure 60 covers the surface of the first passivation structure 50 and the exposed barrier layer 30 away from the substrate 10; the first passivation structure 60 can further enhance the stress of the device, increase the two-dimensional electron gas concentration and mobility in the drift region, and improve the dynamic performance of the device.
[0063] Based on the above embodiments, optionally, refer to Figure 1 The edge of the first opening K1 away from the gate structure 40 is located between the gate structure 40 and the drain 90; or, Figure 2 This is a schematic diagram of the structure of a power device provided in an embodiment of the present invention, for reference. Figure 2 The vertical projection of the edge of the first opening K1 away from the gate structure 40 onto the substrate 10 lies within the vertical projection of the drain 90 onto the substrate 10; or, Figure 3 This is a schematic diagram of the structure of a power device provided in an embodiment of the present invention, for reference. Figure 3 The edge of the first opening K1 away from the gate structure 40 is located on the side of the drain 90 away from the gate structure 40.
[0064] The larger the range of the first opening K1, the better the effect on improving the two-dimensional electron gas concentration and mobility in the drift region. As long as the vertical projection of the field plate 70 onto the substrate 10 does not overlap with the vertical projection of the opening onto the substrate 10, and the effect of electric field modulation is avoided when electronegative atoms are doped at the opening, the range of the first opening K1 can be set according to requirements. If the region between the gate structure 40 and the drain 90 includes multiple field plates 70, multiple first openings K1 can also be set. While increasing the area of the first opening K1, the overlap between the vertical projection of the field plate 70 onto the substrate 10 and the vertical projection of the opening onto the substrate 10 can be avoided, and the effect of electric field modulation is avoided when electronegative atoms are doped at the opening.
[0065] Based on the above embodiments, optionally, refer to Figure 1 Field plate 70 is located on the side of the second passivation structure 60 away from the substrate 10; the vertical projection of field plate 70 on the gate structure 40 covers part of the gate structure 40 and extends between the gate structure 40 and the drain 90.
[0066] The field plate 70 can be made of metal and can be used for electric field modulation to avoid electric field concentration between the gate structure 40 and the drain 90, thereby improving the breakdown voltage of the device. Since the voltage between the gate structure 40 and the drain 90 is relatively large, the vertical projection of the field plate 70 onto the gate structure 40 covers a portion of the gate structure 40 and extends between the gate structure 40 and the drain 90, resulting in better electric field modulation and further improving the breakdown voltage of the device.
[0067] Based on the above embodiments, optionally, refer to Figure 1 The vertical projection of the field plate 70 onto the substrate 10 does not overlap with the vertical projection of the first opening K1 onto the substrate 10.
[0068] Specifically, the vertical projection of the field plate 70 onto the substrate 10 does not overlap with the vertical projection of the opening onto the substrate 10. This avoids affecting the effect of electric field modulation when electronegative atoms are doped at the first opening K1. By ensuring that the vertical projection of the field plate 70 onto the substrate 10 does not overlap with the vertical projection of the first opening onto the substrate 10, the first passivation structure 50 can reduce gate leakage current, while the second passivation structure 60 can further enhance the stress in the drift region, increasing the two-dimensional electron gas concentration and mobility in the drift region, thereby improving the dynamic performance of the device. Furthermore, doping electronegative atoms at the first opening K1 increases the concentration of the two-dimensional electron gas in the drift region, improving the forward performance of the device. At the same time, the field plate 70 can also increase the breakdown voltage of the device.
[0069] Based on the above embodiments, optionally, refer to Figure 1The distance D3 between the vertical projection of the edge of the field plate 70 adjacent to the opening onto the substrate 10 and the vertical projection of the edge of the field plate 70 adjacent to the opening onto the substrate 10 is greater than or equal to 50 nm.
[0070] Specifically, the distance D3 between the vertical projection of the edge of the field plate 70 adjacent to the opening onto the substrate 10 and the vertical projection of the edge of the field plate 70 adjacent to the opening onto the substrate 10 should be greater than or equal to 50nm. This is to avoid the overlap between the vertical projection of the field plate 70 onto the substrate 10 and the vertical projection of the opening onto the substrate 10 due to process errors. This can also prevent the effect of electric field modulation when electronegative atoms are doped at the opening from affecting the effect of electric field modulation.
[0071] Based on the above embodiments, optionally, the distance between the vertical projection of the edge of the first opening K1 adjacent to the field plate 70 onto the substrate 10 and the vertical projection of the edge of the field plate 70 adjacent to the first opening K1 onto the substrate 10 is 50nm-200nm.
[0072] The distance between the vertical projection of the edge of the first opening K1 adjacent to the field plate 70 onto the substrate 10 and the vertical projection of the edge of the field plate 70 adjacent to the first opening K1 onto the substrate 10 is 50nm-200nm, which makes the process simpler and the device more integrated.
[0073] Based on the above embodiments, optionally, the first passivation structure 50 includes a first strain layer 51 and a first passivation layer 52; the first strain layer 51 is located on the side of the gate structure 40 away from the substrate 10, and the first strain layer 51 covers the side of the gate structure 40, the surface of the gate structure 40 away from the substrate 10, and part of the surface of the barrier layer 30 away from the substrate 10; the first passivation layer 52 is located on the side of the first strain layer 51 away from the substrate 10; the first passivation layer 52 covers the first strain layer 51; the second passivation structure 60 includes a second strain layer 61 and a second passivation layer 62, the second strain layer 61 is located on the side of the first passivation layer 52 away from the substrate 10, and the second strain layer 61 covers the surface of the first passivation layer 52 away from the substrate 10 and the surface of the barrier layer 30 exposed by the opening K1 away from the substrate 10; the second passivation layer 62 is located on the side of the second strain layer 61 away from the substrate 10, and the second passivation layer 62 covers the second strain layer 61.
[0074] The materials of the first strain layer 51 and the second strain layer 61 can be the same or different. The materials of the first passivation layer 52 and the second passivation layer 62 can be the same or different. The first strain layer 50 can protect the gate structure 40 and reduce gate leakage current. The first passivation layer 60 can passivate and protect the gate structure 40. Covering the gate structure 40 with the first strain layer 51 and the first passivation layer 52 increases the number of protective layers on the surface and sides of the gate structure 40 away from the substrate 10, resulting in better passivation and device performance. The second strain layer 70 covers the drift region at the opening and can be used to increase the stress of the device, increase the two-dimensional electron gas concentration and mobility, and effectively improve the dynamic performance of the device. The second passivation layer 62 can passivate and protect the device, facilitating the subsequent formation of the field plate and ensuring insulation between the field plate and the gate structure.
[0075] Based on the above embodiments, optionally, refer to Figure 1 Electronegative atoms include at least one of oxygen and fluorine atoms.
[0076] Among them, at least one of oxygen atoms and fluorine atoms can improve the surface states of the barrier layer 30 in the drift region, increase the two-dimensional electron gas concentration and mobility, and effectively improve the dynamic performance of the device.
[0077] Based on the above embodiments, optionally, the material of the first strain layer 51 includes aluminum nitride, and the material of the second strain layer 61 includes aluminum nitride.
[0078] Among them, aluminum nitride is an excellent stress-enhancing and insulating material. It can also repair damaged interfaces, increase the concentration of two-dimensional electron gas, reduce gate leakage current, and improve device performance.
[0079] Based on the above embodiments, optionally, the material of the first passivation layer 52 and the material of the second passivation layer 62 include at least one of silicon nitride, silicon oxide, and silicon oxynitride.
[0080] Silicon oxide, silicon nitride, and silicon oxynitride can serve as passivation protection. They can be used as the first passivation layer 52 to isolate and protect the gate structure 40, reducing leakage current. They can also be used as the second passivation layer 62 to isolate the gate structure 40 and the field plate 70.
[0081] Based on the above embodiments, optionally, refer to Figure 1 The distance D1 between the source 80 and the gate structure 40 is 150nm-250nm; the distance D2 between the gate structure 40 and the drain 90 is 0.6μm-10μm.
[0082] The distance D1 between the source 80 and the gate structure 40 is 150nm-250nm; the distance D2 between the gate structure 40 and the drain 90 is 0.6μm-10μm. In order to ensure the miniaturization and integration of the device, the process can be simplified, the gate leakage current can be reduced, the two-dimensional electron gas concentration and mobility can be increased, and the breakdown voltage of the device can be improved.
[0083] Based on the above embodiments, optionally, the gate structure 40 includes a doped nitride semiconductor layer 41 and a gate 42; the doped nitride semiconductor layer 41 is located on the side of the barrier layer 30 away from the substrate 10; the gate 42 is located on the side of the doped nitride semiconductor layer 41 away from the substrate 10, and the gate 42 covers part of the doped nitride semiconductor layer 41.
[0084] The doped nitride semiconductor layer 41 can be a P-type gallium nitride layer, and the gate 42 can be a titanium nitride layer. The first strain layer 51 covers the side of the gate 42, the surface of the gate 42 away from the substrate 10, the surface of the partially doped nitride semiconductor layer 41 away from the substrate 10, and the surface of the partially barrier layer 30 away from the substrate 10. The first strain layer 51 is used to protect the gate from leakage current and improve device performance.
[0085] Based on the above embodiments, this invention provides a method for fabricating a power device, used to fabricate the power device described in any embodiment of this invention. Figure 4 This is a flowchart of a method for fabricating a power device according to an embodiment of the present invention. Figures 5-9 This is a schematic diagram of an intermediate structure of a power device provided in an embodiment of the present invention, for reference. Figures 4-9 The preparation methods include:
[0086] S110, A trench layer is formed on one side of the substrate.
[0087] Among them, reference Figure 5 A channel layer 20 can be epitaxially grown on one side of the substrate 10; the channel layer 20 covers the substrate 10. The substrate 10 can be made of silicon or silicon carbide; the channel layer 20 can be made of gallium nitride.
[0088] S120. A barrier layer is formed on the side of the channel layer away from the substrate.
[0089] Among them, reference Figure 5 The material of the barrier layer 30 can be AlGaN. The barrier layer 30 can be epitaxially grown on the side of the channel layer 20 away from the substrate 10, and the barrier layer 30 covers the channel layer 20.
[0090] S130. A gate structure is formed on the side of the barrier layer away from the substrate; the gate structure covers part of the barrier layer.
[0091] Among them, reference Figure 5 A doped nitride semiconductor layer 41 can be formed first, and then a gate 42 can be formed. A gate structure 40 can be formed by photolithography etching process. The gate structure 40 includes a doped nitride semiconductor layer 41 and a gate 42.
[0092] S140. A first passivation substructure is formed on the side of the gate structure away from the substrate; the first passivation substructure covers the gate structure and the barrier layer.
[0093] S150, Etch the first passivation substructure to form an opening, forming the first passivation structure; The opening exposes the surface of the barrier layer away from the substrate; The opening includes at least the first opening.
[0094] Among them, reference Figures 6-8 The first passivation structure 50 is formed through deposition and etching processes. An opening is formed through etching.
[0095] S160. Electronegative atoms are doped on the surface of the barrier layer exposed by the opening away from the substrate, and the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.
[0096] Among them, reference Figure 8 By doping the surface of the barrier layer 30 exposed at the opening away from the substrate with electronegative atoms, including at least one of oxygen and fluorine atoms, the surface states of the barrier layer 30 at the drift region can be improved, increasing the concentration of the two-dimensional electron gas in the drift region, thereby enhancing the performance of the power device. Furthermore, since the first passivation structure 50 passivates and protects the gate structure 40 when electronegative atoms are doped at the opening, leakage current in the gate structure 40 can be avoided.
[0097] S170, a second passivation structure is formed on the side of the first passivation structure away from the substrate; the second passivation structure covers the surface of the first passivation structure and the barrier layer exposed by the opening away from the substrate.
[0098] Among them, reference Figure 9 and Figure 1 The second passivation structure 60 is formed through deposition and etching processes.
[0099] S180, A source and a drain are formed on the surface of the barrier layer away from the channel layer; the distance between the source and the gate structure is less than the distance between the gate structure and the drain; the first opening is located on the side of the gate structure adjacent to the drain.
[0100] Among them, reference Figure 1 Through-holes can be formed by etching, extending to the barrier layer, and then the source 80 and drain 90 are formed.
[0101] The power device fabrication method provided by this invention includes a first passivation structure located on the side of the gate structure away from the substrate. The first passivation structure covers the gate structure and part of the barrier layer. This first passivation structure provides passivation protection for the gate structure, preventing leakage. Furthermore, by covering the entire gate structure, it avoids damage to the gate structure when electronegative atoms are doped at the first opening, further preventing leakage. The first passivation structure includes an opening that exposes the surface of the barrier layer away from the substrate. Electronegative atoms are doped onto the exposed surface of the barrier layer away from the substrate. Due to the strong electronegativity of these atoms, the surface states of the barrier layer in the drift region are improved, increasing the concentration of two-dimensional electron gas in the drift region, thereby enhancing the performance of the power device. A second passivation structure is located on the side of the first passivation structure away from the substrate. This second passivation structure covers the first passivation structure and the exposed surface of the barrier layer away from the substrate. The first passivation structure can further enhance the stress on the device, increasing the concentration and mobility of two-dimensional electron gas in the drift region, thus improving the dynamic performance of the device.
[0102] Based on the above embodiments, optionally, electronegative atoms are doped on the surface of the barrier layer exposed at the opening away from the substrate, including:
[0103] Electronegative atoms are doped onto the surface of the barrier layer, which is exposed at an opening, away from the substrate, using a plasma surface treatment process.
[0104] Among them, reference Figure 8 The surface of the barrier layer 30 exposed at the opening, away from the channel layer 20, is doped with at least one of oxygen atoms and fluorine atoms. At least one of oxygen atoms and fluorine atoms can improve the surface states of the barrier layer 30 in the drift region, increase the concentration of the two-dimensional electron gas in the drift region, and thus improve the performance of the power device. Here, electronegative atoms are doped onto the surface of the barrier layer 30 away from the channel layer 20 using a plasma surface treatment process, and the surface of the barrier layer 30 away from the channel layer 20 undergoes interface treatment. The concentration of electronegative atoms inside the barrier layer 202 is negligible. For example, if oxygen atoms are doped onto the surface of the barrier layer 30 away from the channel layer 20, oxygen treatment can be performed on the surface of the barrier layer 30 exposed at the opening, away from the channel layer 20.
[0105] Based on the above embodiments, optionally, the plasma surface treatment process includes placing the surface of the barrier layer with the opening exposed away from the substrate in a plasma atmosphere of oxygen and / or fluorine.
[0106] In this method, placing the exposed surface of the barrier layer away from the substrate in a plasma atmosphere of oxygen and / or fluorine can dope the exposed surface of the barrier layer away from the channel layer with oxygen and / or fluorine atoms. At least one of oxygen and fluorine atoms can improve the surface states of the barrier layer in the drift region, increase the concentration of two-dimensional electron gas in the drift region, and thus improve the performance of the power device.
[0107] Based on the above embodiments, optionally, the present invention provides a flowchart of another method for fabricating a power device, the method comprising:
[0108] S110, A trench layer is formed on one side of the substrate.
[0109] S120. A barrier layer is formed on the side of the channel layer away from the substrate.
[0110] S131. A doped nitride semiconductor layer is formed on the side of the barrier layer away from the substrate; the doped nitride semiconductor layer covers part of the barrier layer.
[0111] Among them, reference Figure 5 The doped nitride semiconductor layer 41 can be a P-type gallium nitride layer. The doped nitride semiconductor material layer can be deposited first, and then photolithography can be performed to form the doped nitride semiconductor layer 41, so that the doped nitride semiconductor layer 41 covers part of the barrier layer 30.
[0112] S132. A gate is formed on the side of the doped nitride semiconductor layer away from the substrate; the gate covers a portion of the doped nitride semiconductor layer.
[0113] Among them, reference Figure 5 The gate 42 can be pre-deposited on the doped nitride semiconductor layer 41, and then the gate 42 can be etched by photolithography to form the gate 42.
[0114] S141. A first strainor layer is formed on the side of the gate away from the substrate; the first strainor layer covers the side of the gate, the surface of the gate away from the substrate, the surface of the partially doped nitride semiconductor layer away from the substrate, and the surface of the barrier layer not covered by the gate structure away from the substrate.
[0115] Among them, reference Figure 6 The first strain quanta layer 501 is formed by a deposition process. The material of the first strain quanta layer 501 includes aluminum nitride.
[0116] S142, A first passivation sublayer is formed on the side of the first strain sublayer away from the substrate; the first passivation sublayer covers the first strain sublayer.
[0117] Among them, reference Figure 7A first passivation sublayer 502 is formed through a deposition process. The material of the first passivation sublayer 502 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.
[0118] S151. Etch the first strain sublayer and the first passivation sublayer to form an opening, and form the first strain layer and the first passivation layer; the first passivation structure includes the first strain layer and the first passivation layer; the first strain layer covers the side of the gate, the surface of the gate away from the substrate, the surface of the partially doped nitride semiconductor layer away from the substrate, and the surface of the partially barrier layer away from the substrate; the first passivation layer covers the first strain layer.
[0119] Among them, reference Figure 7 and Figure 8 The first strain layer 501 and the first passivation layer 502 are etched by photolithography to form an opening, thereby forming the first strain layer 51 and the first passivation layer 52.
[0120] S160, Electronegative atoms are doped on the surface of the barrier layer exposed at the opening, away from the substrate.
[0121] In this application, when electronegative atoms are doped on the surface of the barrier layer away from the substrate through plasma surface treatment, the specific process is as follows: the surface of the barrier layer away from the substrate is placed in a plasma atmosphere of oxygen and / or fluorine. In this process, since the entire device is placed in a plasma atmosphere, the function of the first passivation layer 52 is to isolate the first strain layer 51 and the gate structure from the plasma atmosphere, thereby preventing them from being damaged by the plasma. In other words, without the first passivation layer 52, the surface of the first strain layer 51 would be exposed to the plasma atmosphere, and the effect of reducing the gate leakage current would not be achieved.
[0122] S171, A second strain layer is formed on the side of the first passivation layer away from the substrate; the second strain layer covers the surface of the first passivation layer away from the substrate and the surface of the barrier layer exposed by the opening away from the substrate.
[0123] Among them, reference Figure 9 A second strain layer 61 is formed by a deposition process. The material of the second strain layer includes aluminum nitride.
[0124] S172, A second passivation layer is formed on the side of the second strain layer away from the substrate; the second passivation layer covers the second strain layer.
[0125] Among them, reference Figure 1 A second passivation layer 62 is formed by a deposition process. The material of the second passivation sublayer 62 includes at least one of silicon nitride and silicon oxide.
[0126] S190, a field plate is formed on the side of the second passivation structure away from the substrate; the vertical projection of the field plate on the gate structure covers the gate structure and extends between the gate structure and the drain; the vertical projection of the field plate on the substrate and the vertical projection of the opening on the substrate do not overlap.
[0127] Among them, reference Figure 1 Field plates 70 can be formed through deposition and etching processes.
[0128] S180, A source and a drain are formed on the surface of the barrier layer away from the channel layer; the distance between the source and the gate structure is less than the distance between the gate structure and the drain; the first opening is located on the side of the gate structure adjacent to the drain.
[0129] Optionally, the edge of the first opening away from the gate structure is located between the gate structure and the drain; or, the vertical projection of the edge of the first opening away from the gate structure on the substrate is located within the vertical projection of the drain on the substrate; or, the edge of the first opening away from the gate structure is located on the side of the drain away from the gate structure.
[0130] Optionally, the distance between the vertical projection of the edge of the first opening adjacent to the field plate onto the substrate and the vertical projection of the edge of the field plate adjacent to the first opening onto the substrate is greater than or equal to 50 nm.
[0131] Optionally, the distance between the vertical projection of the edge of the field plate adjacent to the first opening onto the substrate and the vertical projection of the edge of the field plate adjacent to the first opening onto the substrate is 50nm-200nm.
[0132] Optionally, the opening may also include a second opening located between the gate structure and the source.
[0133] Optionally, the distance between the source and gate structures is 150nm-250nm; the distance between the gate structure and the drain is 0.6μm-10μm.
[0134] The method for fabricating the power device provided in this embodiment of the invention has the same beneficial effects as the power device provided in any embodiment of the invention.
[0135] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0136] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A power device, characterized in that, include: Substrate; A channel layer, wherein the channel layer is located on one side of the substrate; A barrier layer, the barrier layer being located on the side of the channel layer away from the substrate; A gate structure, wherein the gate structure is located on the side of the barrier layer away from the channel layer, and the gate structure covers a portion of the barrier layer; The source is located on the surface of the barrier layer away from the channel layer; the drain is located on the surface of the barrier layer away from the channel layer; the distance between the source and the gate structure is smaller than the distance between the gate structure and the drain. A first passivation structure is located on the side of the gate structure away from the substrate, and the first passivation structure covers the gate structure and part of the barrier layer. The first passivation structure includes an opening that exposes the surface of the barrier layer away from the substrate; the opening includes at least a first opening located on the side of the gate structure adjacent to the drain, the surface of the barrier layer exposed by the opening away from the substrate being doped with electronegative atoms, the electronegativity of which is greater than or equal to that of oxygen atoms; A second passivation structure is located on the side of the first passivation structure away from the substrate; The second passivation structure covers the surface of the first passivation structure and the barrier layer exposed by the opening away from the substrate.
2. The power device according to claim 1, characterized in that, The edge of the first opening away from the gate structure is located between the gate structure and the drain; or, the vertical projection of the edge of the first opening away from the gate structure on the substrate is located within the vertical projection of the drain on the substrate; or, the edge of the first opening away from the gate structure is located on the side of the drain away from the gate structure.
3. The power device according to claim 1, characterized in that, The power device further includes: A field plate is located on the side of the second passivation structure away from the substrate; the vertical projection of the field plate onto the gate structure covers a portion of the gate structure and extends between the gate structure and the drain.
4. The power device according to claim 3, characterized in that, The vertical projection of the field plate onto the substrate does not overlap with the vertical projection of the first opening onto the substrate.
5. The power device according to claim 4, characterized in that, The distance between the vertical projection of the edge of the first opening adjacent to the field plate onto the substrate and the vertical projection of the edge of the field plate adjacent to the first opening onto the substrate is greater than or equal to 50 nm.
6. The power device according to claim 5, characterized in that, The distance between the vertical projection of the edge of the first opening adjacent to the field plate onto the substrate and the vertical projection of the edge of the field plate adjacent to the first opening onto the substrate is 50nm-200nm.
7. The power device according to claim 1, characterized in that, The first passivation structure includes a first strain layer and a first passivation layer; the first strain layer is located on the side of the gate structure away from the substrate, and the first strain layer covers the side of the gate structure, the surface of the gate structure away from the substrate, and a portion of the barrier layer away from the substrate. The first passivation layer is located on the side of the first strain layer away from the substrate; The first passivation layer covers the first strain layer; The second passivation structure includes a second strain layer and a second passivation layer. The second strain layer is located on the side of the first passivation layer away from the substrate. The second strain layer covers the surface of the first passivation layer away from the substrate and the surface of the barrier layer exposed by the opening away from the substrate. The second passivation layer is located on the side of the second strain layer away from the substrate, and the second passivation layer covers the second strain layer.
8. The power device according to claim 7, characterized in that, The first strain layer is made of aluminum nitride, and the second strain layer is made of aluminum nitride.
9. The power device according to claim 7, characterized in that, The materials of the first passivation layer and the second passivation layer include at least one of silicon nitride, silicon oxide, and silicon oxynitride.
10. The power device according to claim 1, characterized in that, The electronegative atom includes at least one of oxygen and fluorine atoms.
11. The power device according to claim 1, characterized in that, The gate structure includes a doped nitride semiconductor layer and a gate; the doped nitride semiconductor layer is located on the side of the barrier layer away from the substrate; the gate is located on the side of the doped nitride semiconductor layer away from the substrate, and the gate covers a portion of the doped nitride semiconductor layer.
12. A method for fabricating a power device, characterized in that, include: A trench layer is formed on one side of the substrate; A barrier layer is formed on the side of the channel layer away from the substrate; A gate structure is formed on the side of the barrier layer away from the substrate; the gate structure covers a portion of the barrier layer; A first passivation substructure is formed on the side of the gate structure away from the substrate; The first passivation substructure covers the gate structure and the barrier layer; The first passivation substructure is etched to form an opening, thus forming a first passivation structure; the opening exposes the surface of the barrier layer away from the substrate; the opening includes at least a first opening. Electronegative atoms are doped on the surface of the barrier layer exposed by the opening away from the substrate, the electronegativity of the electronegative atoms being greater than or equal to that of oxygen atoms; A second passivation structure is formed on the side of the first passivation structure away from the substrate; the second passivation structure covers the surface of the first passivation structure and the barrier layer exposed by the opening away from the substrate. A source and a drain are formed on the surface of the barrier layer away from the channel layer; The distance between the source and the gate structure is less than the distance between the gate structure and the drain; the first opening is located on the side of the gate structure adjacent to the drain.
13. The method for fabricating a power device according to claim 12, characterized in that, The surface of the barrier layer exposed by the opening, away from the substrate, is doped with electronegative atoms, including: Electronegative atoms are doped onto the surface of the barrier layer exposed at the opening, away from the substrate, using a plasma surface treatment process.
14. The method for fabricating a power device according to claim 13, characterized in that, The plasma surface treatment process includes placing the surface of the barrier layer exposed by the opening away from the substrate in a plasma atmosphere of oxygen and / or fluorine.
15. The method for fabricating a power device according to claim 12, characterized in that, A gate structure is formed on the side of the barrier layer away from the substrate, comprising: A doped nitride semiconductor layer is formed on the side of the barrier layer away from the substrate; the doped nitride semiconductor layer covers a portion of the barrier layer; A gate is formed on the side of the doped nitride semiconductor layer away from the substrate; the gate covers a portion of the doped nitride semiconductor layer.
16. The method for fabricating a power device according to claim 15, characterized in that, A first passivation substructure is formed on the side of the gate structure away from the substrate, comprising: A first strainor layer is formed on the side of the gate away from the substrate; the first strainor layer covers the side of the gate, the surface of the gate away from the substrate, a portion of the surface of the doped nitride semiconductor layer away from the substrate, and the surface of the barrier layer not covered by the gate structure away from the substrate. A first passivation sublayer is formed on the side of the first strain sublayer away from the substrate; the first passivation sublayer covers the first strain sublayer; Etching the first passivation substructure to form an opening, forming the first passivation structure, includes: The first strain sublayer and the first passivation sublayer are etched to form an opening, and to form a first strain layer and a first passivation layer; the first passivation structure includes a first strain layer and a first passivation layer; the first strain layer covers the side of the gate, the surface of the gate away from the substrate, a portion of the surface of the doped nitride semiconductor layer away from the substrate, and a portion of the surface of the barrier layer away from the substrate; the first passivation layer covers the first strain layer.
17. The method for fabricating a power device according to claim 16, characterized in that, A second passivation structure is formed on the side of the first passivation structure away from the substrate, comprising: A second strain layer is formed on the side of the first passivation layer away from the substrate; the second strain layer covers the surface of the first passivation layer away from the substrate and the surface of the barrier layer exposed by the opening away from the substrate; A second passivation layer is formed on the side of the second strain layer away from the substrate; the second passivation layer covers the second strain layer.
18. The method for fabricating a power device according to claim 17, characterized in that, After forming a second passivation structure on the side of the first passivation structure away from the substrate, the method further includes: A field plate is formed on the side of the second passivation structure away from the substrate; the vertical projection of the field plate onto the gate structure covers a portion of the gate structure and extends between the gate structure and the drain.