Display panel and display device

Abstract

The invention discloses a display panel and a display device, and belongs to the technical field of display. The display panel is provided with a display area, the display area comprises a main display area and an auxiliary display area, the main display area is located on at least one side of the auxiliary display area, and the auxiliary display area comprises at least one pixel area and at least one opening area. The display panel comprises a substrate and a device layer located on one side of the substrate. The device layer comprises a first sub-part located in at least one pixel region and a second sub-part located in at least one opening region, the first sub-part comprises a first pixel circuit, and the first pixel circuit comprises at least two transistors. The at least two transistors of the first pixel circuit are arranged in a stacked mode in the direction away from the substrate. The structure can reduce the area of the pixel region. And correspondingly, the area of the opening area can be increased. In this way, the number of pixels in the auxiliary display area can be guaranteed, it is guaranteed that the resolution ratio of the auxiliary display area is high, and the light transmitting effect of the auxiliary display area can be improved.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to display panels and display devices. Background Technology

[0002] Under-display camera (FDC) technology refers to a solution that eliminates the traditional punch-hole camera on the screen, placing the front-facing camera beneath the display. Compared to current notch or waterdrop screens, it achieves a true full-screen display without any visible holes.

[0003] In OLED (Organic Light-Emitting Diode) display panels, balancing the resolution and light transmission of the FDC (Light-Condensing Diode) area has become an urgent problem to be solved. Summary of the Invention

[0004] This application aims to at least solve one of the technical problems existing in the prior art. To this end, this application proposes a display panel and display device that can improve the light transmission effect of the FDC region without reducing the resolution of the FDC region.

[0005] In a first aspect, this application provides a display panel having a display area, the display area including a main display area and a sub-display area, the main display area being located on at least one side of the sub-display area, and the sub-display area including at least one pixel area and at least one opening area;

[0006] The display panel includes a substrate and a device layer located on one side of the substrate. The device layer includes a first sub-part located in the at least one pixel region and a second sub-part located in the at least one opening region. The first sub-part includes a first pixel circuit, and the first pixel circuit includes at least two transistors.

[0007] The at least two transistors in the first pixel circuit are stacked in a direction away from the substrate.

[0008] In some embodiments, the at least two transistors in the first pixel circuit have at least partial overlap in their orthogonal projections onto the substrate.

[0009] In some embodiments, the at least two transistors in the first pixel circuit have completely overlapping orthogonal projections onto the substrate.

[0010] In some embodiments, the sub-display area includes at least two pixel areas and at least two opening areas, the pixel areas and the opening areas being arranged alternately.

[0011] In some embodiments, a first spacing exists between the central axes of two adjacent opening regions along a first direction, and a second spacing exists between the central axes of two adjacent pixel regions along the first direction. The first spacing and the second spacing satisfy a first relationship: Where W is the moiré width and θ is the angle between the central axis of the opening area and the central axis of the pixel area; W and CSF satisfy the second relation:

[0012] Wherein, when the CSF value is within the first range, there is no moiré pattern between the opening area and the pixel area, and the first range is the numerical range determined according to the CSF function curve.

[0013] In some embodiments, the second sub-part has at least one groove on the side facing away from the substrate.

[0014] In some embodiments, the tank is filled with organic material; the projected area of ​​the cross-section of the tank on the substrate gradually decreases along the direction close to the substrate.

[0015] In some embodiments, the second sub-section includes a plurality of insulating layers, and the groove penetrates at least one of the plurality of insulating layers.

[0016] In some embodiments, the device layer further includes a third sub-section located in the main display area, the third sub-section including a second pixel circuit, the second pixel circuit including at least two transistors, the at least two transistors in the second pixel circuit being stacked in a direction away from the substrate.

[0017] In some embodiments, the first sub-part further includes a light-emitting element, which is a series-connected light-emitting device.

[0018] In some embodiments, the at least two transistors of the first pixel circuit include a driving transistor and at least one switching transistor, the driving transistor being disposed in a first layer of the first sub-section, and at least one switching transistor being disposed in a second layer of the first sub-section, the first layer and the second layer being different layers of the first sub-section.

[0019] In some embodiments, at least one of the switching transistors includes a second polysilicon layer, a third amorphous silicon layer, a fourth metal layer, and a fifth metal layer disposed sequentially away from the substrate, with the second polysilicon layer and the third amorphous silicon layer in direct contact.

[0020] In a second aspect, this application provides a display device, including a display panel as described in the first aspect;

[0021] The display device further includes an optical element located on the non-light-emitting side of the display panel, wherein the orthographic projection of the optical element onto the substrate at least partially overlaps with the orthographic projection of the sub-display area onto the substrate.

[0022] The display panel of this application embodiment has a display area, which includes a main display area and a sub-display area. The main display area is located on at least one side of the sub-display area, and the sub-display area includes at least one pixel area and at least one opening area. The display panel includes a substrate and a device layer located on one side of the substrate. The device layer includes a first sub-part located in at least one pixel area and a second sub-part located in at least one opening area. The first sub-part includes a first pixel circuit, which includes at least two transistors. The at least two transistors of the first pixel circuit are stacked in a direction away from the substrate. Stacking the transistors of the first pixel circuit in the pixel area can reduce the area of ​​the pixel area. Correspondingly, the area of ​​the opening area can be increased. This ensures both the number of pixels in the sub-display area, thereby ensuring a high resolution in the sub-display area, and also improves the light transmission effect of the sub-display area.

[0023] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0024] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0025] Figure 1 This is a schematic structural diagram of a display device provided in an embodiment of this application;

[0026] Figure 2 This is a schematic structural diagram of another display device provided in the embodiments of this application;

[0027] Figure 3 This is a schematic enlarged view of a sub-display area of ​​a display panel provided in an embodiment of this application;

[0028] Figure 4 yes Figure 3 Schematic cross-sectional view of the CC section;

[0029] Figure 5 yes Figure 3 Another schematic cross-sectional view of CC;

[0030] Figure 6 yes Figure 3 Another schematic cross-sectional view of CC;

[0031] Figure 7 This is a schematic enlarged view of the sub-display area of ​​another display panel provided in the embodiments of this application;

[0032] Figure 8 This is a CSF function curve provided in the embodiments of this application;

[0033] Figure 9 This is a schematic structural diagram of a pixel circuit provided in an embodiment of this application;

[0034] Figure 10 yes Figure 9 The signal timing diagram of the pixel circuit is shown. Detailed Implementation

[0035] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0036] Some embodiments of this application provide a display device 1000, which can be any display device that displays text or images, whether moving (e.g., video) or stationary (e.g., still images). More specifically, the display device 1000 of the described embodiments is contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0037] like Figure 1 As shown, the display device 1000 includes a display panel 100 and a cover plate 200.

[0038] In some embodiments, the display panel 100 can be an organic light-emitting diode (OLED) display panel. The cover plate 200 is located on the light-emitting side of the display panel 100, protecting it from external impacts and other damage. The cover plate 200 can be made of glass or resin.

[0039] In some implementations, in some examples, such as Figure 1 As shown, the display device 1000 may also include optical elements 300, such as an under-display camera (Full Display with Camera, abbreviated as FDC), an under-display fingerprint sensor, an infrared transmitter, an infrared receiver, etc., enabling the display device 1000 to realize a variety of different functions such as taking pictures, recording videos, fingerprint recognition, and facial recognition (FaceID).

[0040] The display device 1000 may further include an integrated circuit. The integrated circuit is connected to the display panel 100 and is used to transmit display drive signals to the display panel 100, etc.

[0041] like Figure 1 and Figure 2 As shown, the display panel 100 has a display area A and a peripheral area D. The display area A is the area of ​​the display panel 100 used to display the image, and the peripheral area D is used to house structures such as driving circuits that provide electrical signals (e.g., scan signals, data signals, etc.) to the sub-pixels.

[0042] For example, the shape of display area A can be a rectangle or a rounded rectangle. A rounded rectangle refers to a rectangle whose four corners are rounded.

[0043] See also Figure 2 Display area A includes a main display area A1 and a sub-display area A2 located on at least one side of the main display area A1. That is, the main display area A1 surrounds the sub-display area A2. The sub-display area A2 can be circular, elliptical, or rectangular, etc. The sub-display area A2 is the FDC area.

[0044] When the shape of the display area A is rectangular, the sub-display area A2 can be located at any position in the middle of the rectangle, or the sub-display area A2 can be located near any corner of the rectangle, or the sub-display area A2 can be located near any side of the rectangle.

[0045] Display area A may include at least one sub-display area A2. There may be one sub-display area A2, or there may be two or more sub-display areas A2.

[0046] In the aforementioned display panel 100, portions located in both the main display area A1 and the sub-display area A2 can be used for image display. The light transmittance of the sub-display area A2 can be greater than that of the main display area A1.

[0047] like Figure 1 As shown, the optical element 300 is located on the non-light-emitting side of the display panel 100 and in the sub-display area A2 of the display panel 100. The light-emitting side of the display panel 100 refers to the side of the display panel 100 that can display an image, and the non-light-emitting side of the display panel 100 refers to the side opposite to the light-emitting side of the display panel 100.

[0048] For example, taking a camera as an example where the optical element 300 is used, during the operation of the camera, external light can pass through the portion of the display panel 100 located in the secondary display area A2. The camera can then collect this light to achieve the function of taking a photo or recording a video. For instance, when the camera is working (e.g., taking a selfie), the secondary display area A2 can display a black screen, while the main display area A1 displays the selfie, clearly showing the location of the camera. Alternatively, both the secondary display area A2 and the main display area A1 can display the selfie, without showing the location of the camera.

[0049] Even when the camera is not in operation, the portions of the display panel 100 located in the sub-display area A2 and the main display area A1 can both display images, enabling the display panel 100 and the display device 1000 as a whole to display images.

[0050] For example, taking the optical element 300 as both an infrared receiver and an infrared emitter, during the facial recognition process of the display device 1000, the infrared emitter emits light, such as infrared light, through the portion of the display panel 100 located in the sub-display area A2 to the light-emitting side of the display panel 100. If there is an object with a relatively high temperature (e.g., a human face) on the light-emitting side of the display panel 100, the object can reflect at least a portion of these infrared lights back to the display panel 100, which then enters the infrared receiver through the portion of the display panel 100 located in the sub-display area A2. The infrared receiver then performs facial recognition based on the received infrared light.

[0051] Figure 3 for Figure 2 The enlarged view shows the sub-display area A2 of the display device 1000. The sub-display area A2 of the display panel 100 includes at least one pixel area A21 and at least one opening area A22. The pixel area A21 is provided with a plurality of sub-pixels P. It should be noted that... Figure 3 The schematic diagram of the sub-display area A2 shown may only show a portion of the sub-display area A2.

[0052] For example, the multiple sub-pixels P include: red sub-pixel P1, green sub-pixel P2, and blue sub-pixel P3. Red sub-pixel P1, green sub-pixel P2, and blue sub-pixel P3 form a pixel unit.

[0053] The display pixel backplane TFT (Thin Film Transistor) and film structure are integrated into the FDC (Film Condensation Distributed) area. To increase the transmittance of visible light and infrared (IR) light, the aperture ratio needs to be increased, i.e., the area of ​​the aperture region A22 needs to be increased. Related technologies reduce the number of display pixel units in the FDC area, which lowers the PPI (Pixels Per Inch) of the FDC area, and thus reduces the screen resolution of the FDC area.

[0054] While placing the TFTs and film layers of the display pixel backplane outside the FDC region can improve visible or infrared light transmittance without reducing the screen resolution in the FDC region, this type of display panel is more difficult to manufacture. Therefore, balancing the resolution and light transmittance of the FDC region is a pressing issue in OLED display panels.

[0055] In view of this, this application provides a display panel that can improve the light transmission effect of the FDC area without reducing the resolution of the FDC area. The FDC area refers to the IR sensor area, the face recognition sensor area, or the ambient light sensor area.

[0056] In one aspect, this application provides a display panel 100. Figure 4 According to Figure 3 The diagram shows a cross-sectional view of the display panel 100 along section line CC. (See diagram below.) Figure 4 As shown, the display panel 100 includes a substrate 101 and a device layer 102 located on one side of the substrate 101. The substrate 101 may be a glass substrate or a resin substrate, such as a polyimide substrate (PI substrate). The device layer 102 includes a first sub-section 1021 located in the pixel region A21 and a second sub-section 1022 located in the opening region A22. The first sub-section 1021 includes a first pixel circuit 30, and the first pixel circuit 30 includes at least two transistors 301.

[0057] For example, the first sub-part 1021 (sub-pixel P) includes a light-emitting element. The first pixel circuit 30 is used to drive the light-emitting element to emit light.

[0058] In some implementations, such as Figure 4As shown, the second sub-part 1022 includes: a substrate 101, a barrier layer 331, an insulating layer 332, a buffer layer 333, a first dielectric layer 334, a second dielectric layer 335, a first organic planarization layer 336, a second organic planarization layer 337 (337 can also be an inorganic insulating layer), a third organic planarization layer 338 (338 can also be an inorganic insulating layer), and a fourth organic planarization layer 339, which are stacked in sequence.

[0059] In some embodiments, the transistors 301 in each first pixel circuit 30 are stacked in a direction away from the substrate 101. That is, the transistors 301 in the first pixel circuit 30 of each pixel region are stacked TFT structures.

[0060] like Figure 4 As shown, the first sub-part 1021 includes: a substrate 101, a barrier layer 331, a light-shielding layer 340, an insulating layer 332, a buffer layer 333, a first polysilicon layer 311, a first dielectric layer 334, a first metal layer 312, a second dielectric layer 335, a second metal layer 313, a third metal layer 314 (the third metal layer 314 and the second metal layer 313 are on the same layer), a first organic planarization layer 336, a second polysilicon layer 321, a third amorphous silicon layer 322, a second organic planarization layer 337, a fourth metal layer 323, a third organic planarization layer 338, a fifth metal layer 324, a sixth metal layer 325 (the sixth metal layer 325 and the fifth metal layer 324 are on the same layer), and a fourth organic planarization layer 339, which are stacked sequentially.

[0061] In this context, "same-layer setup" refers to a layer structure formed using the same film deposition process to create a specific pattern, followed by a single patterning process using the same photomask. In other words, one patterning process corresponds to one photomask. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes. The specific pattern in the resulting layer structure can be continuous or discontinuous, and these patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0062] The display panel 100 of this embodiment has a display area A, which includes a main display area A1 and a sub-display area A2 located within the main display area A1. The sub-display area A2 includes at least one pixel area A21 and at least one opening area A22. The display panel 100 includes a substrate 101 and a device layer 102 located on one side of the substrate 101. The device layer 102 includes a first sub-part 1021 located in the pixel area A21 and a second sub-part 1022 located in the opening area A22. The first sub-part 1021 includes a first pixel circuit 30, which includes at least two transistors 301. The transistors 301 of each first pixel circuit 30 are stacked in a direction away from the substrate 101. Stacking the transistors 301 of the first pixel circuit 30 in the pixel area A21 can reduce the area of ​​the pixel area A21. Correspondingly, the area of ​​the opening area A22 can be increased. This approach ensures both the sufficient number of pixels in the sub-display area A2, thus maintaining a high resolution, and also improves the light transmission of the sub-display area A2. Therefore, this embodiment can also meet the functional requirements of sensors such as IR sensors, face recognition sensors, or ambient light sensors located below the FDC area while maintaining the screen resolution of the FDC area.

[0063] In some embodiments, device layer 102 further includes several third sub-sections (not shown) located in the main display area A1. The third sub-sections include second pixel circuits and light-emitting elements. The second pixel circuits are used to drive the light-emitting elements located in the third sub-sections to emit light. The second pixel circuits include at least two transistors.

[0064] The transistors in each second pixel circuit can also be stacked in a direction away from the substrate 101. This reduces the area of ​​each sub-pixel in the main display area A1. By reducing the area of ​​each sub-pixel while keeping the total area of ​​the main display area A1 unchanged, the number of sub-pixels can be increased, thereby improving the screen resolution of the main display area A1.

[0065] The transistors in the second pixel circuit can all be arranged on the same layer, without stacking. Furthermore, the structure of the transistors arranged on the same layer or stacked in the embodiments of this application can be applied to OLED display panels or liquid crystal display panels.

[0066] In some embodiments, both the light-emitting elements included in the first sub-section 1021 and the light-emitting elements included in the third sub-section can employ a tandem design to meet the light-emitting requirements of high-brightness OLEDs. The light-emitting elements using a tandem design are series-connected light-emitting devices, i.e., stacked devices where multiple light-emitting elements are connected together via an intermediate connecting layer. If the brightness limit of a single-layer light-emitting device is 1000 nits, the brightness limit of a two-layer tandem light-emitting device will be increased to 2000 nits.

[0067] In some implementations, the sub-display area A2 may include at least two pixel areas A21 and at least two opening areas A22, and the pixel areas A21 and the opening areas A22 are arranged alternately.

[0068] For example, such as Figure 3 As shown, the sub-display area A2 includes several pixel areas A21 and several opening areas A22, which are arranged alternately. This arrangement ensures that the sub-display area A22 has sufficient pixel areas A21, i.e., sufficient screen resolution, while fully utilizing the gaps between the pixel areas A21 to set the opening areas A22, further improving the light transmission effect of the sub-display area A2. Therefore, it can further meet the functional requirements of sensors such as IR sensors, face recognition sensors, or ambient light sensors below the FDC area.

[0069] In some implementations, such as Figure 5 As shown, the second sub-part 1022 has at least one groove 1023 on the side facing away from the substrate 101, and the groove 1023 can penetrate the insulating layer 332. This allows external light to reach the optical element 300 more easily, thereby further improving the light transmission effect of the FDC area. If the sub-display area A2 has several opening areas A22, a groove 1023 can be provided on the side of each second sub-part 1022 facing away from the substrate 101 located in the opening area A22. Alternatively, depending on the specific position of the optical element 300, a groove 1023 can be provided on the side of the second sub-part 1022 corresponding to a portion of the opening A22 facing away from the substrate 101.

[0070] In some implementations, such as Figure 6 As shown, it is possible to Figure 5 The groove 1023 shown is filled with an organic material, specifically epoxy resin or silicone resin. Epoxy resin and silicone resin have high light transmittance. Therefore, filling the groove 1023 with transparent organic materials such as epoxy resin, silicone resin, or polyimide not only ensures the visible light transmittance and infrared light transmittance of the sub-display area A2, thus meeting the functional requirements of sensors such as IR sensors, face recognition sensors, or ambient light sensors below the sub-display area A2 (FDC area), but also provides better encapsulation, thereby enhancing the reliability of the sub-display area A2.

[0071] In some implementations, such as Figure 5 and Figure 6As shown, the projected area of ​​the cross-section of the groove 1023 on the substrate 101 can gradually decrease along the direction close to the substrate 101. That is, the groove 1023 can be a trapezoidal structure that is wider at the top and narrower at the bottom. This trapezoidal structure of the groove 1023 is not only easy to manufacture, but also has a better light-gathering effect, thereby further improving the light transmission effect of the sub-display area A2.

[0072] The FDC area (sub-display area A2) has pixel display functionality. When the display panel emits light, since the opening area A22 of the FDC area does not have pixel circuits and light-emitting elements, while the pixel area A21 of the FDC area does have pixel circuits and light-emitting elements, and since the pixel area A21 and the opening area A22 of the FDC area are arranged in an alternating manner, it is easy to cause obvious moiré patterns in the FDC area to be visible to the human eye.

[0073] OLED displays typically exhibit moiré patterns, primarily vertical or diagonal, which are formed using the principle of light-shielding. Moiré patterns are created using the principles of light generation, mainly light-shielding and light diffraction interference. A linear grating consists of many equally spaced transparent slits (or reflective lines) and opaque (non-reflective) grating lines. When the moiré pattern is relatively dense (<200 lines / mm), the grating pitch is much larger than the wavelength of light, and the formation of moiré fringes can be understood through the principles of geometric optics. That is, moiré fringes can be considered as being formed by the light-shielding effect of the black lines. If the grating fringes are denser (>300 lines / mm), the pitch is very small, close to the wavelength of light, and light passing through the narrow slits will diffract. In this case, the theory of light diffraction interference must be used to explain the moiré phenomenon. Both geometric optics moiré fringes and diffraction interference moiré fringes have their own mathematical models and can also be analyzed and explained using Fourier spectrum theory. The moiré pattern involved in the embodiments of this application is a vertical moiré pattern.

[0074] To eliminate moiré patterns, in some implementations, the positional relationship between pixel area A21 and opening area A22 can be set. For example... Figure 7 As shown, there is a first spacing P1 between the central axes of two adjacent opening regions A22 along the first direction (X), and a second spacing P2 between the central axes of two adjacent pixel regions A21 along the first direction. The first spacing P1 and the second spacing P2 satisfy a first relationship so that the value of the CSF function is within a first range, where the CSF function is the human eye contrast sensitivity function, and the first range is the range of values ​​determined according to the curve of the CSF function. When the value of the CSF function is within the first range, there is no moiré pattern between the opening region and the pixel region.

[0075] Specifically, the first spacing P1 between the central axes of two adjacent opening regions A22 and the second spacing P2 between the central axes of two adjacent pixel regions A21 satisfy the following relationship:

[0076]

[0077] Where W is the moiré width and θ is the angle between the central axis of the opening area and the central axis of the pixel area;

[0078] W and CSF satisfy the following relationship:

[0079]

[0080] The CSF value is set within a first range to eliminate moiré patterns between the opening area and the pixel area. The first range is determined according to... Figure 8 The numerical range defined by the CSF function curve shown.

[0081] Figure 8 The CSF function curve shown has the horizontal axis representing moire_width (W), which is the moire width, and the vertical axis representing the CSF value. Figure 8 In the CSF function curve shown, if both CSF and moiré width are in the B1 region, there is no moiré pattern. If both CSF and moiré width are in the B2 region, moiré patterns are present. Furthermore, if both CSF and moiré width are in the B21 region, severe moiré patterns will exist.

[0082] from Figure 8 The CSF function curve shown indicates that as the moiré width W increases, the CSF first increases and then decreases. When CSF < 0.3, there will be no moiré pattern in the FDC region; therefore, the first range of CSF values ​​is less than 0.3. Based on the range of CSF values, the range of moiré width W can be obtained. When designing the positional relationship between pixel area A21 and opening area A22 in the FDC region, it is sufficient to satisfy the calculated range of moiré width W to avoid moiré patterns between opening area A22 and pixel area A21.

[0083] The following is an example of the positional relationship between the opening area A22 and the pixel area A21 in the FDC region:

[0084] When the first spacing P1 between two adjacent opening regions A22 is 64.5 micrometers and the second spacing P2 between two adjacent pixel regions A21 is 63.18 micrometers, the moiré width W is 164 micrometers and the CSF value is 0.00315. At this time, the CSF value is less than 0.3, so there is no moiré phenomenon in the FDC region.

[0085] When the first spacing P1 between two adjacent aperture regions A22 is 89.5 micrometers and the second spacing P2 between two adjacent pixel regions A21 is 56.4 micrometers, the moiré width W is 256 micrometers and the CSF value is 0.05. Since the CSF value is less than 0.3, there is no moiré pattern in the FDC region.

[0086] It should be noted that the first direction involved in the above embodiments is as follows: Figure 7 As shown in the X direction, this solves the moiré pattern phenomenon in the X direction. Similarly, if the first direction is as shown... Figure 7 The positional relationship between the opening area A22 and the pixel area A21 can also be designed according to the method of the above embodiment in the Y direction so that there is no moiré pattern in the Y direction.

[0087] In some embodiments, the first pixel circuit 30 includes a DTFT (driving transistor) and at least one STFT (switching transistor), wherein the DTFT is disposed on the first layer of the first sub-part 1021, and the at least one STFT is disposed on the second layer of the first sub-part 1021. The first layer and the second layer are different layers of the first sub-part 1021, thus realizing a dual-layer TFT structure. The display panel 100 may also include an insulating shielding layer with vias, wherein the DTFT and at least one STFT may be stacked on both sides of the insulating shielding layer and can be overlapped through an overlap portion located in the via, thus ensuring effective coupling between the parts in the pixel.

[0088] The first layer can be a layer close to the substrate 101, and the second layer can be a layer far away from the substrate 101.

[0089] Specifically, the first layer includes a barrier layer 331, a light-shielding layer 340, an insulating layer 332, a buffer layer 333, a first polysilicon layer 311, a first dielectric layer 334, a first metal layer 312, a second dielectric layer 335, a second metal layer 313, a third metal layer 314 (the third metal layer 314 is on the same layer as the second metal layer 313), and a first organic planarization layer 336, which are stacked sequentially.

[0090] The second layer includes a second polycrystalline silicon layer 321, a third amorphous silicon layer 322, a second organic planarization layer 337, a fourth metal layer 323, a third organic planarization layer 338, a fifth metal layer 324, a sixth metal layer 325 (the sixth metal layer 325 is on the same layer as the fifth metal layer 324), and a fourth organic planarization layer 339, which are stacked sequentially. Figure 9 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Both the first pixel circuit 30 and the second pixel circuit involved in the above embodiments can be adopted. Figure 9 The circuit structure is shown below. Figure 9As shown, the pixel circuit includes a DTFT (T1), a first switching transistor T2, a second switching transistor T3, a third switching transistor T4, a fourth switching transistor T5, a fifth switching transistor T6, a sixth switching transistor T7, and a capacitor element Cst. The first switching transistor T2, the second switching transistor T3, the third switching transistor T4, the fourth switching transistor T5, the fifth switching transistor T6, and the sixth switching transistor T7 can all be STFTs. Figure 9 The pixel circuit shown is a 7T1C circuit (7 TFT transistors and 1 capacitor C).

[0091] exist Figure 9 In the pixel circuit shown, if the leakage current of the STFT is relatively large, it will cause voltage instability at point N1, which in turn will lead to instability in the gate voltage supplied to T1. Unstable gate voltage of T1 will ultimately lead to unstable OLED brightness and unstable image quality of the display.

[0092] Therefore, the STFT in this embodiment includes a second polysilicon layer 321, a third amorphous silicon layer 322, a fourth metal layer 323, and a fifth metal layer 324 sequentially disposed away from the substrate, and the second polysilicon layer 321 and the third amorphous silicon layer 322 are in direct contact. This structure, in which the second polysilicon layer 321 and the third amorphous silicon layer 322 are in direct contact, allows the STFT to maintain a small leakage current, ensuring voltage stability at point N1, thereby ensuring a stable gate voltage supplied to T1. A stable gate voltage of T1 ensures stable OLED brightness, ultimately ensuring stable image quality of the display screen.

[0093] like Figure 9 As shown, the first data voltage source VDD is coupled to the anode of the light-emitting element D1 through the driving transistor T1, the first terminal of the first switching transistor T2 is coupled to the first terminal of the driving transistor T1, the second terminal of the first switching transistor T2 is coupled to the control terminal of the driving transistor T1, the gate of the first switching transistor T2 is coupled to one end of the capacitor element Cst, and the other end of the capacitor element Cst is coupled to the first data voltage source VDD.

[0094] The first terminal of the second switching transistor T3 is coupled to the gate of the driving transistor T1, the second terminal of the second switching transistor T3 is coupled to the reset voltage source Vinit, and the gate of the second switching transistor T3 is coupled to the Re terminal (reset terminal).

[0095] The first terminal of the third switching transistor T4 is coupled to the first data voltage source VDD, the second terminal of the third switching transistor T4 is coupled to the second terminal of the driving transistor T1, and the gate of the third switching transistor T4 is coupled to the Gate terminal.

[0096] The first terminal of the fourth switching transistor T5 is coupled to the second terminal of the driving transistor T1, the second terminal of the fourth switching transistor T5 is coupled to the second data voltage source Vdata, and the gate of the fourth switching transistor T5 is coupled to the EM terminal (light-emitting terminal).

[0097] The first terminal of the fifth switching transistor T6 is coupled to the first terminal of the driving transistor T1, the second terminal of the fifth switching transistor T6 is coupled to the anode of the light-emitting element D1, and the gate of the fifth switching transistor T6 is coupled to the EM terminal.

[0098] The first terminal of the sixth switching transistor T7 is coupled to the anode of the light-emitting element D1, the second terminal of the sixth switching transistor is coupled to the second terminal of the second switching transistor T3, and the gate of the sixth switching transistor T7 is coupled to the Re terminal.

[0099] The cathode of the light-emitting element D1 is coupled to the third data voltage source VSS.

[0100] The first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. The first electrode and the second electrode are different electrodes.

[0101] based on Figure 9 The pixel circuit structure shown can be divided into three stages for the entire light-emitting process: reset, compensation, and light emission.

[0102] When the pixel circuit is in the reset phase, the RE terminal is turned on (the Gate and EM terminals are turned off). The reset voltage source Vinit charges and resets the anode voltage of point N1 and the light-emitting element D1, so that the light-emitting element D1 is turned off and the voltage at point N1 is initialized.

[0103] When the pixel circuit is in the compensation phase, the Gate terminal is open (RE and EM terminals are closed), and the second data voltage source Vdata is charged to point N1. The critical condition for the driving transistor T1 to turn off at this time is Vgs = Vn1 - Vdata = Vth, Vn1 = Vdata + Vth. Here, Vgs is the voltage difference between the gate and source of the driving transistor T1. For the transistor to form a conductive channel, Vgs must exceed the threshold voltage Vth, allowing current to flow from the source to the drain. Vn1 is the voltage at point N1, and Vth is the minimum Vgs value required for the transistor to switch from the cutoff region to the conduction region. The transistor begins to conduct when Vgs is greater than Vth. Vth is determined by the transistor's physical structure and manufacturing process.

[0104] When the pixel circuit is in the light-emitting stage, the EM terminal is turned on (the Gate and RE terminals are turned off). At this time, the current flows from the first data voltage source VDD to the third data voltage source VSS, causing the light-emitting element D1 to conduct and emit light.

[0105] Figure 10 yes Figure 9 The signal timing diagram of the pixel circuit is shown. Figure 10 As shown, time period t1 corresponds to the reset phase, time period t2 corresponds to the compensation phase, and time period t3 corresponds to the light emission phase. The control signals for the reset phase, compensation phase, and light emission phase need to be strictly separated. Figure 10 The three phases of the 7T1C pixel circuit consist of the RE terminal signal (enabling reset, corresponding to time period t1), the Gate terminal signal (enabling compensation, corresponding to time period t2), and the EM terminal signal (enabling emission, corresponding to time period t3). All three signals are enabled when low. In this circuit, the signals for the three phases must be strictly separated; otherwise, unexpected internal crosstalk will occur, affecting the reset, compensation, and emission performance. During the compensation phase t2, Vdata charges point N1; therefore, Vdata is only high during the compensation phase t2.

[0106] Specifically, during time period t1, the pixel circuit is in the reset phase. The second switching transistor T3 and the sixth switching transistor T7 are closed, while the first switching transistor T2, the third switching transistor T4, the fourth switching transistor T5, and the fifth switching transistor T6 are open. The reset voltage provided by the reset voltage source Vinit is written to node N1.

[0107] During time period t2, the pixel circuit is in the compensation phase, i.e., the data voltage writing phase. The fourth switching transistor T5 and the fifth switching transistor T6 are closed, while the first switching transistor T2, the second switching transistor T3, the third switching transistor T4, and the sixth switching transistor T7 are open. The data voltage provided by the second data voltage source Vdata is written to the first terminal of the driving transistor T1.

[0108] During time period t3, the pixel circuit is in the display stage. The fourth switching transistor T5 and the fifth switching transistor T6 are closed, while the first switching transistor T2, the second switching transistor T3, the third switching transistor T4, and the sixth switching transistor T7 are open. The voltage provided by the first data voltage source VDD is connected to the anode of the light-emitting element D1 through the fourth switching transistor T5, the driving transistor T1, and the fifth switching transistor T6. In this embodiment, the light-emitting element D1 can be a diode.

[0109] It should be noted that the pixel circuit of this application is not limited to the above-mentioned circuit structure, and other types of pixel circuits can also be used, such as 8T1C, 8T2C, 9T2C and other circuit structures.

[0110] Secondly, this application provides a display device 1000, which includes the display panel 100 described in the first aspect and an optical element 300. The optical element 300 is located in the sub-display area A2 of the display panel 100 and is located on the non-light-emitting side of the display panel 100.

[0111] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0112] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0113] In the description of this application, "first feature" and "second feature" may include one or more of the features.

[0114] In the description of this application, "multiple" means two or more.

[0115] In the description of this application, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or it may include the first and second features not being in direct contact but being in contact through another feature between them.

[0116] In the description of this application, the terms "above," "over," and "on top" for the first feature and the second feature include the first feature being directly above or diagonally above the second feature, or simply indicate that the first feature is at a higher horizontal level than the second feature.

[0117] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0118] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A display panel, characterized in that, The display panel has a display area, which includes a main display area and a sub-display area. The main display area is located on at least one side of the sub-display area, and the sub-display area includes at least one pixel area and at least one opening area. The display panel includes a substrate and a device layer located on one side of the substrate. The device layer includes a first sub-part located in the at least one pixel region and a second sub-part located in the at least one opening region. The first sub-part includes a first pixel circuit, and the first pixel circuit includes at least two transistors. The at least two transistors in the first pixel circuit are stacked in a direction away from the substrate.

2. The display panel according to claim 1, characterized in that, The at least two transistors in the first pixel circuit have their orthogonal projections on the substrate at least partially overlapping.

3. The display panel according to claim 1, characterized in that, The at least two transistors in the first pixel circuit have completely overlapping orthogonal projections onto the substrate.

4. The display panel according to claim 1, characterized in that, The sub-display area includes at least two pixel areas and at least two opening areas, with the pixel areas and opening areas arranged alternately.

5. The display panel according to claim 2, characterized in that, There is a first spacing between the central axes of two adjacent opening regions along the first direction, and there is a second spacing between the central axes of two adjacent pixel regions along the first direction. The first spacing and the second spacing satisfy a first relationship: Where W is the moiré width and θ is the angle between the central axis of the opening area and the central axis of the pixel area; W and CSF satisfy the second relation: Wherein, when the CSF value is within the first range, there is no moiré pattern between the opening area and the pixel area, and the first range is the numerical range determined according to the CSF function curve.

6. The display panel according to claim 1, characterized in that, The second sub-part has at least one groove on the side facing away from the substrate.

7. The display panel according to claim 6, characterized in that, The tank is filled with organic material; the cross-sectional area of ​​the tank on the substrate gradually decreases along the direction closer to the substrate.

8. The display panel according to claim 6, characterized in that, The second sub-section includes multiple insulating layers, and the groove penetrates at least one of the multiple insulating layers.

9. The display panel according to claim 1, characterized in that, The device layer further includes a third sub-section located in the main display area. The third sub-section includes a second pixel circuit, which includes at least two transistors. The at least two transistors in the second pixel circuit are stacked in a direction away from the substrate.

10. The display panel according to claim 1, characterized in that, The first sub-part also includes a light-emitting element, which is a series-connected light-emitting device.

11. The display panel according to claim 1, characterized in that, The at least two transistors of the first pixel circuit include a driving transistor and at least one switching transistor. The driving transistor is disposed in the first layer of the first sub-section, and the at least one switching transistor is disposed in the second layer of the first sub-section. The first layer and the second layer are different layers of the first sub-section.

12. The display panel according to claim 11, characterized in that, At least one of the switching transistors includes a second polycrystalline silicon layer, a third amorphous silicon layer, a fourth metal layer, and a fifth metal layer disposed sequentially away from the substrate, wherein the second polycrystalline silicon layer and the third amorphous silicon layer are in direct contact.

13. A display device, characterized in that, include: The display panel as claimed in any one of claims 1 to 12; The display device further includes an optical element located on the non-light-emitting side of the display panel, wherein the orthographic projection of the optical element onto the substrate at least partially overlaps with the orthographic projection of the sub-display area onto the substrate.

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