Semiconductor element

Abstract

The invention discloses a semiconductor element, which mainly comprises an intermetallic dielectric layer arranged on a substrate, a first metal interconnecting line and a second metal interconnecting line arranged in the intermetallic dielectric layer, a lower electrode arranged on the intermetallic dielectric layer, a spin-orbit torque (SOT) layer arranged on the lower electrode, a magnetic tunneling junction (MTJ) layer arranged on the SOT layer, a first metal interconnecting line arranged on the first metal interconnecting line, a second metal interconnecting line arranged on the second metal interconnecting line, and a second metal interconnecting line arranged on the second metal interconnecting line. The MTJ is arranged on the SOT layer, the upper electrode is arranged on the MTJ, and the top surface of the upper electrode comprises a curved surface.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a magnetoresistive random access memory (MRAM). Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] An embodiment of the present invention discloses a semiconductor device, which mainly includes an intermetallic dielectric layer disposed on a substrate, a first metal interconnect and a second metal interconnect disposed within the intermetallic dielectric layer, a lower electrode disposed on the intermetallic dielectric layer, a spin orbit torque (SOT) layer disposed on the lower electrode, a magnetic tunneling junction (MTJ) disposed on the SOT layer, and an upper electrode disposed on the MTJ, wherein the top surface of the upper electrode includes a curved surface. Attached Figure Description

[0005] Figures 1 to 7This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0006] Symbol Explanation

[0007] 12: Base

[0008] 14: MRAM region

[0009] 16: Interlayer dielectric layer

[0010] 18: Metal interconnect structure

[0011] 20: Metal interconnect structure

[0012] 22: Intermetallic dielectric layer

[0013] 24: Metal interconnects

[0014] 26: Stop Layer

[0015] 28: Intermetallic dielectric layer

[0016] 30: Metal interconnects

[0017] 32: Metal interconnects

[0018] 34: Barrier Layer

[0019] 36: Metal layer

[0020] 42: Lower electrode

[0021] 48: MTJ stacked structure

[0022] 50: SOT layer

[0023] 52 free layers

[0024] 54: Barrier Layer

[0025] 56: Fixed layer

[0026] 58:MTJ

[0027] 60: Covering layer

[0028] 62: Upper electrode

[0029] 64: Covering layer

[0030] 66: Intermetallic dielectric layer

[0031] 68: Metal interconnects

[0032] 70: Barrier Layer

[0033] 72: Metal layer

[0034] 74: Stop Layer

[0035] 92: Hard Mask

[0036] 102: Flat surface

[0037] 104: Surface

[0038] 106: Surface

[0039] 108: Doped region Detailed Implementation

[0040] Please refer to Figures 1 to 7 , Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating a semiconductor device, or more specifically, an MRAM cell, according to one embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region (not shown) are preferably defined on the substrate 12.

[0041] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 16 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 16 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0042] Then, metal interconnect structures 18 and 20 are sequentially formed on the interlayer dielectric layer 16 to electrically connect the aforementioned contact plug. The metal interconnect structure 18 includes an intermetal dielectric layer 22 and metal interconnects 24 embedded in the intermetal dielectric layer 22. The metal interconnect structure 20 includes a stop layer 26, an intermetal dielectric layer 28, and a plurality of metal interconnects 30 and 32 embedded in the stop layer 26 and the intermetal dielectric layer 28.

[0043] In this embodiment, each metal interconnect 24 in the metal interconnect structure 18 preferably includes a trench conductor, and the metal interconnects 30 and 32 in the metal interconnect structure 20 include a via conductor. Furthermore, each metal interconnect 24, 30, and 32 in the metal interconnect structures 18 and 20 can be embedded in the intermetallic dielectric layers 22 and 28 and / or the stop layer 26 using a single damascene fabrication process or a double damascene fabrication process and electrically connected to each other. For example, each metal interconnect 24, 30, and 32 may further include a barrier layer 34 and a metal layer 36. The barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited to these. Since single-mount or double-mount fabrication processes are well known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 24 preferably contains copper, the metal layer 36 in the metal interconnects 30 and 32 preferably contains tungsten, the intermetallic dielectric layers 22 and 28 preferably contain silicon oxide or an ultra-low dielectric constant dielectric layer, and the stop layer 26 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0044] like Figure 2 As shown, a lower electrode 42 is then formed on the intermetallic dielectric layer 28. A planarization process, such as chemical mechanical polishing (CMP), is then performed to remove a portion of the lower electrode 42, slightly reducing its thickness on the intermetallic dielectric layer 28 while still fully covering the top surface of the intermetallic dielectric layer 28. In this embodiment, the lower electrode 42 preferably comprises a metal or a metal nitride, such as, but not limited to, tantalum (Ta) or tantalum nitride (TaN).

[0045] like Figure 3 As shown, a spin orbit torque (SOT) layer 50 is then formed on the surface of the lower electrode 42, an MTJ stack structure 48 is formed on the SOT layer 50, and a masking layer 60, an upper electrode 62, and a hard mask 92 are then formed on the MTJ stack structure 48.

[0046] In this embodiment, the MTJ stack structure 48 can be formed by sequentially forming a free layer 52, a barrier layer 54, and a pinned layer 56 on the SOT layer 50. The free layer 52 can be made of a ferromagnetic material, such as iron, cobalt, nickel, or their alloys like cobalt-iron-boron (CoFeB), but is not limited thereto. The magnetization direction of the free layer 52 can be "freely" changed by an external magnetic field. The barrier layer 54 can be made of an insulating material containing oxides, such as aluminum oxide (Al₂O₃). x The material can be magnesium oxide (MgO) or other similar materials, but is not limited to these. The fixing layer 56 can be made of an antiferromagnetic (AFM) material, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. It should be noted that since this embodiment is preferably used to prepare a spin orbit torque (SOT) MRAM, the free layer 52 is preferably located at the bottom layer and directly contacts the SOT layer 50.

[0047] Additionally, the SOT layer 50 is preferably used as a channel for a spin-orbit torque MRAM, therefore its material can include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), and bismuth selenide (Bi). x Se 1-x The masking layer 60 in this embodiment preferably comprises a metal such as tantalum (Ta), and the upper electrode 62 preferably comprises a conductive material such as a metal or a metal nitride, wherein the metal may include titanium and the metal nitride may include titanium nitride. However, it is not limited to this; the masking layer 60 or the upper electrode 62 may comprise conductive or dielectric materials such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or combinations thereof. The hard mask 92 preferably comprises a dielectric material such as silicon oxide, but is not limited to this.

[0048] Then as Figure 4 As shown, an etching process is first performed using a patterned mask, such as a patterned photoresist (not shown), as the mask. For example, a reactive ion etching (RIE) method is used to remove part of the hard mask 92 and part of the upper electrode 62 to form the patterned hard mask 92 and the upper electrode 62. It should be noted that the remaining hard mask 92 after patterning the hard mask 92 in this stage preferably has a curved surface or a relatively flat top surface, and two curved surfaces are provided at the junction of the two side walls and the top surface.

[0049] Then as Figure 5 As shown, the patterned hard mask 92 is first removed, and then one or more etching processes are performed. The reactive ion etching (RIE) or ion beam etching (IBE) process is used to remove part of the masking layer 60 and part of the MTJ stack structure 48 and even part of the SOT layer 50 using the patterned upper electrode 62 as a mask to form MTJ58 on the SOT layer 50.

[0050] It is worth noting that the upper electrode 62 formed by the above-described etching process in this stage preferably has a flat surface 102 extending along a first direction, such as the X direction, a curved surface 104 connecting one side of the flat surface, such as the left side, and another curved surface 106 connecting the other side of the flat surface 102, such as the right side, wherein each curved surface 104, 106 includes a concave curved surface. In detail, there is a height H1 from the top of the upper electrode 62 to the bottom of the left curved surface 104 or the right curved surface 106, a height H2 from the top to the bottom of the center point of the upper electrode 62, a length L1 from the edge of the flat surface 102 at the top of the upper electrode 62 to the edge of the completely vertical sidewall of the upper electrode 62, a length L2 on the bottom surface of the upper electrode 62, and a length L3 on the flat surface 102 of the top surface of the upper electrode 62.

[0051] According to a preferred embodiment of the present invention, the height H1 is preferably between 10 and 30 nanometers, the height H2 is preferably between 30 and 50 nanometers, the length L1 is preferably between 25 and 35 nanometers, and the length L2 is preferably between 75 and 115 nanometers. The ratio of H1 / H2 is approximately 0.3 to 0.6, the ratio of L1 / L2 is preferably approximately 0.2 to 0.5, and the ratio of L3 / L2 is preferably approximately 0.5 to 0.8. In other words, the width or length L3 of the flat surface 102 of the top surface of the upper electrode 62 is preferably greater than half of the overall width or length L2 of the bottom surface of the upper electrode 62 and less than 80% of the overall width or length L2 of the bottom surface of the upper electrode 62.

[0052] It should also be noted that during the process of patterning the MTJ stack structure 48 to form the MTJ 58 using the above-mentioned RIE or IBE fabrication process in this embodiment, some metal atoms of the MTJ 58 may be sputtered upwards and adhere to the curved sidewalls and vertical sidewalls of the upper electrode 62 to form doped regions 108. The doped regions 108 may contain the original material of the upper electrode 62, such as titanium nitride, and the metal materials in the MTJ 58, such as iron, cobalt, nickel, or their alloys. Compared with the prior art, where the upper electrode sidewall is preferably a flat inclined surface or a completely flat surface, the height of the doped region formed when metal atoms are sputtered to the upper electrode sidewall is approximately equal to the entire height of the upper electrode. In this embodiment, because the upper electrode 62 sidewall has the above-mentioned curved surfaces 104 and 106, the height H3 of the doped region 108 formed is preferably slightly lower than 80% or 70% of the entire height H2 of the upper electrode 62. In this embodiment, the doped region 108 includes a width L4 extending along the X direction and a height H3 extending along the Y direction, wherein the ratio of L4 / L2 is preferably between 0.02 and 0.15 and the ratio of H3 / H2 is preferably between 0.3 and 0.7.

[0053] like Figure 6 As shown, a masking layer 64 is subsequently formed on the surfaces of the upper electrode 62, MTJ 58, and SOT layer 50. In this embodiment, the SOT layer 50 may or may not be etched during the patterning of the MTJ stack structure 48. Therefore, after the formation of MTJ 58, the top surface of the SOT layer 50 directly below MTJ 58 may be flush with or slightly higher than the top surfaces of the SOT layer 50 on both sides of MTJ 58, all of which are within the scope of this invention. Furthermore, the masking layer 64 may include, but is not limited to, a nitrogen-doped carbide layer (NDC), silicon nitride (SiN), or silicon nitride carbide (SiCN), and more preferably, silicon nitride.

[0054] Then as Figure 7As shown, an intermetallic dielectric layer 66 is formed on the surface of the masking layer 64. Then, one or more photolithography and etching processes are performed to remove portions of the intermetallic dielectric layer 66 and the masking layer 64, forming contact holes (not shown). Next, conductive material is filled into the contact holes, and a planarization process such as CMP is used to form metal interconnects 68 connecting to the underlying hard mask 62. Then, another stop layer 74 is formed on the surface of the metal interconnects 68. As with the aforementioned metal interconnects 24, the metal interconnects 68 disposed within the intermetallic dielectric layer 66 can be embedded within the intermetallic dielectric layer 66 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnect 68 may further include a barrier layer 70 and a metal layer 72. The barrier layer 70 may be selected from the group consisting of free titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 72 may be selected from the group consisting of free tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto.

[0055] In this embodiment, the intermetallic dielectric layer 66 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, but not limited to silicon oxycarbide (SiOC). The stop layer 74 may comprise, but is not limited to, a nitrogen-doped carbide layer (NDC), silicon nitride (SiN), or silicon nitride carbide (SiCN), and more preferably, silicon nitride, but is not limited thereto. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0056] In summary, this invention mainly discloses a structure for an SOT MRAM device. During the patterning of an MTJ stack structure, etching parameters are adjusted to form an upper electrode 62 with an approximate inverted pan shape. The top of the upper electrode, in detail, has a flat surface 102 extending along a first direction, such as the X direction; a curved surface 104 connecting one side of the flat surface (left side); and another curved surface 106 connecting the other side of the flat surface 102 (right side). According to a preferred embodiment of this invention, presenting the top surface of the upper electrode with the aforementioned curved profile can improve the efficiency of the IBE etching process and significantly reduce the probability of residue adhering to the sidewalls of the upper electrode, thereby improving device stability.

[0057] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Include: Spin-orbit torque layer, disposed on the substrate; A magnetic tunneling junction is disposed on the spin-orbit torque layer; and An upper electrode is disposed on the magnetic tunnel junction, wherein the top surface of the upper electrode includes a curved surface.

2. The semiconductor device of claim 1, further comprising: An intermetallic dielectric layer is disposed on the substrate; The first metal interconnect and the second metal interconnect are disposed within the intermetal dielectric layer. The lower electrode is disposed on the intermetallic dielectric layer; and The spin-orbit torque layer is disposed on the lower electrode.

3. The semiconductor device of claim 1, wherein the magnetic tunneling junction comprises: A free layer is located on the spin-orbit torque type layer; A barrier layer is disposed on the free layer; and A fixing layer is provided on the barrier layer.

4. The semiconductor device of claim 1, wherein the top surface of the upper electrode comprises: A flat surface extending along the first direction; The first curved surface connects to one side of the flat surface; and The second curved surface connects to the other side of the flat surface.

5. The semiconductor element of claim 4, wherein the first surface comprises a concave surface.

6. The semiconductor element of claim 4, wherein the second surface comprises a concave surface.

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