System and method for prioritizing and allocating threads in heterogeneous processor architecture

Abstract

A method and system for prioritizing and allocating threads in a heterogeneous CPU architecture includes receiving an input to create a frame on a display device of a PCD. Next, execution threads responsible for creating the frame and corresponding to a plurality of first CPU cores in the CPU architecture are identified. The CPU architecture includes first CPU cores and second CPU cores, wherein each first CPU core has a first processing capacity and each second CPU core has a second processing capacity. The first processing capacity is greater than the second processing capacity. During a predetermined period of time, a ranking of the threads is created according to the workload levels of the threads. And then determining a workload level for the presence of each first CPU core. A ranking of the first CPU core is created according to an existing workload level of the first CPU core, after which each thread is assigned to a single first CPU core.

Description

Background Technology

[0001] Portable computing devices (such as cellular phones, smartphones, tablets, portable digital assistants (PDAs), virtual reality (VR) devices, and portable game consoles) continue to offer an ever-expanding array of features and services, providing users with unprecedented levels of access to information, resources, and communications. To keep pace with these enhanced services, these devices have become more powerful and complex. Portable computing devices now typically include a System-on-a-Chip (SoC), which comprises one or more chip components (such as one or more central processing units (CPUs), graphics processing units (GPUs), digital signal processors, etc.) embedded on a single substrate.

[0002] Such portable computing devices or other computer systems or devices may include multi-cluster heterogeneous processor architectures, an example of which is referred to as the “big.LITTLE” heterogeneous CPU architecture. “Big.LITTLE” and other heterogeneous architectures typically include groups of processor cores, where a group of relatively slower, lower-power processor cores is coupled to a group of relatively more powerful processor cores.

[0003] For example, a group of processors or processor cores with higher performance capabilities is often referred to as a "Big cluster," while another group of processors or processor cores with minimal power consumption but capable of providing adequate performance (but relatively lower than that of the Big cluster) is referred to as a "Little cluster."

[0004] The CPU scheduler can schedule tasks to be performed by either the Big Cluster or the Little Cluster based on performance and / or power requirements, which can vary based on various use cases. The Big Cluster can be used for situations where higher performance is expected (e.g., graphics, games, etc.), while the Little Cluster can be used for use cases with relatively low power requirements (e.g., text applications, streaming music).

[0005] However, existing multi-cluster heterogeneous processor architectures may not be effectively optimized for performance / power in certain use cases, such as for display-intensive and power-intensive applications (i.e., gaming applications (on mobile phones, tablets, and VR headsets)). Such applications may be problematic for battery-powered portable computing devices, as there will always be at least two competing factors to support them: performance versus power savings.

[0006] Therefore, there is a need in the art for systems and methods for scheduling and managing display frame rendering tasks in portable computing devices with multi-cluster heterogeneous processor architectures with optimized performance and power savings. Summary of the Invention

[0007] Various implementation schemes of methods, systems, and computer programs for prioritizing and allocating threads in a CPU architecture are disclosed.

[0008] A method for prioritizing and assigning threads in a CPU architecture may include: receiving input to create frames at a predetermined rate on a display device of a battery-powered portable computing device; and identifying execution threads responsible for creating the frames and corresponding to a plurality of first CPU cores in the CPU architecture. The CPU architecture may have first CPU cores and second CPU cores, wherein each first CPU core has a first processing capacity and each second CPU core has a second processing capacity. The first processing capacity may be greater than the second processing capacity. Within a predetermined time period, a ranking of the threads is created based on their workload levels. Next, the existing workload levels for each first CPU core may be determined. A ranking of the first CPU cores can then be created based on the existing workload levels. Each thread can be assigned to a single first CPU core based on its ranking and the thread's ranking.

[0009] A system for prioritizing and allocating threads in a CPU architecture may include a scheduler that receives input to create frames at a predetermined rate on a display device of a battery-powered portable computing device. The scheduler may identify the execution threads responsible for creating frames and corresponding to multiple first CPU cores in the CPU architecture. The CPU architecture may include first CPU cores and second CPU cores, wherein each first CPU core has a first processing capacity and each second CPU core has a second processing capacity. The first processing capacity is typically greater than the second processing capacity. Within a predetermined time period, the scheduler may create a ranking of threads based on their workload levels. The scheduler may then determine the workload level of each first CPU core. The scheduler may also create a ranking of the first CPU cores based on their workload levels. The scheduler may then allocate each thread to a single first CPU core based on the ranking of the first CPU cores and, in turn, the ranking of the threads.

[0010] A system for prioritizing and allocating threads in a CPU architecture may include a scheduler that receives input to create frames at a predetermined rate on a display device of a battery-powered portable computing device. The scheduler may identify execution threads responsible for creating frames and corresponding to multiple first processing units in the CPU architecture. The CPU architecture may include first and second processing units, each first processing unit having a first processing capacity and each second processing unit having a second processing capacity. The first processing capacity is generally greater than the second processing capacity. Within a predetermined time period, the scheduler may create a ranking of threads based on their workload levels. The scheduler may determine the workload level of each first processing unit. The scheduler may also create a ranking of the first processing units based on their workload levels, and the scheduler may allocate each thread to a single first processing unit based on the ranking of the first processing unit and the ranking of the threads. The first and second processing units may each include a processing cluster.

[0011] A non-transitory computer program product for prioritizing and allocating threads in a CPU architecture may include instructions that, when executed by the CPU architecture, configure the CPU architecture to: receive input to create frames at a predetermined rate on a display device of a battery-powered portable computing device, and identify execution threads responsible for creating frames and corresponding to a plurality of first CPU cores in the CPU architecture. The CPU architecture may have first CPU cores and second CPU cores, wherein each first CPU core has a first processing capacity and each second CPU core has a second processing capacity. The first processing capacity is typically greater than the second processing capacity. Within a predetermined time period, the instructions may cause the CPU architecture to: create a ranking of threads based on their workload levels, and determine the workload level of each first CPU core. The ranking of the first CPU cores may be created based on their workload levels, and each thread may be assigned to a single first CPU core based on both the ranking of the first CPU cores and the ranking of the threads. Attached Figure Description

[0012] In the accompanying drawings, unless otherwise indicated, similar reference numerals are used throughout the various views to refer to similar parts. For reference numerals with letter character names, such as "102A" or "102B", the letter character names distinguish two similar parts or elements in the same figure. When the aim is to have the reference numerals cover all parts with the same reference numerals in all figures, the letter character names of the reference numerals may be omitted.

[0013] Figure 1This is a functional block diagram illustrating how the Completely Fair Scheduler of the Advanced Operating System (HLOS) of a Portable Computing Device (PCD) manages the execution threads used to render frames on the display device for a gaming computer application running on that PCD.

[0014] Figure 2A It is a functional block diagram of an implementation of a system for prioritizing pipelined threads during a vSync window and assigning those pipelined threads to a single dedicated core in a multi-cluster heterogeneous processor architecture, wherein the system has a single prime core.

[0015] Figure 2B It is a functional block diagram of another implementation of a system for prioritizing pipelined threads during a vSync window and assigning those pipelined threads to a single dedicated core in a multi-cluster heterogeneous processor architecture, wherein the system does not have any master core;

[0016] Figure 2C It is a functional block diagram of another implementation of a system for prioritizing pipelined threads during a vSync window and assigning those pipelined threads to a single dedicated core in a multi-cluster heterogeneous processor architecture, wherein the system has two main cores;

[0017] Figure 3A A flowchart illustrating a method, according to an implementation scheme, for prioritizing pipelined threads during a vSync window and assigning those pipelined threads to a single dedicated core of a CPU architecture;

[0018] Figure 3B-1 Examples Figure 3A A further flowchart of the method for prioritizing pipelined threads during a vSync window and assigning those pipelined threads to a single dedicated core of a CPU architecture, according to the implementation scheme.

[0019] Figure 3B-2 Examples Figure 3B-1 A further flowchart of the method for prioritizing pipelined threads during a vSync window and assigning those pipelined threads to a single dedicated core of a CPU architecture, according to the implementation scheme.

[0020] Figure 3C Examples Figure 3A A further flowchart of the method for prioritizing pipelined threads during a vSync window and assigning those pipelined threads to a single dedicated core of a CPU architecture, according to the implementation scheme.

[0021] Figure 4A An example is given of using conventional thread allocation techniques according to the implementation scheme. Figure 2A CPU utilization of the two large CPU cores and the single main core;

[0022] Figure 4B An example of using the method shown in Figure 3 is provided. Figure 2A The CPU utilization of the two large CPU cores and the single main core; and

[0023] Figure 5 An example of a battery-powered portable computing device (such as a mobile phone) is illustrated, which performs the method of Figure 3 for prioritizing pipelined threads during the vSync window and assigning the pipelined threads to a single dedicated core of the CPU architecture. Detailed Implementation

[0024] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as preferred or superior to other aspects.

[0025] In this description, the terms "application" or "image" may also include files with executable content, such as object code, scripts, bytecode, markup language files, and patches. Furthermore, the term "application" as used herein may also include files that are not inherently executable, such as documents that may need to be opened or other data files that need to be accessed.

[0026] The term "content" can also include files with executable content, such as object code, scripts, bytecode, markup language files, and patches. Furthermore, the "content" submitted herein can also include files that are not inherently executable, such as documents that may need to be opened or other data files that need to be accessed.

[0027] As used in this description, the terms “component,” “database,” “module,” “system,” and similar terms are intended to refer to a computer-related entity, whether it is hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. By way of example, an application running on a computing device and the computing device itself can both be components. One or more components may exist within a process and / or a thread of execution, and components may reside in a single computer and / or be distributed across two or more computers. Furthermore, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes, based on signals having one or more data packets (e.g., data from a component that interacts with a local system, another component in a distributed system, and / or other systems across a network such as the Internet).

[0028] Now for reference Figure 1 The figure illustrates a portable computing device (PCD) 500 (see Figure 500). Figure 5 How does the Completely Fair Scheduler of the Advanced Operating System (HLOS) manage the gaming computer applications 135 running on PCD 500 on display device 514 (see...) Figure 5 The functional block diagram shows the execution threads A, B, and C for rendering frames (N, N-1, N-2) on the current frame. Figure 1 As shown, most game workloads associated with the game application 135 running on the PCD500 have at least two or three critical CPU threads (A, B, C) that periodically wake up on the display device 514 every other display refresh interval, a phenomenon known to those skilled in the art as vertical synchronization (vSync).

[0029] The term "vSync" typically refers to how the frame rate of a gaming application is synchronized with the refresh rate of the game monitor (i.e., an 8.33ms interval for a 120Hz display panel). The workload for these two or three pipeline threads (A, B, and C) generally needs to be completed within the display vSync time budget (i.e., 8.33ms) to meet the desired game frame rate per second (fps) (i.e., 120fps). These threads A, B, and C are managed by the Completely Fair Scheduler (CFS) 145, which is part of the Advanced Operating System (HLOS) of the PCD 500. The CFS 145 will be described in more detail below.

[0030] The critical periodic per-frame CPU threads A, B, and C used for display frame rendering are known to those skilled in the art as frame pipeline threads / tasks (A, B, and C). The CPU workload for a given frame (N, N-1, N-2) is essentially split across these pipeline threads (A, B, and C); and all these pipeline threads (A, B, and C) run concurrently every vSync (here, for example, 8.33ms for a frame rate of 120Hz).

[0031] For computer game applications running on a PCD 500 with three pipelined threads (A, B, and C), the architecture of the frame pipeline 77 on the CPU500 is typically as follows: while thread A is working on frame (N); thread B will work concurrently on frame (N-1); and thread C will work concurrently on frame (N-2).

[0032] Once thread C has completed the final stage of its share of CPU work, it then submits its frames (N-2) to the graphics processing unit (GPU) 102 (see...). Figures 2A to 2B -GPU cluster 102) to complete the final hardware (HW) (i.e., GPU) accelerated frame rendering. Once GPU 102 has completed frame rendering, it will then signal to the display device (514 - see below). Figure 5 The newly rendered frame will be shown / displayed on display device 514 when the next vSync window begins.

[0033] The background section listed above generally refers to one problem in the prior art that involves balancing performance and power when supporting gaming applications 135, especially when the PCD 500 is running on battery power. A specific problem in the prior art is that if one of the pipeline threads (i.e., A, B, or C) does not complete its share of CPU work in time within the vSync budget (e.g., 8.33ms for a 120Hz frame rate), that particular thread (A, B, or C) may cause frame drops or junk.

[0034] PCD 500 HLOS (like the ANDROID™ brand and APPLE™ HLOS) typically have a large / significant CPU task density for a given gaming application 135 (e.g., approximately 35 tasks or more for gaming application 135). Typical gaming applications 135 known as of the time of writing include, but are not limited to, GENSHIN™ / HOK™ / FORTNITE™ branded games.

[0035] Supporting all threads / tasks in threads / tasks A, B, and C of these game applications requires CPUs 102 and 104 of the PCD 500 within the given SoC 502 (see...). Figures 2A to 2B The service is provided on time. This work is managed by the Completely Fair Scheduler (CFS) 145 mentioned above, which is typically located within the HLOS of the PCD 500 (like the ANDROID™ branded HLOS as of the time of writing).

[0036] Although there are numerous tasks / threads A, B, and C on the operating system, pipelined threads A, B, and C in conventional technologies typically do not have deterministic CPU scheduling from HLOS. Deterministic scheduling in existing technologies is generally not used because HLOSCFS 145 is designed as a general-purpose framework, and it is generally unaware that display frame rendering tasks will periodically wake up and run concurrently on a per-frame basis, such as... Figure 1 exemplified.

[0037] The existing HLOS CFS 145 typically causes these pipeline threads A, B, and C used for display frame rendering to hop around multiple CPUs 102, 104 based on a CFS strategy (which typically includes best-effort service power-efficient scheduling within a big.Little (bL) system, described in more detail below with reference to Figure 2). This can lead to a reduction in CPU instructions per cycle (IPC) and a decrease in CPU cache temporal locality.

[0038] Often, based on the workload patterns of these pipelined threads A, B, and C, a standard HLOS CFS 145 can package and schedule multiple critical pipelined tasks / threads A, B, and C onto the same CPUs 102 and 104 (tasks packaged on a single CPU 102 or 104); this, in turn, can drive each CPU 102 or 104 to operate at higher frequency corners, thus enabling operation on CPUs 102 and 104 that rely on limited battery power (see [link to relevant documentation]). Figure 5 The PCD 500 operates with significantly higher power extraction.

[0039] Such high power draw in existing technology for gaming applications typically results in both poor performance (frame dropping and low FPS) and high power consumption (watts) on the PCD 500. For high-performance gaming applications (such as, but not limited to, real-time 3D (RT3D) computer applications), the high power draw on the PCD 500 can easily lead to high heat dissipation, and the PCD 500 may approach or exceed its thermal specifications / limits.

[0040] Each game application 135 can have a different number / count of pipelined threads A, B, and C. Game application 135 can use a popular userspace thread hinting framework 140 known as of the time of writing (i.e., an Android™ branded operating system including the ANDROID™ Dynamic Performance Framework (ADPF) Application Performance Interface (API) and the Qualcomm Adaptive Performance Engine (QAPE) API) to mark these critical threads A, B, and C as pipelined threads. The thread hinting framework 140 in... Figure 1 As shown in the example, it communicates with HLOS CFS 145.

[0041] If CPU pipeline threads A, B, or C cannot operate on small CPUs 108 and 110 ( Figures 2A to 2B (For lightweight workloads, typically ordered execution CPUs) running to meet their per-frame vSync timing requirements, they are considered by CFS 145 and / or thread hinting framework 140 to be in the bL CPU subsystem (see...) Figures 2A to 2B ) is heavy-duty. Threads A, B, or C of this type are typically heavy-duty at CPUs with millions of instructions per second (MIPS), and also require high-performance CPUs like 114, 116, and 119. Figures 2A to 2B (Usually an out-of-order execution CPU) runs on to meet its vSync timing requirements per frame.

[0042] Figure 1 For bL CPU subsystem (see Figures 2A to 2B The HLOS CFS 145 manages task / thread allocation, causing heavy CPU threads (A, B, or C) to be scheduled on large CPUs 114, 116, and 119, while lightweight threads (D, E, or F, not listed) are scheduled on small CPUs 108 and 110.

[0043] Pipeline threads A, B, and C used for high-performance gaming are typically heavy on CPU MIPS, and even more so on large CPU cores 114, 116, and 119 (in...). Figures 2A to 2B It runs on the bL system shown. Generally speaking, the regular HLOS CFS 145 can only use the main core 119 when threads A, B, or C exceed a certain workload (CPU utilization threshold). Figure 2A (described in more detail below), at which point the thread will be moved to main core 119, only to be moved back to another smaller capacity core 114, 116 once its load drops below a predefined load threshold.

[0044] For example, in the prior art, most frequently after task / thread A, B, or C is moved back from main core 119, main core 119 (see [link to relevant documentation]) Figure 2AIt can be instructed to enter a deep power collapse state, which causes all local CPU caches 118 to be refreshed, and only wakes up again for a short period of time for the same heavy pipeline threads A, B or C; resulting in energy waste and loss of time cache locality.

[0045] While such conventional HLOS strategies for CPU core switching generally work adequately for CPU workloads at computational limits, these conventional HLOS strategies are less effective for... Figure 1 Display types with heavy CPU workloads, such as threads A, B, or C, do not scale or function well.

[0046] Therefore, in contrast to the conventional HLOS strategy, and according to one aspect of system 100 and method 101, each thread A, B, or C is assigned to a single large CPU core 114, 116, or 119, such that when thread A, B, or C is being processed during the vSync / scheduler compute window, each thread A, B, or C has a single dedicated core 114, 116, or 119 without any core switching.

[0047] Regarding this exemplary aspect, note that pipeline threads A, B, or C can be switched to different cores 114, 116, and 119 after the vSync window expires (i.e., after 8.33ms at 120Hz). According to another aspect, when the main core 119 exists in the CPU architecture (see...),... Figure 2A In the case of vSync windows, the heaviest pipeline threads (A, B, or C) determined by CFS 145 with the help of thread hinting framework 140 can be assigned by CFS 145 to the main core 119 for vSync windows. Other exemplary aspects of system 100 and method 101 will be described in further detail below.

[0048] Now for reference Figure 2A This diagram is a functional block diagram of an implementation of a system 100A with a multi-cluster heterogeneous processor architecture, including prioritizing pipelined threads A, B, and C during the vSync / scheduler compute window and assigning those pipelined threads to individual dedicated cores 114, 116, and 119. System 100A can be used on any computing device 500 (see [link to documentation]). Figure 5 This is implemented in the context of computing devices, including personal computers, workstations, servers, and portable computing devices (PCDs) such as cellular phones, portable digital assistants (PDAs), portable game consoles, handheld computers, or tablet computers.

[0049] The multi-cluster heterogeneous processor architecture includes multiple processor clusters 102, 104 communicating with the Fully Fair Scheduler 145 of the HLOS 130. As known in the art, each processor cluster 102, 104, 106 may include one or more processors or processor cores with corresponding dedicated caches 112, 118, 124 (e.g., Central Processing Units (CPUs) 108, 110, 114, 116, 119, Graphics Processing Units (GPUs) 120, 122, Digital Signal Processors (DSPs) 507 – see [link]). Figure 5 (etc.). Note that although regular hardware interrupts are understood by those skilled in the art, CPU clusters 104 and 106 can communicate with GPU cluster 106 at the hardware level.

[0050] exist Figure 2A In an exemplary implementation, processor clusters 102 and 104 may include a “big.LITTLE” heterogeneous architecture as described above, wherein processor cluster 102 includes a Little cluster and processor cluster 104 includes a Big cluster. The Little processor cluster 102 includes multiple central processing unit (CPU) cores 108 and 110 that are relatively slower and consume less power than the CPU cores 114, 116, and 119 in the Big processor cluster 104.

[0051] It should be understood that Big cluster CPU cores 114, 116, and 119 can be distinguished from Little cluster CPU cores 108 and 110 by, for example, relatively high instructions per cycle (IPC), higher operating frequency, and / or microarchitectural features that achieve relatively high performance at the cost of additional power. Furthermore, additional processor clusters can be included in system 100, such as processor cluster 106 including, for example, GPU cores 120 and 122.

[0052] The Big processor cluster may also include one or more master core CPUs 119. The master core CPU 119 may have relatively high instructions per cycle (IPC), high operating frequency, and / or achieve relatively higher performance than its adjacent big cores 114 and 116, but at the cost of additional power consumption, with one or more microarchitectural features. That is, the master core CPU 119 may have the highest IPC capacity and the highest power consumption compared to its two adjacent big cores 114 and 116.

[0053] System 100A is not limited to two small CPU cores 108, 110 and two large CPU cores 114, 116 and a single main CPU core 119. Additional or fewer CPU cores (i.e., more than two large CPU cores or more than one main CPU core) are possible and are included within the scope of this disclosure.

[0054] Each processor cluster 102, 104, and 106 may have independent cache memories 112, 118, and 124 used by the corresponding processor in system 100 to reduce the average time for accessing data from main memory 144. In one embodiment, the independent cache memories 112, 118, and 124 and main memory 144 may be organized into a hierarchical structure of cache levels (e.g., Level 1 (L1), Level 2 (L2), and Level 3 (L3)). Processor cluster 102 may include L2 cache 112, processor cluster 104 may include L2 cache 118, and processor cluster 106 may include L2 cache 124.

[0055] The Completely Fair Scheduler (CFS) 145 is part of the High-Level Operating System (HLOS) 130, as previously combined Figure 1 As described, the HLOS CFS 130 is responsible for managing the pipeline threads A, B, and C of frame pipeline 77. Specifically, the HLOS CFS 130 instructs which heavy-duty pipeline threads A, B, and C are assigned to each of the two large cores 114 and 116 and the single master core 119. The HLOS CFS 130 can maintain an ordered / ranked list of pipeline threads A, B, and C, where the workload size of each thread can be determined by the thread hinting frame and the HLOS CFS 130.

[0056] More specifically, HLOS CFS 130 can create a ranked / ordered list of threads A, B, and C marked as workload-intensive pipeline threads (i.e., heavy pipeline threads prompted by prompting frame 140). The workload of pipeline threads A, B, and C can be characterized as how long each thread will spend completing its task on the highest capacity CPU (which is... Figure 2A The agent working on a single main core 119 of the illustrated system 100A.

[0057] The largest CPU in CPU subsystem 104 (which is referred to as a single “main” core 119 of CPU cluster 104) is such a large CPU that it also gives the best CPU IPC for a given CPU workload at ISO-CPU frequency (the ISO prefix means equal) across all other large cores 114, 116 in CPU cluster, and typically also has a higher CPU-fMax corner (i.e., the maximum allowed CPU frequency) compared to the other large CPUs 114, 116 in CPU subsystem 104.

[0058] The more demanding the pipeline threads A, B, or C are, the more time they will typically take to complete their share of CPU work per frame. Due to the CPU IPC advantages of a single or multiple main cores (microarchitectural advantages and typically larger CPU caches), the inventors have observed that the most demanding threads A, B, or C will run at a relatively lower CPU frequency corner compared to the same threads running on the larger cores 114 and 116 of the CPU cluster 104, resulting in a significant power benefit for the same performance.

[0059] Therefore, according to an exemplary aspect of system 100A, HLOS CFS 130 will always instruct that single most demanding pipeline thread A, B, or C from an ordered / ranked list of threads to be executed by the highest-capacity master core 119. As the game scene being displayed on the display device 514 of PCD 500 changes, the relative demandingness order of these pipeline threads A, B, or C can easily change from one scene to the next; and the same applies to their placement on the master core 119 and the two large cores 114, 116.

[0060] Generally speaking, as a basis for comparison and in contrast to System 100A, a standard HLOS CFS 130 will typically only use the primary core 119 when thread A, B, or C exceeds a certain workload (CPU utilization) threshold. Once the workload threshold of a standard system is exceeded, the CFS 130 will move that thread (i.e., A, B, or C) to the primary core 119, only to move it back to another lower-capacity large core 114, 116 once its workload drops below a predefined workload threshold. Switching between cores 114, 116, or 119 can occur during a vSync window.

[0061] Meanwhile, contrary to conventional techniques, the method 101 and system 100 described herein generally avoid this back-and-forth migration across large cores 114, 116 and / or main core 119, and instead keep each pipeline thread A, B or C dedicated to a single core (114, 116 or 119).

[0062] according to Figure 2A In System 100A and Method 101, HLOS CFS 145 assigns the most heavily loaded pipeline thread (A, B, or C) from an ordered list of such threads to a single master core 119 if and only if the most heavily loaded pipeline thread is deemed worthy of prime. A pipeline thread is considered and marked as worthy of prime if it can no longer complete its work per frame within the vSync boundary at the Fmax of the large cores 114 and 116 CPUs, as evaluated in the most recent vSync window.

[0063] Once a pipelined thread is marked as worthy of Prime, System 100 can choose to have a lag window (a predefined time threshold; such as, but not limited to, approximately 100.0 milliseconds) until it can host the pipelined thread on the same main core 319; this further helps smooth frame-to-frame workload jitter and also avoids frequent task migrations. If SoC 502 has more than one main core (i.e., 119A, 119B - see below) Figure 2C If the process is complete, the next ordered heavy pipeline thread will repeat the process. The first and heaviest pipeline thread among the prime pipeline threads will be placed on the least loaded available main CPU core 319.

[0064] Once all pipeline threads worthy of a primary core have been allocated to the available number of primary cores 319, the next heavy pipeline thread (A, B, or C) from the ordered list of the next heavy pipeline threads (A, B, or C) will then be placed on the next highest capacity primary core 114 or 116; until all tasks / threads in the list of heavy pipeline threads maintained by CFS 145 are placed on their respective primary cores 114 or 116.

[0065] Typically, if there are more than one large core 114 or 116 with the same CPU capacity (i.e., the same CPU microarchitecture and the same CPU-fMax), CFS 145 will first select the large CPU 114 or 116 that has the lightest load for all other non-pipelined threads; this, in turn, allows for a more even distribution of the overall CPU workload across the system 100A. On some SoCs 502, the CPU capacity increment on large cores 114 or 116 may come solely from the CPU-fMax increment of large cores 114 or 116 (while the microarchitecture of all large cores 114 or 116 remains unchanged).

[0066] There are heavy migration costs associated with these pipeline threads (A, B, or C) (among the list of heavy pipeline threads maintained by CFS 145), which typically (in most cases) will continue to be served on the same large CPU 114, 116, or one or more main CPU 119s, unless their own relative heaviness changes significantly (possibly when the game scenario changes). The heaviness of these groups of pipeline threads A, B, or C is continuously monitored by HLOS CFS 145 approximately every other vSync window (i.e., an 8ms window at a 120Hz display refresh rate), which ensures that the heaviest pipeline thread among the pipeline threads (A, B, or C) is always served by the highest capacity large CPU 114, 116, or one or more main cores 119 (if the main core 119 exists in CPU architecture 100A).

[0067] For a given game scene displayed on display device 514 of PCD 500, the inventors have observed that the workload ranking / sorting of the group of heavy pipeline threads A, B, or C does not change frequently; and therefore, the pipeline thread placement between cores 114, 116, and 119 of cluster 104 improves processing efficiency, as follows: Figures 4A to 4B exemplified.

[0068] Figure 2A System 100A and Method 101 (see Figure 3) do not employ hard CPU affinity, but rather soft bias to avoid frequent and often unnecessary task migrations / load balancing. Pipeline threads (of A, B, or C) are typically assigned to a single CPU core 114, 116, or 119. This also results in a more consistent load pattern across all large CPU cores 114, 116, and the main core 119, and significantly reduces load spikes, which in turn leads to better SoC power consumption and performance. Method 101 and System 100 can significantly reduce fMax residency per large CPU.

[0069] Figure 2B It is a functional block diagram of an implementation of a system 100B with a multi-cluster heterogeneous processor architecture that includes prioritizing pipeline threads A, B, or C during a vSync window and assigning the pipeline threads to a single dedicated core. Figure 2B Basically similar Figure 2A The illustrated exemplary implementation is shown. Therefore, only the differences between the two figures will be described below.

[0070] Figure 2A The system 100A's multi-cluster heterogeneous processor architecture and Figure 2BA key difference between the multi-cluster heterogeneous processor architecture of System 100B and System 100B is that System 100B does not have a master core 119 in the large CPU cluster 104'. Instead of a master core 119, the large CPU cluster 104' has another large CPU core 121, which has the same processing capacity as the other two large CPU cores 114 and 116.

[0071] In other words, the three large cores 114, 116, and 121 of the large CPU cluster 104' have substantially equivalent processing capacity and power consumption. However, the system 100B is not limited to two small CPU cores 108 and 110 and three large CPU cores 114, 116, and 121. Additional or fewer CPU cores are possible for the system 100B and are included within the scope of this disclosure.

[0072] according to Figure 2B In one exemplary aspect of system 100B, the HLOS CFS 130 will always instruct the most heavily pipelined thread A, B, or C from an ordered / ranked list of threads to be executed by the large CPU cores 114, 116, or 121 with the lightest workload. As the game scene being displayed on the display device 514 of PCD 500 changes, the relative heaviness order of these pipelined threads A, B, or C can easily change from one scene to the next; and the same applies to thread placement on the three large cores 114, 116, and 121.

[0073] according to Figure 2B In System 100B and Method 101, once the HLOS CFS 145 assigns the most demanding pipeline thread (A, B, or C) from an ordered list of the most demanding pipeline threads (A, B, or C) to the first of the three large CPU cores 114, 116, or 121, the next demanding pipeline thread (A, B, or C) from an ordered list of the next demanding pipeline threads (A, B, or C) will then be placed on the next large CPU core 114, 116, or 121 with the next lightest workload; this continues until all tasks / threads in the list of demanding pipeline threads maintained by CFS 145 are placed on the corresponding large core 114, 116, or 121. This placement of threads among the three large CPU cores 114, 116, or 121 allows for a more even distribution of the overall CPU workload in System 100B.

[0074] Now for reference Figure 2CThe figure is a functional block diagram of an implementation of a system 100C with a multi-cluster heterogeneous processor architecture that includes prioritizing pipeline threads A, B, or C during the vSync window and assigning the pipeline threads to a single dedicated core. Figure 2C Basically similar Figure 2A The illustrated exemplary implementation is shown. Therefore, only the differences between the two figures will be described below.

[0075] Figure 2A The system 100A's multi-cluster heterogeneous processor architecture and Figure 2C A key difference between the System 100C and its multi-cluster heterogeneous processor architecture is that the System 100C has two main cores, 119A and 119B, within a large CPU cluster 104'.

[0076] Now for reference Figure 3A The diagram illustrates the use of vSync window 77 ( Figure 1 The flowchart of method 101 is as follows: During the process, pipeline threads A, B, or C are prioritized and assigned to a single dedicated core 114, 116, 119, or 121 of CPU architectures 104 and 104'. Step 305 is the first step of method 101.

[0077] In step 305, the Fully Fair Scheduler 145 can receive input from the game application 135 running on the PCD 500 to display the game on the display device 514 (see [link]). Figure 5 Frames N, N-1, and N-2 are created on the device at a predetermined frame rate (i.e., frames per second - fps). (See [link to documentation]) Figure 1 The predetermined frame rate is generally less than or equal to the display panel refresh rate.

[0078] As previously noted, as of the time of writing, the display device 514 of the PCD 500 can have a refresh rate of approximately 120.0 Hz. This translates to an interval of approximately 8.33 milliseconds (ms) to achieve this refresh rate of approximately 120.0 Hz. Other refresh rates, whether higher or lower, are possible and are included within the scope of this disclosure. For example, another common refresh rate as of the time of writing is 60 Hz, for which it translates to an interval of approximately 16.6 ms per frame.

[0079] Subsequently, in step 310, the identifier is responsible for creating frames N, N-1, and N-2 on the display device 514 every display refresh cycle (see...). Figure 1Multiple high-priority heavy CPU threads (i.e., periodic heavy threads, also known as pipeline threads). The number of such threads N, N-1, N-2 generally corresponds to the number of large cores 114, 116, 121 and one or more main cores 119 (if any) within the CPU architecture 104, 104'.

[0080] The term "high-priority heavy" generally corresponds to a workload level, meaning that the most CPU-loaded thread will have the highest priority and the least CPU-loaded thread will have the lowest priority. This workload priority generally corresponds to CPU utilization, as understood by those skilled in the art.

[0081] This step 310 is generally performed by the Completely Fair Scheduler (CFS) 145 running on the CPU with the assistance of the thread hint framework 140, as described above. Figure 1 As described. If the thread indicates that frame 140 does not exist, CFS 145 will perform step 310 entirely on its own.

[0082] Next, in step 315, during a predetermined time period that occurs again while the game application 135 is running on PCD 500 (i.e., every 8ms for a refresh rate of 120Hz, or, as another example, approximately every 100.0ms), CFS 145 creates a ranking (i.e., an ordered list) of high-priority heavy threads based on the workload level of each heavy thread. The heavy thread workload history in step 315 can be maintained by CFS 145. Figure 1 In the example described, three threads N, N-1, and N-2 will be ranked / placed in priority, with the heaviest thread having the highest priority and the lightest thread having the lowest priority.

[0083] Furthermore, in step 315, CFS 145 also determines the workload of each CPU core, including the large CPU cores 114, 116, and 121, and the primary CPU cores 119, 119A, and 119B (if any primary cores are present). During step 315, CFS 145 also creates a ranking of the workload levels of CPU cores 114, 116, 121, 119, 119A, and 119B based on their respective workload levels.

[0084] Subsequently, in decision step 320, it is determined whether there is one or more pipeline threads worthy of the Prime CPU.

[0085] like Figure 2A and Figure 2C As illustrated, these diagrams depict a large CPU cluster 104 with one or more main cores 119 ( Figure 2A ) or 104 ( Figure 2C As previously described, Figure 2A The largest CPU in the large CPU cluster 104, 119, is generally the main CPU core 119. The main CPU cores 119, 119A, and 119B of the large CPU cluster 104 typically provide optimal CPU IPC for a given CPU workload across all other large cores 114 and 116 in the CPU cluster 104 at ISO-CPU frequency. The main CPU cores 119, 119A, and 119B typically have a higher CPU-fMax corner (i.e., maximum allowed CPU frequency) compared to the other large CPUs 114 and 116 in the CPU subsystem / architecture 104.

[0086] at the same time, Figure 2B The CPU subsystem / architecture 104' does not have a main core 119 (see [link]). Figure 2A ). Rather, compared to Figure 2A The CPU architecture 104 features two large CPU cores, 114 and 116. Figure 2B The CPU architecture 104' has three large CPU cores 114, 116, and 121. As previously noted, method 100 and system 101 are not limited to... Figures 2A to 2C The illustrated number of cores 108, 110, 114, 116, 119, 119A, 119B, 121, 120, and 122. Fewer or more cores may be used, including the main cores 119, 119A, and 119B, without departing from this disclosure.

[0087] This decision step 320 depends on the type of CPU architecture 104, 104' used. If a CPU architecture with main CPU cores 119, 119A, 119B exists, then... Figure 3A Method 101A proceeds from decision step 320 along the "Yes" branch to step 325. If a CPU architecture 104', which has no main core but only large CPU cores 114, 116, and 121, is adopted, then... Figure 3A Method 101A proceeds from decision step 320 along the "No" branch to step 330.

[0088] In step 325, Figure 3A Method 101A then continue to Figure 3B-1 Step 335. Meanwhile, in step 330, Figure 3A Method 101A then continue to Figure 3C Step 365.

[0089] Now for reference Figure 3B-1 The illustration shows Figure 3AThe flowchart continues from method 101A for prioritizing pipelined threads A, B, or C during vSync window 77 and assigning those pipelined threads to individual dedicated cores 114, 116, 119, 119A, 119B, 121 of CPU architectures 104, 104'. Step 335 determines... Figure 3B-1 The first step of method 101B listed in the document is from... Figure 3A Step 325 follows.

[0090] In decision step 335, CFS 145 determines whether a ( Figure 2A ) or more than one ( Figure 2C Unallocated main CPU cores 119, 119A, and 119B. If the query for step 335 is negative, the process follows the "No" branch to step 339, in which method 101B proceeds to... Figure 3C Step 365.

[0091] However, if the query for decision step 335 is affirmative, then proceed to decision step 350 via the "yes" branch. In decision step 350, CFS 145 iterates over the list of unassigned pipeline threads for the value PRIME (traversing each pipeline thread in the list of unassigned pipeline threads for that value PRIME).

[0092] Next, in decision step 351, for a specific thread worthy of PRIME, CFS 145 determines whether the currently worthy thread has already been assigned to main CPUs 119, 119A, and 119B. If the query for decision step 351 is negative, the process proceeds to step 353 via the "No" branch. If the query for decision step 351 is positive, the process proceeds to step 352 via the "Yes" branch.

[0093] In step 352, CFS 145 uses the same main CPUs 119, 119A, and 119B as the thread currently worthy of PRIME in order to avoid frequent task migrations. Method 101B then returns to stage 350.

[0094] Simultaneously, in step 353, as a result of the "No" branch of step 351, CFS 145 can place the heaviest pipelined thread among the pipelined threads worthy of PRIME onto the main CPUs 119, 119A, and 119B that have not yet been assigned pipelined threads. Among the unassigned main CPUs 119, 119A, and 119B, the main CPUs 119, 119A, and 119B with the lowest load can be selected. During this step 353, CFS 145 can create a ranking of the main CPUs 119, 119A, and 119B based on their existing / current workload levels. And in this step 353, the main CPUs 119, 119A, and 119B with the lowest load can be selected. In step 353, main CPU cores 119, 119A, and 119B with lighter workload levels receive higher priority threads with higher workload levels, and main CPU cores 119, 119A, and 119B with heavier workload levels receive lower priority threads with lighter workload levels.

[0095] Next, in decision step 354, CFS 145 can determine whether there are any remaining unallocated pipeline threads worthy of PRIME, and whether there are any unallocated main CPU cores 119 available for allocation by CFS 145. If the query for decision step 354 is affirmative, the process follows the "yes" branch back to step 350, where CFS 145 iterates / examines the list of pipeline threads worthy of PRIME to determine which pipeline threads have not yet been allocated. If the query for decision step 354 is negative, the process follows the "no" branch to step 355.

[0096] In step 355, CFS 145 iterates over its list of pipelined threads that have not yet been assigned to large CPUs 114, 116, and 121. Then, in decision step 356, CFS 145 examines the specific pipelined thread from the list of specific pipelined threads to determine whether that specific pipelined thread has already been assigned to large CPUs 114, 116, and 121. If the query for decision step 356 is affirmative, method 101B follows the "yes" branch and continues to step 357. If the query for decision step 356 is negative, it follows the "no" branch to step 358.

[0097] In step 357, CFS 145 uses the same large CPUs 114, 116, and 121 that have already been assigned to existing pipeline threads to avoid frequent task migrations. Method 101B then continues back to step 355, in which CFS 145 iterates through its list to identify those threads that have not yet been assigned to large CPUs 114, 116, and 121.

[0098] In step 358, flowing from the "No" branch of decision step 356, CFS 145 can place the next heaviest pipelined thread in the pipelined threads onto the large CPUs 114, 116, and 121 that have not yet been assigned to pipelined threads. Among the unassigned large CPUs 114, 116, and 121, the large CPU with the lowest load can be selected. During this step 358, CFS 145 can create a ranking of the large CPUs 114, 116, and 121 based on their existing / current workload levels. And in this step 358, the large CPUs 114, 116, and 121 with the lowest load can be selected. After step 358, method 101B flows to... Figure 3B-2 Step 359.

[0099] Now for reference Figure 3B-2 The illustration shows Figure 3B-1 The following is a continuation flowchart of method 101B for prioritizing pipelined threads during the vSync window and assigning those threads to a single dedicated core of the CPU architecture. Step 359 is... Figure 3B-2 The first step. From the above Figure 3B-1 Step 358 leads to step 359, which is the final decision step.

[0100] In decision step 359, CFS 145 determines whether there are any remaining pipeline threads to be allocated to large CPUs 114, 116, and 121. If the query in decision step 359 is affirmative, the process returns to the "yes" branch. Figure 3B-1 Step 355. If the query for decision step 359 is negative, then follow the "No" branch to decision step 361.

[0101] In step 361, CFS 145 determines all threads (N, N-1, N-2-) at the end of the vSync window / schedule computation period. Figure 1 Have all threads completed their workloads (i.e., no more frames to render for the application)? If application 135 has more frames to render on display device 514, proceed to decision step 362 via the "Yes" branch. Otherwise, if CFS 145 determines all threads (N, N-1, N-2-) at the end of the vSync window... Figure 1 Once all methods have completed their workloads, method 101B can proceed from decision step 361 along the "No" branch, where method 101B then terminates and / or can return to... Figure 3A Step 305.

[0102] In decision step 362, it is determined whether the predetermined time period for the recurrence of step 315 (when the rank of the high-priority thread is created) has ended. If the time period has not expired, the process follows the "No" branch back to decision step 361. If the time period has expired, the process follows the "Yes" branch to step 363, which causes method 101C to return to... Figure 3A Step 315.

[0103] Now for reference Figure 3C The illustration shows Figure 3A The flowchart continues from method 101A, which prioritizes pipelined threads A, B, or C during vSync window 77 and assigns those pipelined threads to individual dedicated cores 114, 116, 119, 121 of CPU architectures 104, 104'. Step 365 is the first step of method 101C, as listed in Figure 3B, and is from... Figure 3A Step 330 or Figure 3B-1 Step 339 follows.

[0104] In step 365, CFS 145 iterates over the list of unassigned pipeline threads with the value BIG. This step 365 is similar to... Figure 3B-1 Step 355.

[0105] Subsequently, in decision step 370, for each pipeline thread worthy of BIG, CFS 145 determines whether the pipeline thread worthy of BIG has already been assigned to large CPUs 114, 116, and 121. If the query in decision step 370 is affirmative, the process proceeds to step 371 via the "yes" branch. If the query in decision step 370 is negative, the process proceeds to step 373 via the "no" branch.

[0106] In step 371, CFS 145 uses the same large CPUs already allocated to specific large CPUs 114, 116, and 121 to avoid task migration. Method 101C then returns to step 365, where CFS 145 searches for unallocated pipeline threads worthy of a BIG.

[0107] In step 373, which is a result of the "No" branch of step 370, CFS 145 can place the next heaviest pipeline thread among the pipeline threads worthy of BIG onto the large CPUs 114, 116, and 121 that have not yet been allocated pipeline threads. This step 373 is similar to the one described above. Figure 3B-1 Step 358. Among the unassigned large CPUs 114, 116, and 121, the large CPU with the lowest load can be selected.

[0108] exist Figure 3CDuring step 373, CFS 145 can create a ranking of the large CPUs 114, 116, and 121 based on their existing / current workload levels. And in step 373, the large CPUs 114, 116, and 121 with the lowest workload can be selected. After step 373, method 101B flows to... Figure 3C The decision step is 374. Through step 373, large CPU cores 114, 116, and 121 with lighter workload levels receive higher priority threads with higher workload levels, and large CPU cores 114, 116, and 121 with heavier workload levels receive lower priority threads with lighter workload levels.

[0109] exist Figure 3C In decision step 374, CFS 145 determines whether there are any remaining pipeline threads of BIG value to be allocated to large CPUs 114, 116, and 121. This step 374 is similar to... Figure 3B-2 Step 359. If the answer to the question in step 374 is yes, then follow the "yes" branch back to... Figure 3C Step 365. If the query for decision step 374 is negative, then follow the "No" branch to decision step 381.

[0110] Subsequently, in decision step 381, CFS 145 determines all threads (N, N-1, N-2-) at the end of the vSync window. Figure 1 ) Have they all completed their workloads (i.e., there are no more frames to render for the application)? If the application has more frames to render on display device 514, then follow the "Yes" branch to decision step 382.

[0111] Otherwise, if CFS 145 determines all threads (N, N-1, N-2-) at the end of the vSync window... Figure 1 If they have completed their workload, then Figure 3C Method 101C can follow the "No" branch from decision step 381, where method 101C then ends and / or can return to... Figure 3A Step 305.

[0112] In decision step 382, ​​it is determined whether the predetermined time period for the recurrence of step 315 (when the ranking of the high-priority thread is created) has ended. If the time period has not expired, the process follows the "No" branch back to decision step 381. If the time period has expired, the process follows the "Yes" branch to step 383, which causes method 101C to return to... Figure 3A Step 315.

[0113] Now for reference Figure 4A This diagram illustrates the use of conventional thread allocation techniques. Figure 2A The CPU utilization of the two large CPU cores (114 and 116) and the single main core (119). Meanwhile, Figure 4B An example of using the method shown in Figure 3 is provided. Figure 2A CPU utilization of the two large CPU cores 114 and 116 and a single main core 119.

[0114] Figures 4A to 4B The Y-axis represents the CPU utilization per CPU core (ranging from 0 to 1024; higher CPU utilization corresponds to higher CPU frequency), where Figures 4A to 4B The X-axis can represent the actual time elapsed, usually in seconds. Figure 4A This shows the CPU utilization of pipelined threads managed by conventional thread allocation techniques compared to... Figure 4B The CPU utilization shown is significantly higher and noisy.

[0115] like Figure 4B As shown, method 101 typically significantly reduces the CPU utilization of each large CPU core 114, 116 by 400B. Meanwhile, compared to conventional thread allocation, method 101 slightly increases the CPU utilization of the main core 119 by 400B (by...). Figure 4A The utilization graph of the main core 119 and Figure 4B (Compare the utilization graph of the main core 119). That is, Figure 4A Conventional pipelined thread allocation techniques may not fully utilize the main core 119, while method 101 in Figure 3 uses the main core 119 at a slightly higher workload level without maximizing its utilization.

[0116] Figure 4A The random spikes in CPU utilization shown have been significantly reduced and / or eliminated, such as Figure 4B As shown. Figure 4B This demonstrates how the two large CPU cores, 114 and 116, can be compared. Figure 4A The CPU frequency shown executes the same pipelined threads at a much lower frequency.

[0117] Now for reference Figure 5 The diagram illustrates an example of a PCD 500 (such as a mobile phone, portable digital assistant (PDA), portable game console, VR console, handheld computer, or tablet computer). The PCD 500 performs the operations shown in Figure 3 for pipeline threads N, N-1, and N-2 during the vSync window. Figure 1 The method of prioritizing and assigning the pipeline thread to a single dedicated core 104 of its CPU architecture 504.

[0118] PCD 500 may include Figures 2A to 2B The multi-cluster heterogeneous processor architecture includes multiple processor clusters 102, 104, 106, and the Nth cluster, all controlled by HLOS. For clarity, Figure 5 Some interconnects, signals, etc. are not shown.

[0119] PCD 500 may include SoC 502. SoC 502 may include CPU 504, Neural Processing Unit (NPU) 505 (for Artificial Intelligence (AI) components), Graphics Processing Unit (GPU) 506, Digital Signal Processor (DSP) 507, Analog Signal Processor 508, Modem / Modem Subsystem 554, or other processors. CPU 504 may include as described above and as... Figures 2A to 2B One or more CPU clusters 102, 104, 104' and 106 are illustrated.

[0120] The core of clusters 102, 104, and 106 can be found in the above text. Figures 2A to 2B The CPU clusters 102, 104, and 106 can be configured in the manner described in Figure 3 to perform the above-described operations of the pipelined thread allocation system and method of this disclosure. They can also perform other operations of the type typically performed in the PCD 500.

[0121] Alternatively or additionally, any processor in the processor (such as NPU 505, GPU 506, DSP 507, etc.) may have cores, as referenced above. Figures 2A to 2B Configure the above operations of the pipelined thread allocation system and method of this disclosure in the manner described in Figure 3.

[0122] Display controller 509 and touchscreen controller 512 are coupled to CPU 504. A touchscreen display 514 external to SoC 502 is coupled to display controller 510 and touchscreen controller 512. The display or display panel 514 can present... Figure 1 The pipeline threads N, N-1, and N-2 are illustrated.

[0123] PCD 500 may also include a video decoder 516 coupled to CPU 504. A video amplifier 518 may be coupled to the video decoder 516 and the touchscreen display 514. A video port 520 may be coupled to the video amplifier 518. A universal serial bus (“USB”) controller 522 may also be coupled to CPU 504, and a USB port 524 may be coupled to the USB controller 522. A subscriber identity module (“SIM”) card 526 may also be coupled to CPU 504.

[0124] One or more memory 144 (see also) Figures 2A to 2C This memory can be coupled to CPU 504. One or more memory modules 144 may include both volatile and non-volatile memory. Examples of volatile memory include static random access memory (“SRAM”) and dynamic random access memory (“DRAM”). Such memory may be external to SoC 502 or internal to SoC 502. One or more memory modules 144 may include local cache memory or system-level cache memory 112, 118, 124, such as... Figures 2A to 2B As shown.

[0125] A stereo audio codec 534 can be coupled to an analog signal processor 508. Additionally, an audio amplifier 536 can be coupled to the stereo audio codec 534. A first stereo speaker 538 and a second stereo speaker 540 can be coupled to the audio amplifier 536, respectively. Furthermore, a microphone amplifier 542 can be coupled to the stereo audio codec 534, and a microphone 544 can be coupled to the microphone amplifier 542.

[0126] An FM radio tuner 546 may be coupled to a stereo audio codec 534. An FM antenna 548 may be coupled to an FM radio tuner 546. Additionally, a stereo headset 550 may be coupled to a stereo audio codec 534. Examples of other devices that may be coupled to a CPU 504 include one or more digital (e.g., CCD or CMOS) cameras 552.

[0127] A modem or RF transceiver 554 can be coupled to an analog signal processor 508 and a CPU 504. An RF switch 556 can be coupled to an RF transceiver 554 and an RF antenna 558. Additionally, a keypad 560 and a mono headset 562 with a microphone can be coupled to the analog signal processor 508. (This is in addition to the components located at cores 5041 to 504.) M In addition to a thermal sensor located in or near the SoC 502, the SoC 502 may also have one or more internal or on-chip thermal sensors 570. A power supply 574 and a PMIC 576 power the SoC 502.

[0128] like Figure 5 (and Figures 1 to 2B The Completely Fair Scheduler 145 illustrated herein may include software and / or firmware executed by a multi-core CPU 504 having various CPU clusters 102, 104. The firmware or software may be stored in any of the aforementioned memories, or in local memory directly accessible to the processor hardware executing the software or firmware thereon.

[0129] Execution of such firmware or software can control aspects of any of the methods described above or configure aspects of any of the systems described above. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware can be an example of a "computer-readable medium" as understood in the patent dictionary.

[0130] In certain respects, one or more method steps in the method steps described herein (such as...) Figures 3A to 3C (As illustrated) can be stored in memory 144 as computer program instructions. These instructions can be executed by a digital signal processor or a multi-core heterogeneous central processing unit 504, digital signal processor 507, or another processor to perform the methods described herein. Furthermore, the multi-core CPU 504, memory 144, instructions stored in that memory, or combinations thereof can serve as components for performing one or more method steps in the method steps described herein.

[0131] Certain steps in the process or process flow described in this specification naturally occur before other steps in order for the invention to function as described. However, the invention is not limited to the order of the described steps if such order or sequence does not alter the functionality of the invention. That is, it is to be understood that certain steps may be performed before, after, or in parallel (substantially) with other steps without departing from the scope and spirit of the invention. In some cases, certain steps may be omitted or not performed without departing from the invention. Furthermore, words such as "then," "furthermore," and "next step" are not intended to limit the order of steps. These words are only used to guide the reader through the description of the exemplary method.

[0132] Furthermore, those skilled in the art of programming can, without difficulty, write computer code or identify appropriate hardware and / or circuitry to implement the disclosed invention, based on flowcharts and associated descriptions, for example, in this specification.

[0133] Therefore, it is considered that disclosures of specific program code instruction sets or detailed hardware devices are not necessary for a full understanding of how to implement and use the invention. The inventive functionality of the claimed computer-implemented process is explained in more detail above, in conjunction with diagrams illustrating various process flows.

[0134] In one or more exemplary aspects, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored or transmitted as one or more instructions or code on a computer-readable medium.

[0135] Computer-readable media include both computer storage media and communication media, encompassing any medium that facilitates the transfer of a computer program from one location to another. Storage media can be any available medium that a computer can access. For example, and not limitingly, such computer-readable media can include RAM, ROM, EEPROM, NAND flash memory, NOR flash memory, M-RAM, P-RAM, R-RAM, CD-ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

[0136] Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (“DSL”), or wireless technologies such as infrared, radio, and microwave, then that coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.

[0137] Specific implementation examples are described in the following numbered clauses.

[0138] 1. A method for prioritizing and allocating threads in a CPU architecture, wherein the method includes:

[0139] Receive input to create frames at a predetermined rate on the display device of a battery-powered portable computing device;

[0140] The identifier is responsible for creating the frame and corresponds to the execution thread of multiple first CPU cores in the CPU architecture, the CPU

[0141] The architecture includes a first CPU core and a second CPU core, each first CPU core having a first processing capacity and each second CPU core having a second processing capacity, wherein the first processing capacity is greater than the second processing capacity.

[0142] Within a predetermined time period, a ranking of the threads is created based on their workload levels.

[0143] Determine the workload level of each primary CPU core;

[0144] A ranking of the first CPU cores is created based on the workload level of their existence; and

[0145] Each thread is assigned to a single first CPU core based on the ranking of the first CPU core and the ranking of the threads.

[0146] 2. The method according to Clause 1, wherein a first CPU core with a lighter workload level receives a higher priority thread with a higher workload level, and a first CPU core with a heavier workload level receives a lower priority thread with a lighter workload level.

[0147] 3. The method according to any one of Clauses 1 to 2, wherein the CPU architecture includes a main CPU core, and the method further includes: allocating a highest priority thread with the highest workload to the main CPU core.

[0148] 4. The method according to any one of clauses 1 to 3, the method further comprising: after allocating the highest priority thread with the highest workload to the main CPU core, allocating any remaining threads of ranking among the first CPU cores.

[0149] 5. The method according to any one of Clauses 1 to 4, wherein the predetermined time period includes a multiple of the display device refresh rate.

[0150] 6. The method according to any one of clauses 1 to 5, wherein the fully fair scheduler identifies the execution thread responsible for creating the frame and corresponding to at most the number of first CPU cores in the CPU architecture.

[0151] 7. The method according to any one of clauses 1 to 6, wherein the fully fair scheduler receives data about the executing thread from the thread hinting framework.

[0152] 8. The method according to any one of Clauses 1 to 7, wherein the execution thread assigned to the first CPU core continues to use the same first CPU core until the thread is ranked as the highest priority most intensive thread at the end of the predetermined time period, at the end of the predetermined time period, the highest priority thread will be moved to a single master core or one of a plurality of master cores in a subsequent predetermined time period.

[0153] 9. The method according to any one of clauses 1 to 8, wherein if an execution thread is assigned to a first CPU core, the thread will continue to use the same first CPU core until frame rendering is complete.

[0154] 10. The method according to any one of Clauses 1 to 9, wherein the battery-powered portable computing device includes at least one of: a mobile phone, a portable digital assistant (PDA), a portable game console, a VR console, a handheld computer, or a tablet computer.

[0155] 11. A system for prioritizing and allocating threads in a CPU architecture, the system comprising:

[0156] A scheduler, configured to receive input to create frames at a predetermined rate on a display device of a battery-powered portable computing device, identifies execution threads responsible for creating the frames and corresponding to a plurality of first CPU cores in a CPU architecture, the CPU architecture including first CPU cores and second CPU cores, each first CPU core having a first processing capacity and each second CPU core having a second processing capacity, the first processing capacity being greater than the second processing capacity; and

[0157] Within a predetermined time period, the scheduler creates a ranking of the threads based on their workload levels; the scheduler determines the workload level of each first CPU core; the scheduler creates a ranking of the first CPU cores based on their workload levels; and the scheduler assigns each thread to a single first CPU core based on the ranking of the first CPU cores and the ranking of the threads.

[0158] 12. The system according to Clause 11, wherein a first CPU core with a lighter workload level receives a higher priority thread with a higher workload level, and a first CPU core with a heavier workload level receives a lower priority thread with a lighter workload level.

[0159] 13. The system according to any one of Clauses 11 to 12, wherein the CPU architecture includes a single or multiple main CPU cores, and the system further includes: a single main core or one of the multiple main CPU cores, wherein the single main core or one of the multiple main CPU cores is assigned a highest priority thread with the highest workload.

[0160] 14. The system according to any one of clauses 11 to 13, the system further comprising: after allocating the highest priority thread with the highest workload to the single master core or one of the plurality of master CPU cores, the scheduler allocates any remaining threads of ranking among the first CPU cores.

[0161] 15. The system according to any one of Clauses 11 to 14, wherein the predetermined time period includes a multiple of the display device refresh rate.

[0162] 16. The system according to any one of clauses 11 to 15, wherein the scheduler identifies the execution thread responsible for creating the frame and corresponding to at most the number of first CPU cores in the CPU architecture.

[0163] 17. The system according to any one of clauses 11 to 16, wherein the scheduler receives data about the executing thread from the thread hinting framework.

[0164] 18. The system according to any one of Clauses 11 to 17, wherein an execution thread assigned to a first CPU core continues to use the same first CPU core until the thread is ranked as the highest priority most demanding thread at the end of the predetermined time period, at which point the highest priority thread will be moved to the single master core or one of the multiple master cores in a subsequent predetermined time period.

[0165] 19. The system according to any one of clauses 11 to 18, wherein, when an execution thread is assigned to a first CPU core, the thread continues to use the same first CPU core until frame rendering is complete.

[0166] 20. The system according to any one of Clauses 11 to 19, wherein the battery-powered portable computing device includes at least one of: a mobile phone, a portable digital assistant (PDA), a portable game console, a VR console, a handheld computer, or a tablet computer.

[0167] 21. A system for prioritizing and allocating threads in a CPU architecture, the system comprising:

[0168] A scheduler configured to receive input to create frames at a predetermined rate on a display device of a battery-powered portable computing device, the scheduler also configured to identify execution threads responsible for creating the frames and corresponding to a plurality of first processing units in the CPU architecture, the CPU architecture including first processing units and second processing units, each first processing unit having a first processing capacity and each second processing unit having a second processing capacity, the first processing capacity being greater than the second processing capacity; and

[0169] Within a predetermined time period, the scheduler is configured to create a ranking of the threads based on their workload levels; the scheduler is configured to determine the workload level of each first processing unit; the scheduler is configured to create a ranking of the first processing units based on their workload levels; and the scheduler is configured to assign each thread to a single first processing unit based on the ranking of the first processing units and the ranking of the threads.

[0170] 22. The system according to Clause 21, wherein the first processing unit and the second processing unit include at least one of: a central processing unit, a multi-core processing unit, a digital signal processor, a graphics processing unit, and combinations thereof.

[0171] 23. The system according to clauses 21 to 22, wherein a first processing unit having a lighter workload level receives a higher priority thread having a higher workload level, and a first processing unit having a heavier workload level receives a lower priority thread having a lighter workload level.

[0172] 24. The system according to clauses 21 to 23, wherein the CPU architecture includes a single master core or multiple master CPU cores, and the system further includes: one of the single master core or multiple master CPU cores, wherein the single master core or multiple master CPU cores is assigned a highest priority thread with the highest workload.

[0173] 25. A computer program product for prioritizing and allocating threads in a CPU architecture, the computer program product having a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form, the instructions configuring the CPU architecture, when executed by the CPU architecture, to:

[0174] Receive input to create frames at a predetermined rate on the display device of a battery-powered portable computing device;

[0175] The identifier is responsible for creating the frame and corresponds to the execution thread of a plurality of first CPU cores in the CPU architecture, the CPU architecture including first CPU cores and second CPU cores, each first CPU core having a first processing capacity and each second CPU core having a second processing capacity, the first processing capacity being greater than the second processing capacity;

[0176] Within a predetermined time period, a ranking of the threads is created based on their workload levels.

[0177] Determine the workload level of each primary CPU core;

[0178] A ranking of the first CPU cores is created based on the workload level of their existence; and

[0179] Each thread is assigned to a single first CPU core based on the ranking of the first CPU core and the ranking of the threads.

[0180] 26. The computer program product according to Clause 25, wherein a first CPU core having a lighter workload level receives a higher priority thread having a higher workload level, and a first CPU core having a heavier workload level receives a lower priority thread having a lighter workload level.

[0181] 27. The computer program product according to Clauses 25 to 26, wherein the CPU architecture includes a single main CPU core or multiple main CPU cores, and the method further includes: assigning a highest priority thread with the highest workload to one of the single main CPU core or multiple main CPU cores.

[0182] 28. The computer program product according to clauses 25 to 27, wherein the instructions further configure the CPU architecture to: after allocating the highest priority thread with the highest workload to the main CPU core, allocate any remaining threads of ranking among the first CPU cores.

[0183] 29. The computer program product according to Clauses 25 to 28, wherein the predetermined time period includes a multiple of the display device refresh rate.

[0184] 30. The computer program product according to Articles 25 to 29, wherein the instructions further configure the CPU architecture to: identify the execution thread responsible for creating the frame and corresponding only to at most the number of first CPU cores in the CPU architecture.

[0185] Alternative embodiments will become apparent to those skilled in the art to which this disclosure pertains, without departing from the scope of this disclosure. Therefore, while the selected aspects have been illustrated and described in detail, it should be understood that various substitutions and changes may be made therein without departing from the scope of this disclosure as defined by the following claims.

Claims

1. A method for prioritizing and allocating threads in a CPU architecture, the method comprising: Receive input to create frames at a predetermined rate on the display device of a battery-powered portable computing device; The identifier is responsible for creating the frame and corresponds to the execution thread of a plurality of first CPU cores in the CPU architecture, the CPU architecture including first CPU cores and second CPU cores, each first CPU core having a first processing capacity and each second CPU core having a second processing capacity, the first processing capacity being greater than the second processing capacity; Within a predetermined time period, a ranking of the threads is created based on their workload levels. Determine the workload level of each primary CPU core; A ranking of the first CPU cores is created based on the workload level of the first CPU cores. as well as Each thread is assigned to a single first CPU core based on the ranking of the first CPU core and the ranking of the threads.

2. The method of claim 1, wherein a first CPU core with a lighter workload level receives a higher priority thread with a higher workload level, and a first CPU core with a heavier workload level receives a lower priority thread with a lighter workload level.

3. The method according to claim 1, wherein the CPU architecture includes a main CPU core, and the method further includes: The highest priority thread with the highest workload is assigned to the main CPU core.

4. The method according to claim 3, further comprising: After allocating the highest priority thread with the highest workload to the main CPU core, any remaining threads ranked among the first CPU cores are allocated.

5. The method according to claim 1, wherein the predetermined time period includes a multiple of the display device refresh rate.

6. The method of claim 1, wherein the Fully Fair Scheduler identifies the execution thread responsible for creating the frame and that corresponds at most to the number of first CPU cores in the CPU architecture.

7. The method of claim 6, wherein the Fully Fair Scheduler receives data about the executing thread from the thread hinting framework.

8. The method of claim 4, wherein the execution thread assigned to the first CPU core continues to use the same first CPU core until the thread is ranked as the highest priority most intensive thread at the end of the predetermined time period, at which point the highest priority thread will be moved to a single master core or one of a plurality of master cores in a subsequent predetermined time period.

9. The method of claim 1, wherein if the execution thread is assigned to the first CPU core, the thread will continue to use the same first CPU core until frame rendering is complete.

10. The method of claim 1, wherein the battery-powered portable computing device comprises at least one of: a mobile phone, a portable digital assistant (PDA), a portable game console, a VR console, a handheld computer, or a tablet computer.

11. A system for prioritizing and allocating threads in a CPU architecture, the system comprising: A scheduler configured to receive input to create frames at a predetermined rate on a display device of a battery-powered portable computing device, the scheduler being configured to identify an execution thread responsible for creating the frames and corresponding to a plurality of first CPU cores in the CPU architecture, the CPU architecture including first CPU cores and second CPU cores, each first CPU core having a first processing capacity and each second CPU core having a second processing capacity, the first processing capacity being greater than the second processing capacity; and Within a predetermined time period, the scheduler is configured to create a ranking of the threads based on their workload levels. The scheduler is configured to determine the workload level of each first CPU core; the scheduler is configured to create a ranking of the first CPU cores based on the workload level of the first CPU cores. Furthermore, the scheduler is configured to assign each thread to a single first CPU core based on the ranking of the first CPU core and the ranking of the threads.

12. The system of claim 11, wherein a first CPU core having a lighter workload level receives a higher priority thread having a higher workload level, and a first CPU core having a heavier workload level receives a lower priority thread having a lighter workload level.

13. The system of claim 11, wherein the CPU architecture comprises one or more main CPU cores, and the system further comprises: A single master core or one of the plurality of master CPU cores is assigned a highest priority thread with the highest workload.

14. The system of claim 13, further comprising: After assigning the highest priority thread with the highest workload to the single master core or one of the plurality of master CPU cores, the scheduler assigns any remaining threads of ranking among the first CPU cores.

15. The system of claim 11, wherein the predetermined time period includes a multiple of the display device refresh rate.

16. The system of claim 11, wherein the scheduler identifies the execution thread responsible for creating the frame and corresponding to at most the number of first CPU cores in the CPU architecture.

17. The system of claim 16, wherein the scheduler receives data about the executing thread from the thread hinting framework.

18. The system of claim 14, wherein the execution thread assigned to the first CPU core continues to use the same first CPU core until the thread is ranked as the highest priority most intensive thread at the end of the predetermined time period, at which point the highest priority thread will be moved to the single master core or one of the multiple master cores in a subsequent predetermined time period.

19. The system of claim 11, wherein if an execution thread is assigned to a first CPU core, the thread will continue to use the same first CPU core until frame rendering is complete.

20. The system of claim 11, wherein the battery-powered portable computing device comprises at least one of: a mobile phone, a portable digital assistant (PDA), a portable game console, a VR console, a handheld computer, or a tablet computer.

21. A system for prioritizing and allocating threads in a CPU architecture, the system comprising: A scheduler is configured to receive input to create frames at a predetermined rate on a display device of a battery-powered portable computing device. The scheduler identifies an execution thread responsible for creating the frames and corresponding to a plurality of first processing units in the CPU architecture, the CPU architecture including first processing units and second processing units, each first processing unit having a first processing capacity and each second processing unit having a second processing capacity, the first processing capacity being greater than the second processing capacity. and Within a predetermined time period, the scheduler creates a ranking of the threads based on their workload levels. The scheduler determines the workload level of each first processing unit. The scheduler creates a ranking of the first processing units based on the workload level of the first processing unit. Furthermore, the scheduler assigns each thread to a single first processing unit based on the ranking of the first processing unit and the ranking of the threads.

22. The system of claim 21, wherein the first processing unit and the second processing unit comprise at least one of: a central processing unit, a multi-core processing unit, a digital signal processor, a graphics processing unit, and combinations thereof.

23. The system of claim 21, wherein a first processing unit having a lighter workload level receives a higher priority thread having a higher workload level, and a first processing unit having a heavier workload level receives a lower priority thread having a lighter workload level.

24. The system of claim 21, wherein the CPU architecture comprises a single main core or multiple main CPU cores, and the system further comprises: The single master core or one of the multiple master CPU cores is assigned the highest priority thread with the highest workload.

25. A computer program product for prioritizing and allocating threads in a CPU architecture, the computer program product comprising a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form, the instructions configuring the CPU architecture, when executed by the CPU architecture, to: Receive input to create frames at a predetermined rate on the display device of a battery-powered portable computing device; The identifier is responsible for creating the frame and corresponds to the execution thread of a plurality of first CPU cores in the CPU architecture, the CPU architecture including first CPU cores and second CPU cores, each first CPU core having a first processing capacity and each second CPU core having a second processing capacity, the first processing capacity being greater than the second processing capacity; Within a predetermined time period, a ranking of the threads is created based on their workload levels. Determine the workload level of each primary CPU core; A ranking of the first CPU cores is created based on the workload level of the first CPU cores. as well as Each thread is assigned to a single first CPU core based on the ranking of the first CPU core and the ranking of the threads.

26. The computer program product of claim 25, wherein a first CPU core having a lighter workload level receives a higher priority thread having a higher workload level, and a first CPU core having a heavier workload level receives a lower priority thread having a lighter workload level.

27. The computer program product of claim 26, wherein the CPU architecture comprises a single main CPU core or multiple main CPU cores, and the method further comprises: Assign the highest priority thread with the highest workload to the single main CPU core or one of the multiple main CPU cores.

28. The computer program product of claim 27, wherein the instructions further configure the CPU architecture to: after allocating the highest priority thread with the highest workload to the main CPU core, allocate any remaining threads of ranking among the first CPU cores.

29. The computer program product of claim 27, wherein the predetermined time period includes a multiple of the display device refresh rate.

30. The computer program product of claim 27, wherein the instructions further configure the CPU architecture to: identify the execution thread responsible for creating the frame and corresponding only to at most the number of first CPU cores in the CPU architecture.

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