Double-two logic chiplet

Abstract

Embodiments herein describe various 2x2 configurations of integrated circuits (ICs), where the ICs can communicate with a plurality of neighboring ICs using a chip-to-chip interface. Thus, the 2x2 configuration is an improvement to other levels of chip integration formats, such as 1x2, 1x3, and 1x4, where some of the ICs may communicate directly with only one other IC.

Description

Technical Field

[0001] The examples in this disclosure generally involve arranging integrated circuits in a 2x2 configuration. Background Technology

[0002] Many devices comprise multiple integrated circuits (or dies or chips) interconnected on a substrate or interposer. That is, chip-to-chip connections can be used in devices configured as 1x2, 1x3, 1x4, etc. However, in a 1x2 configuration, two integrated circuits (ICs) communicate using only one side, limiting the number of chip-to-chip signals. With a 1x3 configuration, only the middle chip uses multiple sides to communicate with other chips. Similarly, in a 1x4 configuration, only two of the four ICs can use multiple sides to communicate with other chips. Summary of the Invention

[0003] One embodiment described herein is an apparatus comprising: an interposer having horizontal and vertical seams formed by overlapping exposure areas; and four integrated circuits (ICs) disposed on the interposer in a 2×2 configuration, wherein each of the four ICs is connected to an adjacent IC on both sides via the interposer.

[0004] One embodiment described herein is a method comprising forming an interposer layer having horizontal and vertical seams using overlapping exposure areas, and placing four ICs on the interposer layer in a 2×2 configuration, wherein each of the four ICs is connected to an adjacent IC on both sides via the interposer layer.

[0005] One embodiment described herein is an apparatus comprising four integrated circuits (ICs) arranged in a 2×2 configuration, wherein each of the four ICs is connected to an adjacent IC on at least two sides, and wherein the four ICs have the same design. Attached Figure Description

[0006] To gain a more detailed understanding of the features described above, a more specific description of the brief summary can be obtained by referring to the exemplary embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical exemplary embodiments and should not be considered as limiting the scope of the description.

[0007] Figure 1 An example of a 2x2 configuration of ICs on the intermediary layer is shown.

[0008] Figure 2 This is a flowchart based on an example of an intermediary layer for forming a 2×2 configuration with horizontal and vertical seams to support ICs.

[0009] Figure 3An example of an intermediate layer with horizontal and vertical seams is shown.

[0010] Figure 4 An example of a 2×2 configuration of an IC using a mirrored IC is shown.

[0011] Figure 5 An example of a 2×2 configuration of an IC using a rotating IC is shown.

[0012] Figure 6 This example illustrates how using a rotating IC can improve yield.

[0013] Figure 7 This example illustrates how using a rotating IC can improve yield.

[0014] For ease of understanding, the same reference numerals are used where possible to denote common elements in the accompanying figures. It is conceivable that elements of one example can be advantageously incorporated into other examples. Detailed Implementation

[0015] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by similar reference numerals in all the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended to provide an exhaustive description of the embodiments herein, nor are they intended to limit the scope of the claims. Furthermore, the illustrated examples do not necessarily possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or so explicitly described.

[0016] The implementations described in this paper depict various 2x2 configurations of ICs, where the IC can communicate with multiple adjacent ICs using a chip-to-chip interface. Therefore, the 2x2 configuration is an improvement over other horizontal chip integration formats (such as 1x2, 1x3, and 1x4), where some of these ICs can communicate directly with only one other IC.

[0017] In one implementation, ICs configured in a 2×2 shape are disposed on an interposer layer via horizontal and vertical seams. The seams allow the interposer layer to be larger than the mask size, enabling multiple dies (also constrained by the mask size) to be placed on the same interposer layer. To form the vertical and horizontal seams, the interposer layer is fabricated using four exposure areas (located at or below the mask size and slightly overlapping). The ICs can then be disposed at the four corners of the interposer layer and interconnected using traces within the interposer layer.

[0018] Although the ICs in a 2×2 configuration can be different, in one implementation, two of the ICs are of the same design (e.g., completely identical), while the other two ICs are mirror images of that design. This aligns the IC interfaces, allowing for direct interconnects when the ICs are arranged in a 2×2 configuration.

[0019] In another implementation, the same IC can be used to form a 2×2 configuration, but the IC is rotatable, allowing straight connections to be formed in the interconnect when connecting adjacent chips. Using straight connections simplifies wiring in the interconnect and allows for more chip-to-chip connections compared to an intermediary that supports crossover connections in the intermediary layer.

[0020] In another implementation, a rotatable IC can be used to improve yield. IC manufacturing processes typically introduce defects into ICs. Defective ICs can be used to form devices with smaller capabilities or performance than devices containing only fully functional ICs, rather than simply discarding any defective IC. Using a rotatable IC means that the defective IC can be rotated while being placed in the device, so that the defective area of ​​the IC is placed in an unused portion of the device, thereby improving yield.

[0021] Figure 1 A 2x2 configuration of IC 105 on interposer 100 according to an example is illustrated. In this top view, IC 105 is positioned in corresponding corners of interposer 100. Interposer 100 provides connectivity between adjacent ICs 105. For example, interposer 100 may be a silicon interposer comprising one or more layers, which include traces for forming connection 110. In one embodiment, IC 105 may be mounted on the interposer using, for example, copper pillars, which then electrically couple IC 105 to connection 110, which routes electrical signals from one IC 105 to an adjacent IC 105.

[0022] Unlike a 1x2, 1x3, or 1x4 arrangement where at least some of the ICs communicate with adjacent ICs only on one side, in Figure 1 In the 2x2 configuration shown, each IC 105 communicates with two adjacent ICs using both sides. For example, IC 105C communicates with IC 105D using horizontal connection 110B and with IC 105A using vertical connection 110A. Therefore, the 2x2 configuration effectively doubles the number of chip-to-chip connections that some ICs in a 1x2, 1x3, or 1x4 arrangement can have compared to those that only use one side for communication.

[0023] In this embodiment, the interposer 100 has a surface area exceeding the mask limitations of the manufacturing technology used to manufacture the interposer. The size of the IC 105 is limited by the mask limitations, which define the amount of area that can be exposed and processed using the mask. Currently, for a monolithic die, the maximum size is limited to 33 mm to 26 mm as a mask limitation. Therefore, the width and height of the IC 105 are limited by these mask limitations.

[0024] In order for the interposer 100 to support multiple ICs 105 with dimensions equal to or just below the mask limit, the interposer must have a surface area exceeding the mask limit. This means that the interposer 100 cannot be fabricated using a single exposure process. Instead, the interposer 100 includes vertical seams 120 and horizontal seams 130, where multiple exposure areas slightly overlap. This allows the interposer to still have traces to form connections 110 and sufficient surface area to support a 2×2 configuration of ICs 105. Figure 2 and Figure 3 The manufacturing intermediary layer 100 is discussed in more detail.

[0025] In one implementation, interposer 100 has a total surface area three times the size of the mask limit (e.g., maximum mask field). Furthermore, unlike interposers supporting 1x2, 1x3, and 1x4 configurations that may only have horizontal seams, interposer 100 has both a horizontal seam 130 and a vertical seam 120.

[0026] Figure 2 This is a flowchart of method 200 for manufacturing an interposer layer with horizontal and vertical seams to support a 2×2 configuration of an IC, according to an example. At block 205, method 200 forms an interposer layer with horizontal and vertical seams. In one embodiment, at block 210, these seams are formed by performing four overlapping exposures.

[0027] Figure 3 An intermediate layer 100 is illustrated having a horizontal seam 120 and a vertical seam 130 formed using four exposure regions 305A to 305D. In this example, each exposure region 305 has a size equal to or less than a mask limit (e.g., maximum mask field). Therefore, each of the exposure regions 305 can be fabricated using a separate set of masks.

[0028] As shown in the figure, exposure area 305A overlaps with exposure area 305B on the right and with exposure area 305C at the bottom. Exposure area 305A also slightly overlaps with exposure area 305D at the middle of the interposer layer 100 (all four exposure areas 305 overlap slightly). In addition to overlapping with exposure area 305A, exposure area 305B overlaps with exposure area 305D at the bottom. Furthermore, exposure area 305D overlaps with exposure area 305C on the left.

[0029] By ensuring that the exposure areas 305 slightly overlap, this provides the ability to form vertical seams 120 and horizontal seams 130 in these overlapping portions. Where there is no overlap with the exposure areas 305 (e.g., if the exposure areas are touched but not overlapped), traces are patterned into the interposer layer 100 to form... Figure 1 The chip-to-chip connection shown would be very difficult. This is due to misalignment between the two exposures. In one embodiment, the overlap of the exposures and the minimum width and space of the features (metal lines) on the interposer layer 100 near the seam area are greater than the maximum misalignment. Without overlapping with the exposure areas 305, it will be difficult to pattern the traces extending between the exposure areas 305 to form a connection. Figure 1 The chip-to-chip connection 110 is shown.

[0030] While mask sets are expensive, a mask for interposer 100 currently fabricated using 65nm methods is significantly cheaper than a mask set for ICs currently fabricated using 7nm or 3nm methods. Therefore, forming an interposer beyond the mask set's limitations is relatively inexpensive. Conversely, using 7nm or 3nm technologies might not allow for the formation of ICs exceeding the mask set's limitations using overlapping exposure areas.

[0031] Returning to method 200, at block 215, four ICs are connected in a 2×2 configuration using an interposer. For example, the interposer may include bonding pads through which the ICs are soldered to the interposer. This electrically connects the ICs to chip-to-chip connections extending between adjacent ICs, such as... Figure 1 As shown.

[0032] Figure 4 This illustrates a 2×2 configuration of the IC using a mirrored IC, based on the example. Although not labeled, Figure 4 Intermediate layer 100 may include the vertical and horizontal seams discussed in the above embodiments. That is, intermediate layer 100 may exceed the maximum mask field. However, this is not necessary. For example, intermediate layer 100 may have dimensions within the maximum mask field, but the ICs on intermediate layer 100 may be much smaller than the maximum mask field, so they can be mounted on intermediate layer 100.

[0033] Figure 4 An example is shown where two pairs of ICs are arranged in a 2×2 configuration on an interposer. Each pair of ICs can be identical (e.g., formed using the same mask set). In this embodiment, IC 405A and IC 405B are identical ICs, as are IC 410A and IC 410B. The “F” character indicates the rotation of the ICs relative to each other. In this example, IC 405A is identical to IC 405B, but has been rotated 180 degrees when placed on interposer 100. This aligns the I / O and transceivers on IC 405 with each other. Therefore, the chip-to-chip connection between IC 405A and IC 405B can be straight, which, as described above, can significantly increase the number of chip-to-chip connections that can extend through interposer 100. The same applies to IC 410, where IC 410A is identical to IC 410B, but has been rotated 180 degrees when placed on interposer 100.

[0034] Furthermore, IC 410A and IC 410B are mirror designs of IC 405A and IC 405B. For example, after designing IC 405A and IC 405B, the chip designer can instruct the software design application to mirror the design. This is exemplified by the "F" character on IC 405A and IC 405B, which is a mirror image of the "F" character on IC 410A and IC 410B. By mirroring the ICs, the I / O and transceiver alignment between IC 405A and IC 410A, and between IC 405B and IC 410B, allows horizontal chip-to-chip connections to extend straight through the interposer 100 as vertical chip-to-chip connections (i.e., without crossing). Therefore, Figure 4 The device in the example illustrates two pairs of ICs with essentially the same performance and functions, one pair being a mirror version of the other.

[0035] While using two pairs of mirrored ICs enables direct chip-to-chip interconnection through interposer 100, this also means using two mask sets. That is, ICs 405A and 405B are manufactured using different mask sets than ICs 410A and 410B, which increases cost. However, Figure 5 This avoids the cost of additional mask sets.

[0036] Figure 5 This illustrates a 2×2 configuration of an IC using a rotating IC, based on the example. (Compared to...) Figure 4 similar, Figure 5 An example is shown where four ICs 505A to IC 505D (which may or may not exceed the maximum mask field) are mounted on interposer 100. However, with Figure 4Unlike other ICs, all four IC 505s are identical in design (e.g., formed using the same mask set). Therefore, IC 505s have the same performance and functionality as each other.

[0037] Similarly, the "F" character is used to illustrate the relative rotation of IC 505. In this example, IC 505B is rotated 90 degrees relative to IC 505A, IC 505C is rotated 90 degrees relative to IC 505B (and 180 degrees relative to IC 505A), and IC 505D is rotated 90 degrees relative to IC 505C (and 270 degrees relative to IC 505A).

[0038] Although Figure 5 The 2×2 configuration illustrated uses the same IC design (therefore, only one mask set is needed), but designing IC 505 makes aligning the I / O and transceivers on the sides more difficult when rotated as shown. In other words, having straight, non-crossing chip-to-chip connections through interposer 100 is much more difficult for IC 505. For example, the circuitry in a rotated IC 505 may not be perfectly horizontally and vertically aligned between adjacent ICs 505, complicating the interposer wiring connecting the ICs 505. Furthermore, IC 505 may have to be a perfect square to align when rotated as shown, while... Figure 4 In this case, the die can be rectangular, where two of the sides are longer than the other vertical side, while still aligning its I / O circuitry.

[0039] Figure 6 This example illustrates how using a rotating IC can improve yield. Figure 6 Explained Figure 5 The 2x2 rotating IC configuration can be used in scenarios that improve yield. Despite significant improvements in IC manufacturing, defects can still occur in ICs. This can lead to an IC having to be discarded due to a single defect.

[0040] However, in order to improve yield, manufacturers may sell devices advertised as having lower performance than fully functional devices. As an example, if... Figure 5 The device shown has four fully functional IC 505s (e.g., none of the IC 505s are defective), so the device is sold as a fully functional device. Conversely, Figure 6 An example is device 600, defined as having only 75% (or 75%) of the resources (or performance) of a fully functional device. That is, the product definition of device 600 could indicate that 25% of device 600 includes unused circuitry 605, while the remaining 75% of device 600 consists of used circuitry 610. Specifically, unused circuitry 605 includes at least one defect, while used circuitry 610 is free of defects.

[0041] Figure 6 Four ICs 650 with the same design are also illustrated, but two of them are defective. For example, after manufacturing IC 650, a testing process can be used to identify that IC 650A has a defect 655 and IC 650B has a defect 660, while ICs 650C and 650D are not defective. However, instead of discarding ICs 650A and 650B, they can still be used in device 600 that meets the product definition of device 670 (i.e., 75% of the circuitry is usable).

[0042] As shown in the figure, defects (or multiple defects) exist in half of IC 650A and IC 650B. In reality, the defects may affect very small portions of IC 650A and IC 650B, but to meet the product definition of Device 600, only half of the circuitry in IC 650A and IC 650B must be usable. The slashed fill illustrates half of IC 650A and IC 650B that will not be used due to the defects.

[0043] Because IC 650 is rotatable, IC 650A and IC 650B can be used to form device 670. That is, according to the product definition of device 600, the first 25% of the circuitry should not be used. Therefore, because defect 655 is in the upper half of IC 650A, that half of IC 650A can be deactivated and then placed in the upper right corner of device 670. Conversely, defect 660 is in the lower left of IC 650B, causing the left half of that IC to be deactivated. Therefore, when IC 650B is rotated while placed in device 670, the deactivated half is now located in the upper half of device 670. Because IC 650 is rotatable, they can be rotated and still connected to adjacent ICs. Therefore, IC 650A and IC 650B meet the product definition in which the first 25% of the circuitry is unused, while the remaining 75% of the circuitry is used (which includes the available half of IC 650A and IC 650B, as well as all the circuitry in IC 650C and IC 650D).

[0044] Advantageously, having a rotatable IC 650 means that defects can be located in various positions of the IC and it can still be used in products with reduced performance, such as device 600. In this example, if the defect is in the upper half or lower left corner of IC 650, the IC can still be used in device 670. Therefore, IC 650 can have defects in 75% of its area and can still be used in device 670. However, if the defect is in the lower right corner, the IC cannot be used because it cannot be rotated to meet the product definition of device 600. Those ICs can be discarded or used in devices with different product definitions. In any case, using a rotatable die can improve yield by providing more opportunities to use defective ICs in lower-performance devices compared to devices that do not use rotatable dies in a 2×2 configuration.

[0045] Figure 7 This illustrates how using a rotatable IC can improve yield, based on an example. Figure 6 similar, Figure 7 This illustrates what happens when the IC is defective. Figure 5 The rotating 2x2 IC configuration in the diagram can be used to improve yield. For ease of explanation, in... Figure 6 Discussed in the context of device 600 Figure 7 In the implementation scheme, the device is defined as having only 75% of the resources (or 75% of the performance) of a fully functional device. That is, the product definition of device 600 may indicate that 25% of device 600 includes unused circuitry 605, while the remaining 75% of device 600 is used circuitry 610.

[0046] exist Figure 6 In this configuration, each IC 650 can be rotated and used in a 2×2 configuration. Figure 7 In this context, each IC 705 is identical, but each IC 705 possesses complete logical rotational symmetry, allowing for four orientations: -0 degrees, 90 degrees, 180 degrees, or 270 degrees. That is to say, although... Figure 6 Device 670 in the middle has a product-grade rotational symmetry axis, but Figure 7 The device 750 has both a product-level rotational symmetry axis and a die-level rotational symmetry axis.

[0047] Device 750 may include an interposer layer on which dummy ICs 710A to IC 710D, IOICs 715A to IO ICs 715H, and ICs 705A to IC 705D are disposed. The dummy IC 710 is optional and may be used for mechanical integrity reasons. IOIC 715 may include I / O circuitry and a transceiver coupled to circuitry in IC 705. The interposer layer may provide a direct chip-to-chip connection between IO IC 715 and IC 705.

[0048] In one embodiment, IC 705 includes programmable logic (e.g., a programmable texture) with direct connections that couple the programmable logic (or programmable texture) to a chip-to-chip connection that extends through an interposer and extends to IO IC 715. Although not shown, IO IC 715 may also be connected to an external connection via the interposer, which allows external devices to communicate with IC 705 via IO IC 715.

[0049] The "F" designation on ICs 705A to 705D indicates that their rotation is irrelevant. That is, ICs 705A to 705D are designed so that they can be placed in any orientation at any location on device 750. This is consistent with... Figure 6 The device 670 is different, wherein each position on the device 670 corresponds to a specific orientation of the IC 650.

[0050] To meet the product definition of device 600, the first 25% of the circuitry of device 750 may be unused, giving manufacturers the opportunity to sell devices that include defective IC 705. Figure 7 Four ICs 705E to IC 705H are illustrated, two of which (i.e., IC 705E and IC 705F) have corresponding defects, while the other two ICs (i.e., 705G and 705H) are not defective.

[0051] Figure 7 An example is shown where device 770 is formed from ICs 705E to ICs 705H. In this example, IC 705E is placed at the upper left of device 770. IC 705F is placed at the upper right corner of device 770, and relative to its position... Figure 7 The orientation shown is rotated 180 degrees. However, due to the rotational symmetry of the IC, the orientation of IC 705 does not affect its function. That is, because IC 705E and IC 705F are defective, the defective areas of these ICs are rotated into a portion of the device 770 that includes unused circuitry 775. This can be achieved by rotating IC 705F 180 degrees as shown, or by rotating IC 705F 90 degrees (counterclockwise). In either case, the defective portion of IC 705F is part of the unused circuitry 775 of the device.

[0052] Therefore, with Figure 6 Similarly, half of IC 705E and IC 705F are not used in device 770. By having rotational symmetry, IC 705 can be defective across 100% of its area and still be used in device 770. That is to say, Figure 6IC 650 can be recovered from defects in 75% of its area, but IC 705 can be recovered from defects in any area (e.g., the top left and top right corners, and the bottom left and bottom right corners). Therefore, if IC 705 is defective anywhere, it can still be used to meet the product definition corresponding to device 770. That is, these defective ICs can be used in two upper locations of device 770.

[0053] If IC 705 has multiple defects, it can still be used in device 770. For example, if two defects exist in the same quarter of the die (e.g., multiple defects in the upper left region), it can be used as follows: Figure 7 The diagram shows the use of IC 705. Furthermore, if multiple defects exist in two adjacent regions (e.g., defects in both the top left and top right corners or in both the top left and bottom left corners), the IC can still be rotated so that the defective regions are within the unused circuitry 775. However, if defects exist in all three regions of IC 705 (e.g., the three corners), or in discontinuous regions of IC 705 (e.g., defects in both the top left and bottom right corners), then those ICs cannot be used in device 770. In any case, by using IC 705 with rotational symmetry, the yield of those ICs 705 can be relative to... Figure 6 The equipment in the system has been further improved.

[0054] also, Figure 6 and Figure 7 The redundancy and yield improvement techniques discussed in the article are not limited to using, for example... Figures 1 to 5 The intermediate layer described herein has vertical and horizontal seams. For example, Figure 6 and Figure 7 The devices within the device can include a seamless interposer. Alternatively, ICs within the device can be connected without using any interposer, for example, by using the IC's substrate to achieve a chip-to-chip connection.

[0055] Reference has been made to the embodiments presented in this disclosure. However, the scope of this disclosure is not limited to the specifically described embodiments. Rather, any combination of the described features and elements (whether or not it relates to different embodiments) is contemplated as an implementation and practice of the contemplated embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved through a given embodiment does not limit the scope of this disclosure. Therefore, the foregoing aspects, features, embodiments, and advantages are merely illustrative and should not be considered as elements or limitations of the appended claims unless expressly recited in the claims.

[0056] As those skilled in the art will understand, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Therefore, aspects may take the form of entirely hardware implementations, entirely software implementations (including firmware, resident software, microcode, etc.), or implementations combining software and hardware aspects, all of which may generally be referred to herein as “circuit,” “module,” or “system.” Furthermore, aspects may take the form of computer program products embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0057] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be (e.g., but not limited to) an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (not an exhaustive list) of computer-readable storage media will include: electrical connections having one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium is any tangible medium that can contain or store programs for use by or in connection with an instruction execution system, apparatus, or device.

[0058] Computer-readable signal media may include propagated data signals having computer-readable program code embodied therein (e.g., in baseband or as part of a carrier wave). Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. Computer-readable signal media may be any computer-readable medium that is not a computer-readable storage medium and can convey, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device.

[0059] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, RF, or any suitable combination of the foregoing.

[0060] Computer program code used to perform operations relating to the aspects of this disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Java, Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" programming language or similar programming languages). The program code may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet through an Internet service provider).

[0061] Various aspects of this disclosure are described below with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments presented in this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executable via the processor of the computer or other programmable data processing apparatus, create components for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0062] These computer program instructions may also be stored in a computer-readable medium that can instruct a computer, other programmable data processing apparatus or other device to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing including instructions that implement the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0063] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operational steps to be performed on the computer, other programmable apparatus or other equipment to produce a computer-implemented method, such that the instructions, which execute on the computer or other programmable apparatus, provide a process for implementing the function / action specified in one or more boxes of a flowchart and / or block diagram.

[0064] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible specific implementations of systems, methods, and computer program products according to various examples of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions indicated in the blocks may not occur in the order shown in the figures. For example, depending on the functionality involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0065] While the foregoing is directed to specific examples, other and additional examples may be devised without departing from the basic scope of the invention, the scope of which is defined by the appended claims.

Claims

1. An apparatus, the apparatus comprising: An intermediate layer having horizontal and vertical seams formed by overlapping exposure areas; and Four integrated circuits (ICs) are arranged in a 2x2 configuration on the interposer layer, wherein each of the four ICs is connected to an adjacent IC on both sides via the interposer layer.

2. The apparatus of claim 1, wherein the total surface area of ​​the intermediate layer is greater than the maximum mask field corresponding to the exposure area.

3. The device of claim 2, wherein the total surface area of ​​the intermediate layer is at least three times the size of the maximum mask field.

4. The device of claim 2, wherein the horizontal seam and the vertical seam are formed by slightly overlapping the four exposure areas, wherein each of the four exposure areas is at or below the maximum mask field.

5. The device of claim 1, wherein the first pair of ICs of the four ICs has the same design, and the second pair of ICs of the four ICs has the same design, wherein the design of the first pair of ICs is different from the design of the second pair of ICs, wherein the first IC of the first pair of ICs is oriented 180 degrees relative to the second IC of the first pair of ICs, and the third IC of the second pair of ICs is oriented 180 degrees relative to the fourth IC of the second pair of ICs.

6. The device of claim 1, wherein the four ICs have the same design, wherein the first IC of the four ICs is oriented at a 90-degree angle relative to the second IC of the four ICs, the third IC of the four ICs is oriented at a 180-degree angle relative to the second IC of the four ICs, and the fourth IC of the four ICs is oriented at a 270-degree angle relative to the second IC of the four ICs.

7. A method, the method comprising: An intermediate layer with horizontal and vertical seams is formed by using overlapping exposure areas; as well as Four ICs are disposed on the intermediary layer in a 2×2 configuration, wherein each of the four ICs is connected to an adjacent IC on both sides via the intermediary layer.

8. The method of claim 7, wherein the total surface area of ​​the interposer layer is greater than the maximum mask field for forming the interposer layer using the overlapping exposure areas, wherein the total surface area of ​​the interposer layer is at least three times the size of the maximum mask field, and wherein the horizontal seam and the vertical seam are formed by slightly overlapping four exposure areas, wherein each of the four exposure areas is at or below the maximum mask field.

9. The method of claim 7, wherein the first pair of ICs of the four ICs has the same design, and the second pair of ICs of the four ICs has the same design, wherein the design of the first pair of ICs is a mirror image of the design of the second pair of ICs, and wherein the first IC of the first pair of ICs is oriented 180 degrees relative to the second IC of the first pair of ICs when disposed on the interposer layer, and the third IC of the second pair of ICs is oriented 180 degrees relative to the fourth IC of the second pair of ICs when disposed on the interposer layer.

10. The method of claim 7, wherein the four ICs have the same design, wherein the first IC of the four ICs is oriented at a 90-degree angle relative to the second IC of the four ICs, the third IC of the four ICs is oriented at a 180-degree angle relative to the second IC of the four ICs, and the fourth IC of the four ICs is oriented at a 270-degree angle relative to the second IC of the four ICs.

11. The method of claim 7, wherein the four ICs have the same design, wherein the four ICs have rotational symmetry, such that the four ICs can be arranged on the interposer in any orientation without changing their function or performance.

12. An apparatus, the apparatus comprising: Four integrated circuits (ICs) arranged in a 2×2 configuration, wherein each of the four ICs is connected to an adjacent IC on at least two sides, and The four ICs mentioned above have the same design.

13. The device of claim 12, wherein the first IC of the four ICs is oriented at a 90-degree angle relative to the second IC of the four ICs, the third IC of the four ICs is oriented at a 180-degree angle relative to the second IC of the four ICs, and the fourth IC of the four ICs is oriented at a 270-degree angle relative to the second IC of the four ICs.

14. The device according to claim 6 or 12, wherein both the first IC and the second IC are defective, and the defective portions of the first IC and the second IC are disposed in the unused portion of the device.

15. The device according to claim 1 or 12, wherein the four ICs have rotational symmetry, such that the four ICs can be arranged in any orientation without changing their function or performance.

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