Light detection device and electronic apparatus

Abstract

The charge transfer characteristic is improved. The light detection device includes: a semiconductor layer; and a photoelectric conversion region provided in the semiconductor layer to be separated by the separation region. The photoelectric conversion region includes: a photoelectric conversion portion including a first semiconductor region of a first conductivity type, and provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided between the partition region and the first semiconductor region; a charge holding section of a first conductivity type provided adjacent to the partition region in plan view and overlapping the second semiconductor region on the first surface side of the semiconductor layer; and a transfer transistor provided on the first surface side of the semiconductor layer, and transferring the signal charge photoelectrically converted by the photoelectric conversion portion to the charge holding portion. The separation region includes a fixed charge film having a positive fixed charge. In an interface between the semiconductor layer and the separation region, the fixed charge film is provided closer to the second surface side than at least the charge holding portion.

Description

Technical Field

[0001] This technology (based on the technology disclosed herein) relates to photodetectors and electronic devices, and in particular, to a photodetector having a transmission transistor in a photoelectric conversion region applied to a semiconductor layer, and an electronic device incorporating such a photodetector. Background Technology

[0002] In optical detection devices such as ranging devices and solid-state imaging devices, the photoelectric conversion region of the semiconductor layer is separated by a partition region. Furthermore, the photoelectric conversion region includes: a photoelectric conversion section comprising an n-type semiconductor region; an n-type floating diffusion region (charge holding section) that holds (accumulates) the signal charge photoelectrically converted in the photoelectric conversion section; and a transmission transistor that transmits the signal charge photoelectrically converted in the photoelectric conversion section to the n-type floating diffusion region.

[0003] On the one hand, it is known that trench-type partition regions, which are formed in the semiconductor layer to define the photoelectric conversion region, are partition regions (Patent Document 1). In addition, it is also known that a p-type pinning layer with a conductivity type opposite to that of the n-type semiconductor region of the photoelectric conversion region is provided between the n-type semiconductor region of the photoelectric conversion region and the trench portion of the partition region, in order to suppress dark current caused by damage at the interface between the semiconductor layer and the trench portion of the partition region (Patent Document 2). [List of cited references] [Patent Literature]

[0004] Patent Document 1: JP 2011-222900 A Patent Document 2: JP 2021-103793 A Summary of the Invention [Technical Issues]

[0005] In conventional photodetectors, when the separation distance between the n-type floating diffusion region and the p-type pinning layer decreases along the thickness direction of the semiconductor layer, the n-type floating diffusion region and the p-type pinning layer interfere with each other. Consequently, the capacitance added to the charge transport path used for signal charge (signal charge transport path) increases, which becomes a factor in the degradation of signal charge transport characteristics. Therefore, it is necessary to improve the signal charge transport characteristics.

[0006] In recent years, due to market demand for high-resolution image sensors, image sensors with reduced pixel sizes have been developed. However, as pixel sizes decrease, the separation distance between the n-type floating diffusion region and the p-type pinning layer tends to shrink. From the perspective of pixel size reduction, it is also necessary to improve the signal charge transmission characteristics.

[0007] The purpose of this technology is to improve the signal charge transmission characteristics. [Solutions to Technical Problems]

[0008] (1) A photodetector according to one aspect of the present technology includes: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; A separating region, comprising a trench extending from the first facet side of the semiconductor layer toward the second facet side; and A photoelectric conversion region is disposed in the semiconductor layer and is separated by the partition region. Furthermore, the photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type disposed in the semiconductor layer and spaced apart from the first face; A second semiconductor region of a second conductivity type is disposed between the separating region and the first semiconductor region; A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the separating region in a plan view, and overlapping with the second semiconductor region in a plan view. A transmission transistor is disposed on the first face side of the semiconductor layer, overlaps with the first semiconductor region in a plan view, and transmits the signal charge that has been photoelectrically converted in the photoelectric conversion section to the charge holding section. Furthermore, the separating region includes a fixed-charge film with a positive fixed charge, and The fixed charge film is positioned at the interface between the semiconductor layer and the separating region at least closer to the second face side than the charge holding portion.

[0009] (2) The light detection device according to another aspect of the present technology includes: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; A separating region, comprising a trench extending from the first facet side of the semiconductor layer toward the second facet side; and A photoelectric conversion region is disposed in the semiconductor layer and is separated by the partition region. Furthermore, the photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type disposed in the semiconductor layer and separated from the first face; A second semiconductor region of a second conductivity type is disposed between the separating region and the first semiconductor region; A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the separating region in a plan view, and overlapping with the second semiconductor region in a plan view. A transmission transistor is disposed on the first face side of the semiconductor layer, overlaps with the first semiconductor region in a plan view, and transmits the signal charge that has been photoelectrically converted in the photoelectric conversion section to the charge holding section. Furthermore, the separating region includes an extension that protrudes further toward the photoelectric conversion region than one and the other ends of the separating region located on opposite sides in the thickness direction of the semiconductor layer, and the extension overlaps with the charge holding portion in a plan view. The extension portion is spaced apart from the charge holding portion and is adjacent to the first semiconductor region between the charge holding portion and the second semiconductor region.

[0010] (3) The light detection device according to another aspect of the present technology includes: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; A separating region, comprising a trench extending from the first facet side of the semiconductor layer toward the second facet side; and A photoelectric conversion region is disposed in the semiconductor layer and is separated by the partition region. Furthermore, the separating region includes: a first longitudinal portion disposed on the first facet side of the semiconductor layer; and The second vertical portion extends from the first vertical portion toward the second face side of the semiconductor layer and is narrower than the width of the first vertical portion. Furthermore, the photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type disposed in the semiconductor layer and spaced apart from the first face; A second semiconductor region of a second conductivity type is disposed between the second longitudinal portion of the partition region and the first semiconductor region; A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the separating region in a plan view, and overlapping with the second semiconductor region in a plan view; and A transmission transistor is disposed on the first face side of the semiconductor layer, overlaps with the first semiconductor region in a plan view, and transmits the signal charge that has been photoelectrically converted in the photoelectric conversion section to the charge holding section. Furthermore, the first longitudinal portion has an inclined portion on the charge holding portion side, and the inclined portion forms an acute angle with the first face of the semiconductor layer.

[0011] (4) An electronic device according to another aspect of the present technology includes: Optical detection device; An optical lens that images light from the subject onto the imaging surface of the detection device; and A signal processing circuit that performs signal processing on the signal output from the optical detection device. Attached Figure Description

[0012] [ Figure 1 ] Figure 1 This is a chip layout diagram illustrating a construction example of a solid-state camera device according to a first embodiment of the present technology. [ Figure 2 ] Figure 2 This is a block diagram illustrating a construction example of a solid-state imaging device according to a first embodiment of the present technology. [ Figure 3 ] Figure 3 This is an equivalent circuit diagram illustrating an example of the construction of a pixel and pixel circuit according to a first embodiment of the present technology. [ Figure 4A ] Figure 4A It is shown schematically. Figure 1 A plan view of an example of the construction of pixel blocks included in the pixel array shown. [ Figure 4B ] Figure 4B By magnification Figure 4A A magnified planar view of the central region of the pixel block shown. [ Figure 5A ] Figure 5A This is a schematic longitudinal sectional view of the longitudinal section structure taken along line a4-a4 in Figure 4. [ Figure 5B ] Figure 5B By magnification Figure 5A A portion of the longitudinal sectional view obtained. [ Figure 6A ] Figure 6A This is a schematic longitudinal sectional view illustrating the longitudinal section structure of the reference example. [ Figure 6B ] Figure 6B This demonstrates that when the separation distance between the n-type floating diffusion region and the p-type semiconductor region is sufficient, Figure 6A A diagram illustrating an example of the potential in a charge transport path, as shown in the reference example. [ Figure 6C ] Figure 6CThis illustrates the case where the separation distance between the n-type floating diffusion region and the p-type semiconductor region is small. Figure 6A A diagram illustrating an example of the potential in a charge transport path for a conventional reference example. [ Figure 7A ] Figure 7A This is a plan view schematically illustrating the steps of a method for manufacturing a solid-state imaging device according to a first embodiment of the present technology. [ Figure 7B ] Figure 7B It is an illustrative representation of the path along Figure 7A The longitudinal section view of the longitudinal section structure taken by line a7-a7. [ Figure 8A ] Figure 8A It is shown schematically. Figure 7A A plan view of the steps following the steps shown. [ Figure 8B ] Figure 8B It is an illustrative representation of the path along Figure 8A The longitudinal section view of the longitudinal section structure cut by line a8-a8. [ Figure 9A ] Figure 9A It is shown schematically. Figure 8A A plan view of the steps following the steps shown. [ Figure 9B ] Figure 9B It is an illustrative representation of the path along Figure 9A The longitudinal section view of the longitudinal section structure cut by line a9-a9. [ Figure 10 ] Figure 10 It is shown schematically. Figure 9A A longitudinal sectional view of the steps following the steps shown. [ Figure 11 ] Figure 11 It is shown schematically. Figure 10 A longitudinal sectional view of the steps following the steps shown. [ Figure 12 ] Figure 12 It is shown schematically. Figure 11 A longitudinal sectional view of the steps following the steps shown. [ Figure 13A ] Figure 13A It is shown schematically. Figure 12 A plan view of the steps following the steps shown. [ Figure 13B ] Figure 13B It is an illustrative representation of the path along Figure 13A The longitudinal section view of the longitudinal section structure taken by line a13-a13. [ Figure 14A ] Figure 14AIt is shown schematically. Figure 13A A plan view of the steps following the steps shown. [ Figure 14B ] Figure 14B It is an illustrative representation of the path along Figure 14A The longitudinal section view of the longitudinal section structure cut by line a14-a14. [ Figure 15 ] Figure 15 It is shown schematically. Figure 14A A longitudinal sectional view of the steps following the steps shown. [ Figure 16 ] Figure 16 It is shown schematically. Figure 16 A longitudinal sectional view of the steps following the steps shown. [ Figure 17 ] Figure 17 It is shown schematically. Figure 14A A longitudinal sectional view of the steps following the steps shown. [ Figure 18A ] Figure 18A This is a schematic plan view of a variation 1-1 of the first embodiment of the present technology. [ Figure 18B ] Figure 18B It is an illustrative representation of the path along Figure 18A The longitudinal section view of the longitudinal section structure cut by line a18-a18. [ Figure 19 ] Figure 19 The diagram illustrates a longitudinal sectional view of a variation 1-2 of the first embodiment of the present technology. [ Figure 20 ] Figure 20 The diagram illustrates plan views of variations 1-3 of the first embodiment of the present technology. [ Figure 21 ] Figure 21 This is a plan view schematically illustrating an example of the construction of pixel blocks included in the pixel array section of a solid-state imaging device according to a second embodiment of the present technology. [ Figure 22 ] Figure 22 This is a plan view schematically illustrating an example of the construction of pixel blocks included in the pixel array section of a solid-state imaging device according to a third embodiment of the present technology. [ Figure 23 ] Figure 23 This is a plan view schematically illustrating an example of the construction of pixel blocks included in the pixel array section of a solid-state imaging device according to a fourth embodiment of the present technology. [ Figure 24 ] Figure 24 It is an illustrative representation of the path along Figure 23The longitudinal section view of the longitudinal section structure taken by line a23-a23. [ Figure 25 ] Figure 25 It is magnification Figure 24 A longitudinal sectional view obtained from a portion of the data. [ Figure 26 ] Figure 26 It is shown schematically. Figure 24 A plan view of the planar pattern of the extended portion of the partitioned area shown. [ Figure 27 ] Figure 27 It is shown schematically. Figure 24 A plan view of the planar pattern of the second longitudinal section of the partitioned area. [ Figure 28 ] Figure 28 This is a plan view schematically illustrating the steps of a method for manufacturing a solid-state imaging device according to a fourth embodiment of the present technology. [ Figure 29 ] Figure 29 It is shown schematically. Figure 28 A longitudinal sectional view of the steps following the steps shown. [ Figure 30 ] Figure 30 It is shown schematically. Figure 29 A longitudinal sectional view of the steps following the steps shown. [ Figure 31 ] Figure 31 It is shown schematically. Figure 30 A longitudinal sectional view of the steps following the steps shown. [ Figure 32 ] Figure 32 It is shown schematically. Figure 31 A longitudinal sectional view of the steps following the steps shown. [ Figure 33 ] Figure 33 It is shown schematically. Figure 32 A longitudinal sectional view of the steps following the steps shown. [ Figure 34 ] Figure 34 It is shown schematically. Figure 33 A longitudinal sectional view of the steps following the steps shown. [ Figure 35 ] Figure 35 It is shown schematically. Figure 34 A longitudinal sectional view of the steps following the steps shown. [ Figure 36 ] Figure 36 It is shown schematically. Figure 35 A longitudinal sectional view of the steps following the steps shown. [ Figure 37 ] Figure 37It is shown schematically. Figure 36 A longitudinal sectional view of the steps following the steps shown. [ Figure 38 ] Figure 38 The diagram illustrates a plan view of a variation 4-1 of the fourth embodiment of the present technology. [ Figure 39 ] Figure 39 This is a schematic plan view of a variation 4-2 of the fourth embodiment of the present technology. [ Figure 40 ] Figure 40 This is a plan view schematically illustrating an example of the construction of pixel blocks included in the pixel array section of a solid-state imaging device according to a fifth embodiment of the present technology. [ Figure 41 ] Figure 41 It is an illustrative representation of the path along Figure 40 The longitudinal section view of the longitudinal section structure taken by line a40-a40. [ Figure 42 ] Figure 42 By magnification Figure 41 A portion of the longitudinal sectional view obtained. [ Figure 43 ] Figure 43 This is a longitudinal sectional view schematically illustrating the steps of a method for manufacturing a solid-state imaging device according to a fifth embodiment of the present technology. [ Figure 44 ] Figure 44 This is a schematic plan view of a variation 5-1 of the fifth embodiment of the present technology. [ Figure 45 ] Figure 45 This is a schematic plan view of a variation 5-2 of the fifth embodiment of the present technology. [ Figure 46 ] Figure 46 This is a plan view schematically illustrating an example of the construction of pixel blocks included in the pixel array section of a solid-state imaging device according to a sixth embodiment of the present technology. [ Figure 47 ] Figure 47 It is an illustrative representation of the path along Figure 46 The longitudinal section view of the longitudinal section structure taken by line a46-a46. [ Figure 48 ] Figure 48 By magnification Figure 47 A portion of the longitudinal sectional view obtained. [ Figure 49 ] Figure 49 This is a longitudinal sectional view schematically illustrating the steps of a method for manufacturing a solid-state imaging device according to a sixth embodiment of the present technology. [ Figure 50 ] Figure 50 It is shown schematically. Figure 49 A longitudinal sectional view of the steps following the steps shown. [ Figure 51 ] Figure 51 It is shown schematically. Figure 50 A longitudinal sectional view of the steps following the steps shown. [ Figure 52 ] Figure 52 It is shown schematically. Figure 51 A longitudinal sectional view of the steps following the steps shown. [ Figure 53 ] Figure 53 It is shown schematically. Figure 52 A longitudinal sectional view of the steps following the steps shown. [ Figure 54 ] Figure 54 It is shown schematically. Figure 53 A longitudinal sectional view of the steps following the steps shown. [ Figure 55 ] Figure 55 It is shown schematically. Figure 54 A longitudinal sectional view of the steps following the steps shown. [ Figure 56 ] Figure 56 It is shown schematically. Figure 55 A longitudinal sectional view of the steps following the steps shown. [ Figure 57 ] Figure 57 It is shown schematically. Figure 56 A longitudinal sectional view of the steps following the steps shown. [ Figure 58 ] Figure 58 It is shown schematically. Figure 57 A longitudinal sectional view of the steps following the steps shown. [ Figure 59 ] Figure 59 This is a longitudinal sectional view schematically illustrating the steps of a manufacturing method of a sixth embodiment of the present technology, variant 6-1. [ Figure 60 ] Figure 60 It is shown schematically. Figure 60 A longitudinal sectional view of the steps following the steps shown. [ Figure 61 ] Figure 61 This is a diagram illustrating a construction example of an electronic device according to a seventh embodiment of the present technology. Detailed Implementation

[0013] The implementation scheme of this technology will be described in detail below with reference to the accompanying drawings. Note that in the description of the referenced figures, identical or similar parts will be indicated by identical or similar reference numerals. However, it should be noted that the figures are schematic, and the relationships between thickness and planar dimensions, the thickness ratios of each layer, etc., may differ from actual conditions. Therefore, specific thicknesses and dimensions should be determined based on the following description.

[0014] Furthermore, it goes without saying that the accompanying drawings include parts whose dimensional relationships and scales differ from each other. Moreover, the effects described in this specification are merely illustrative and not intended to be limiting. Other effects may also be provided.

[0015] Furthermore, the following embodiments are intended to illustrate the apparatus and methods for embodying the technical concept of this technology, and are not intended to limit the construction to the construction described below. In other words, the technical concept of this technology can be modified in various ways within the scope of the claims.

[0016] Furthermore, the definitions of directions such as up and down in the following description are merely for ease of explanation and are not intended to limit the technical ideas of this technology. For example, needless to say, when an object is rotated 90 degrees and observed, up and down are converted to left and right, and when an object is rotated 180 degrees and observed, up and down are reversed.

[0017] Furthermore, in the following embodiments, "first conductivity type" refers to either p-type or n-type, and "second conductivity type" refers to either p-type or n-type that is different from "first conductivity type". Then, in the following embodiments, an example will be given where "first conductivity type" is n-type and "second conductivity type" is p-type.

[0018] Furthermore, in the following embodiments, in three directions that are orthogonal to each other in space, the first and second directions, which are orthogonal to each other in the same plane, are defined as the X and Y directions, respectively, and the third direction, which is orthogonal to both the first and second directions, is defined as the Z direction. Then, in the following embodiments, the thickness direction of the semiconductor layer 21, which will be described later, is defined as the Z direction. Furthermore, in the following embodiments, the “thickness” of semiconductor layer 21 refers to the separation distance between the first face S1 and the second face S2 located on opposite sides in the Z direction, and the thickness direction of semiconductor layer 21 refers to the direction representing the thickness of semiconductor layer 21. Furthermore, in the following embodiments, a "plan view" refers to a view of the semiconductor layer 21 viewed from the Z direction (one direction). A cross-sectional view refers to a cross-section along the Z direction (one direction) as viewed from a direction orthogonal to the cross-section (Z direction).

[0019] [First Implementation Plan] In this first embodiment, an example of the application of this technology to a solid-state imaging device as a back-illuminated CMOS (complementary metal-oxide-semiconductor) image sensor used as a light detection device will be described.

[0020] Furthermore, in this first embodiment, a fixed-charge film having a positive fixed charge will be described.

[0021] <<Overall Structure of Solid State Camera Device>> First, the overall structure of the solid-state imaging device 1A will be explained.

[0022] like Figure 1 As shown, the solid-state imaging device 1A according to the first embodiment of this technology is mainly composed of a semiconductor chip 2, which has a rectangular two-dimensional planar shape when viewed from a plane. In other words, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as a separate imaging device 1A. Figure 61 As shown, the solid-state imaging device 1A (101) receives image light (incident light 106) from the subject through an optical lens 102 (not shown), converts the amount of light of the incident light 106 that forms an image on the imaging surface into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal.

[0023] like Figure 1 As shown, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted includes a rectangular pixel array portion 2A disposed in a central region and a peripheral portion 2B disposed outside the pixel array portion 2A to surround the pixel array portion 2A in a two-dimensional plane including mutually orthogonal X and Y directions. The semiconductor chip 2 is formed during the manufacturing process by dividing a semiconductor wafer, including the semiconductor layer 21 which will be described later, into individual wafers corresponding to the respective chip formation regions. Therefore, even in the wafer state before the semiconductor wafer is divided, the structure of the solid-state imaging device 1A described below is generally the same. Therefore, this technology is applicable to both the semiconductor chip state and the semiconductor wafer state.

[0024] Pixel array section 2A is a receiver, for example, by Figure 61 The optical lens (optical system) 102 shown is a light-receiving surface that focuses light. Then, in the pixel array section 2A, a plurality of pixels 3 (sensor pixels) are arranged in a matrix pattern in a two-dimensional plane including the X and Y directions. In other words, the pixels 3 are repeatedly arranged in the two-dimensional plane in each of the X and Y directions that are orthogonal to each other.

[0025] like Figure 1As shown, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. For example, each of the plurality of bonding pads 14 is arranged along each of the four sides of the two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 serves as an input / output terminal for an external device that electrically connects the semiconductor chip 2.

[0026] <Logic Circuits> Semiconductor chip 2 includes Figure 2 The logic circuit 13 shown is as follows. Figure 2 As shown, logic circuit 13 includes vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, output circuit 7, and control circuit 8. For example, logic circuit 13 is constructed as a field-effect transistor using a CMOS (complementary MOS) circuit with n-channel MOSFETs and p-channel MOSFETs.

[0027] Figure 2 The direct drive circuit 4 shown is, for example, composed of a shift register. The vertical drive circuit 4 sequentially selects the desired pixel drive line 10 and supplies pulses for driving the pixel 3 to the selected pixel drive line 10, thereby driving each pixel 3 row by row. In other words, the vertical drive circuit 4 selectively scans each pixel 3 of the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixel 3, based on the signal charge generated by the photoelectric conversion section of each pixel 3 according to the amount of received light, to the column signal processing circuit 5 through the vertical signal line 11.

[0028] The column signal processing circuit 5 is configured for each column of the pixel 3, and performs signal processing such as noise cancellation on the signal output from the pixel 3 in a row, column by column. For example, the column signal processing circuit 5 performs signal processing such as CDS (correlated double sampling) and AD (analog-to-digital) conversion to eliminate the fixed-pattern noise inherent in the pixel.

[0029] Figure 2 The horizontal drive circuit 6 shown is, for example, composed of a shift register. The horizontal drive circuit 6 sequentially selects each column signal processing circuit 5 by outputting horizontal scan pulses to the column signal processing circuit 5, and causes each column signal processor 5 to output the processed pixel signal to the horizontal signal line 12.

[0030] Figure 2 The output circuit 7 shown performs signal processing on the pixel signals sequentially supplied from each column signal processing circuit 5 via the horizontal signal line 12, and outputs the pixel signals. Examples of signal processing may include buffering, black level adjustment, column offset correction, and various digital signal processing techniques.

[0031] Figure 2The control circuit 8 shown generates clock and control signals based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, which serve as references for the operation of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0032] <pixel blocks> Semiconductor chip 2 includes Figure 3 The pixel block 15 and pixel circuit (reading circuit) 16 are shown. like Figure 3 and Figure 4A As shown, pixel block 15 includes a plurality of pixels 3. Pixel block 15 of this first embodiment is not limited thereto. For example, pixel block 15 may include four pixels 3 (3a, 3b, 3c, and 3d) in a 2×2 layout arranged as a unit, with two pixels adjacent to each other in the X and Y directions respectively when viewed in a planar view. Figure 3 and Figure 4A The image shows a main pixel block 15. However, pixel block 15 is repeatedly arranged in both the X and Y directions, thus forming... Figure 1 The pixel array section 2A shown.

[0033] like Figure 3 As shown, each of the four pixels 3a, 3b, 3c, and 3d included in a pixel block 15 has common components. Specifically, each of the four pixels 3a, 3b, 3c, and 3d included in a pixel block 15 includes a photoelectric conversion unit 25; a floating diffusion region FD, which serves as a charge holding unit for retaining (accumulating) the signal charge photoelectrically converted in the photoelectric conversion unit 25; and a transmission transistor TR, which transmits the signal charge photoelectrically converted in the photoelectric conversion unit 25 to the floating diffusion region FD. Furthermore, each of the four pixels 3a, 3b, 3c, and 3d in a pixel block 15 also includes... Figure 5A The photoelectric conversion region (photoelectric conversion unit) 22 of the semiconductor layer 21 shown. Furthermore, as... Figure 5A As shown, the photoelectric conversion unit 25, the floating diffusion region FD, and the transmission transistor TR are each disposed in the photoelectric conversion region 22.

[0034] (Photoelectric conversion unit) Figure 3 The photoelectric conversion unit 25 shown is, for example, composed of a pn photodiode (PD), and generates signal charge according to the amount of light received. Furthermore, the photoelectric conversion unit 25 temporarily retains (accumulates) the generated signal charge. The cathode side of the photoelectric conversion unit 25 is electrically connected to the source region of the transmission transistor TR, and its anode side is electrically connected to the reference potential line (e.g., ground).

[0035] (Transmission transistor) Figure 3 The transmission transistor TR shown transmits the signal charge converted by photoelectric conversion in the photoelectric conversion unit 25 to the floating diffusion region FD. The source region of the transmission transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and its drain region is electrically connected to the floating diffusion region FD. Furthermore, the gate electrode of the transmission transistor TR is electrically connected to... Figure 2 The transmission transistor driving line in the pixel driving line 10 shown.

[0036] (Floating diffusion area) Figure 3 The floating diffusion region FD shown in Figure A temporarily accumulates and retains the signal charge transmitted from the photoelectric conversion unit 25 via the transmission transistor TR.

[0037] <Pixel Circuit> like Figure 3 As shown, the input side of the pixel circuit 16 is electrically connected to the floating diffusion region FD. In this first embodiment, the pixel circuit 16 is provided for each pixel block 15, and is shared by four pixels 3 (3a, 3b, 3c and 3d) included in a pixel block 15.

[0038] Here, in this first embodiment, a circuit configuration in which one pixel circuit 16 is assigned to a pixel block 15 comprising four pixels 3 as a unit is used as an example. However, this first embodiment is not limiting. For example, a circuit configuration in which one pixel circuit 16 is assigned to a pixel block 15 comprising two or more pixels 3 as a unit can be used, or a circuit configuration in which one pixel circuit 16 is assigned to multiple pixel blocks 15 comprising multiple pixels 3 as a unit can be used. Furthermore, a circuit configuration in which one pixel circuit 16 is assigned to one pixel 3 can be used. Figure 3 The input stage of the pixel circuit 16 shown is electrically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) included in a pixel block 15. The pixel circuit 16 then reads the signal charge held in the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) and outputs a pixel signal based on the read signal charge. In other words, the pixel circuit 16 converts the signal charge converted by photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charge and outputs the pixel signal.

[0039] like Figure 3As shown, the pixel circuit 16 includes, but is not limited to, for example, an amplifying transistor AMP, a selecting transistor SEL, a reset transistor RST, and a switching transistor FDG as pixel transistors Q. These pixel transistors Q (AMP, SEL, RST, and FDG) and the aforementioned transmission transistor TR are constructed as insulated-gate field-effect transistors, for example, using MOSFETs (metal-oxide-semiconductor field-effect transistors) with a gate insulating film made of silicon oxide (SiO2). Alternatively, these pixel transistors may also be MISFETs (metal-insulator-semiconductor FETs) with a gate insulating film made of silicon nitride (Si3N4) or a laminate of silicon nitride and silicon oxide.

[0040] In the pixel circuit 16, among the pixel transistors Q (AMP, SEL, RST, and FDG), the select transistor SEL, the reset transistor RST, and the switch transistor FDG are mainly used as switching elements. Furthermore, the remaining amplifying transistor AMP is mainly used as an amplifying element.

[0041] Figure 3 The source region of the amplifying transistor AMP shown is electrically connected to the drain region of the select transistor SEL, and its drain region is electrically connected to the power line Vdd and the drain region of the reset transistor RST. Furthermore, the gate electrode of the amplifying transistor AMP is electrically connected to the respective floating diffusion regions FD of the four pixels 3 (3a, 3b, 3c, and 3d) and the source region of the reset transistor RST.

[0042] Figure 3 The source region of the selected transistor SEL is electrically connected to the vertical signal line 11 (VSL), and its drain region is electrically connected to the source region of the amplifying transistor AMP. Furthermore, the gate electrode of the selected transistor SEL is electrically connected to... Figure 2 The pixel driving line 10 shown is the selection transistor driving line.

[0043] Figure 3 The source region of the reset transistor RST shown is electrically connected to the drain of the switching transistor FDG, and its drain region is electrically connected to the power supply line Vdd and the drain region of the amplifying transistor AMP. Furthermore, the gate electrode of the reset transistor RST is electrically connected to... Figure 2 The reset transistor drive line in the pixel drive line 10 shown. Figure 3 The drain region of the switching transistor FDG shown is electrically connected to the source region of the reset transistor RST, and its source region is electrically connected to the gate electrode of the amplifying transistor AMP and the respective floating diffusion regions FD of the four pixels 3 (3a, 3b, 3c, and 3d). Furthermore, the gate electrode of the switching transistor FDG is electrically connected to... Figure 2 The switching transistor driving line in the pixel driving line 10 shown.

[0044] Note that the selection transistor SEL and the switching transistor FDG can be omitted as needed. When the select transistor SEL is omitted, the source region of the amplifier transistor AMP is electrically connected to the vertical signal line 11 (VSL). Furthermore, when the switch transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode of the amplifier transistor AMP and the floating diffusion region FD.

[0045] When the transfer transistor TR is turned on Figure 3 The transmission transistor TR shown transmits the signal charge generated by the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0046] When the reset transistor RST is turned on Figure 3 The reset transistor RST shown resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd. The select transistor SEL controls the output timing of the pixel signal from the pixel circuit 16.

[0047] Figure 3 The amplifying transistor AMP shown generates a signal as a pixel signal having a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplifying transistor AMP forms a source follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated by the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifying transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to that potential via the vertical signal line 11 (VSL) nematic signal processing circuit 5.

[0048] Figure 3 The switching transistor FDG shown controls the charge held in the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplified transistor AMP.

[0049] During operation of the solid-state imaging device 1A according to the first embodiment, the signal charge generated by the photoelectric conversion unit 25 of pixel 3 is held (accumulated) in the floating diffusion region FD via the transfer transistor TR of pixel 3. Then, pixel circuit 16 reads the signal charge held in the floating diffusion region FD and applies it to the gate electrode of amplification transistor AMP of pixel circuit 16. A horizontal line selection control signal is supplied from the vertical shift register to the gate electrode of selection transistor SEL of pixel circuit 16. Then, by changing the selection control signal to a high (H) level, selection transistor SEL becomes on, and current corresponding to the potential of the floating diffusion region FD amplified by amplification transistor AMP flows to vertical signal line 11. Furthermore, by changing the reset control signal applied to the gate electrode of reset transistor RST of pixel circuit 16 to a high (H) level, reset transistor RST becomes on, thereby resetting the signal charge accumulated in the floating diffusion region FD.

[0050] Figure 3 The photoelectric conversion unit 25, the transmission transistor TR, and the floating diffusion region FD shown are each mounted in the semiconductor layer 21, which will be described later (see reference). Figure 5A Furthermore, although not limited to this, Figure 3 The pixel transistors Q (AMP, SEL, RST, and FDG) included in the pixel circuit 16 shown are also mounted in the semiconductor layer 21, for example.

[0051] <<Detailed Structure of Solid State Camera Devices>> Next, we will use Figure 4A , Figure 4B , Figure 5A and Figure 5B The specific structure of semiconductor chip 2 (solid-state imaging device 1A) is explained.

[0052] exist Figure 4A , Figure 4B , Figure 5A and Figure 5B To improve clarity in the accompanying diagrams, the multiple wiring layers, which will be described below, have been omitted. Furthermore, Figure 1 The light incident surface side of semiconductor chip 2 is shown, while Figure 4A This is a plan view of semiconductor chip 2 when viewed from the opposite side of the light incident surface (from the multilayer wiring layer side).

[0053] like Figure 5AAs shown, the semiconductor chip 2 includes: a semiconductor layer 21 having a first facet S1 and a second facet S2 located on opposite sides in the thickness direction (Z direction); a separation region 31 disposed in the semiconductor layer 21 and extending from the first facet S1 side of the semiconductor layer 21 toward the second facet S2 side; and a photoelectric conversion region 22 separated by the separation region 31.

[0054] Furthermore, although omitted in the figure, the semiconductor chip 2 also includes a multilayer wiring layer disposed on the first facet S1 side of the semiconductor layer 21. In addition, the semiconductor chip 2 also includes a planarization film 51, a filter 53, and a microlens (on-chip lens) 54 disposed sequentially from the second facet S2 side of the semiconductor layer 21.

[0055] Here, the first surface S1 of the semiconductor layer 21 can also be referred to as the main surface or the element forming surface, and the second surface S2 can also be referred to as the back surface. Furthermore, the solid-state imaging device 1A according to this first embodiment uses a photoelectric conversion unit 25 (photodiode PD) disposed in the photoelectric conversion region 22 of the semiconductor layer 21 to perform photoelectric conversion on incident light from the second surface S2 side of the semiconductor layer 21. Therefore, in this first embodiment, the second surface S2 of the semiconductor layer 21 can also be referred to as the light incident surface.

[0056] like Figure 4A As shown, in the planar diagram, the four pixels 3 (3a, 3b, 3c, and 3d) included in a pixel block 15 are arranged in pairs along the X and Y directions, thus forming a 2×2 layout. In other words, in Figure 1 In the pixel array section 2A shown, pixel blocks 15, each having four pixels 3 (3a, 3b, 3c and 3d) as a unit, are repeatedly arranged in the X and Y directions.

[0057] <Planarization films, filters, and microlenses> Figure 5A The planarization film 51 shown is disposed on the second face S2 side of the semiconductor layer 21 to cover the second face S2 side of the semiconductor layer 21, thereby planarizing the second face S2 side of the semiconductor layer 21. Figure 5A The filter 53 and microlens 54 shown are provided for each pixel 3. The filter 53 separates the color of light incident from the light incident surface side (second surface S2 side) of the semiconductor chip 2. The microlens 54 focuses the illumination light and makes the focused light effectively incident on the pixel 3.

[0058] <Semiconductor layer> like Figure 5AAs shown, the semiconductor layer 21 includes a separating region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21 and a photoelectric conversion region 22 separated by the separating region 31. The photoelectric conversion region 22 is provided for each pixel 3. A Si substrate, a SiGe substrate, an InGaAs substrate, etc., can be used as the semiconductor layer 21. In this first embodiment, although not limited to this, a p-type semiconductor substrate made of, for example, monocrystalline silicon is also used as the semiconductor layer 21.

[0059] <Separating Areas> (Flat pattern) like Figure 4A As shown in the plan view, the dividing region 31 includes a first planar portion 31x extending in the X direction and a second planar portion 31y extending in the Y direction. Furthermore, the dividing region 31 also includes an intersection (intersection point) where the first planar portion 31x and the second planar portion 31y intersect each other on the same plane. In this first embodiment, the first planar portion 31x and the second planar portion 31y are, for example, orthogonal.

[0060] The first planar portion 31x is repeatedly arranged in the Y direction at predetermined intervals. Furthermore, the second planar portion 31y is repeatedly arranged in the X direction at predetermined intervals. In other words, the dividing region 31 has a grid-like planar pattern in the plan view.

[0061] like Figure 4A As shown in the plan view, the partition region 31 corresponding to a photoelectric conversion region 22 has a rectangular annular planar pattern (ring planar pattern) and surrounds the periphery of a photoelectric conversion region 22. Furthermore, the partition region 31 corresponding to a pixel block 15 is a composite planar pattern, wherein a cross-shaped planar pattern of a first planar portion 31x and a second planar portion 31y arranged orthogonally to each other is included within a square annular planar pattern.

[0062] like Figure 4A As shown, in the partition region 31 corresponding to a pixel block 15, the intersection (intersection point) 31xy between the first planar portion 31x and the second planar portion 31y is located in the central region of the pixel block 15. Furthermore, surrounding this intersection 31xy, the photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c and 3d) are arranged in a matrix pattern.

[0063] (Cross-sectional shape) like Figure 5AAs shown, the separating region 31 extends in the thickness direction (Z direction) of the semiconductor layer 21, and the electrical and optical separations are two photoelectric conversion regions 22 adjacent to each other in the plan view. Furthermore, as will be described in detail later, the separating region 31 is, for example, a trench type, wherein a first trench portion and a second trench portion (32a and 32b) are formed in the semiconductor layer 21 to divide and separate the photoelectric conversion regions 22.

[0064] The separating region 31 includes, in the thickness direction (Z direction) of the semiconductor layer 21, a first vertical portion 31z1 disposed on the first surface S1 side of the semiconductor layer 20; and a second vertical portion 31z2 extending from the first vertical portion 31z1 toward the second surface S2 side of the semiconductor layer 21, and having a width narrower than that of the first vertical portion 31z1. Furthermore, the separating region 31 includes a stepped portion 31zs (see reference) resulting from the width difference between the first vertical portion 31z1 and the second vertical portion 31z2. Figure 5B For example, the second vertical portion 31z2 of the first embodiment reaches the second face portion S2 of the semiconductor layer 21, but is not limited thereto.

[0065] The first longitudinal portion 31z1 and the second dividing portion 31z2 are respectively formed in the first planar portion 31x and the second planar portion 31y. In other words, the first planar portion 31x and the second planar portion 31y of the dividing region 31 each include the first longitudinal portion 31z1 and the second longitudinal portion 31z2.

[0066] (Construction of the first longitudinal section) like Figure 5A As shown, the first longitudinal portion 31z1 includes: a first trench portion 32a, which is recessed from the first surface portion S1 of the semiconductor layer 21 toward the second surface portion S2; a separating insulating film 36, which is disposed in the first trench portion 32a; and a fixed charge film 37, which is disposed in the first trench portion 32a and has a positive fixed charge.

[0067] like Figure 4A As shown, the fixed-charge film 37 with a positive fixed charge is mainly selectively disposed at the intersection 31xy where the first planar portion 31x and the second planar portion 31y intersect each other in the partition region 31 located in the central region of the pixel block 15. On the other hand, the partition insulating film 36 is mainly disposed on the entire first longitudinal portion 31z1 of the partition region 31, except for the intersection 31xy in the central region of the pixel block 15. For example, a silicon oxide film can be used as the partition insulating film 36.

[0068] (Construction of the second longitudinal section) like Figure 5AAs shown, the second longitudinal portion 31z2 includes a second trench portion 32b, which extends from the first trench portion 32a toward the second surface area S2 side of the semiconductor layer 21 and has a width narrower than that of the first trench portion 32a; a separating insulating film 34, which is disposed along the inner wall of the second trench portion 32b; and a conductive material 35, which is disposed in the second trench portion 32b through the separating insulating film 34. For example, a silicon oxide film can be used as the separating insulating film 34. For example, a doped polycrystalline silicon film incorporating impurities to reduce resistance can be used as the conductive material 35.

[0069] (Groove section) like Figure 5A As shown, the first trench portion and the second trench portions 32a and 32b are included in a stepped trench portion 32 extending along the thickness direction (Z direction) of the semiconductor layer 21. Furthermore, this trench portion 32 is included in the partition region 31. In other words, the partition region 31 includes the trench portion 32 extending from the first facet S1 side to the second facet S2 side of the semiconductor layer 21.

[0070] <Photoelectric conversion region> like Figure 4A As shown in the plan view, the photoelectric conversion region 22 is surrounded by the dividing region 31 and has a rectangular planar shape. Specifically, the photoelectric conversion region 22 is surrounded by two first planar portions 31x extending in the X direction and spaced apart in the Y direction, and two second planar portions 31y extending in the Y direction and spaced apart in the X direction. Furthermore, the photoelectric conversion region 22 is divided by these planar portions and separated from other photoelectric conversion regions 22.

[0071] like Figure 5A As shown, the photoelectric conversion region 22 has a photoelectric conversion unit 25, which includes: an n-type semiconductor region 24 disposed in the semiconductor layer 21 and spaced apart from the first facet S1 of the semiconductor layer 21; and a p-type semiconductor region 33 disposed between the n-type semiconductor layer 24 and the separating region 31.

[0072] In addition, the photoelectric conversion region 22 also has an n-type floating diffusion region FD that serves as a charge holding part, which is disposed on the first surface S1 side of the semiconductor layer 21, adjacent to the separation region 31 in the plan view, and overlapping with the p-type semiconductor region 33 in the plan view; and a transmission transistor TR, which is disposed on the first surface S1 side of the semiconductor layer 21, overlapping with the n-type semiconductor region 24 in the plan view, and transmits the signal charge converted by photoelectric conversion in the photoelectric conversion part 25 to the floating diffusion region TD.

[0073] In addition, the photoelectric conversion region 22 also has a p-type well region 23 that is located closer to the first face S1 side of the semiconductor layer 21 than the n-type semiconductor region 24, and a p-type power contact region 45 located on the first face S1 side of the semiconductor layer 21.

[0074] Here, in this first embodiment, the n-type semiconductor region 24 corresponds to a specific example of the "first semiconductor region of the first conductivity type" of the present technology, and the p-type semiconductor region 33 corresponds to the "second semiconductor region of the second conductivity type" of the present technology. Furthermore, in this first embodiment, the n-type floating diffusion region FD corresponds to a specific example of the "charge holding part" of the present technology, and the p-type well region 23 corresponds to a specific example of the "second conductivity type well region" of the present technology. The photoelectric conversion region 22 also has included Figure 3 The pixel transistor Q in the pixel circuit 16 shown. In this first embodiment, although not limited thereto, however... Figure 4A The diagram shows an example of four pixels 3 (3a, 3b, 3c, and 3d) included in a pixel block 15, wherein the photoelectric conversion region 22 of pixel 3a also has an amplifying transistor AMP as a pixel transistor Q, the photoelectric conversion region 22 of pixel 3b also has a selection transistor SEL as a pixel transistor Q, the photoelectric conversion region 22 of pixel 3c also has a reset transistor RST as a pixel transistor Q, and the photoelectric conversion region 22 of pixel 3d also has a switching transistor FDG.

[0075] (n-type semiconductor region) like Figure 4A and Figure 5A As shown, an n-type semiconductor region 24 is disposed in the semiconductor layer 21 and spaced apart from the partition regions 31 (first and second longitudinal portions 31z1 and 31z2) surrounding the periphery of the photoelectric conversion region 22. Furthermore, the n-type semiconductor region 24 extends in the thickness direction (Z direction) of the semiconductor layer 21 and is spaced apart from each of the first facet S1 and the second facet S2 of the semiconductor layer 21.

[0076] (p-type trap region) like Figure 5A As shown, the p-type well region 23 is positioned closer to the first face S1 side of the semiconductor layer 21 than the n-type semiconductor region 24, and overlaps with the n-type semiconductor region 24 in the plan view. Furthermore, the p-type well region 23 is also positioned on the second face S2 side of the semiconductor layer 21, and overlaps with the n-type semiconductor region 24 in the plan view. Moreover, the p-type well region 23 contacts the n-type semiconductor region 24 on both the first face S1 side and the second face S2 side of the semiconductor layer 21, thereby forming a pn junction with the n-type semiconductor region 24. The p-type well region 23 is composed of a p-type semiconductor region.

[0077] (n-type floating diffusion region) like Figure 5A As shown, an n-type floating diffusion region FD is disposed in a p-type well region 23 on the first face S1 side of semiconductor layer 21. Furthermore, the n-type floating diffusion region FD overlaps with each of the n-type semiconductor region 24 and p-type semiconductor region 33 in the plan view, and is spaced apart from the n-type semiconductor region 24 and p-type semiconductor region 33 in the thickness direction (Z direction) of semiconductor layer 21. In other words, the p-type well region 23 is disposed between the n-type floating diffusion region FD and the n-type semiconductor region 24 and p-type semiconductor region 33.

[0078] Here, in this first embodiment, the n-type floating diffusion region FD overlaps with the n-type semiconductor region 24 in a plan view. However, in a plan view, the n-type floating diffusion region FD may not overlap with the n-type semiconductor region 24.

[0079] like Figure 5B As shown, the n-type floating diffusion region FD is positioned closer to the first face S1 side of the semiconductor layer 21 than the step portion 31zs between the first vertical portion 31z1 and the second vertical portion 31z2 of the separating region 31. In other words, the n-type floating diffusion region FD is positioned closer to the first face S1 side of the semiconductor layer 21 than the second vertical portion 31z2 of the separating region 31. Furthermore, the impurity concentration of the n-type floating diffusion region FD is higher than the impurity concentration of the n-type semiconductor region 24.

[0080] like Figure 4A As shown, the n-type floating diffusion region FD of each of the four photoelectric conversion regions 22 (four pixels 3a, 3b, 3c and 3d) included in a pixel block 15 is set to be adjacent to the intersection 31xy and outside the intersection 31xy, so as to surround the intersection 31xy of the dividing region 31 in the plan view.

[0081] (p-type semiconductor region) like Figure 5A As shown, the p-type semiconductor region 33 is disposed between the n-type semiconductor region 24 and the separating region 31 along the separating region 31, and extends in the thickness direction (Z direction) of the semiconductor layer 21. Furthermore, as... Figure 4A As shown, the p-type semiconductor region 33 surrounds the periphery of the n-type semiconductor region 24 and has an annular planar pattern (ring planar pattern) in the plan view.

[0082] like Figure 5AAs shown, the p-type semiconductor region 33 contacts the separator region 31 along the thickness direction (Z direction) of the semiconductor layer 21. This p-type semiconductor region 33 exhibits pinning damage (dangling bond) at the interface between the semiconductor layer 21 and the separator region 31; that is, it exhibits pinning damage (dangling bond) at the inner wall of the trench portion 22b of the separator region 31 in the semiconductor layer 21, thereby suppressing the dark current caused by this damage. In other words, the p-type semiconductor region 33 serves as a pinning layer. Since electrons causing dark current are absorbed by holes representing the majority carriers in the p-type semiconductor region 33, the dark current is suppressed.

[0083] In addition, such as Figure 5A As shown, the p-type semiconductor region 33 contacts the n-type semiconductor region 24 along the thickness direction of the semiconductor layer 21. Furthermore, the p-type semiconductor region 33 and the n-type semiconductor region form a pn junction, and a junction capacitance is constructed at the pn junction to temporarily retain the signal charge converted by photoelectric conversion in the n-type semiconductor region 24. The impurity concentration of the p-type semiconductor region 33 is higher than that of the p-type well region 23.

[0084] (Photoelectric conversion unit) Figure 5A The photoelectric conversion unit 25 shown includes a p-type well region 23, a p-type semiconductor region 33, and an n-type semiconductor region 24, and is constructed as a pn junction photodiode (PD) through a pn structure formed between the n-type semiconductor region 24 and the p-type well region 23 and the p-type semiconductor region 33. The photoelectric conversion unit 25 converts light incident on the n-type semiconductor region 24 from the second facet S2 side of the semiconductor layer 21 into signal charge in the n-type semiconductor region 24, and temporarily maintains (accumulates) the converted signal charge at the pn junction between the n-type semiconductor layer 24 and the p-type well region 23 and the p-type semiconductor region 33. The photoelectric conversion unit 25 is provided for each photoelectric conversion region 22 (pixel 3).

[0085] (Transmission transistor) like Figure 5A As shown, the transfer transistor TR is disposed on the first facet S1 side of the semiconductor layer 21. The transfer transistor TR has a gate electrode 43 disposed on the first facet S1 side of the semiconductor layer 21, and a gate insulating film 42 disposed between the gate electrode 43 and the semiconductor layer 21. Furthermore, the transfer transistor TR also has an n-type semiconductor region 24 and an n-type floating diffusion region FD serving as the source and drain regions, respectively, and a p-type well region 23 serving as the channel formation region. This transfer transistor TR can be configured, for example, as a vertical type, but is not limited to this configuration.

[0086] like Figure 4A and Figure 4BAs shown, the transfer transistors RT of the four photoelectric conversion regions 22 (four pixels 3a, 3b, 3c, and 3d) included in a pixel block 15 are set to be biased toward the cross-section 31xy side of the separation region 31 in the plan view. In addition, the gate electrodes 43 of the transfer transistors TR of the four photoelectric conversion regions 22 are provided outside the n-type floating diffusion region FD so as to surround the cross-section 31xy of the separation region 31 in the plan view.

[0087] As Figure 5B shown, the gate electrode 43 of the transfer transistor TR has a head 43a provided outside the first face S1 of the semiconductor layer 21, with a gate insulating film 42 between the head 43a and the first face S1 of the semiconductor layer 21; and a leg 43b protruding from the head 43a into the interior of the semiconductor layer 21 and adjacent to the semiconductor layer 21, with a gate insulating film 42 between the leg 43b and the semiconductor layer 21. In the gate electrode 43 of this first embodiment, for example, the width of the leg 43b is narrower than the width of the head 43a, but is not limited to this configuration. The leg 43b of the gate electrode 43 is provided in the trench portion 41 of the semiconductor layer 21, and there is a gate insulating film 42 between the leg 43b and the trench portion 41; and the leg 43b reaches the n-type semiconductor region 24. The gate insulating film 42 is made of, for example, a silicon oxide film. The gate electrode 43 is made of, for example, a polysilicon film doped with impurities for reducing the resistance value.

[0088] As Figure 5B shown, when the transfer transistor TR is turned on by applying a gate voltage to the gate electrode 43, a charge transfer path (channel) R1 that electrically connects the n-type semiconductor region 24 and the n-type floating diffusion region FD is formed in the p-type well region 23. Then, the signal charges photoelectrically converted in the n-type semiconductor region 24 of the photoelectric conversion unit 25 are transferred from the n-type semiconductor region 24 to the n-type floating diffusion region FD via the charge transfer path (signal charge transfer path) R1.

[0089] <p-type power supply contact region> As Figure 4A shown, in each of the four photoelectric conversion regions 22 included in a pixel block 15, the p-type power supply contact region 45 is provided outside the other cross-section located on the side opposite to the cross-section 31xy of the separation region 31 in the central region of the pixel block 15 in the plan view. In addition, as Figure 5AAs shown, a p-type power contact region 45 is disposed in a p-type well region 23 on the first surface S1 side of the semiconductor layer 21. Furthermore, in the plan view, the p-type power contact region 45 overlaps with the n-type semiconductor region 24 and the p-type semiconductor region 33, and is spaced apart from each of the n-type semiconductor region 24 and the p-type semiconductor region 33 via the p-type well region 23. This p-type power contact region 45 is made of a p-type semiconductor region and is electrically connected to each of the n-type well region 23 and the p-type semiconductor region 33.

[0090] <Fixed charge film> like Figure 5B As shown, a positively charged fixed-charge film 37 is disposed in the first vertical portion 31z1 to fill the first trench portion 32a of the separating region 31. Furthermore, the fixed-charge film 37 is configured to straddle the n-type floating diffusion region FD and the p-type semiconductor region 33 in the first trench portion 32a (first vertical portion 31z1). Moreover, the fixed-charge film 37 is in contact with and adjacent to each of the n-type floating diffusion region FD, the p-type well region 23, and the p-type semiconductor region 33. In other words, the fixed-charge film 37 overlaps with each of the n-type floating diffusion region FD, the p-type well region 23, and the p-type semiconductor region 33 in the X and Y directions. For example, silicon nitride (SiN) films, silicon carbonitride (SiCN) films, etc., can be used as the fixed-charge film 37.

[0091] like Figure 5B As shown, the positively charged fixed charge film 37 protrudes towards the second face S2 side of the semiconductor layer 21 in the thickness direction (Z direction) of the semiconductor layer 21, more so than the floating diffusion region FD. In other words, at the interface between the semiconductor layer 21 and the separating region 31, the fixed charge film 37 is positioned at least closer to the second face S2 side of the semiconductor layer 21 than the n-type floating diffusion region FD. In this first embodiment, the fixed charge film 37 is configured to straddle the n-type floating diffusion region FD and the p-type semiconductor region 33.

[0092] In addition, such as Figure 4B As shown in the plan view, the fixed charge film 37 with a positive fixed charge is more prominent than the floating diffusion region FD in both the X and Y directions extending from the partition region 31. In other words, the entire surface of the floating diffusion region FD facing the partition region 31 is in contact with the fixed charge film 37.

[0093] <<Methods for Manufacturing Solid State Cameras>> Next, we will use Figures 7A to 17 A method for manufacturing a solid-state imaging device 1A according to a first embodiment of the present technology is described. In this first embodiment, the manufacturing of the partition region 31 and the photoelectric conversion region 22 included in the manufacturing method of the solid-state imaging device 1A will be described. also, Figures 7A to 17 It shows the relationship with Figure 4A and Figure 5A The pixel block forming region 17 corresponding to one pixel block 15 is shown. Therefore, the pixel block forming region 17 includes four photoelectric conversion regions 22, each of which is surrounded by the trench forming region 32Z.

[0094] First, such as Figure 7A As shown in plan view (7B) and longitudinal sectional view (7B), p-type well regions 23 and n-type semiconductor regions 24 are formed in semiconductor layer 21. The p-type well region 23 is formed over the entire region of semiconductor layer 21, including photoelectric conversion regions 22 and trench formation regions 32Z. The n-type semiconductor regions 24 are selectively formed for each photoelectric conversion region 22. Figure 7A In the diagram, four undivided photoelectric conversion regions 22 are shown within a pixel block forming region 17. Furthermore, the four photoelectric conversion regions 22 are arranged in a 2×2 configuration, with each region distributed in pairs along the X and Y directions. The p-type well region 23 and the n-type semiconductor region 24 can be formed using known photolithography techniques and impurity ion implantation methods.

[0095] In this step, the n-type semiconductor region 24 is disposed inside the p-type well region 23, and its upper surface, lower surface and four sides (a total of six surfaces) are surrounded by the p-type well region 23. Furthermore, in this step, each photoelectric conversion region 22 has not yet been divided, and in subsequent steps, its periphery is actually formed with a first trench portion 32a (see reference). Figure 8A and Figure 8B ) and second groove 32b (refer to Figure 10 The groove forming region 32Z surrounds the area. The groove forming region 32Z is ​​not physically formed, but has a grid-like planar pattern surrounding the periphery of each photoelectric conversion region 22.

[0096] Here, in the manufacturing of the solid-state imaging device 1A of the first embodiment, a thinning step is performed to reduce the thickness of the semiconductor layer 21 in the Z direction (see reference). Figure 17 In this thinning step, the semiconductor layer 21 is thinned to... Figure 7B The thinning line S2a is shown.

[0097] Next, as Figure 8A (Floor plan) and Figure 8B As shown in the longitudinal cross-sectional view, the trench forming region 32Z is ​​selectively etched to form a first trench 32a that is recessed from the first face S1 toward the second face S2 on the first face S1 side of the semiconductor layer 21. The first trench portion 32a is formed as a grid-like planar pattern surrounding the periphery of each photoelectric conversion region 22. For example, the first trench portion 32a can be formed by selectively etching the trench portion forming region 32Z of the semiconductor layer 21 using known photolithography techniques and anisotropic dry etching techniques.

[0098] Next, as Figure 9A and Figure 9B As shown, an etching mask M1 is formed on the first face S1 side of the semiconductor layer 21. The etching mask M1 includes: an opening M1a having a grid-like planar pattern reflecting the grid-like planar pattern of the first trench portion 32a; and a mask portion M1b, divided by the opening M1a, covering the first face S1 side of the semiconductor layer 21 and the side surface portion of the semiconductor layer 21 inside the first trench portion 32a for each photoelectric conversion region 22. The etching mask M1 is made of a material that provides etching selectivity relative to the semiconductor layer 21. The opening M1a of the etching mask M1 is located at the first trench portion 32a and is narrower than the width of the first trench portion 32a. The width of the opening M1a defines the width of the second trench portion 32b, which will be explained below.

[0099] Next, using, for example, anisotropic dry etching, the trench formation region 32Z of the semiconductor layer 21 exposed through the opening M1a of the etching mask M1 is selectively etched to form, for example, the trench formation region 32Z of the semiconductor layer 21. Figure 10 The second trench portion 32b shown is continuous with the first trench portion 32a and extends from the first trench portion 32a toward the second surface S2 side of the semiconductor layer 21, and its width is narrower than that of the first trench portion 32b. The second trench portion 32b is formed to be deeper than the thinning line S2a of the semiconductor layer 21 that will be defined in the subsequent thinning step. In this step, the stepped trench portion 32 is formed to include a first trench portion 32a and a second trench portion 32b with different widths, and extends from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side. The stepped trench portion 32 is formed as a grid-like planar pattern surrounding each photoelectric conversion region 22. Furthermore, each photoelectric conversion region 22 is divided and separated by the stepped trench portion 32.

[0100] Next, as Figure 11 As shown, a p-type semiconductor region 33 is formed between the second trench portion 32b and the n-type semiconductor region 24 along the thickness direction (Z direction) of the semiconductor layer 21. The p-type semiconductor region 33 is formed with a higher impurity concentration than the p-type well region 23. Furthermore, the p-type semiconductor region 33 is formed in a grid-like planar pattern to surround the periphery of each n-type semiconductor region 24. p-type semiconductor regions 33 can be formed by, for example, ion implantation or solid-state diffusion. In the case of ion implantation, with each photoelectric conversion region 22 covered by the etched mask M1, boron (B) is implanted through the trench portion 32. + ) ions and boron difluoride (BF2) + Impurity ions, such as ions exhibiting p-type conductivity, are selectively implanted into the side surface of the semiconductor layer 21 in the second trench 32b. Then, a heat treatment is performed to activate the impurities. Therefore, a p-type semiconductor region 33 can be selectively formed on the side surface of the semiconductor layer 21 in the second trench 32b. Furthermore, in the case of solid-state diffusion, with each photoelectric conversion region 22 covered by the etch mask M1, boron (B2O3) exhibiting p-type conductivity is selectively formed in the second trench portion 32b. + ) or boron difluoride (BF2) + A solid-state diffusion film is formed. Subsequently, a heat treatment is performed to diffuse impurities from the solid-state diffusion film into the side surface portion of the semiconductor layer 21 in the second trench portion 32b. Therefore, the p-type semiconductor region 33 can be selectively formed on the side surface portion of the semiconductor layer 21 in the second trench portion 32b. In this first embodiment, the n-type semiconductor region 33 is formed by, for example, ion implantation.

[0101] In this step, the p-type semiconductor region 33 extends from the second trench portion 32b side towards the n-type semiconductor region 24 side, and impurity diffusion caused by heat treatment also extends in the thickness direction (Z direction) of the semiconductor layer 21. Therefore, the extension of the p-type semiconductor region 33 reduces the separation distance Sd1 between the first facet S1 of the semiconductor layer 21 and the p-type semiconductor region 33. As the separation distance Sd1 decreases, the n-type floating diffusion region FD (see [link to relevant documentation]) formed in subsequent steps will [expand further]. Figure 16 The separation distance Sd2 between the p-type semiconductor region 33 and the p-type semiconductor region 33 is also reduced. Boron and boron difluoride, which exhibit p-type conductivity, become easier to diffuse because they are lighter than phosphorus (p) or arsenic (As), which exhibit n-type conductivity.

[0102] Furthermore, in this step, a pn junction is formed between the n-type semiconductor region 24 and the p-type semiconductor region 33, and a photoelectric conversion unit 25 including the pn junction and the n-type semiconductor region 24 is formed.

[0103] Next, after removing the etching mask M1, as follows Figure 12 As shown, a separating insulating film 34 and a conductive material 35 are selectively formed inside the second trench portion 32b. The separating insulating film 34 is formed along the inner wall (side wall portion and bottom wall portion) of the second trench portion 32b. The conductive material 35 is formed inside the second trench portion 32b through the separating insulating film 34.

[0104] For example, a separating insulating film 34 and a conductive material 35 are sequentially formed on the entire surface of the first facet S1 side of the semiconductor layer 21, including inside the stepped trench portion 32. Then, the conductive material 35 and the separating insulating film 34, excluding the inside of the stepped trench portion 32, on the first facet S1 of the semiconductor layer 21 are selectively removed sequentially using a CMP method or the like. Next, the conductive material 35 and the separating insulating film 34 inside the first trench portion 32a are selectively removed. Therefore, the separating insulating film 34 and the conductive material 35 can be formed. The conductive material 35 and the separating insulating film 34 inside the first trench portion 32a can be removed by selectively performing etching using known photolithography techniques and anisotropic dry etching. For example, a silicon oxide film can be used as the separating insulating film 34. For example, a doped polysilicon film, introduced during or after deposition to reduce resistance, can be used as the conductive material 35. The conductive material 35 is electrically separated from the semiconductor layer 21 through the separating insulating film 34.

[0105] Next, as Figure 13A and Figure 13B As shown, a separating insulating film 36 is selectively formed inside the first trench portion 32a. For example, the separating insulating film 36 inside the first trench portion 32a can be formed by: forming the separating insulating film 36 on the entire surface of the semiconductor layer 21 on the first facet S1 side, including the interior of the first trench portion 32b; and then selectively removing the separating insulating film 36 on the first facet S1 of the semiconductor layer 21, except for the interior of the first trench portion 32a, by a CMP method or the like. Therefore, a separating insulating film 36 can be formed inside the first trench portion 32a. For example, a silicon oxide film deposited by CVD can be used as the separating insulating film 36. In this step, the interior of the first trench portion 32a is filled with a separating insulating film 36. Furthermore, in this step, a partition region 31 with a grid-like planar pattern is formed. The partition region 31 has: a first longitudinal portion 32z1, which includes a first groove portion 32a and a partition insulating film 36; a second longitudinal portion 32z2, which includes a second groove portion 32b and a partition insulating film 34; and a first planar portion 31x and a second planar portion 32y, which respectively include the first longitudinal portion 32z1 and the second longitudinal portion 32z2, and the first planar portion 31x and the second planar portion 31y intersect each other in the same plane. Furthermore, in this step, each photoelectric conversion region 22 is separated by a separation region 31, and two adjacent photoelectric conversion regions 22 are electrically and optically separated by the separation region 31. Furthermore, in this step, the separating region 31 has an intersection 31xy located between a first planar portion 31x and a second planar portion 31y in the central region of a pixel block forming region 17 that includes four photoelectric conversion regions 22.

[0106] Next, as Figure 14A and 14B As shown, at the central region of the pixel block forming region 17, the separating insulating film 36 at the intersection 31xy of the separating regions 31 is selectively removed to form an opening 36a. The separating insulating film 36 can be selectively removed using known photolithography techniques and anisotropic dry etching techniques. In this step, the side surface of the semiconductor layer 21 inside the opening 36a is exposed.

[0107] Next, as Figure 15 As shown, a fixed charge film 37 with a positive fixed charge is selectively formed inside the opening 36a at the intersection 31xy of the separating regions 31 to contact the semiconductor layer 21 inside the opening 36a. In this first embodiment, for example, the fixed charge film 37 is formed to fill the interior of the opening 36a, but it is not limited to this configuration. For example, the fixed charge film 37 is formed on the entire surface of the semiconductor layer 21 on the first surface S1 side, including the interior of the opening 36a. Then, the fixed charge film 37 on the first surface S1 of the semiconductor layer 21, except for the interior of the opening 36a, is selectively removed by a CMP method or the like. Therefore, a fixed charge film 37 can be formed. For example, silicon nitride films, silicon carbonitride films, etc., which can be deposited by CVD methods can be used as the fixed charge film 37. In this first embodiment, for example, a silicon carbonitride film is used as the fixed charge film 37.

[0108] Through this step, a separation region 31 is formed, including a fixed charge film 37 with a positive fixed charge. The separation region 31 is selectively configured to contact the semiconductor layer 21 at the first longitudinal portion 31z1 of the intersection portion 31xy where the first planar portion 31x and the second planar portion 31y intersect each other in the same plane.

[0109] Next, in each photoelectric conversion region 22, as Figure 16 As shown, an n-type floating diffusion region FD, a gate electrode 43, and a p-type power contact region 45 are formed in the surface layer portion on the first face S1 side of the semiconductor layer 21, and a pixel transistor Q is also formed thereal, although not shown.

[0110] A floating diffusion region FD is formed outside the intersection 31xy at the central region of the pixel block forming region 17, so as to surround the intersection 31xy of the separating region 31 in the plan view, and is formed to contact the intersection 31xy for each photoelectric conversion region 22. Furthermore, in the plan view, the floating diffusion region FD overlaps with the n-type semiconductor region 24 and the p-type semiconductor region 33, and is formed to be spaced apart from each of the n-type semiconductor region 24 and the p-type semiconductor region 33. This can be achieved by selectively introducing phosphorus ions (P... +) or arsenic ions (As + Impurity ions exhibiting n-type conductivity are implanted into the surface layer portion of the first face S1 side of the semiconductor layer 21, and then heat treatment is performed to activate the implanted impurity ions to form the floating diffusion region FD.

[0111] For each photoelectric conversion region 22, the gate electrode 43 is formed outside the floating diffusion region FD at the central region of the pixel block formation region 17, so as to surround the intersection 31xy of the separating region 31 in the plan view and be spaced apart from the floating diffusion region FD. The gate electrode 43 is formed by the following steps: forming a trench portion 41 extending from the first facet S1 side toward the second facet S2 side in the surface layer portion of the semiconductor layer 21; then forming a gate insulating film 42 along the inner wall (side wall and bottom wall) inside the trench portion 41; then forming a gate electrode film on the first facet S1 side of the semiconductor layer 21 to fill the interior of the trench portion 41 with the gate insulating film 42 in between; and then patterning the gate electrode film. For example, a doped polysilicon film for reducing resistance values ​​introduced during or after deposition can be used as the gate electrode film. The gate electrode 43 of the first embodiment has: a head 43a disposed on the first face S1 side of the semiconductor layer 21, and a gate insulating film 42 disposed between the head 43a and the first face S1; and a leg 43b protruding from the head 43a into the trench portion 41 of the semiconductor layer 21 and adjacent to the semiconductor layer 21, and a gate insulating film 42 disposed between the leg 43b and the semiconductor layer 21.

[0112] In each of the four photoelectric conversion regions 22 included in a pixel block forming region 17, a p-type power contact region 45 is formed on the outer side of the other intersections in the plan view, opposite to the intersection 31xy of the separating region 31. Furthermore, in the plan view, the p-type power contact region 45 overlaps with each of the n-type semiconductor regions 24 and 33, and is formed to be spaced apart from each of the n-type semiconductor regions 24 and 33. This can be achieved by using materials such as boron (B...) + ) or boron difluoride (BF2) + Impurity ions exhibiting p-type conductivity are implanted into the surface layer portion of the first face S1 side of the semiconductor layer 21, and then heat treatment is performed to activate the implanted impurity ions to form a p-type power contact region 45. The p-type power contact region 45 is formed in the p-type well region 23 and is electrically connected to each of the p-type well region 23 and the p-type semiconductor region 33.

[0113] In this step, a vertical transmission transistor TR is formed, which has a trench portion 41, a gate insulating film 42, a gate electrode 43, an n-type semiconductor region 24 and an n-type floating diffusion region FD serving as the source region and the drain region, respectively, and an n-type well region 23 serving as the channel formation region.

[0114] Furthermore, in this step, a photoelectric conversion region 22 is formed, comprising a p-type well region 23, an n-type semiconductor region 24, a photoelectric conversion section 25, a p-type semiconductor region 33, a p-type power contact region 45, a floating diffusion region FD, and a transmission transistor RT.

[0115] Next, although not shown, after forming the n-type floating diffusion region FD, the gate electrode 43, the p-type power contact region 45 and the pixel transistors (AMP, SEL, RST and FDG) Q, a multilayer wiring layer is formed on the first face S1 side of the semiconductor layer 21.

[0116] Next, after forming multiple wiring layers, such as Figure 17 As shown, a thinning step is performed to reduce the thickness of the semiconductor layer 21 by thinning the second face S2 of the semiconductor layer 21 to the thinning line S2a using, for example, CMP cutting. In this step, a partition region 31 is formed that extends from the first face S1 side of the semiconductor layer 21 along the thickness direction (Z direction) of the semiconductor layer 21 and reaches the second face S2 of the semiconductor layer 21, and a photoelectric conversion region 22 divided by the partition region 31 is also formed.

[0117] Then, by sequentially forming a planarization film 51, a filter 53, and a microlens 54 on the second face S2 side of the semiconductor layer 21, a... Figures 4A to 5B The state shown.

[0118] <<Main Effects of the First Implementation Plan>> Next, we will refer to Figures 6A to 6C The standard reference example shown illustrates the main effects of this first embodiment. Figure 6A This is a schematic longitudinal sectional view illustrating a conventional reference example of a longitudinal sectional structure. Figure 6B This demonstrates that when the separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33 is sufficient, Figure 6A A diagram illustrating an example of the potential in the charge transport path R1 of a conventional reference example. Figure 6C This illustrates the case where the separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33 is small. Figure 6AA diagram illustrating an example of the potential in the charge transport path R1 of a conventional reference example.

[0119] exist Figure 6A In the conventional reference example shown, the separating insulating film 36 is also provided at the intersection 31xy of the separating region 31 adjacent to the n-type floating diffusion region FD in the plan view.

[0120] exist Figure 6A In the conventional reference example shown, when the separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33 along the thickness direction (Z direction) of the semiconductor layer 21 is sufficient, such as Figure 6B As shown, the potential in the charge transport path (signal charge transport path) R1, in which the signal charge converted by photoelectric conversion in the n-type semiconductor region 24 is transported from the n-type semiconductor region 24 to the n-type floating diffusion region FD, becomes smooth. Therefore, the transport of signal charge from the n-type semiconductor region 24 to the n-type floating diffusion region FD can be performed smoothly.

[0121] On the other hand, when the separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33 is small, the n-type floating diffusion region FD and the p-type semiconductor region 33 interfere with each other, resulting in an increase in the parasitic capacitance added to the charge transport path R1. Therefore, as Figure 6C As shown, a potential barrier is formed in the charge transport path R1, which becomes a factor in the degradation of the signal charge transport characteristics.

[0122] On the other hand, such as Figure 5B As shown, in the solid-state imaging device 1A of this first embodiment, a fixed charge film 37 having a positive fixed charge is disposed at the intersection 3xy of the partition region 31 adjacent to the n-type floating diffusion region FD in the plan view. Furthermore, the fixed charge film 37 is positioned at the interface between the semiconductor layer 21 and the partition region 31 at a distance at least closer to the second face side of the semiconductor layer 21 than the floating diffusion region FD. Therefore, the substantial hole concentration near the floating diffusion region FD can be reduced. Even when the separation distance Sd1 between the n-type floating diffusion region FD and the p-type semiconductor region 33 is small, parasitic capacitance added to the charge transport path R1 due to interference between the n-type floating diffusion region FD and the p-type semiconductor region 33 can be suppressed. Furthermore, the potential in the charge transport path R1 can be smoothed, and the transmission of signal charge from the n-type semiconductor region 24 to the n-type floating diffusion region FD can be performed smoothly. Therefore, in the solid-state imaging device 1A of this first embodiment, the transmission of signal charge from the n-type semiconductor region 24 included in the photoelectric conversion unit 25 to the n-type floating diffusion region FD can be improved.

[0123] Furthermore, in the solid-state imaging device 1A according to this first embodiment, the p-type semiconductor region 33 is pinned and damaged at the interface between the semiconductor layer 21 and the trench portion 32 of the separating region 31. Therefore, dark current caused by damage at the interface between the semiconductor layer 21 and the trench portion 32 of the separating region 31 can be suppressed, and the transmission characteristics of signal charge from the n-type semiconductor region 24 included in the photoelectric conversion unit 25 to the n-type floating diffusion region FD can be improved.

[0124] Furthermore, during the manufacturing process, due to impurity diffusion caused by heat treatment, the p-type semiconductor region 33 extends in the thickness direction of the semiconductor layer 21. This causes the separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33 to decrease due to the extension of the p-type semiconductor region 33. Even when the separation distance Sd2 decreases, the parasitic capacitance added to the charge transport path R1 due to interference between the n-type floating diffusion region FD and the p-type semiconductor region 33 can be suppressed. In addition, the potential in the charge transport path R1 can be smoothed, and the transmission of signal charge from the n-type semiconductor region 24 to the n-type floating diffusion region FD can be performed smoothly. Therefore, in the solid-state imaging device 1A of this first embodiment, the transmission characteristics of signal charge from the n-type semiconductor region 24 included in the photoelectric conversion unit 25 to the n-type floating diffusion region FD can be improved.

[0125] Furthermore, the improved signal charge transmission characteristics enable a reduction in pixel size, thus providing a solid-state imaging device 1A with higher image quality.

[0126] <<Variations on the First Implementation Plan>> <Variation Example 1-1> In the first implementation scheme described above, it has been explained that... Figure 4A The illustration shows a case where a fixed charge film 37 is selectively disposed at the intersection 31xy of the partition regions 31. However, this technology is not limited to the first embodiment where the fixed charge film 37 is selectively disposed at the intersection 31xy of the partition regions 31. For example, such as Figure 18A and Figure 18B As shown, the fixed charge film 37 can be disposed along the partition region 31 surrounding the photoelectric conversion region 22 in the plan view. In this case, as Figure 18A and Figure 18B As shown, the fixed charge film 37 can be continuously arranged along the dividing region 31 in the plan view, or it can be intermittently arranged along the dividing region 31, although not shown. In this variation 1-1, the same effect as the first embodiment described above was also achieved.

[0127] <Variations 1-2> Furthermore, in the first embodiment described above, it has already been explained that... Figure 5A The first groove portion 32a at the intersection 31xy of the partition region 31 shown is filled with a fixed charge film 37 in the partition region 31. However, the present invention is not limited to the partition region 31 in the first embodiment where the first groove portion 32a is filled with a fixed charge film 37. For example, such as Figure 19 As shown, the separating region 31 may have a fixed charge film 37 disposed along the inner wall of the first trench portion 32a; and a low refractive index film 38 disposed inside the fixed charge film 37 and having a refractive index lower than that of the fixed charge film 37. In other words, the separating region 31 may have a fixed charge film 37 disposed along the inner wall of the first trench portion 32a, and a low refractive index film 38 disposed inside the first trench portion 32b, separated from the fixed charge film 37, and having a refractive index lower than that of the fixed charge film 37. For example, a silicon oxide film may be used as the low refractive index film 38. In these variations 1-2, the same effect as the first embodiment described above was also achieved. Furthermore, in these modified examples 1-2, a low-refractive-index film 38, with a refractive index lower than that of the fixed-charge film, is disposed inside the first trench portion 32a, separated by the fixed-charge film 37. Therefore, compared to the first embodiment described above, the light-shielding performance of the first longitudinal portion 31z1 of the partition region 31 can be improved. Note that this variation 1-2 can be combined with the above-described variation 1-1. In other words, the fixed charge film 37 and the low refractive index film 38 can be arranged continuously or intermittently along the partition region 31 surrounding the photoelectric conversion region 22 in the plan view.

[0128] <Variations 1-3> Furthermore, as a construction different from variations 1-2, such as Figure 20 As shown, the partition region 31 may have a fixed charge film 37 disposed along the inner wall of the first groove portion 32a and a cavity 39 disposed inside the fixed charge film 37. In other words, the partition region 31 may have a fixed charge film 37 disposed along the inner wall of the first groove portion 32a, and a cavity 39 disposed inside the first groove portion through the fixed charge film 37. In these variations 1-3, the same effect as the first embodiment described above was also achieved. Furthermore, the refractive index of the cavity 39 is lower than that of the silicon nitride or silicon carbonitride film used to fix the charge film 37. Therefore, in these modifications 1-3, the light-shielding performance of the first longitudinal portion 31z1 of the partition region 31 can be improved in the same manner as in the first embodiment described above, as in modifications 1-2 described above. Note that this variation 1-3 can also be combined with the above-described variation 1-1. In other words, the fixed charge film 37 and the cavity 39 can be arranged continuously or intermittently along the partition region 31 surrounding the photoelectric conversion region 22 in the plan view.

[0129] [Second Implementation Plan] The solid-state camera device 1B according to the second embodiment of the present technology has a structure that is substantially the same as that of the solid-state camera device 1A according to the first embodiment described above, but the arrangement of the floating diffusion region FD is different.

[0130] In other words, such as Figure 4A As shown, in the first embodiment described above, the floating diffusion region FD of each of the four photoelectric conversion regions 22 included in a pixel block 15 is configured to surround the intersection 31xy of the separating region 31 in a planar view. Furthermore, a fixed charge film 37 is selectively disposed at the intersection 31xy of the separating region 31.

[0131] On the other hand, in the solid-state imaging device 1B according to the second embodiment, such as Figure 21 As shown in the plan view, the respective floating diffusion regions FD of two photoelectric conversion regions 22 arranged in the X direction are arranged adjacent to each other across a separating region 31. Furthermore, a fixed charge film 37 is selectively disposed in the separating region 31 between these two adjacent floating diffusion regions FD. Alternatively, in this second embodiment, the separating region 31 including the fixed charge film 37 can also be constructed in the same manner as in the first embodiment described above.

[0132] In the solid-state camera device 1B according to the second embodiment, the same effect as that of the solid-state camera device 1A according to the first embodiment is also achieved.

[0133] <<Variations on the Second Implementation Plan>> Note that although not shown, when referring to Figure 21 As shown, even when the respective floating diffusion regions FD of the two photoelectric conversion regions 22 arranged in the Y direction in the plan view are adjacent to each other across the partition region 31, the fixed charge film 37 can be selectively disposed in the partition region 31 between the two floating diffusion regions FD. In this case, the same effect as the second embodiment described above is also obtained.

[0134] Furthermore, similar to the second embodiment described above, even when the respective floating diffusion regions FD of the two photoelectric conversion regions 22 arranged in the X direction in the plan view are arranged adjacent to each other across the separating region 31, the above-described modifications 1-1, 1-2, and 1-3 can be applied.

[0135] [Third Implementation Plan] The solid-state camera device 1C according to the first embodiment of the present technology has a substantially the same structure as the solid-state camera device 1A according to the first embodiment described above, but the structure of the pixel 3 is different.

[0136] In other words, such as Figure 4A As shown, the pixel 3 of the first embodiment described above has a structure in which a photoelectric conversion unit 25 is disposed in a photoelectric conversion region 22. on the other hand, Figure 22 In the third embodiment shown, pixel 3 is configured as a phase difference pixel, which detects the phase difference between two photoelectric conversion units 25 disposed in a photoelectric conversion region 22. This technology can also be applied to light detection devices that include such phase difference pixels.

[0137] like Figure 22 As shown, in pixel 3 of this third embodiment, the photoelectric conversion region 22 surrounded by the dividing region 31 is divided by the internal dividing region 56 into a first photoelectric conversion unit 22L and a second photoelectric conversion unit 22R. Furthermore, each of the first photoelectric conversion unit 22L and the second photoelectric conversion unit 22R has a photoelectric conversion section 25, a floating diffusion region FD, and a transmission transistor TR. Figure 22 The image shows two pixels 3 arranged in the Y direction out of four pixels 3 included in a pixel block 15.

[0138] In the plan view, the internal partition region 56 protrudes inwardly from the middle portions of the two first planar portions 31x and 31x extending in the X direction of the partition region 31 and between which the photoelectric conversion region 22 is located, and is spaced apart from each other. In other words, in the photoelectric conversion region 22, the first photoelectric conversion unit 23L and the second photoelectric conversion unit 23R, which are adjacent to each other in the X direction, are selectively separated by two internal partition regions 56, which protrude inwardly facing each other from the middle portions of the two first planar portions 31x and 31x extending in the X direction of the partition region 31.

[0139] The internal partition region 56 is integrated with the partition region 31. Furthermore, although not shown, the internal partition region 56 has the same structure as the partition region 31 along the thickness direction (Z direction) of the semiconductor layer 21. In other words, the partition region 31 includes the internal partition region 56.

[0140] like Figure 22As shown, the partition region 31 in this third embodiment also includes an intersection 31xy1, where the first planar portion 31x located between the two photoelectric conversion regions 22 arranged in the Y direction intersects with the internal partition region 56 extending intersecting each of the two photoelectric conversion regions 22 at the intersection 31xy1. Furthermore, in this third embodiment, the floating diffusion regions FD included in the first photoelectric conversion unit and the second photoelectric conversion units 22L and 22R of the two photoelectric conversion regions 22 arranged in the Y direction are arranged to surround the intersection 31xy1 of the partition region 31. Additionally, a fixed charge film 37 with a fixed charge is selectively disposed at the intersection 31xy1 of the partition region 31.

[0141] In this third embodiment, the fixed charge film 37 is configured in a planar view to extend over the first planar portion 31x and the inner partition region 56 of the partition region 31, and protrudes beyond the floating diffusion region FD in both the X and Y directions extending from the partition region 31 in the planar view. Furthermore, in this third embodiment, similar to the fixed charge film 37 in the first embodiment described above, the fixed charge film 37 is formed to straddle the n-type floating diffusion region FD and the p-type semiconductor region 33 at the interface between the semiconductor layer 21 and the partition region 31.

[0142] In the solid-state camera device 1C according to the third embodiment, the same effect as that of the solid-state camera device 1A according to the first embodiment is also achieved.

[0143] <<Variations on the Third Implementation Plan>> Note that even as in the third embodiment described above, when the floating diffusion regions FD included in the first photoelectric conversion unit and the second photoelectric conversion units 22L and 22R arranged in the two photoelectric conversion regions 22 in the Y direction are arranged to surround the intersection 31x1 of the partition region 31, the above-described variations 1-1 to 1-3 can also be applied.

[0144] [Fourth Implementation Plan] The fourth implementation plan will explain the extension section. Figure 23 This schematically illustrates a solid-state imaging device 1D according to a fourth embodiment of the present technology, including... Figure 1 A plan view of an example of the construction of pixel block 15 in pixel array section 2A shown. Figure 24 It is an illustrative representation of the path along Figure 23 The longitudinal section view of the longitudinal section structure cut by section line a23-a23. Figure 25 By magnification Figure 24 A portion of the longitudinal sectional view obtained. Figure 26It is shown schematically. Figure 24 A plan view of the planar pattern of the extension portion 31z3 of the partition region 31 shown. Figure 27 It is shown schematically. Figure 24 A plan view of the planar pattern of the second longitudinal portion 31z2 of the partition region 31 shown.

[0145] like Figure 23 and Figure 24 As shown, the solid-state imaging device 1D according to the fourth embodiment of the present invention has a structure substantially the same as that of the solid-state imaging device 1A according to the first embodiment described above, and the difference lies in the structure of the partition region 31. Furthermore, in the solid-state imaging device 1D according to the fourth embodiment, the partition insulating film 36 is also provided at the intersection 31xy of the partition region 31 adjacent to the n-type floating diffusion region FD in the plan view. Other structures are generally the same as those of the first embodiment described above. Therefore, in the fourth embodiment, the partition region 31 will be described primarily with reference to the first embodiment described above. Figure 23 In, with the aforementioned first implementation scheme Figure 4A Similarly, a pixel block 15 is shown containing four pixels 3 (3a, 3b, 3c, and 3d).

[0146] like Figure 24 As shown, the partition region 31 of this fourth embodiment includes an extension 31z3 that protrudes toward the photoelectric conversion region 22 beyond one and the other ends of the partition region 31 on opposite sides in the thickness direction (Z direction) of the semiconductor layer 21, and overlaps with the n-type floating diffusion region FD in the plan view. Furthermore, the extension 31z3 is spaced apart from the n-type floating diffusion region FD, and is adjacent to the n-type semiconductor region 24 between the n-type floating diffusion region FD and the p-type semiconductor region 33.

[0147] Furthermore, the partition region 31 of this fourth embodiment also includes: a first vertical portion 31z1, which is located on the first surface S1 side of the semiconductor layer 21 and adjacent to the n-type floating diffusion region FD in a plan view; and a second vertical portion 31z2, which is located on the second surface S2 side of the semiconductor layer 21 and adjacent to the p-type semiconductor region 33 in a plan view. Additionally, an extension portion 31z3 is located between the first vertical portion 31z1 and the second vertical portion 31z2, and is connected to each of the first and second vertical portions 31z1 and 31z2.

[0148] like Figure 24As shown, the extension portion 31z3 reaches the n-type semiconductor region 24 in the planar direction of the semiconductor layer 21. In the thickness direction (Z direction) of the semiconductor layer 21, the extension portion 31z3 is further away from the first facet S1 of the semiconductor layer 21 than the n-type semiconductor region 24. Furthermore, the width of the extension portion 31z3 is larger than the width of each of the first vertical portion 31z1 and the second vertical portion 31z2.

[0149] like Figure 24 As shown, the groove portion 32 included in the partition region 31 of this fourth embodiment is also structurally different from the groove portion 32 included in the isolation region 31 of the first embodiment described above. In other words, the groove portion 32 of this fourth embodiment includes: a first groove portion 32a, which is included in the first longitudinal portion 31z1; an extension groove portion 32c, which is included in the extension portion 31z3; and a second groove portion 32b, which is included in the second longitudinal portion 31z2. Furthermore, in the groove portion 32 of this fourth embodiment, the first groove portion 32a, the extension groove portion 32c, and the second groove portion 32b are connected sequentially.

[0150] like Figure 25 As shown, the first longitudinal portion 31z1 includes: a first trench portion 32a, which is recessed from the first surface portion S1 of the semiconductor layer 21 toward the second surface portion S2; a separating insulating film 34, which is disposed along the inner wall of the first trench portion 31a; and a separating insulating film 36, which is disposed in the first trench portion 32a through the separating insulating film 34. In this fourth embodiment, unlike the first embodiment described above, the separating insulating film 36 is also disposed at the intersection 31xy of the separating regions 31.

[0151] Note that the insulating membrane 34 of the first longitudinal portion 31z1 can be omitted.

[0152] like Figure 25 As shown, the extension portion 31z3 includes, for example, an extension trench portion 32c that extends from the first trench portion 32a toward the second surface S2 side of the semiconductor layer 21 and has a width greater than the width of each of the first and second trench portions 32a and 32b; a separating insulating film 34 disposed along the inner wall of the extension trench portion 32c; and a conductive material 35 disposed in the extension trench portion 32c through the separating insulating film 34. The extension portion 31z3 included in the separating region 31 of this fourth embodiment has an elliptical longitudinal cross-sectional shape along the thickness direction (Z direction) of the semiconductor layer 21.

[0153] like Figure 25As shown, the second longitudinal portion 31z2 includes: a second trench portion 32b, which extends from the extending trench portion 32c toward the second surface S2 side of the semiconductor layer 21 and has a width narrower than that of the first trench portion 32a; a separating insulating film 34, which is disposed along the inner wall of the second trench portion 32b; and a conductive material 35, which is disposed in the second trench region 32b through the separating insulating film 34.

[0154] Here, the difference between the width of the extension 31z3 and the widths of the first and second longitudinal portions 31z1 and 31z2 can also be defined as the protrusion.

[0155] like Figure 27 As shown, a p-type semiconductor region 33 is provided for each photoelectric conversion region 22. Furthermore, in the plan view, the p-type semiconductor region 33 is provided along the second longitudinal portion 31z2 of the partition region 31 surrounding the photoelectric conversion region 22 in the plan view.

[0156] like Figure 26 As shown, the extension portion 31z3 of the separating region 31 is disposed along the second longitudinal portion 31z2 of the separating region 31 to surround the photoelectric conversion region 22 in the plan view. In other words, the extension portion 31z3 is disposed along the separating region 31 that surrounds the photoelectric conversion region 22 in the plan view. Furthermore, the extension portion 31z3 overlaps with the p-type semiconductor region 33 in the plan view. Furthermore, as... Figure 25 As shown, in the thickness direction (Z direction) of the semiconductor layer 21, the extension portion 31z3 is set to be closer to the n-type floating diffusion region FD side than the p-type semiconductor region 33.

[0157] like Figure 24 As shown, the p-type semiconductor region 33 terminates at the extension portion 31z3 of the separator region 31 on the first surface S1 side of the semiconductor layer 21, thus suppressing the expansion in the thickness direction (Z direction) of the semiconductor layer 21 caused by impurity diffusion due to heat treatment. As described in the first embodiment, the p-type semiconductor region 33 expands not only due to heat treatment during its formation process but also due to other heat treatments during the manufacturing process. Therefore, the extension portion 31z3 of the separator region 31 is used to suppress the expansion of the p-type semiconductor region 33 in the thickness direction (Z direction) of the semiconductor layer 21.

[0158] <<Methods for Manufacturing Solid State Cameras>> Next, we will use Figures 28 to 37 A method for manufacturing a solid-state camera device 1D according to a fourth embodiment of the present technology is described. In this fourth embodiment, the manufacturing of the partitioned region 31, which is included in the manufacturing of the solid-state imaging device 1D, is described.

[0159] First, perform the same steps as in the first implementation scheme described above until a result is formed. Figure 28 The etching mask M1 is shown.

[0160] Next, as Figure 29 As shown, with the side surface of the semiconductor layer 21 on the first face S1 side and inside the first trench portion 32a covered by the mask portion M1b of the etching mask M1, the trench portion forming region 32Z of the semiconductor layer 21 exposed through the opening M1a of the etching mask M1 is selectively etched using, for example, an isotropic etching technique, to form an extended trench portion 32c that is continuous with the first trench portion 32a and has a width larger than the width of the first trench portion 32a.

[0161] In this step, an extended trench 32c with an elliptical longitudinal cross-section is formed along the thickness direction (Z direction) of the semiconductor layer 21. Furthermore, in this step, an extended groove 32c is formed along the first groove 32a that surrounds the periphery of the photoelectric conversion region 22 in the plan view.

[0162] Here, when the p-type semiconductor region 33 is formed in a subsequent step, the extended trench portion 32c can suppress the longitudinal (thickness direction (Z direction) of the semiconductor layer 21) expansion of the p-type semiconductor region 33 due to impurity diffusion caused by heat treatment. Therefore, it is preferable to form the extended trench portion 32c to reach the n-type semiconductor region 24, but it can be slightly separated from the n-type semiconductor region 24. In this fourth embodiment, the extended trench portion 32c is formed to have a width that slightly extends into the n-type semiconductor region 24.

[0163] Next, as Figure 30 As shown, after removing the etch mask M1, an etch mask M2 is formed that covers the inner walls of the first trench portion 32a and the extended trench portion 32c, as well as the first surface portion S1 of the semiconductor layer 21. The etch mask M2 is made of a material that provides etching selectivity relative to the semiconductor layer 21.

[0164] Next, the etch mask M2 on the semiconductor layer 21 side (the trench formation region 32Z side) directly below the extended trench 32c is selectively removed to form an opening. Then, as... Figure 31 As shown, the trench portion forming region 32Z exposed through the opening is selectively etched using, for example, anisotropic dry etching technology, to form a second trench portion 32b that is continuous with the extended trench portion 32c, extends from the extended trench portion 32c toward the second face S2 side of the semiconductor layer 21, and has a width narrower than that of the first trench portion 42a. The second trench portion 32b is formed to be deeper than the thinning line S2a of the semiconductor layer 21 (which will be performed in a subsequent thinning step).

[0165] In this step, a stepped trench portion 32 is formed, comprising a first trench portion 32a, an extending trench portion 32c, and a second trench portion 32b, each with a different width, and extending from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side. Similar to the first embodiment described above, the stepped trench portion 32 is formed as a grid-like planar pattern surrounding each photoelectric conversion region 22. Furthermore, each photoelectric conversion region 22 is divided and separated by the stepped trench portion 32.

[0166] Next, as Figure 32 As shown, a p-type semiconductor region 33 is formed between the second trench portion 32b and the n-type semiconductor region 24 along the thickness direction (Z direction) of the semiconductor layer 21. The p-type semiconductor region 33 is formed with a higher impurity concentration than the p-type well region 23. Furthermore, the p-type semiconductor region 33 is formed in a grid-like planar pattern to surround the periphery of each n-type semiconductor region 24. Similar to the first embodiment described above, the p-type semiconductor region 33 can be formed by, for example, ion implantation or solid-state diffusion.

[0167] In this step, the p-type semiconductor region 33 extends from the second trench portion 32b side toward the n-type semiconductor region 24 side, and also extends in the thickness direction (Z direction) of the semiconductor layer 21 due to impurity diffusion caused by heat treatment. However, in this fourth embodiment, the trench portion 32 included in the separating region 31 has an extending trench portion 32c protruding toward the n-type semiconductor region 24 side between the first trench portion 32a and the second trench portion 32b. Therefore, the extension of the p-type semiconductor region 33 toward the first face S1 side of the semiconductor layer 21 can be suppressed, thereby suppressing the reduction of the separation distance Sd1 between the first face S1 of the semiconductor layer 21 and the p-type semiconductor region 33. If the separation distance Sd1 decreases, it will be affected in subsequent steps (see...). Figure 36 The separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33 formed in the process is also reduced. In other words, by suppressing the reduction of the separation distance Sd1, the reduction of the separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33 can be suppressed.

[0168] Next, remove the etch mask M2, and then, as follows Figure 33 As shown, a separating insulating film 34, for example made of silicon oxide film, is formed along the inner wall of the trench portion 32, which includes a first trench portion 32a, an extended trench portion 32c, and a second trench portion 32b, by a CVD method. In this step, a separating insulating film 34 is also formed on the first face S1 side of the semiconductor layer 21.

[0169] Next, as Figure 34As shown, conductive material 35 is selectively formed inside each of the extended trench portion 32c and the second trench portion 32b, separated by a separating insulating film 34. For example, conductive material 35 is formed on the entire surface of the first facet S1 of the semiconductor layer 21, including the interior of the trench portion 32. Then, conductive material 35 on the first facet S1 of the semiconductor layer 21, except for the interior of the trench portion 32, is selectively removed by a CMP method or the like. Next, conductive material 35 inside the first trench portion 32a can be selectively removed. Thus, conductive material 35 can be formed. The conductive material 35 of the first trench portion 32 can be removed by selectively performing etching using known photolithography techniques and anisotropic dry etching. For example, a doped polysilicon film for reducing resistance values, introduced during or after deposition, can be used as conductive material 35. The conductive material 35 is electrically insulated from the semiconductor layer 21 by the separating insulating film 34.

[0170] Next, as Figure 35 As shown, a separating insulating film 36 is selectively formed inside the first trench portion 32a. For example, the separating insulating film 36 inside the first trench portion 32a is formed on the entire surface of the semiconductor layer 21 on the first surface S1 side, including inside the first trench portion 32b. Then, the separating insulating film 36 on the first surface S1 of the semiconductor layer 21, except for the inside of the first trench portion 32a, is selectively removed by a method such as CMP. Therefore, the separating insulating film 36 inside the first trench portion 32a can be formed. For example, a silicon oxide film deposited by CVD can be used as the separating insulating film 36. In this step, the interior of the first trench portion 32a is filled with a separating insulating film 36. Furthermore, in this step, a first longitudinal portion 31z1 including a first trench portion 32a and a separating insulating film 36, an extension portion 31z3 including an extended trench portion 32c, a separating insulating film 34 and a conductive material 35, and a second longitudinal portion 31z2 including a second trench portion 32b, a separating insulating film 34 and a conductive material 35 are formed.

[0171] Furthermore, in this step, a partition region 31 with a grid-like planar pattern is formed. The partition region 31 has a first planar portion 31x and a second planar portion 31y. Each of the first planar portion 31x and the second planar portion 31y includes a first longitudinal portion 31z1, an extension portion 31z3 and a second longitudinal portion 31z2. The first planar portion 31x and the planar portion 31y intersect each other in the same plane. Furthermore, in this step, each photoelectric conversion region 22 is divided by a separating region 31, and two adjacent photoelectric conversion regions 22 are electrically and optically separated by the separating region 31. Furthermore, in this step, the separating region 31 has an intersection 31xy between a first planar portion 31x and a second planar portion 31y located in the central region of a pixel block forming region 17 that includes four photoelectric conversion regions 22.

[0172] Next, in each photoelectric conversion region 22, as Figure 36 As shown, an n-type floating diffusion region FD, a gate electrode 43, and a p-type power contact region 45 are formed in the surface layer portion on the first face S1 side of the semiconductor layer 21, and a pixel transistor Q is also formed thereal, although not shown. Each of the n-type floating diffusion region FD, the gate electrode 43, the p-type power contact region 45, and the pixel transistor Q is formed in the same manner as in the first embodiment described above.

[0173] In this step, a vertical transmission transistor RT is formed having a trench portion 41, a gate insulating film 42, a gate electrode 43, an n-type semiconductor region 24 and an n-type floating diffusion region FD that serve as source and drain regions respectively, and an n-type well region 23 that serves as a channel formation region. Furthermore, in this step, a photoelectric conversion region 22 is formed, comprising a p-type well region 23, an n-type semiconductor region 24, a photoelectric conversion section 25, a p-type semiconductor region 33, a p-type power contact region 45, a floating diffusion region FD, and a transmission transistor RT.

[0174] Furthermore, in this step, the n-type floating diffusion region FD and the p-type power contact region 45 are formed by selectively implanting impurity ions and then performing heat treatment to activate the implanted impurity ions. Therefore, even during this heat treatment, the p-type semiconductor region 33 attempts to expand. However, since the extension portion 31z3 of the separating region 31 is provided between the n-type floating diffusion region FD and the p-type semiconductor region 33, it is possible to suppress the expansion of the p-type semiconductor region 33 toward the n-type floating diffusion region FD beyond the extension portion 31z3.

[0175] Next, a multilayer wiring layer is formed on the first face S1 side of the semiconductor layer 21, and then, as follows Figure 37 As shown, a thinning step is performed by thinning the second face S2 of the semiconductor layer 21 to the thinning line S2a by cutting, for example, using a CMP method. In this step, a separation region 31 is formed, which extends from the first face S1 side of the semiconductor layer 21 along the thickness direction (Z direction) of the semiconductor layer 21 and reaches the second face S2 of the semiconductor layer 21, and a photoelectric conversion region 22 divided by the separation region 31 is also formed.

[0176] Then, by sequentially forming a planarization film 51, a color filter 53, and a microlens 54 on the second face S2 side of the semiconductor layer 21, a solution is obtained. Figures 23 to 27 The state shown.

[0177] <<Main Effects of the Fourth Implementation Plan>> Next, the main effects of this fourth implementation plan will be explained. like Figure 24 As shown, the partition region 31 of the solid-state imaging device 1D according to the fourth embodiment includes an extension 31z3. The extension 31z3 protrudes further toward the photoelectric conversion region 22 than one end and the other end of the partition region 31 located on opposite sides in the thickness direction of the semiconductor layer 21, and overlaps with the n-type floating diffusion region FD in the plan view. Furthermore, the extension 31z3 is spaced apart from the n-type floating diffusion region FD, and is adjacent to the n-type semiconductor region 24 between the n-type floating diffusion region FD and the p-type semiconductor region 33. Additionally, the partition region 31 includes a trench portion 32, and the extension 31z3 includes an extended trench portion 32c.

[0178] Therefore, during the manufacturing process, the expansion of the p-type semiconductor region 33 in the thickness direction (Z direction) of the semiconductor layer 21 due to impurity diffusion caused by heat treatment can be suppressed, thereby suppressing the separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33 (refer to...). Figure 25 Therefore, the interference between the n-type floating diffusion region FD and the p-type semiconductor region 33 can be suppressed, thereby suppressing the increase of parasitic capacitance in the charge transport path (signal charge transport path) R1 that transfers the photoelectric converted signal charge in the n-type semiconductor region 24 from the n-type semiconductor region 24 to the n-type floating diffusion region FD, and suppressing the degradation of the signal charge transport characteristics.

[0179] Therefore, in the solid-state imaging device 1D of the fourth embodiment, the transmission characteristics of signal charge from the n-type semiconductor region 24 included in the photoelectric conversion unit 25 to the n-type floating diffusion region FD can be improved.

[0180] Furthermore, the pn junction between the p-type semiconductor region 33 and the n-type semiconductor region 24 is physically separated from the charge transport path R1 by the extension portion 31z3. Therefore, the saturation charge can be increased. This enables the achievement of excellent charge transport characteristics and a high saturation charge.

[0181] Furthermore, improvements in signal charge transmission characteristics enable a reduction in pixel size, thus allowing for the provision of solid-state imaging devices with higher image quality.

[0182] <<Variations on the Fourth Implementation Plan>> <Variation Example 4-1> In the fourth embodiment described above, it has been explained that the extension portion 31z3 of the partition region 31 is provided along the second longitudinal portion 31z2 that surrounds the partition region 31 of the photoelectric conversion region 22 in the plan view. However, the present technology is not limited to the extension portion 31z3 of the fourth embodiment described above.

[0183] For example, such as Figure 38 As shown, the extension 31z3 can be selectively disposed at the intersection 31xy of the partition region 31 adjacent to the n-type floating diffusion region FD in the plan view. In this variation 4-1, the same effect as the fourth embodiment described above was also achieved.

[0184] like Figure 38 As shown, the n-type floating diffusion regions FD of the four photoelectric conversion regions 22 included in a pixel block 15 are disposed around the intersection 31xy of two separating regions 31 (a first planar portion 31x extending in the X direction and a second planar portion 31y extending in the Y direction) that intersect each other in the plan view. Furthermore, in the plan view, the extension portion 31z3 of the separating region 31 is selectively disposed at the intersection 31xy.

[0185] <Variation Example 4-2> Furthermore, the aforementioned fourth implementation plan can be combined with the aforementioned first implementation plan. For example, such as Figure 39 As shown, a fixed charge film 37 with a positive fixed charge can be disposed at the intersection 31xy of the partition region 31 adjacent to the n-type floating diffusion region FD in the plan view.

[0186] <Other variations> Furthermore, although not shown, the fourth embodiment described above can also be combined with any of the above variations 1-1, 1-2 and 1-3. Furthermore, although not shown, the partition region 31 including the extension portion 31z3 of the fourth embodiment described above can also be applied to each of the second and third embodiments described above.

[0187] [Fifth Implementation Plan] like Figure 40 and Figure 41 As shown, the solid-state imaging device 1E according to the fifth embodiment of the present technology has essentially the same structure as the solid-state imaging device 1D according to the fourth embodiment described above, except that the longitudinal cross-sectional shape of the extension portion 31z3 of the partition region 31 is different. Other structures are generally the same as those described in the fourth embodiment.

[0188] like Figure 41 and Figure 42As shown, in this fifth embodiment, the extension 31z3 of the partition region 31 has a rectangular longitudinal section shape along the thickness direction (Z direction) of the semiconductor layer 21. This rectangular extension 31z3 can be formed by processing the longitudinal section shape of the extended trench portion 32c into a rectangular shape. This can be achieved by using a semiconductor layer 21 with a (111) crystal plane of monocrystalline silicon, and by including it in the manufacturing process of the solid-state imaging device 1E. Figure 43 In the rectangular trench formation step (including in the manufacturing process of the solid-state imaging device 1E), the semiconductor layer 21 is wet-etched under etching conditions aligned with the (111) crystal plane of monocrystalline silicon to easily form the extended trench 32c. Figure 43 As shown, in the same manner as the fourth embodiment described above, the semiconductor layer 21 is etched while the side surface portion of the semiconductor layer 21, including the first face S1 side and the interior of the first trench portion 32a, is covered by the mask portion M1b of the etching mask M1. This etching process forms a rectangular extended trench portion 32c that is continuous with the first trench portion 32a and has a width greater than that of the first trench portion 32a.

[0189] In the solid-state camera device 1E according to the fifth embodiment, the same effect as that of the solid-state camera device 1D according to the fourth embodiment is also achieved.

[0190] <<Variations on the Fifth Implementation Plan>> <Variation Example 5-1> In the fifth embodiment described above, it has been explained that the extension portion 31z3 of the partition region 31 is provided along the extension portion 31z3 of the partition region 31 surrounding the photoelectric conversion region 22 in the plan view. However, the present technology is not limited to the extension portion 31z3 of the fifth embodiment described above.

[0191] For example, such as Figure 44 As shown, the extension portion 31z3 can be selectively disposed at the intersection 31xy of the partition region 31 adjacent to the n-type floating diffusion region FD in the plan view. In this variation 5-1, the same effect as the fifth embodiment described above was also achieved.

[0192] <Variation Example 5-2> Furthermore, the fifth implementation plan described above can also be combined with the first implementation plan described above. For example, such as Figure 45 As shown, a fixed charge film 37 with a positive fixed charge can be disposed at the intersection 31xy of the partition region 31 adjacent to the n-type floating diffusion region FD in the plan view.

[0193] <Other variations> Furthermore, although not shown, the fifth embodiment described above can also be combined with any of the above variations 1-1, 1-2 and 1-3. Furthermore, although not shown, the partition region 31 including the extension portion 31z3 of the fifth embodiment described above can also be applied to each of the second and third embodiments described above.

[0194] [Sixth Implementation Plan] In this sixth embodiment, the first longitudinal portion having an inclined portion will be described. Figure 46 This schematically illustrates a solid-state imaging device 1F according to a sixth embodiment of the present technology, in which... Figure 1 A plan view of an example of the construction of pixel blocks 15 included in the pixel array section 2A shown. Figure 47 It is an illustrative representation of the path along Figure 46 The longitudinal section view of the longitudinal section structure cut by section line a46-a46. Figure 48 By magnification Figure 47 A portion of the longitudinal sectional view obtained.

[0195] like Figure 46 and Figure 47 As shown, the solid-state imaging device 1F according to the sixth embodiment of the present technology has a structure substantially the same as that of the solid-state imaging device 1A according to the first embodiment described above, except that the structure of the partition region 31 is different. Other structures are generally the same as those of the first embodiment described above. Therefore, in this sixth embodiment, the partition region 31 will be described primarily with reference to the first embodiment described above. Compared with the first embodiment described above... Figure 4A Similarly, in Figure 46 The image shows four pixels 3 (3a, 3b, 3c and 3d) included in a pixel block 15.

[0196] like Figure 47 As shown, similar to the partition region 31 of the first embodiment described above, the partition region 31 of this sixth embodiment includes a trench portion 32 extending from the first facet S1 side of the semiconductor layer 21 toward the second facet S2 side. Furthermore, the partition region 31 has a first vertical portion 31z1 disposed on the first facet S1 side of the semiconductor layer 21; and a second vertical portion 31z2 extending from the first vertical portion 31z1 toward the second facet S2 side of the semiconductor layer 21 and having a width narrower than the width of the first vertical portion 31z1. In other words, the first vertical portion 31z1 protrudes further toward the photoelectric conversion region 22 than the second vertical portion 31z1.

[0197] like Figure 47As shown, in the same manner as the first embodiment described above, the photoelectric conversion region 22 has a photoelectric conversion section 25, which includes: an n-type semiconductor region 24 disposed in the semiconductor layer 21 and spaced apart from the first facet S1; and a p-type semiconductor region 33 disposed between the second vertical portion 31z2 of the separating region 31 and the n-type semiconductor region 24, and serving as a pinning layer. Furthermore, the photoelectric conversion region 22 also includes: an n-type floating diffusion region FD disposed on the first facet S1 side of the semiconductor layer 21, adjacent to the first vertical portion 31z1 of the separating region 31 in a plan view, and overlapping with the p-type semiconductor region 33 in a plan view; and a transmission transistor TR disposed on the first facet S1 side of the semiconductor layer 21, overlapping with the n-type semiconductor region 24 in a plan view, and transmitting the photoelectrically converted signal charge in the n-type semiconductor region 24 to the n-type floating diffusion region FD (see reference 1) via a charge transport path R1. Figure 48 ).

[0198] like Figure 48 As shown, the first vertical portion 31z1 of this sixth embodiment has an inclined portion 61, which forms an acute angle θ1 with the first facet S1 of the semiconductor layer 21 on the FD side of the n-type floating diffusion region. Furthermore, the inclined portion 61 is located closer to the first facet S1 of the semiconductor layer 21 than the n-type semiconductor region 24. Additionally, the inclined portion 61 protrudes further toward the photoelectric conversion region 22 than the second vertical portion 31z2.

[0199] like Figure 48 As shown, the first vertical portion 31z1 overlaps with the p-type semiconductor region 33 in the plan view and contacts the n-type semiconductor region 24. Furthermore, one end of the p-type semiconductor region 33 on the first surface S1 side of the semiconductor layer 21 terminates at the first vertical portion 31z1 of the separating region 31, suppressing the expansion in the thickness direction (Z direction) of the semiconductor layer 21 caused by impurity diffusion due to heat treatment. As described in the first embodiment, the p-type semiconductor region 33 expands not only due to heat treatment during its formation process but also due to other heat treatments in the manufacturing process. Therefore, in this sixth embodiment, the first vertical portion 31z1 of the separating region 31 is used to suppress the expansion of the p-type semiconductor region 33 in the thickness direction (Z direction) of the semiconductor layer 21.

[0200] Here, the difference between the width of the first longitudinal portion 31z1 and the width of the second longitudinal portion 31z2 can also be defined as the protrusion.

[0201] like Figure 48As shown, unlike the first longitudinal portion 31z1 of the first embodiment described above, the first longitudinal portion 31z of this sixth embodiment has a cavity 63. Specifically, the first longitudinal portion 31z1 of this sixth embodiment has: a separating insulating film 62 disposed along the inner wall portion (side wall portion and lower wall portion) of the first trench portion 32a, sealing the opening side of the first trench portion 32a; and a cavity 63 surrounded by the separating insulating film 62. Using a film with low coverage as the separating insulating film 62 during film formation allows the inner wall portion of the first trench portion 31a to be covered without filling the first trench portion 32a, and allows the opening side of the first trench portion 32b to be sealed to form the cavity 63. For example, a silicon nitride film can be used as the separating insulating film 62.

[0202] <<Methods for Manufacturing Solid State Cameras>> Next, we will use Figures 49 to 57 The manufacturing method of the solid-state camera device 1F according to the sixth embodiment of this technology is described. In this sixth embodiment, the manufacturing of the partition region 31 included in the manufacturing of the solid-state imaging device 1F will be described with a focus on the manufacturing process.

[0203] First, perform the same steps as in the first implementation scheme described above, until formation... Figure 49 The state shown.

[0204] Next, as Figure 50 As shown, the trench formation region 32Z of the semiconductor layer 21 is selectively etched to form a shallow recess 65. The shallow recess 65 is formed as a grid-like planar pattern surrounding the periphery of the photoelectric conversion region 22. The shallow recess 65 is formed using, for example, known photolithography techniques and anisotropic dry etching techniques.

[0205] Next, as Figure 51 As shown, the trench forming region 32Z of the semiconductor layer 21 is selectively etched in the trench forming region 32Z by a shallow trench 65 to form a first trench 32a recessed from the first face S1 towards the second face S2 side on the first face S1 side of the semiconductor layer 21. The first trench 32a is formed with an inclined portion 61, which forms an acute angle θ1 (θ1 < 90°) with the first face S1 of the semiconductor layer 21. In this sixth embodiment, although not limited thereto, for example, the first trench 32a is formed with an inclined portion 61a of θ1 = 45°. This inclined portion 61a defines the inclined portion 61 of the first longitudinal portion 31z1, which will be described later. The first trench portion 32a with the inclined portion 61 can be easily formed using known photolithography techniques and anisotropic wet etching techniques.

[0206] Here, when the p-type semiconductor region 33 is formed in a subsequent step, the first trench portion 32a can suppress the longitudinal (thickness direction (Z direction) of the semiconductor layer 21) expansion of the p-type semiconductor region 33 due to impurity diffusion caused by heat treatment. Therefore, it is preferable to form the first trench portion 32a in contact with the n-type semiconductor region 24, but it can be slightly separated from the n-type conductor region 24. In this sixth embodiment, the first trench portion 32a is formed in contact with the n-type semiconductor region 24.

[0207] Next, as Figure 52 As shown, an etching mask M3 is formed covering the inner wall portion of the first trench 32a and the first surface portion S1 of the semiconductor layer 21. The etching mask M3 is made of a material that provides etching selectivity relative to the semiconductor layer 21.

[0208] Next, the etch mask M3 on the bottom surface of the first trench portion 32a is selectively removed to form an opening. Then, as... Figure 53 As shown, anisotropic dry etching is used to selectively etch the trench portion forming region 32Z exposed through the opening to form a second trench portion 32b that is continuous with the first trench portion 32a, extends from the first trench portion 32b toward the second face S2 side of the semiconductor layer 21, and has a width narrower than that of the first trench portion 42a. The second trench portion 32b is formed to be deeper than the thinning line S2a of the semiconductor layer 21 (which will be performed in a subsequent thinning step).

[0209] In this step, a stepped trench portion 32 is formed, comprising a first trench portion 32a and a second trench portion 32b, each with a different width, and extending from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side. Similar to the first embodiment described above, the stepped trench portion 32 is formed as a grid-like planar pattern surrounding the photoelectric conversion region 22. Furthermore, each photoelectric conversion region 22 is divided and separated by the stepped trench portion 32.

[0210] Next, as Figure 53 As shown, a p-type semiconductor region 33 is formed between the second trench portion 32b and the n-type semiconductor region 24 along the thickness direction (Z direction) of the semiconductor layer 21. The p-type semiconductor region 33 is formed with a higher impurity concentration than the p-type well region 23. Furthermore, the p-type semiconductor region 33 is formed in a grid-like planar pattern to surround the periphery of each n-type semiconductor region 24. Similar to the first embodiment described above, the p-type semiconductor region 33 can be formed by, for example, ion implantation or solid-state diffusion.

[0211] In this step, the p-type semiconductor region 33 extends from the second trench portion 32b side toward the n-type semiconductor region 24 side, and also extends in the thickness direction (Z direction) of the semiconductor layer 21 due to impurity diffusion caused by heat treatment. However, in this sixth embodiment, the trench portion 32 included in the separation region 31 has a first trench portion 32a extending toward the n-type semiconductor region 24 side and contacting the n-type semiconductor region 24. Therefore, the extension of the p-type semiconductor region 33 toward the first face portion S1 side of the semiconductor layer 21 can be suppressed, thereby suppressing the reduction of the separation distance Sd1 between the first face portion S1 of the semiconductor layer 21 and the p-type semiconductor region 33. If the separation distance Sd1 decreases, the n-type floating diffusion region FD (refer to) formed in subsequent steps will be affected. Figure 58 The separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33 also decreases. In other words, by suppressing the decrease in separation distance Sd1, it is possible to suppress the decrease in separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33.

[0212] Next, after removing the etching mask M3, as follows Figure 55 As shown, a separating insulating film 34 and a conductive material 35 are selectively formed inside the second trench portion 32b. The separating insulating film 34 is formed along the inner wall (side wall portion and bottom wall portion) of the second trench portion 32b. The conductive material 35 is formed inside the second trench portion 32b through the separating insulating film 34. For example, a separating insulating film 34 and a conductive material 35 are sequentially formed on the entire surface of the first facet S1 side of the semiconductor layer 21, including inside the stepped trench portion 32. Then, the conductive material 35 and the separating insulating film 34 on the first facet S1 of the semiconductor layer 21, except inside the stepped trench portion 32, are selectively removed sequentially using a CMP method or the like. Next, the conductive material 35 and the separating insulating film 35 inside the first trench portion 32a are selectively removed. Thus, the separating insulating film 34 and the conductive material 35 can be formed. The conductive material 35 and the separating insulating film 34 inside the first trench portion 32a can be removed by selectively performing etching using known photolithography techniques and anisotropic dry etching. For example, a silicon oxide film can be used as the separating insulating film 34. For example, a doped polysilicon film, introduced during or after deposition to reduce resistance, can be used as the conductive material 35. The conductive material 35 is electrically separated from the semiconductor layer 21 by the separating insulating film 34. In this step, a second longitudinal portion 31z2 is formed, comprising a second trench portion 32b, a separating insulating film 34, and a conductive material 35.

[0213] Next, as Figure 56As shown, inside the first trench portion 32a, a separating insulating film 62 is formed extending along the inner wall portion (side wall portion and bottom wall portion) of the first trench portion 31a and sealing the opening side of the first trench portion 32a, and a cavity 63 surrounded by the separating insulating film 62 is also formed. The separating insulating film 62 is formed to seal the opening side of the first trench portion 32a without filling the interior of the first trench portion 32b. For example, a silicon nitride film with low coverage can be used as the separating insulating film 62 to form the cavity 63. In this step, a first longitudinal portion 31z1 is formed, including a first trench portion 32a, an inclined portion 61, a separating insulating film 62, and a cavity 63. In other words, the first longitudinal portion 31z1 has an inclined portion 61 and is formed in a shape that contacts the n-type semiconductor region 24. Furthermore, in this step, a partition region 31 is formed, including a first groove portion 32a and a second groove portion 32b.

[0214] Next, in each photoelectric conversion region 22, as Figure 57 As shown, an n-type floating diffusion region FD, a gate electrode 43, and a p-type power contact region 45 are formed in the surface layer portion on the first face S1 side of the semiconductor layer 21, and a pixel transistor Q is also formed thereal, although not shown. Each of the n-type floating diffusion region FD, the gate electrode 43, the p-type power contact region 45, and the pixel transistor Q is formed in the same manner as in the first embodiment described above.

[0215] In this step, a vertical transmission transistor TR is formed having a trench portion 41, a gate insulating film 42, a gate electrode 43, an n-type semiconductor region 24 and an n-type floating diffusion region FD that serve as source and drain regions respectively, and an n-type well region 23 that serves as a channel formation region. Furthermore, in this step, a photoelectric conversion region 22 is formed, comprising a p-type well region 23, an n-type semiconductor region 24, a photoelectric conversion section 25, a p-type semiconductor region 33, a p-type power contact region 45, a floating diffusion region FD, and a transmission transistor RT.

[0216] Furthermore, in this step, by selectively implanting impurity ions and then performing heat treatment to activate the implanted impurity ions, an n-type floating diffusion region FD and a p-type power contact region 45 are formed. Therefore, even during this heat treatment, the p-type semiconductor region 33 attempts to expand. However, since the first vertical portion is provided on the first face side of the semiconductor layer and protrudes further toward the photoelectric conversion region 22 than the second vertical portion, and overlaps with the p-type semiconductor region 33 in the plan view, the expansion of the p-type semiconductor region 33 toward the n-type floating diffusion region FD side can be suppressed.

[0217] Next, a multilayer wiring layer is formed on the first face S1 side of the semiconductor layer 21, and then, as follows Figure 58 As shown, a thinning step is performed by thinning the second face S2 of the semiconductor layer 21 to the thinning line S2a by cutting, for example, using a CMP method. In this step, a partition region 31 is formed that extends from the first face S1 side of the semiconductor layer 21 along the thickness direction (Z direction) of the semiconductor layer 21 and reaches the second face S2 of the semiconductor layer 21, and a photoelectric conversion region 22 divided by the partition region 31 is also formed.

[0218] Then, by sequentially forming a planarization film 51, a color filter 53, and a microlens 54 on the second face S2 side of the semiconductor layer 21, a solution is obtained. Figures 46 to 48 The state shown.

[0219] <<Main Effects of the Sixth Implementation Plan>> Next, the main effects of the sixth implementation plan will be explained. like Figure 47 As shown, the partition region 31 of the solid-state imaging device 1F according to the sixth embodiment includes a first longitudinal portion 31z1 and a second longitudinal portion 31z2. Furthermore, the first longitudinal portion 31z1 protrudes further toward the photoelectric conversion region 22 than the second longitudinal portion 31z2, and has an inclined portion 61. Additionally, the partition region 31 includes a groove portion 32, and the first longitudinal portion 31z1 includes a first groove portion 31a.

[0220] Therefore, during the manufacturing process, the expansion of the p-type semiconductor region 33 in the thickness direction (Z direction) of the semiconductor layer 21 due to impurity diffusion caused by heat treatment can be suppressed, thereby suppressing the separation distance Sd2 between the n-type floating diffusion region FD and the p-type semiconductor region 33 (refer to...). Figure 25 The interference between the n-type floating diffusion region FD and the p-type semiconductor region 33 can be suppressed, thereby suppressing the increase of parasitic capacitance added to the charge transport path R1 that transfers the photoelectric converted signal charge in the n-type semiconductor region 24 from the n-type semiconductor region 24 to the n-type floating diffusion region FD, and suppressing the degradation of the signal charge transport characteristics.

[0221] Therefore, in the solid-state imaging device 1F of the sixth embodiment, the charge transfer characteristics for transferring signal charge from the n-type semiconductor region 24 included in the photoelectric conversion unit 25 to the n-type floating diffusion region FD can be improved.

[0222] Furthermore, the pn junction between the p-type semiconductor region 33 and the n-type semiconductor region 24 is physically separated from the charge transport path R1 by the extension portion 31z3. Therefore, the saturation charge can be increased. This enables the achievement of both excellent charge transport characteristics and a high saturation charge.

[0223] Furthermore, improvements in the charge transfer characteristics of the signal charge can reduce pixel size, enabling the provision of solid-state imaging devices 1F with higher image quality.

[0224] Furthermore, since the first vertical portion 31z1 in this sixth embodiment has an inclined portion 61, the reduction in the volume of the n-type floating diffusion region FD can be suppressed compared to simply extending the first vertical portion 31z1 towards the photoelectric conversion region 22. Therefore, in the solid-state imaging device 1F of this sixth embodiment, charge transport characteristics can be improved while suppressing the reduction in the volume of the n-type floating diffusion region FD. Since the volume of the n-type floating diffusion region FD affects the charge retention capability, suppressing the reduction in the volume of the n-type floating diffusion region FD is also useful from the perspective of improving image quality.

[0225] Furthermore, since the first longitudinal portion 31z1 of the sixth embodiment has a cavity 63, the light-shielding performance of the first longitudinal portion 31z1 of the partition region 31 can be improved in the same manner as in the above-described modifications 1-3.

[0226] <<Variations on the Sixth Implementation Plan>> <Variation Example 6-1> In the sixth embodiment described above, a manufacturing method for forming a p-type semiconductor region 33 after forming a first trench portion 32a with an inclined portion 61 has been described. However, the present technology is not limited to the manufacturing method of the sixth embodiment described above. For example, such as Figure 59 As shown, the p-type semiconductor region 33 can be formed before the first trench portion 32a, and then as... Figure 60 The first trench portion 32a is formed as shown. In this case, the longitudinal (Z direction) expansion of the p-type semiconductor region 33 due to heat treatment after the formation of the p-type semiconductor region 33 can be suppressed.

[0227] <Other variations> In the sixth embodiment described above, it has been explained that the first longitudinal portion 31z1 with the inclined portion 61 is arranged along the second longitudinal portion 31z2 that surrounds the partition region 31 of the photoelectric conversion region 22 in the plan view. However, the present technology is not limited to the first longitudinal portion 31z1 of the sixth embodiment described above.

[0228] For example, although not shown, but referring to the above variation 5-1 Figure 44The first longitudinal portion 31z1 with the inclined portion 61 can be selectively disposed at the intersection 31xy of the partition region 31 adjacent to the n-type floating diffusion region FD in the plan view.

[0229] Furthermore, the sixth implementation plan mentioned above can also be combined with the first implementation plan mentioned above. Furthermore, the sixth embodiment described above can also be combined with any of the above variations 1-1, 1-2 and 1-3.

[0230] Furthermore, the dividing region 31 of the sixth embodiment can also be applied to each of the second and third embodiments described above.

[0231] [Seventh Implementation Plan] <<Examples of Electronic Device Applications>> For example, this technology (based on the technology disclosed herein) can be applied to various types of electronic devices, such as camera devices including digital cameras and digital video cameras, mobile phones with camera functions, or other devices with camera functions.

[0232] Figure 61 This is a diagram illustrating a schematic construction of an electronic device (e.g., a camera) according to a seventh embodiment of the present technology.

[0233] like Figure 61 As shown, the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. This electronic device 100 illustrates an embodiment of the solid-state imaging device 1A according to a first embodiment of the present technology, used as a solid-state imaging device 101 in an electronic device (e.g., a camera).

[0234] Optical lens 102 forms image light (incident light 106) from the subject onto the imaging surface of solid-state imaging device 101. Therefore, signal charge accumulates in solid-state imaging device 101 for a period of time. Shutter device 103 controls the illumination period and shading period of solid-state imaging device 101. Drive circuit 104 supplies drive signals to control the transmission operation of solid-state imaging device 101 and the shutter operation of shutter device 103. The charge accumulated in solid-state imaging device 101 is transferred based on the drive signal (timing signal) supplied from drive circuit 104. Signal processing circuit 105 performs various types of signal processing on the signal (pixel signal (image signal)) output from solid-state imaging device 101. The signal-processed video signal is stored in a storage medium such as a memory or output to a monitor.

[0235] This structure improves the charge transfer characteristics of the solid-state imaging device 101, where the signal charge converted by photoelectric conversion is transferred from the photoelectric conversion unit to the floating diffusion region FD. Therefore, the image quality performance of the electronic device 100 according to the third embodiment can be improved.

[0236] Note that the electronic device 100 to which the above-described embodiment of the solid-state imaging device can be applied is not limited to a camera, and the solid-state imaging device can also be applied to other electronic devices. For example, the solid-state imaging device can be applied to imaging devices such as camera modules for mobile devices including mobile phones and tablet computers.

[0237] Furthermore, this technology can be applied not only to solid-state imaging devices used as image sensors, as described above, but also to all types of light detection devices known as Time-of-Flight (ToF) sensors, including range sensors that measure distance. A range sensor is a sensor that emits illumination light towards an object, detects the reflected light returning from the object's surface, and calculates the distance to the object based on the time of flight from emission to reception of the reflected light. Even in such a range sensor, the aforementioned pixel transistor can be employed.

[0238] Note that this technology can also be constructed in the following ways. (1) A light detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; A separating region, comprising a trench extending from the first facet side of the semiconductor layer toward the second facet side; and A photoelectric conversion region is disposed in the semiconductor layer and separated by the separating region. in, The photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type, the first semiconductor region being disposed in the semiconductor layer and spaced apart from the first facet. A second semiconductor region of a second conductivity type is disposed between the separating region and the first semiconductor region. A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the separating region in a plan view, and overlapping with the second semiconductor region in a plan view. A transmission transistor is disposed on the first facet side of the semiconductor layer, overlapping with the first semiconductor region in a plan view, and transmits the photoelectrically converted signal charge in the photoelectric conversion unit to the charge holding unit. The partition region includes a fixed-charge film with a positive fixed charge, and The fixed charge film is positioned at the interface between the semiconductor layer and the separating region at least closer to the second face side than the charge holding portion. (2) According to the photodetector of (1) above, the fixed charge film is configured to straddle the charge holding portion and the second semiconductor region in the thickness direction of the semiconductor layer. (3) According to the photodetector of (1) or (2) above, the fixed charge film is adjacent to each of the charge holding portion and the second semiconductor region. (4) According to any one of (1) to (3) above, the photodetector includes: a first longitudinal portion disposed on the first surface side of the semiconductor layer; and a second longitudinal portion extending from the first longitudinal portion toward the second surface side of the semiconductor layer and having a width narrower than the width of the first longitudinal portion. The fixed charge film is selectively disposed in the first longitudinal section. (5) According to the photodetector of (4) above, the charge holding portion is disposed closer to the first face side of the semiconductor layer than the second longitudinal portion of the partition region. (6) According to any one of (1) to (5) above, the photodetector further comprises: a second conductivity type well region disposed on the first face side of the semiconductor layer; and The impurity concentration in the second semiconductor region of the second conductivity type is higher than the impurity concentration in the well region of the second conductivity type. (7) The light detection device according to any one of (1) to (6) above further includes: a pixel block comprising four photoelectric conversion regions arranged adjacent to each other in a planar view in a first direction and a second direction that intersect each other, separated by the partition region, wherein, The dividing regions have an intersection at the central region of the pixel block in the plan view, and the dividing regions extending in the first direction and the dividing regions extending in the second direction intersect at the intersection. In the plan view, the charge holding portion of each of the four photoelectric conversion regions is disposed around the intersection, and In the plan view, the fixed charge film is selectively disposed at the intersection. (8) According to any one of (1) to (7) above, the fixed charge film is arranged along the partition region in a plan view. (9) According to any one of (1) to (8) above, the optical detection device further includes a film disposed inside the fixed charge film and having a refractive index higher than that of the fixed charge film. (10) According to any one of (1) to (8) above, the optical detection device further includes a cavity disposed inside the fixed charge film. (11) According to any one of (1) to (10) above, the fixed charge film is selectively disposed in the partition region between two adjacent photoelectric conversion regions in a plan view. (12) According to any one of (1) to (11) above, the photodetector is wherein the fixed charge film is one of silicon nitride film and silicon carbonitride film. (13) A light detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; A separating region, comprising a trench extending from the first facet side of the semiconductor layer toward the second facet side; and A photoelectric conversion region is disposed in the semiconductor layer and separated by the separating region. in, The photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type, the first semiconductor region being disposed in the semiconductor layer and spaced apart from the first face; A second semiconductor region of a second conductivity type is disposed between the separating region and the first semiconductor region; A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the separating region in a plan view, and overlapping with the second semiconductor region in a plan view; and A transmission transistor is disposed on the first facet side of the semiconductor layer, overlapping with the first semiconductor region in a plan view, and transmits the photoelectrically converted signal charge in the photoelectric conversion unit to the charge holding unit. The separating region includes an extension that protrudes further toward the photoelectric conversion region than one end and the other end of the separating region located on the opposite side in the thickness direction of the semiconductor layer, and the extension overlaps with the charge holding portion in a plan view. The extension portion is spaced apart from the charge holding portion and is adjacent to the first semiconductor region between the charge holding portion and the second semiconductor region. (14) According to the light detection device of (13) above, the extension reaches the first semiconductor region. (15) According to the light detection device of (13) or (14) above, in the thickness direction of the semiconductor layer, the extension portion is further away from the first face of the semiconductor layer than the first semiconductor region. (16) According to any one of (13) to (15) above, the optical detection device further includes: A first vertical portion, located on the first surface side of the semiconductor layer, and adjacent to the charge-retaining portion in a plan view, and The second vertical portion is located on the second surface side of the semiconductor layer and is adjacent to the second semiconductor region in the plan view. The extension is located between the first longitudinal section and the second longitudinal section, and is connected to each of the first longitudinal section and the second longitudinal section. (17) According to any one of (13) to (16) above, the optical detection device, wherein the trench portion includes: The first groove portion is included within the first longitudinal portion. An extended groove portion, which is included in the extended portion, and The second groove portion is contained within the second longitudinal portion. (18) According to any one of (13) to (17) above, the light detection device is provided along the partition region in the plan view. (19) The light detection device according to any one of (13) to (18) above further includes: a pixel block comprising four photoelectric conversion regions arranged adjacent to each other in a planar view in a first direction and a second direction that intersect each other, separated by the partition region, wherein The charge holding portion of each of the four photoelectric conversion regions is disposed around the intersection of the two separating regions with different extending directions in the plan view, and In the plan view, the extension is selectively disposed at the intersection. (20) According to any one of (13) to (19) above, the optical detection device wherein the extension has an elliptical longitudinal section shape along the thickness direction of the semiconductor layer. (twenty one) According to any one of (13) to (19) above, the optical detection device wherein the semiconductor layer has a 111 crystal plane, and The extension has a rectangular longitudinal section shape along the thickness direction of the semiconductor layer. (twenty two) A light detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; A separating region, comprising a trench extending from the first facet side of the semiconductor layer toward the second facet side; and A photoelectric conversion region is disposed in the semiconductor layer and separated by the separating region. in, The partition region includes: a first longitudinal portion disposed on the first facet side of the semiconductor layer; and The second vertical portion extends from the first vertical portion toward the second facet side of the semiconductor layer, and its width is narrower than that of the first vertical portion. The photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type, the first semiconductor region being disposed in the semiconductor layer and spaced apart from the first face; A second semiconductor region of a second conductivity type is disposed between the second longitudinal portion of the partition region and the first semiconductor region; A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the first longitudinal portion of the partition region in a plan view, and overlapping with the second semiconductor region in a plan view; and A transmission transistor, disposed on the first facet side of the semiconductor layer, overlaps with the first semiconductor region in a plan view, and transmits the photoelectrically converted signal charge in the photoelectric conversion unit to the charge holding unit. The first longitudinal portion has an inclined portion on the charge holding portion side, and the inclined portion forms an acute angle with the first face of the semiconductor layer. (twenty three) According to the light detection device of (22) above, the inclined portion is located at a position closer to the first face side of the semiconductor layer than the first semiconductor region. (twenty four) According to the light detection device of (22) or (23) above, the inclined portion protrudes further toward the photoelectric conversion region than the second longitudinal portion. (25) According to any one of (22) to (24) above, the optical detection device wherein the first longitudinal portion overlaps with the second semiconductor region and is in contact with the first semiconductor region in a plan view. (26) According to any one of (22) to (25) above, the optical detection device has a cavity inside the first longitudinal portion. (27) According to any one of (22) to (26) above, the optical detection device, wherein the trench portion includes: The first groove portion is included within the first longitudinal portion. The second groove portion is contained within the second longitudinal portion. (28) An electronic device includes: Optical detection device; An optical lens that enables image light from the subject to be imaged on the imaging surface of the light detection device; and The signal processing circuit performs signal processing on the signal output from the photodetector. in, The optical detection device includes: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; A separating region, comprising a trench extending from the first facet side of the semiconductor layer toward the second facet side; and A photoelectric conversion region is disposed in the semiconductor layer and separated by the separating region. in, The photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type, the first semiconductor region being disposed in the semiconductor layer and spaced apart from the first facet. A second semiconductor region of a second conductivity type is disposed between the separating region and the first semiconductor region. A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the separating region in a plan view, and overlapping with the second semiconductor region in a plan view. A transmission transistor is disposed on the first facet side of the semiconductor layer, overlapping with the first semiconductor region in a plan view, and transmits the photoelectrically converted signal charge in the photoelectric conversion unit to the charge holding unit. The partition region includes a fixed-charge film with a positive fixed charge, and The fixed charge film is positioned at the interface between the semiconductor layer and the separating region at least closer to the second face side than the charge holding portion.

[0239] The scope of this technology is not limited to the exemplary embodiments shown and described, but also includes all embodiments that provide equivalent effects to the intended results of this technology. Furthermore, the scope of this technology is not limited to the combination of features of the invention as defined in the claims, but may also be defined by any desired combination of specific features from all disclosed features. [List of reference numerals]

[0240] 1A Solid-State Camera 2 Semiconductor chips 2A pixel array section 2B Peripheral Department 3 pixels 4 Vertical drive circuit 5-column signal processing circuits 6. Horizontal drive circuit 7 Output Circuit 8. Control Circuit 10-pixel drive line 11 Vertical signal line 12 Horizontal Signal Lines 13 Logic Circuits 14. Bonding pads 15-pixel block 16-pixel circuit 17. Trench Formation Area 21 Semiconductor layer 22 Photoelectric conversion region 22L First Photoelectric Conversion Unit 22R Second Photoelectric Conversion Unit 23 p-type trap region 24 n-type semiconductor region 25. Photoelectric conversion unit 31, 31B Separated Areas 31x First Plane Part 31y Second Plane 31xy intersection (intersection point) 31z1 First longitudinal section 31z2 Second longitudinal section 31zs Step section 32. Groove section 32a First Groove Section 32b Second Groove Section 32xy intersection 32Z Trench Formation Area 33 p-type semiconductor region (pinning layer) 34. Separating Insulating Film 35 Conductive Materials 36. Separating Insulating Film 36a Opening 37. Fixed-charge film with negative charge 38 Low Refractive Index Film 39. Cavity 41. Groove section 42 Gate insulating film 43 Gate electrode 43a Head 43b Legs 45 p-type power contact area 51 Planarization film 53 Color Filters 54 microlenses 56 Internal partition areas 61 Inclined section 62. Separating Insulation Film 63 Cavity 65 Shallow groove section M1 Etching Mask M1a Opening M2b mask section R1 charge transport path θ1 Acute angle

Claims

1. A light detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; The partition region includes a trench extending from the first face side of the semiconductor layer toward the second face side; and A photoelectric conversion region is disposed in the semiconductor layer and separated by the separating region. in, The photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type, the first semiconductor region being disposed in the semiconductor layer and spaced apart from the first facet. A second semiconductor region of a second conductivity type is disposed between the separating region and the first semiconductor region. A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the separating region in a plan view, and overlapping with the second semiconductor region in a plan view. A transmission transistor is disposed on the first facet side of the semiconductor layer, overlapping with the first semiconductor region in a plan view, and transmits the photoelectrically converted signal charge in the photoelectric conversion unit to the charge holding unit. The partition region includes a fixed-charge film with a positive fixed charge, and The fixed charge film is positioned at the interface between the semiconductor layer and the separating region at least closer to the second face side than the charge holding portion.

2. The optical detection device according to claim 1, wherein, The fixed charge film is configured to straddle the charge holding portion and the second semiconductor region in the thickness direction of the semiconductor layer.

3. The optical detection device according to claim 1, wherein, The fixed charge film is adjacent to both the charge holding portion and the second semiconductor region.

4. The optical detection device according to claim 1, wherein, The partition region includes: a first longitudinal portion disposed on the first face side of the semiconductor layer; and a second longitudinal portion extending from the first longitudinal portion toward the second face side of the semiconductor layer and having a width narrower than the width of the first longitudinal portion. The fixed charge film is selectively disposed in the first longitudinal section.

5. The optical detection device according to claim 4, wherein, The charge-retaining portion is positioned closer to the first face side of the semiconductor layer than the second longitudinal portion of the separating region.

6. The optical detection device according to claim 1, wherein, The photoelectric conversion region further includes: a well region of a second conductivity type, which is disposed on the first face side of the semiconductor layer; and The impurity concentration in the second semiconductor region of the second conductivity type is higher than the impurity concentration in the well region of the second conductivity type.

7. The optical detection device according to claim 1, further comprising: A pixel block comprises four photoelectric conversion regions arranged adjacent to each other across the separating regions in a first and second intersecting direction in a planar view. The dividing regions have an intersection at the central region of the pixel block in the plan view, and the dividing regions extending in the first direction and the dividing regions extending in the second direction intersect at the intersection. In the plan view, the charge holding portion of each of the four photoelectric conversion regions is disposed around the intersection, and In the plan view, the fixed charge film is selectively disposed at the intersection.

8. The optical detection device according to claim 1, wherein, The fixed charge film is arranged along the dividing region in the plan view.

9. The optical detection device according to claim 1, wherein, The separating region also includes a film disposed inside the fixed charge film and having a higher refractive index than the fixed charge film.

10. The optical detection device according to claim 1, wherein, The partition region also includes a cavity disposed inside the fixed charge film.

11. The optical detection device according to claim 1, wherein, The fixed charge film is selectively disposed in the separating region between two adjacent photoelectric conversion regions in the plan view.

12. The optical detection device according to claim 1, wherein, The fixed charge film is one of silicon nitride film and silicon carbonitride film.

13. A light detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; The partition region includes a trench extending from the first face side of the semiconductor layer toward the second face side; and A photoelectric conversion region is disposed in the semiconductor layer and separated by the separating region. in, The photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type, the first semiconductor region being disposed in the semiconductor layer and spaced apart from the first face; A second semiconductor region of a second conductivity type is disposed between the separating region and the first semiconductor region; A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the separating region in a plan view, and overlapping with the second semiconductor region in a plan view; and A transmission transistor is disposed on the first facet side of the semiconductor layer, overlapping with the first semiconductor region in a plan view, and transmits the photoelectrically converted signal charge in the photoelectric conversion unit to the charge holding unit. The separating region includes an extension that protrudes further toward the photoelectric conversion region than one end and the other end of the separating region located on the opposite side in the thickness direction of the semiconductor layer, and the extension overlaps with the charge holding portion in a plan view. The extension portion is spaced apart from the charge holding portion and is adjacent to the first semiconductor region between the charge holding portion and the second semiconductor region.

14. The optical detection device according to claim 13, wherein, The extension reaches the first semiconductor region.

15. The optical detection device according to claim 13, wherein, In the thickness direction of the semiconductor layer, the extension portion is further away from the first face of the semiconductor layer than the first semiconductor region.

16. The optical detection device according to claim 13, wherein, The partitioned region also includes: A first vertical portion, located on the first surface side of the semiconductor layer, and adjacent to the charge-retaining portion in a plan view, and The second vertical portion is located on the second surface side of the semiconductor layer and is adjacent to the second semiconductor region in the plan view. The extension is located between the first longitudinal section and the second longitudinal section, and is connected to each of the first longitudinal section and the second longitudinal section.

17. The photodetector according to claim 16, wherein the trench portion comprises: The first groove portion is included within the first longitudinal portion. An extended groove portion, which is included in the extended portion, and The second groove portion is contained within the second longitudinal portion.

18. The optical detection device according to claim 13, wherein, The extension is arranged along the dividing area in the plan view.

19. The optical detection device according to claim 13, further comprising: A pixel block comprising four photoelectric conversion regions arranged adjacent to each other across the separating regions in a first and second direction intersecting each other in a planar view, wherein... The charge holding portion of each of the four photoelectric conversion regions is disposed around the intersection of the two separating regions with different extending directions in the plan view, and In the plan view, the extension is selectively disposed at the intersection.

20. The optical detection device according to claim 13, wherein, The extension has an elliptical longitudinal cross-sectional shape along the thickness direction of the semiconductor layer.

21. The optical detection device according to claim 13, wherein, The semiconductor layer has 111 crystal planes, and The extension has a rectangular longitudinal section shape along the thickness direction of the semiconductor layer.

22. A light detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; The partition region includes a trench extending from the first face side of the semiconductor layer toward the second face side; and A photoelectric conversion region is disposed in the semiconductor layer and separated by the separating region. in, The partition region includes: a first longitudinal portion disposed on the first facet side of the semiconductor layer; and The second vertical portion extends from the first vertical portion toward the second facet side of the semiconductor layer, and its width is narrower than that of the first vertical portion. The photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type, the first semiconductor region being disposed in the semiconductor layer and spaced apart from the first face; A second semiconductor region of a second conductivity type is disposed between the second longitudinal portion of the partition region and the first semiconductor region; A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the first longitudinal portion of the partition region in a plan view, and overlapping with the second semiconductor region in a plan view; and A transmission transistor, disposed on the first facet side of the semiconductor layer, overlaps with the first semiconductor region in a plan view, and transmits the photoelectrically converted signal charge in the photoelectric conversion unit to the charge holding unit. The first longitudinal portion has an inclined portion on the charge holding portion side, and the inclined portion forms an acute angle with the first face of the semiconductor layer.

23. The optical detection device according to claim 22, wherein, The inclined portion is located at a position closer to the first face side of the semiconductor layer than the first semiconductor region.

24. The optical detection device according to claim 22, wherein, The inclined portion protrudes further toward the photoelectric conversion region than the second longitudinal portion.

25. The optical detection device according to claim 22, wherein, The first vertical portion overlaps with the second semiconductor region and is in contact with the first semiconductor region in the plan view.

26. The optical detection device according to claim 22, wherein, The interior of the first longitudinal section has a cavity.

27. The optical detection device according to claim 22, wherein, The groove portion includes: The first groove portion is included within the first longitudinal portion. The second groove portion is contained within the second longitudinal portion.

28. An electronic device comprising: Optical detection device; An optical lens that enables image light from the subject to be imaged on the imaging surface of the light detection device; and The signal processing circuit performs signal processing on the signal output from the photodetector. in, The optical detection device includes: A semiconductor layer having a first facet and a second facet located on opposite sides in the thickness direction; A separating region, comprising a trench extending from the first facet side of the semiconductor layer toward the second facet side; and A photoelectric conversion region is disposed in the semiconductor layer and separated by the separating region. in, The photoelectric conversion region has: A photoelectric conversion unit includes a first semiconductor region of a first conductivity type, the first semiconductor region being disposed in the semiconductor layer and spaced apart from the first facet. A second semiconductor region of a second conductivity type is disposed between the separating region and the first semiconductor region. A charge-retaining portion of a first conductivity type is disposed on the first surface side of the semiconductor layer, adjacent to the separating region in a plan view, and overlapping with the second semiconductor region in a plan view. A transmission transistor is disposed on the first facet side of the semiconductor layer, overlapping with the first semiconductor region in a plan view, and transmits the photoelectrically converted signal charge in the photoelectric conversion unit to the charge holding unit. The partition region includes a fixed-charge film with a positive fixed charge, and The fixed charge film is positioned at the interface between the semiconductor layer and the separating region at least closer to the second face side than the charge holding portion.

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