Pattern generation method for reticle version marking

Abstract

The disclosure provides a version mark pattern generation method of a mask plate, comprising: obtaining a width of a version mark area, and obtaining a total length of the version mark area according to a process type and a number of layers of the mask plate; forming one or more rectangular frames with corresponding sizes in the version mark area of a corresponding layer respectively; forming a product code pattern at a corresponding position of the version mark area in a preset layer; and forming a layer coding pattern of the layer and a version information pattern in the version mark area at a corresponding position in the layer respectively, wherein the rectangular frame, the product code pattern, the layer coding pattern and the version information pattern are used to constitute the version mark of the mask plate. The pattern generation method can be compatible with multiple requirements, and can improve the drawing accuracy and efficiency of the version mark pattern.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for generating a pattern of version marks for a photomask. Background Technology

[0002] In semiconductor manufacturing, the photomask is a key tool for pattern transfer, and the version mark (VCMark), as an important component of the photomask, performs several key functions. The VCMark is mainly used to identify the version information of the photomask and ensure the accuracy and traceability of the photomask during the production process.

[0003] As semiconductor technology continues to advance and semiconductor manufacturing processes become increasingly complex, the demand for VC Marks is also constantly increasing and changing. For example, different process nodes, different types of photoresists (positive photoresist, negative photoresist), and different graphic design requirements (such as mirroring) all require flexible responses.

[0004] However, currently, the creation of VC Marks mainly relies on manual operation. First, the product manager proposes the design requirements for VC Marks based on specific needs; second, the layout team manually draws the VC Mark Layout diagram in accordance with layout rules; finally, the final mask template is made based on the manually drawn VC Mark Layout diagram.

[0005] Although manually drawing VC Marks can meet current needs to some extent, it has many problems such as being cumbersome, inefficient, error-prone, repetitive, and costly. Specifically, manual drawing requires multiple steps, each of which requires precise operation, increasing the complexity of the work.

[0006] Manual drawing is time-consuming; a typical 10-layer VC Mark requires an average of 60 minutes of manual time. Manual operation is prone to human error, leading to inaccurate VC Marks, which in turn affects product quality and production efficiency. Many steps in the drawing process are repetitive, increasing the workload of operators. Manual drawing requires significant human resources and relies on EDA (Electronic Design Automation) software licenses, increasing production costs.

[0007] With the continuous advancement of semiconductor manufacturing technology, the demands for VC Marks from different products have become increasingly diverse. For example, different process nodes, different types of photoresist, and varying graphic design requirements all necessitate flexible solutions. Existing manual drawing methods are insufficient to efficiently and accurately meet these diverse needs; therefore, a more efficient, automated, and flexible VC Mark generation method is urgently required. Summary of the Invention

[0008] In view of the above problems, there is a need to propose a new method for generating patterns of version marks for mask templates, as well as its system and medium.

[0009] According to a first aspect of this disclosure, a method for generating a pattern of version markers for a mask template is provided, comprising:

[0010] Obtain the width of the version mark area, and obtain the total length of the version mark area according to the process type and the number of mask layers;

[0011] Create one or more rectangles of appropriate size in the version mark area of ​​the corresponding layer;

[0012] A product code pattern is formed at the corresponding position in the version mark area of ​​the preset layer; and

[0013] The layer encoding pattern and version information pattern of each layer are respectively formed in the corresponding positions of the version mark area.

[0014] The rectangle, the product code pattern, the layer encoding pattern, and the version information pattern are used to form the version mark of the mask template.

[0015] Optionally, obtaining the total length of the version mark area based on the process type and the number of layers in the mask includes: obtaining a first parameter, a second parameter, and a third parameter, wherein the first parameter is the number of layers in the mask plus 1, the second parameter is the maximum value of the short side of the rectangle in each layer, and the third parameter is a preset fixed value.

[0016] When the process type is a 90-nanometer process node, the total length of the version marker region is the sum of the product of the first parameter, the second parameter, and the third parameter.

[0017] When the process type is a non-90nm process node process, the total length of the version marking region is the product of the first parameter and the second parameter.

[0018] Optionally, the preset layer includes a 1F layer, a metal layer, and a gate layer.

[0019] Optionally, forming the layer code pattern and version information pattern of the layer in the corresponding positions of the version marking area in different layers includes forming the layer code pattern and the version information pattern in the same position of the version marking area in layers with the same attributes.

[0020] Optionally, the layer encoding pattern and the version information pattern are either mirror images or non-mirror images.

[0021] Optionally, forming one or more rectangles of corresponding sizes in the version mark area of ​​the corresponding layer includes:

[0022] In the base layer, multiple rectangular frames of reference dimensions are arranged to fill the entire version mark area of ​​the base layer.

[0023] Optionally, when the layers of the mask template are superimposed, the product code pattern, the layer encoding pattern, and the version information pattern are distributed within the corresponding rectangular frames in the version mark area of ​​the base layer.

[0024] Optionally, when the various layers of the mask are superimposed, the product code pattern is evenly distributed within the rectangular frame located at the end of the version mark area in the base layer.

[0025] Optionally, forming one or more rectangles of corresponding sizes in the version mark area of ​​the corresponding layer further includes:

[0026] Determine whether each layer of the photomask, excluding the base layer, is for positive photoresist lithography dark-field imaging or negative photoresist lithography clear imaging. If the determination result is no, then it is not necessary to form a rectangular box within the version marking area of ​​that layer; and

[0027] If the determination result is yes, then a rectangle of the corresponding size will be formed in the version mark area of ​​the corresponding layer.

[0028] Optionally, if the determination result is yes, then a rectangle of the corresponding size is formed in the version mark area of ​​the corresponding layer, and:

[0029] If the corresponding layer is layer 1F, then, apart from the areas corresponding to the layer coding patterns, version information patterns, and product code patterns of layers 5F and 1F, multiple rectangles of the first size are arranged in the remaining version marking areas of that layer; and / or

[0030] If the corresponding layer is layer 2F, and a rectangle has already been set in layer 1F, then, in addition to the areas corresponding to the layer code patterns, version information patterns, and product code patterns of layers 5F, 1F, and 2F, multiple rectangles of the second size are arranged in the remaining version marking areas of this layer; and / or

[0031] If the corresponding layer is the gate layer, then, in addition to the areas corresponding to the layer coding patterns, version information patterns, and product code patterns of the 5F, 1F, and gate layers, multiple rectangles of the third size are arranged in the remaining version marking areas of this layer; and / or

[0032] If the corresponding layer is a metal layer, then, in addition to the areas corresponding to the layer code pattern, version information pattern, and product code pattern of the metal layer, multiple rectangles of the fourth size are arranged in the remaining version marking areas of the layer; and / or

[0033] If the corresponding layer is layer K, then, apart from the areas corresponding to the layer code pattern, version information pattern, and product code pattern of layer K, multiple rectangles of the fifth size are arranged in the remaining version marking areas of that layer; and / or

[0034] If the corresponding layers are BP and TP layers, then in the version mark area of ​​the BP layer, set a rectangle of the sixth size corresponding to the position of the layer code pattern and version information pattern of the TP and NK layers, respectively; and in the version mark area of ​​the TP layer, set a rectangle of the seventh size corresponding to the position of the layer code pattern and version information pattern of the NK layer, respectively. The BP, TP, and NK layers are overlay layers; and / or

[0035] If the corresponding layer is a layer other than 1F, 2F, gate, metal, K, and overlay layers, then multiple rectangles of the eighth size are arranged in the version mark area of ​​that layer, excluding the positions of its own layer encoding pattern and version information pattern.

[0036] Wherein, none of the first to the eighth size specifications are larger than the reference size specification.

[0037] According to a second aspect of this disclosure, a pattern generation system for version marks of a mask template is provided for obtaining a pattern of version marks of a mask template according to the method described above.

[0038] According to a third aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0039] One of the above technical solutions has the following unexpected technical effect:

[0040] This invention provides a method for generating patterns of version markers for a mask template. This method significantly improves the drawing efficiency and accuracy of VC Mark through automated steps. Specific technical effects are as follows:

[0041] Improved drawing efficiency: By automatically calculating the total length of the version mark area and automatically generating rectangles, product code patterns, layer code patterns, and version information patterns, the complexity and time-consuming nature of manual drawing are reduced. Compared to traditional manual drawing methods, this method can reduce drawing time from an average of 60 minutes to just a few seconds, significantly improving work efficiency.

[0042] Reduced error rate: Automated methods reduce human error, ensuring the accuracy and consistency of VC Marks. This helps improve product quality and production efficiency, reducing production delays and cost increases caused by VC Mark errors.

[0043] Adapting to diverse needs: This method can flexibly adjust the total length and pattern of version markers according to different process types and the number of layers, meeting the needs of different products and process nodes. For example, for 90nm process nodes and non-90nm process nodes, this method can calculate the total length separately and adjust the size of the product code pattern to adapt to different process requirements.

[0044] Cost reduction: Automation reduces reliance on human resources and EDA software licenses, thus lowering production costs. Furthermore, by reducing errors and increasing efficiency, this approach also helps reduce additional costs incurred due to errors.

[0045] Improved readability and traceability of patterns: By creating layer-coded patterns and version information patterns in different layers, this method improves the readability and traceability of VC Marks. This facilitates the rapid identification and traceability of mask version and layer information during production, ensuring the accuracy and traceability of the production process.

[0046] Optimized pattern layout: This method optimizes the pattern layout by evenly distributing rectangles and patterns within the version marker area. This helps improve pattern clarity and readability, reducing recognition difficulties caused by pattern overlap or crowding.

[0047] In summary, the method of the present invention significantly improves the drawing efficiency, accuracy and adaptability of mask version markers through automated and flexible pattern acquisition, reduces production costs, optimizes pattern layout, and has important industrial application value.

[0048] It should be noted that the above general description and the following detailed description are exemplary and explanatory only and do not limit this disclosure. Attached Figure Description

[0049] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0050] Figure 1 A flowchart illustrating the steps of the method for generating a pattern of version markers for a mask template in an embodiment of this disclosure is shown.

[0051] Figure 2 This diagram illustrates the location of the version marker area in an embodiment of the mask template.

[0052] Figure 3 This illustration shows a partial region diagram of the version mark after multiple layers of the mask template are superimposed in an embodiment of this disclosure;

[0053] Figure 4 This illustration shows a schematic diagram of the rectangular arrangement of version markers on the base layer of the mask template in an embodiment of this disclosure;

[0054] Figure 5 This illustration shows a first-size schematic diagram of the product code pattern of the version mark of the mask template in an embodiment of this disclosure;

[0055] Figure 6 This illustration shows a second-size schematic diagram of the product code pattern of the version mark of the mask template in an embodiment of this disclosure;

[0056] Figure 7 This illustration shows a schematic diagram of the layer coding pattern and version information pattern dimensions of the mask template in an embodiment of this disclosure;

[0057] Figure 8 This illustration shows a schematic diagram of the rectangular arrangement of version markers on the 1F layer of the mask template in an embodiment of this disclosure;

[0058] Figure 9 This illustration shows a schematic diagram of the rectangular arrangement of version markers for the mask template gate layer in an embodiment of this disclosure;

[0059] Figure 10 This illustration shows a schematic diagram of the rectangular arrangement of version markers for the metal layer of the mask template in an embodiment of this disclosure;

[0060] Figure 11 This illustration shows a schematic diagram of the rectangular arrangement of version markers for the K layer of the mask template in an embodiment of this disclosure;

[0061] Figure 12 This illustration shows a schematic diagram of the rectangular frame arrangement after the version marks of the TP layer, BP layer and NK layer of the mask template are superimposed in an embodiment of this disclosure;

[0062] Figure 13 A schematic diagram showing the rectangular arrangement of version marks for other layers of the mask template in an embodiment of this disclosure is shown. Detailed Implementation

[0063] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0064] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.

[0065] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0066] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0067] This application may be presented in various forms, some of which will be described below.

[0068] See Figure 1 The method for generating a pattern of version markers for a mask template according to embodiments of this disclosure includes:

[0069] In step S01, the width of the version mark area is obtained, and the total length of the version mark area is obtained according to the process type and the number of mask layers;

[0070] In step S02, one or more rectangles of corresponding sizes are formed in the version mark area of ​​the corresponding layer;

[0071] In step S03, a product code pattern is formed at the corresponding position in the version mark area of ​​the preset layer;

[0072] In step S04, the layer encoding pattern and version information pattern of the layer are formed in the corresponding positions of the version mark area in different layers.

[0073] Among them, the rectangle, product code pattern, layer encoding pattern, and version information pattern are used to form the version mark of the mask template.

[0074] The following will combine Figures 2 to 13 The steps of the method for generating a pattern of version mark of a mask template according to embodiments of the present disclosure will be described in detail.

[0075] See Figure 2 Version marking areas 10 are provided on the edges or other locations of the photomask 100. In actual production, a product requires multiple photomasks 100, each corresponding to a different photomask layer, and the version marking area 10 of each photomask 100 has the same position and size. In this embodiment, the width D of the marking area 10 is a given 40nm.

[0076] The total length L of the version marking region 10 is obtained based on the process type and the number of layers N of the mask 100, including: obtaining the first parameter, the second parameter and the third parameter, wherein the first parameter is N+1, the second parameter can be set to 14nm, and the third parameter is a preset fixed value, such as the third parameter can be set to 22nm.

[0077] In the case of a 90-nanometer process node, the total length L of the version marking region 10 is the product of the first parameter, the second parameter, and the third parameter, that is, the total length L is (N+1)·14+22, in nm.

[0078] When the process type is a normal process or a process type other than the 90nm process node, the total length L of the version marker region 10 is the product of the first parameter and the second parameter, that is, the total length L is (N+1)·14, in nm.

[0079] See Figure 3 , Figures 8 to 13After multiple layers of the mask are superimposed, the rectangular blocks, product code patterns (logos), layer encoding patterns, and version information patterns of each layer are displayed in the version marking area 10. In this embodiment, the rectangular blocks have multiple size specifications, namely, a base size specification, a first size specification, a second size specification, a third size specification, a fourth size specification, a fifth size specification, a sixth size specification, a seventh size specification, and an eighth size specification, wherein the first to eighth size specifications are all no larger than the base size specification. Since the base size specification is the largest size, the short side of the rectangle of the base size specification is the maximum value of the short side of the rectangles in each layer, and this maximum value of the short side corresponds to the second parameter. The long side of the rectangle of the base size specification is the maximum value of the long side of the rectangles in each layer, and this maximum value of the long side corresponds to the width D of this marking area 10. In some optional embodiments, the third size specification is smaller than the eighth size specification (the length and width of the rectangle in the third size specification are both smaller than the length and width of the rectangle in the eighth size specification), the first size specification is smaller than the third size specification, the fifth size specification is smaller than the first size specification, the second size specification is smaller than the fifth size specification, the first size specification is the same as the fourth size specification, the fifth size specification, the sixth size specification, and the seventh size specification are the same, and the eighth size specification is the same as the reference size specification. However, the embodiments disclosed herein are not limited to this, and those skilled in the art can make other settings for the size of the rectangle as needed.

[0080] In this embodiment, the product code pattern consists of letter and number patterns, or only letter patterns, for example... Figure 3 The rightmost letter "GMSVV" indicates which product it corresponds to. The product code symbol can also be "GER8D" or "GGNSO", etc., which can be set as needed by those skilled in the art.

[0081] The layer coding pattern consists of letter and number patterns, or only letter patterns, for example... Figure 3 The first two patterns within the rectangles other than the rightmost one include “5F”, “2F”, “1F”, “2I”, “4I”, “5I”, “3D”, “4D”, “5D”, “2N”, “5N”, “2P”, “3E”, “1G”, “TM”, “2K”, “NK”, “BP”, “TP”, etc. These layer code patterns are also called “mask code names”. For example, layer “1F” can represent the active area. Those skilled in the art can find clear definitions in MPD (Mask Preparation Data) files, which will not be elaborated here.

[0082] The version information pattern consists of letter patterns, for example Figure 3The last pattern in each of the rectangles except the rightmost one is the version information pattern 1FA, specifically, the A in the third rectangle from the right. For example, A represents the first version, B represents the second version, and so on.

[0083] In some preferred embodiments, layer encoding patterns and version information patterns in layers with the same attributes can be formed in the same position in the version marking area 10. For example... Figure 3 Within the fourth rectangle from the right, "2IA", "4IA", and "5IA" are superimposed, thus saving the total length of the version marking area 10. Optionally, when the layer coding pattern ends with "A", "N", "P", "I", "D", "K", "S", "J", "Z", or "Q", these layer coding patterns and the corresponding version information patterns can be formed in the same position in the version marking area 10. Optionally, the layer coding pattern and the version information pattern can be either mirror images or both non-mirror images.

[0084] See Figure 2 and Figure 4 The process of forming one or more rectangles of corresponding sizes in the version mark area of ​​the corresponding layer includes: in the base layer, filling and arranging multiple rectangles of the reference size specifications throughout the entire version mark area 10 of the layer. The base layer includes (221,0), (200,0), and (199,0). Those skilled in the art can find clear definitions for (221,0), (200,0), and (199,0) in the MPD file; for example, (221,0) is a Cell Block Layer, and (200,0) is a secondary exposure layer, etc., which will not be elaborated further here.

[0085] See Figure 3 , Figure 5 and Figure 6 When the layers of the mask 100 are superimposed, the product code pattern is evenly distributed within the rectangular frame located at the ends of the version mark area 10 in the base layer, such as the right or left end. The preset layers that need to form the product code pattern include the 1F layer, the metal layer, and the gate layer. The metal layer corresponds to the TM layer mentioned above, and the gate layer corresponds to the 1G layer mentioned above.

[0086] Compared to non-90nm process nodes, the font size of the letters and numbers in the product code pattern is larger when the process node is 90nm.

[0087] See Figure 3 and Figure 7When the various layers of the mask template 100 are superimposed, the product code pattern, layer encoding pattern and version information pattern are evenly distributed in the corresponding rectangular boxes in the version mark area 10 of the base layer, and there is a preset spacing between adjacent patterns.

[0088] However, the embodiments disclosed herein are not limited thereto, and those skilled in the art can make other settings for the size of the product code pattern, layer encoding pattern and version information pattern of the mask template as needed.

[0089] Based on semiconductor manufacturing processes, photoresist lithography can be categorized into four main types: positive photoresist clear imaging (positive photoresist - clearTone), positive photoresist dark imaging (positive photoresist - darkTone), negative photoresist clear imaging (negative photoresist - clearTone), and negative photoresist dark imaging (negative photoresist - darkTone). When the layer is for positive photoresist dark imaging or negative photoresist clear imaging, a rectangular frame needs to be set. The rectangular frame setting is further divided into 1F layer, 2F layer, gate layer, K layer, metal layer, special overlay layer, and other layers.

[0090] See Figure 2 , Figures 8 to 13 In addition to forming one or more rectangles of appropriate size in the version mark area of ​​the corresponding layer, the following also applies:

[0091] Determine whether each layer of the photomask, excluding the base layer, is for positive photoresist lithography dark-field imaging or negative photoresist lithography clear imaging. If the determination result is no, then it is not necessary to form a rectangular box within the version marker area 10 of that layer; and

[0092] If the judgment result is yes, then a rectangle of the corresponding size will be formed in the version mark area 10 of the corresponding layer.

[0093] Furthermore, if the judgment result is yes, a rectangle of the corresponding size is formed in the version mark area 10 of the corresponding layer, and:

[0094] If the corresponding layer is layer 1F, then, apart from the areas corresponding to the layer coding patterns, version information patterns, and product code patterns of layers 5F and 1F, multiple rectangles of the first size are arranged in the remaining version marking areas 10 of layer 1F, such as... Figure 8 As shown.

[0095] If the corresponding layer is layer 2F, and a rectangle has been set in layer 1F, then in addition to the areas corresponding to the layer code pattern, version information pattern and product code pattern of layers 5F, 1F and 2F, multiple rectangles of the second size are arranged in the remaining version marking areas of layer 2F.

[0096] If the corresponding layer is the gate layer, then, apart from the areas corresponding to the layer coding patterns, version information patterns, and product code patterns of the 5F, 1F, and gate layers, multiple rectangles of the third size are arranged in the remaining version marking areas 10 of the gate layer, such as... Figure 9 As shown.

[0097] If the corresponding layer is a metal layer, then, apart from the areas corresponding to the layer code pattern, version information pattern, and product code pattern of the metal layer, multiple rectangles of the fourth size are arranged in the remaining version mark areas 10 of the metal layer, such as... Figure 10 As shown.

[0098] If the corresponding layer is layer K, then, apart from the areas corresponding to the layer code pattern, version information pattern, and product code pattern of layer K, multiple rectangles of the fifth size are arranged in the remaining version marking areas 10 of layer K, such as... Figure 11 As shown.

[0099] If the corresponding layer is a BP layer or a TP layer, then in the version marking area 10 of the BP layer, a rectangle of the sixth size corresponding to the position of the layer code pattern and version information pattern of the TP layer and NK layer, respectively, is set. Similarly, in the version marking area 10 of the TP layer, a rectangle of the seventh size corresponding to the position of the layer code pattern and version information pattern of the NK layer is set. Figure 12 As shown. Among them, the BP layer, TP layer, and NK layer are overlay layers, and the NK layer itself does not need to have a rectangular frame set.

[0100] If the corresponding layer is a layer other than 1F, 2F, gate, metal, K, and overlay layers, then multiple rectangles of the eighth size are arranged in the version mark area 10 of that layer, excluding the positions of its own layer encoding pattern and version information pattern. Figure 13 As shown.

[0101] The method for generating a pattern of version mark of a mask template according to the embodiments of this disclosure can be implemented on a software platform based on the design of the mask template.

[0102] This disclosure also provides a system for generating a pattern of version marks for a mask template, used to obtain a pattern of version marks for a mask template according to the method described above.

[0103] This disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0104] One of the above technical solutions has the following unexpected technical effect:

[0105] This invention provides a method for generating patterns of version markers for a mask template. This method significantly improves the drawing efficiency and accuracy of VC Mark through automated steps. Specific technical effects are as follows:

[0106] Improved drawing efficiency: By automatically calculating the total length of the version mark area and automatically generating rectangles, product code patterns, layer code patterns, and version information patterns, the complexity and time-consuming nature of manual drawing are reduced. Compared to traditional manual drawing methods, this method can reduce drawing time from an average of 60 minutes to just a few seconds, significantly improving work efficiency.

[0107] Reduced error rate: Automated methods reduce human error, ensuring the accuracy and consistency of VC Marks. This helps improve product quality and production efficiency, reducing production delays and cost increases caused by VC Mark errors.

[0108] Adapting to diverse needs: This method can flexibly adjust the total length and pattern of version markers according to different process types and the number of layers, meeting the needs of different products and process nodes. For example, for 90nm process nodes and non-90nm process nodes, this method can calculate the total length separately and adjust the size of the product code pattern to adapt to different process requirements.

[0109] Cost reduction: Automation reduces reliance on human resources and EDA software licenses, thus lowering production costs. Furthermore, by reducing errors and increasing efficiency, this approach also helps reduce additional costs incurred due to errors.

[0110] Improved readability and traceability of patterns: By creating layer-coded patterns and version information patterns in different layers, this method improves the readability and traceability of VC Marks. This facilitates the rapid identification and traceability of mask version and layer information during production, ensuring the accuracy and traceability of the production process.

[0111] Optimized pattern layout: This method optimizes the pattern layout by evenly distributing rectangles and patterns within the version marker area. This helps improve pattern clarity and readability, reducing recognition difficulties caused by pattern overlap or crowding.

[0112] High compatibility: This method is compatible with a variety of requirements and can meet the product requirements of all current NTO (full mask fabrication) products, such as: mirror drawing, special block overlay, and special logo layout.

[0113] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Furthermore, any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory.

[0114] As described above, these embodiments of the present disclosure do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present disclosure, thereby enabling those skilled in the art to make good use of the present disclosure and modifications based on it. The scope of protection of this disclosure should be determined by the scope defined by the claims and their equivalents.

Claims

1. A method for generating a version mark pattern of a mask, comprising: obtaining a width of a version mark area and a total length of the version mark area according to a process category and a number of layers of the mask; forming one or more rectangular frames of corresponding sizes in the version mark area of a corresponding layer, respectively; forming a product code pattern in a corresponding position of the version mark area in a preset layer; and forming a layer code pattern and a version information pattern of the layer in the corresponding position of the version mark area in different layers, respectively, wherein the rectangular frame, the product code pattern, the layer code pattern and the version information pattern are used to constitute the version mark of the mask, the total length of the version mark area according to the process category and the number of layers of the mask comprises: obtaining a first parameter, a second parameter and a third parameter, the first parameter is the number of layers of the mask plus 1, the second parameter is a maximum value of a short side of the rectangular frame in each layer, and the third parameter is a preset fixed value, in a case where the process category is a 90-nanometer process node, the total length of the version mark area is a sum of a product of the first parameter and the second parameter and the third parameter, in a case where the process category is a non-90-nanometer process node, the total length of the version mark area is a product of the first parameter and the second parameter, the forming of the layer code pattern and the version information pattern of the layer in the corresponding position of the version mark area in different layers, respectively, comprises: forming the layer code pattern and the version information pattern in the same position of the version mark area in layers with the same attribute. the preset layer comprises a 1F layer, a metal layer and a gate layer.

2. The pattern generation method according to claim 1, wherein the layer code pattern and the version information pattern are both mirror patterns or both non-mirror patterns.

3. The pattern generation method according to claim 1, wherein the forming of the one or more rectangular frames of corresponding sizes in the version mark area of the corresponding layer, respectively, comprises:

4. The pattern generation method according to any one of claims 1 to 3, wherein in a base layer, arranging a plurality of rectangular frames of reference size specifications in the version mark area of the base layer. after superimposing each layer of the mask, the product code pattern, the layer code pattern and the version information pattern are distributed in the corresponding rectangular frame in the version mark area in the base layer.

5. The pattern generation method according to claim 4, wherein after superimposing each layer of the mask, the product code pattern is uniformly distributed in the rectangular frame at an end portion in the version mark area in the base layer.

6. The pattern generation method according to claim 5, wherein the forming of the one or more rectangular frames of corresponding sizes in the version mark area of the corresponding layer, respectively, further comprises:

7. The pattern generation method according to claim 4, wherein judging whether each layer of the mask except the base layer is positive photoresist lithography dark field imaging or negative photoresist lithography clear field imaging, if the result of the judgment is no, no rectangular frame needs to be formed in the version mark area of the layer; and if the result of the judgment is yes, a rectangular frame of a corresponding size is formed in the version mark area of the corresponding layer. 8.The method according to claim 7, wherein if the result of the judgment is yes, a rectangular frame of a corresponding size is formed in the version mark area of the corresponding layer, and ​ If the corresponding layer is the 1F layer, a plurality of rectangular frames of a first size are arranged in the remaining version mark area of the layer, except for the area corresponding to the layer coding pattern, version information pattern and product code pattern of the 5F layer and 1F layer; and / or If the corresponding layer is the 2F layer, and rectangular frames have been arranged in the 1F layer, a plurality of rectangular frames of a second size are arranged in the remaining version mark area of the layer, except for the area corresponding to the layer coding pattern, version information pattern and product code pattern of the 5F layer, 1F layer and 2F layer; and / or If the corresponding layer is the gate layer, a plurality of rectangular frames of a third size are arranged in the remaining version mark area of the layer, except for the area corresponding to the layer coding pattern, version information pattern and product code pattern of the 5F layer, 1F layer and gate layer; and / or If the corresponding layer is the metal layer, a plurality of rectangular frames of a fourth size are arranged in the remaining version mark area of the layer, except for the area corresponding to the layer coding pattern, version information pattern and product code pattern of the metal layer; and / or If the corresponding layer is the K layer, a plurality of rectangular frames of a fifth size are arranged in the remaining version mark area of the layer, except for the area corresponding to the layer coding pattern, version information pattern and product code pattern of the K layer; and / or If the corresponding layer is the BP layer and TP layer, a sixth size rectangular frame corresponding to the positions of the layer coding pattern and version information pattern of the TP layer and NK layer is arranged in the version mark area of the BP layer, and a seventh size rectangular frame corresponding to the positions of the layer coding pattern and version information pattern of the NK layer is arranged in the version mark area of the TP layer, the BP layer, TP layer and NK layer being cover layers; and / or If the corresponding layer is other than the 1F layer, 2F layer, gate layer, metal layer, K layer and cover layers, a plurality of eighth size rectangular frames are arranged in the version mark area of the layer, except for the positions of the layer coding pattern and version information pattern of the layer itself, wherein the first size to the eighth size are all not greater than the reference size. ​

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