Metadata bitmap flashing method

Abstract

The application discloses a metadata bitmap flashing method, and relates to the technical field of computers, which comprises the following steps: dividing the storage space of a disk array into at least two storage areas; assigning a processing thread sequence to the storage areas, wherein the processing thread sequence comprises at least two processing threads, the processing threads are one-to-one mapped with metadata bitmap areas of the storage areas, and the metadata bitmap areas are used for storing metadata bitmaps of strips in the storage areas; in response to metadata bitmap writing instructions for at least two target metadata bitmap areas of the storage areas, determining the processing threads corresponding to the target metadata bitmap areas respectively, and executing data writing on the metadata bitmaps in the target metadata bitmap areas through the processing threads corresponding to the target metadata bitmap areas, so that the flashing efficiency of the metadata bitmaps can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a metadata bitmap writing method. BACKGROUND

[0002] In a storage system, a RAID (Redundant Array of Independent Disks) divides a disk array into strips and records the execution state (such as whether initialization, reconstruction, etc. is completed) of each strip in combination with a metadata bitmap.

[0003] In the related art, the writing operation of the metadata bitmap is serially executed on a fixed thread, and there is a problem of low metadata bitmap writing efficiency. SUMMARY

[0004] The present application provides a metadata bitmap writing method to at least solve the problem of low metadata writing efficiency in the related art.

[0005] The present application provides a metadata bitmap writing method, comprising:

[0006] dividing a storage space of a disk array into at least two storage areas;

[0007] allocating a processing thread sequence to the storage area, the processing thread sequence comprising at least two processing threads, the processing threads being one-to-one mapped with metadata bitmap areas of the storage area, and the metadata bitmap areas being used to store metadata bitmaps of strips in the storage area;

[0008] in response to a metadata bitmap writing instruction for at least two target metadata bitmap areas of the storage area, determining the processing threads corresponding to the target metadata bitmap areas respectively, and performing data writing on the metadata bitmaps in the target metadata bitmap areas through the processing threads corresponding to the target metadata bitmap areas.

[0009] The present application further provides a metadata bitmap writing device, comprising:

[0010] a dividing module configured to divide a storage space of a disk array into at least two storage areas;

[0011] an allocating module configured to allocate a processing thread sequence to the storage area, the processing thread sequence comprising at least two processing threads, the processing threads being one-to-one mapped with metadata bitmap areas of the storage area, and the metadata bitmap areas being used to store metadata bitmaps of strips in the storage area;

[0012] The processing module is used to respond to metadata bitmap write instructions for at least two target metadata bitmap regions of the storage area, determine the processing thread corresponding to each target metadata bitmap region, and perform data writing on the metadata bitmap within the target metadata bitmap region through the processing thread corresponding to the target metadata bitmap region.

[0013] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described metadata bitmap writing methods when executing the computer program.

[0014] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described metadata bitmap writing methods.

[0015] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described metadata bitmap writing methods.

[0016] The metadata bitmap writing method provided in this application divides the storage space of the disk array into multiple storage areas, each storage area corresponding to a metadata bitmap area, and allocates multiple processing threads to the storage areas, so that the metadata bitmap area and the processing thread are mapped one by one. This allows multiple processing threads to be started simultaneously to write multiple metadata bitmap areas concurrently when performing metadata bitmap writing operations, thereby improving the efficiency of metadata operations. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A basic flowchart for attribution allocation provided in the embodiments of this application;

[0019] Figure 2 A flowchart illustrating the metadata bitmap writing method provided in this application embodiment. Figure 1 ;

[0020] Figure 3 for Figure 2 A flowchart illustrating the specific implementation of step S201 in the illustrated embodiment;

[0021] Figure 4 This is a schematic diagram illustrating the process of allocating processing threads to a storage area, as provided in an embodiment of this application.

[0022] Figure 5 For Figure 2 a flow chart of the specific implementation of step S203 in the embodiment shown in the figure;

[0023] Figure 6 a data writing process schematic diagram provided by the embodiment of the present application;

[0024] Figure 7 a flow chart of the metadata bitmap flashing method provided by the embodiment of the present application Figure 2 ;

[0025] Figure 8 a processor core allocation schematic diagram provided by the embodiment of the present application;

[0026] Figure 9 an execution flow schematic diagram of the read-write operation triggered background task process provided by the embodiment of the present application;

[0027] Figure 10 a structure schematic diagram of the metadata bitmap flashing device provided by the embodiment of the present application;

[0028] Figure 11 a structure schematic diagram of the electronic device provided by the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0030] It should be noted that, in the description of the present application, the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0031] First, the terms involved in the present application are explained:

[0032] RAID: Redundant Array of Independent Disks, independent disk redundant array, here refers to a software system for realizing disk data consistency protection at the software level, which is referred to as a disk array in the present application.

[0033] A stripe is the smallest unit of data recovery that is uniformly divided into storage areas on a disk array. It is further divided into several strips.

[0034] Metadata Bitmap: A data bitmap that records the execution status of each stripe during the execution of background tasks; each bit on the bitmap uniquely corresponds to one stripe, with 1 representing not executed and 0 representing executed. It is used to accurately record the execution status of each stripe when the node ownership information of the stripe unit changes in a multi-controller system that manages the same RAID array.

[0035] Attribution Information: In a multi-controller system that manages the same RAID array, each stripe has a designated attribution information record that the I / O execution processing of the current stripe area is performed by a certain node to avoid mutual interference between multiple controllers; this attribution information is generally default, or may be changed in real time later due to business scenarios such as load balancing.

[0036] Processing thread (fibre): An execution unit in the execution queue bound to each CPU core. The execution queue executes sequentially according to the execution unit. There are corresponding fibre queues for each CPU core. They are independent of each other and run simultaneously.

[0037] With the continuous development of storage systems, centralized multi-controller storage systems are increasingly widely used. In the technical field where this technology is applied, at the read / write area management level, the disk arrays used by users for storage are first arranged and organized to create RAID for management and fault tolerance. For multiple RAIDs, the total capacity can be managed, allocated, and used by one or more storage pools.

[0038] RAID is used to divide the storage space on the disk and generate the smallest storage data recovery unit stripe. Read and write requests (IO) from the upper layer are executed according to the fixed ownership region of the current node. For any ownership changes that may occur, the upper layer issues a change task to notify RAID to update the metadata bitmap recording the ownership information. This ensures consistency of ownership information between the upper and lower layers, and that the execution regions of RAID's background tasks for fault tolerance and recovery (formatting, disk failure reconstruction) and host IO remain consistent. The upper layer then issues IO with the new ownership distribution information, thereby enabling data read and write operations based on additional storage functions (data redundancy / fault tolerance, ownership volume expansion / shrinkage, ownership region changes under load balancing).

[0039] At the level of the storage pool, the space provided by the lower layer is divided into basic units of a block (128M). During the IO process, the address (Logical address) of the IO processing is obtained according to the volume ID and the address of the IO processing (Logical address) when the volume issues the IO, and the address at the pool level, i.e., the physical address (Physical address), is obtained through a mapping relationship and then transmitted to the lower layer for IO processing.

[0040] In a related space management technology, IO is divided into corresponding nodes for processing through homing division, Figure 1 The basic flowchart of the homing division provided by the embodiments of the present application is shown in the figure. IO is the read and write request of the host or upper layer system to the storage device, such as data writing, reading operation, etc. node0 / node1 / node2 / node3 refers to the controller node (Controller Node) in the storage system, which is the core unit for processing IO requests and managing storage resources. Multiple controller nodes can improve system performance and reliability in cooperation. mdisk refers to the managed disk (Managed Disk), which is a logical disk constructed based on the underlying physical disk. drive (disk) refers to the physical disk (Physical Disk), which is a hardware medium (such as a mechanical hard disk or a solid state disk) for storing data. Managed means that the mdisk manages the underlying drive (such as organizing disks through RAID, allocating storage space, and maintaining data consistency).

[0041] During homing division, the IO request of the upper layer system can be sent to any controller node (node0 - node3). Each controller node can share access to the same mdisk, realizing the cooperative use of storage resources (such as load balancing: different nodes processing IO requests for different areas of the mdisk). The storage space of the mdisk is allocated to different nodes for management or processing.

[0042] In the classification and exception handling technology of related background task metadata, there are multiple metadata information for assisting service execution for RAID, in which the domain information is a bitmap used to record the execution node information of the current stripe, which is used to record the scenario of creating a home volume / volume expansion with a user, and is updated with the change of the home information to maintain the consistency of the RAID background task and the host IO read / write area in the state of realizing space load balancing (average IO execution pressure of multiple controllers). Meanwhile, RAID has an array formatting task (init bitmap) and a reconstruction task (reb bitmap) for recovering disk data to a hot standby after the disk is offline. These two tasks have self-generated IO read / write in the module, which is mutually exclusive with the foreground IO and maintains consistency in the home area. For the above tasks, there is bitmap information of the initialization task and bitmap information of the reconstruction task, which records the execution of each stripe unit in units of stripes to accurately execute the unexecuted area and avoid repeated execution. In addition, after the ownership information changes or the controller fails between multiple controller systems, the execution information is lost or the progress is rolled back due to the different execution progress of the controllers.

[0043] For a newly created RAID, the home bitmap, formatting bitmap, and reconstruction bitmap are in the default state. The home bitmap needs to be initialized according to the home division logic. Since the bitmap occupies a certain space, the bitmap initialization action will increase the waiting time of the RAID creation process.

[0044] When the ownership changes, the initialization bitmap on the current controller needs to be modified synchronously to avoid missing the part of the area that needs to be reinitialized. At the same time, the area where the ownership changes cannot have IO, so the upper layer will control the IO not to fall in this area, and the RAID will control the background task to stop before changing and start the background task after the change is completed. The rate of writing the bitmap during the change will affect the execution time of the change task and the response speed of the service expansion, and will also affect the waiting time of the background task, which will affect the overall time consumption of the background task in the configuration with the home expansion volume.

[0045] If the ownership information changes when all controllers fail at the same time, the ownership information that has not been changed successfully will be saved in the persistent memory (harden memory). After the controller is restored and the service is restored, the domain bitmap of the part that has not been changed successfully will be re-flushed. If the flushing time is certain, it will increase the waiting time of the service recovery during this process.

[0046] In the related art, in order to ensure the atomicity of metadata operation, that is, to ensure the order preservation of metadata operation, all operations of metadata update and setting / modification are executed on the same thread, and the operation on metadata needs to be switched to a specified thread (master fibre) to ensure the order preservation and accuracy of metadata operation.

[0047] For each use scenario of metadata, including:

[0048] 1. In the scenario of executing a background task in real time, after the background task is executed on other threads, it is necessary to switch to the master fibre to update the metadata asynchronously, and after the metadata update operation on the master fibre is completed, the original fibre callback completion function is switched back. In the scenario of pre-write initialization and pre-write reconstruction, the IO needs to wait for the completion of the above process of the background task, which may increase the latency of read / write IO execution.

[0049] 2. When initializing the domain bitmap and formatting bitmap after creating the RAID: At this time, the business is not supported, and the business needs to wait for the RAID to complete the update of the metadata in series and in sequence on the master fibre, and then respond to the business and the background task of the RAID.

[0050] 3. The scenario of load balancing or the scenario of stripe ownership change due to volume expansion in the presence of ownership volume configuration: the same action is executed on each controller, the RAID and the upper layer stop the background task, the upper layer issues the ownership change information to the RAID, the RAID updates these information to the ownership information bitmap through the master fibre in series, and after the completion, each upper layer is called back, and after all the ownership information update is completed, the upper layer starts the background task of the RAID.

[0051] 4. All controller failures occur during the ownership information change process: at this time, due to the time sequence difference between the controllers due to all controller failures, it is necessary to refresh all the unfinished ownership changes after the node is restored, this process is not full and one-time, and the business and the background task of the RAID can be restarted / start after the RAID is written in this process.

[0052] In the above technology, since all metadata operations are executed in series on the master fibre, there are problems of low metadata operation efficiency, slow business recovery, increased IO latency, wasted CPU resources, etc.

[0053] Based on this, the embodiment of the present application provides a metadata bitmap flashing method, the storage space of the disk array is divided into a plurality of storage areas, each storage area corresponds to a metadata bitmap area, and a plurality of processing threads are allocated to the storage area, so that the metadata bitmap area and the processing thread are one-to-one mapped, so that when the metadata bitmap flashing operation is performed, a plurality of processing threads can be started simultaneously to flash a plurality of metadata bitmap areas concurrently, and the metadata operation efficiency is improved.

[0054] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0055] Figure 2 Flowchart of the metadata bitmap flashing method provided by the embodiment of the present application Figure 1 As shown in Figure 2 The embodiment of the present application provides a metadata bitmap flashing method, and the method is described in detail as follows.

[0056] S201, the storage space of the disk array is divided into at least two storage areas.

[0057] The metadata bitmap flashing method provided by the embodiment of the present application can be executed by a computing device, which can be a server, a storage array controller, etc.

[0058] The storage space of the disk array refers to a unified logical storage space with fault tolerance capability formed by a plurality of physical disks through RAID technology, and the storage area is a plurality of continuous subspaces divided from the logical storage space.

[0059] The size of the storage area is determined by the area division length, and the storage space of the disk array can be divided into at least two storage areas according to the area division length.

[0060] Exemplarily, as shown in Figure 3 The storage space of the disk array can be divided into at least two storage areas in the following manner:

[0061] S2011, obtaining disk configuration information of the disk array, the disk configuration information including at least one of the number of processing threads, the minimum storage length of the bitmap, and the stripe length.

[0062] The number of processing threads can be determined in advance according to the CPU model of the computing device and the mapping relationship between the software and the CPU core in the computing device, and can be changed according to the use condition; if the bitmap is stored in the form of 32-bit unsigned integer (4 bytes), the minimum storage length is 32.

[0063] S2012, determining the area division length according to the disk configuration information.

[0064] The region division length is, for example, the number of processing threads × the minimum storage length of the bitmap × the strip length, wherein the strip length can be adjusted.

[0065] S2013, dividing the storage space of the disk array into at least two storage regions according to the region division length.

[0066] The storage regions are divided according to the ratio of the length of the storage space to the region division length, wherein the ratio is the number of the storage regions.

[0067] In the above scheme, the region division length is determined according to the disk configuration information, and the storage space is divided according to the region division length, which provides a basis for subsequent processing thread allocation and multi-processing thread simultaneous operation.

[0068] S202, allocating a processing thread sequence to the storage region.

[0069] The processing thread sequence includes at least two processing threads, and the processing threads are one-to-one mapped to the metadata bitmap regions of the storage regions, and the metadata bitmap regions are used to store the metadata bitmaps of the strips in the storage regions.

[0070] The processing thread sequence is a set of fibre collections, and the processing thread sequence can include multiple fibres.

[0071] The metadata bitmap is a data bitmap used to record the execution status of each strip during the execution of the background task, and the metadata bitmap region is a region used to store the metadata bitmap. Each bit in the metadata bitmap uniquely corresponds to a strip in the storage space of the disk array, and the value (0 or 1) of the bit is used to indicate a certain state (such as whether the initialization is completed, whether the data reconstruction is completed, which controller it belongs to, etc.) of the strip.

[0072] The one-to-one mapping of the processing threads to the metadata bitmap regions of the storage regions means that one processing thread is fixedly and exclusively responsible for the metadata bitmap operation of one or more storage regions.

[0073] In the embodiment of the present application, the processing threads include multiple processing threads, and the processing thread sequence can be allocated to the storage region according to a set allocation strategy, for example, sequential and cyclic allocation.

[0074] Exemplarily, the processing thread sequence can be allocated to the storage region in the following manner: numbering the N processing threads, determining the processing thread corresponding to the processing thread number, and the processing thread number is a positive integer from 1 to N; sequentially allocating the N processing threads to the storage regions from 1, until all the N processing threads are allocated, and then re-allocating the processing threads to the remaining storage regions from 1, until all the storage regions are allocated to the corresponding processing threads.

[0075] The above process is described in detail below with a specific example as shown in Figure 4 Figure 4 The process of allocating processing threads to storage areas provided by the embodiments of the present application is shown in the following. When there are 16 fibres (i.e. N = 16) and 20 storage areas, the numbers of the fibres are determined as fibre1 to fibre16 respectively. First, fibre1 to fibre16 are allocated to storage area 1 to storage area 16 respectively. Then, fibre1 is allocated to storage area 17, fibre2 is allocated to storage area 18, and so on. Finally, fibre4 is allocated to storage area 20. The processing thread sequence is fibre1 to fibre16, fibre2 to fibre4.

[0076] In the above process, since one storage area is only operated by one processing thread, there is no case of multiple processing threads writing to the same storage area at the same time, so that lock-free concurrency can be achieved, greatly improving the efficiency.

[0077] S203, in response to the metadata bitmap write instruction for at least two target metadata bitmap areas of the storage area, determining the processing thread corresponding to the target metadata bitmap area respectively, and performing data write on the metadata bitmap in the target metadata bitmap area through the processing thread corresponding to the target metadata bitmap area.

[0078] The metadata bitmap write instruction is used to indicate updating the metadata state of a specific strip range, such as marking the state of strip 100 to strip 200 as "initialized", i.e. clearing the corresponding bit.

[0079] The target metadata bitmap area is the metadata bitmap area corresponding to the storage area indicated by the metadata bitmap instruction.

[0080] Since a corresponding processing thread is allocated to each storage area, and the storage area and the metadata bitmap area are one-to-one mapped, the processing thread corresponding to the metadata bitmap area of the storage area can be determined. Then, for the target metadata bitmap area, the data write on the metadata bitmap in the target metadata bitmap area can be performed through the processing thread allocated to the storage area by step S202.

[0081] ​For example, the storage area corresponding to the target metadata bitmap area is storage area 2 to storage area 4, and the processing threads corresponding to storage area 2 to storage area 4 are fibre2 to fibre4 according to step S202. Data writing is performed on the metadata bitmap in the target metadata bitmap area by the processing threads fibre2 to fibre4, wherein the target metadata bitmap area is also divided into a plurality of sub-bitmap areas according to the division manner corresponding to the storage area, and each processing thread is responsible for data writing of the corresponding sub-bitmap area.

[0082] In a possible implementation, in response to a metadata bitmap writing instruction for at least two target metadata bitmap areas of a storage area, a processing thread corresponding to each target metadata bitmap area is determined, and data writing is performed on the metadata bitmap in the target metadata bitmap area by the processing thread corresponding to the target metadata bitmap area, including: determining a first target strip and a second target strip that need to perform data writing according to the metadata bitmap writing instruction; determining a first target metadata bitmap area where the first target strip is located and a second target metadata bitmap area where the second target strip is located by the first target strip and the second target strip; determining a first bitmap area identifier of the first target metadata bitmap area and a second bitmap area identifier of the second target metadata bitmap area according to the first target metadata bitmap area and the second target metadata bitmap area; determining a first processing thread corresponding to the first bitmap area identifier and a second processing thread corresponding to the second bitmap area identifier according to a processing thread sequence of the storage area and the first bitmap area identifier; triggering a background task by the first target strip and the second target strip to call the first processing thread and the second processing thread to asynchronously write first target data to the first target strip and write second target data to the second target strip.

[0083] In a possible implementation, the specific implementation of S203 can be as shown in Figure 5

[0084] S2031, the processing thread traverses the task record table to determine the metadata bitmap writing instruction.

[0085] The task record table is used to indicate the change of the ownership information of the strip in the disk array, and the task record table includes at least two change records.

[0086] ​The metadata bitmap write instruction can be determined according to a change record, and the change record at least records a strip range and a target state. The strip range indicates which strip range in the disk array the change record is for, such as strip number A to strip number B. The target state indicates that the metadata bits corresponding to the strip are required to be updated to which state, such as all 0 (executed) or updated to a new home node ID. The metadata bitmap write instruction includes the above strip range and target state, so that the processing thread determines the strip to be written and the specific data to be written according to the metadata bitmap write instruction.

[0087] In the embodiment of the application, all processing threads traverse the task record table at the same time, that is, fibre1 to fibre16 simultaneously access each change record in the task record table.

[0088] S2032, determining a target metadata bitmap region according to the metadata bitmap write instruction.

[0089] In the embodiment of the application, the target metadata bitmap region is the strip range indicated in the metadata bitmap write instruction, such as strip number A to strip number B.

[0090] Exemplarily, the target metadata bitmap region can be determined in the following manner: determining the start strip number and the end strip number of the strip to be written according to the metadata bitmap write instruction; determining the storage region indicated by the change record according to the start strip number and the end strip number; and determining the metadata bitmap region corresponding to the storage region indicated by the change record as the target metadata bitmap region.

[0091] The start strip number and the end strip number of the strip to be written are, for example, strip number A and strip number B. If the metadata bitmap region corresponding to the storage region between strip number A and strip number B in the disk array needs to be written, the metadata bitmap region corresponding to the storage region between strip number A and strip number B is determined as the target storage region.

[0092] S2033, determining a processing thread corresponding to the target metadata bitmap region, and performing data writing on the metadata bitmap in the target metadata bitmap region through the processing thread corresponding to the target metadata bitmap region.

[0093] The target metadata bitmap region can correspond to multiple divided storage regions, such as a region from stripe number A to stripe number B, stripe number A to stripe number C corresponds to storage region 1, and stripe number C+1 to stripe number B corresponds to storage region 2, and storage region 1 corresponds to fibre 1 and storage region 2 corresponds to fibre 2 by step S202, then the data write operation of the metadata bitmap in the metadata bitmap region corresponding to stripe number A to stripe number C in the target metadata bitmap region is processed by fibre 1, and the data write operation of the metadata bitmap in the metadata bitmap region corresponding to stripe number C+1 to stripe number B in the target metadata bitmap region is processed by fibre 2.

[0094] Exemplarily, the processing thread corresponding to the target metadata bitmap region can be determined as follows: for any one stripe in the change record indication, the result of the ratio of the stripe number of the stripe to the region division length is rounded up to obtain the target sequence number corresponding to the stripe; and the processing thread in the processing thread sequence with the same processing thread number as the target sequence number is determined as the processing thread corresponding to the metadata bitmap region.

[0095] The above process is explained in detail below with a specific example: for example, by step S202, in the processing thread sequence allocated for the storage region, when the region length is 32, stripe number 1 to stripe number 32 correspond to fibre 1, stripe number 33 to stripe number 64 correspond to fibre 2, stripe number 65 to stripe number 96 correspond to fibre 3, and so on.

[0096] For the stripe number of any one stripe in the change record, for example, 50, the target sequence is the ratio of 50 to 32, and the target sequence number corresponding to stripe number 50 is 2.

[0097] The processing thread with the same processing thread number as the target sequence number is determined as the processing thread corresponding to the metadata bitmap region of stripe number 50, that is, fibre 2 is determined as the processing thread corresponding to the metadata bitmap region of stripe number 50.

[0098] In the above process, each processing thread simultaneously determines the target sequence number corresponding to each stripe in the change record, and when the target sequence number is the same as the current processing thread number, the data write of the metadata bitmap region corresponding to the stripe number is processed by the processing thread.

[0099] For example, fibre1 traverses each stripe number in the change record and determines that stripe numbers 1 to 32 are the same as the current fibre sequence number, and then fibre1 processes data write of the metadata bitmap area corresponding to stripe numbers 1 to 32, while fibre2 traverses each stripe number in the change record and determines that stripe numbers 33 to 64 are the same as the current fibre sequence number, and then fibre2 processes data write of the metadata bitmap area corresponding to stripe numbers 33 to 64, and so on.

[0100] Through the above process, multiple processing threads can simultaneously perform write operations on the metadata bitmaps corresponding to different stripes in the change record, thereby improving the write efficiency.

[0101] The following will be described in conjunction with Figure 6 The process of step S203 will be described. As shown in Figure 6 , Figure 6 The data write process diagram provided by the embodiments of the present application. Record is a task record table, recording metadata update / refresh tasks, which include multiple change records, each fibre simultaneously traverses Record, and each fibre has a corresponding storage area (pack), wherein PART is an abstraction of N storage areas into a block, and each block corresponds to a part of the mdisk bitmap space, such as pack1 to packN corresponding to PART1 part of the bitmap space.

[0102] Exemplarily, after the metadata bitmap in the target metadata bitmap area is executed by the processing thread corresponding to the target metadata bitmap area, the method further includes: based on the data write result of the metadata bitmap, performing a target redundant array of independent disks function.

[0103] The target redundant array of independent disks function includes one of the following: disk array initialization attribution information, attribution information change triggered by load balancing or volume expansion, and refresh of attribution information after controller failure recovery.

[0104] The target redundant array of independent disks function refers to the initial controller node attribution relationship configured for all stripes after creating a new RAID or expansion. This process needs to batch write the calculated initial attribution information into the metadata bitmap to establish the most basic IO routing basis in the multi-controller system.

[0105] The attribution information change triggered by load balancing or volume expansion refers to the operation of dynamically adjusting part of the stripe attribution relationship to achieve load balancing or adapt to the space changes caused by volume expansion. This process updates the attribution information of the corresponding stripe in the metadata bitmap to realize the redistribution of IO processing tasks.

[0106] The reflush of the home information after the controller recovers from the failure refers to the operation performed after the controller has a total failure to recover the system consistency. Since the failure can cause the ongoing home change not to be completely persisted, after the controller recovers, the uncompleted home change operation needs to be re-executed according to the change record in the log or the memory before the failure, to ensure that the metadata bitmap is consistent with the expected state.

[0107] The metadata bitmap flushing method provided by the embodiment of the present application divides the storage space of the disk array into a plurality of storage regions, each storage region corresponds to a metadata bitmap region, and a plurality of processing threads are allocated to the storage regions, so that the metadata bitmap region and the processing thread are one-to-one mapped, so that when the flushing operation of the metadata bitmap is performed, a plurality of processing threads can be started simultaneously to flush a plurality of metadata bitmap regions concurrently, and the metadata operation efficiency is improved.

[0108] Figure 7 Flowchart of the metadata bitmap flushing method provided by the embodiment of the present application Figure 2 As shown in Figure 7 The embodiment of the present application provides a metadata bitmap flushing method, which is described in detail as follows.

[0109] S701, determine the number K of disk arrays, the number M of processor cores, and the number N of processing threads.

[0110] Each disk array corresponds to N processing threads, and N≤M.

[0111] S702, allocate at least one processor core to the processing threads of the K disk arrays.

[0112] The processor core can be repeatedly allocated.

[0113] For example, the processor core can be allocated to the processing thread in the following manner: the first to Nth processor cores are sequentially allocated to the processing threads of the first disk array; the N+1th to Mth processor cores are sequentially allocated to the first to M-Nth processing threads of the next disk array, and the remaining processing threads are sequentially allocated from the first processor core, until the processing threads of the K disk arrays are all allocated to the processor cores.

[0114] The allocation process of the processor core can be as shown in Figure 8 , Figure 8 The allocation of the processor core provided by the embodiment of the present application is shown in the figure, wherein the number M of processor cores is 20, the first to 20th processor cores are numbered, the number K of disk arrays is 3, and the first to 16th processing threads are numbered, and the number N of processing threads is 16. Figure 8The first disk array corresponds to the first processing thread, the second disk array corresponds to the fourth processing thread, and the third disk array corresponds to the eighth processing thread.

[0115] S703, dividing the storage space of the disk array into at least two storage regions.

[0116] S704, assigning a processing thread sequence to the storage region.

[0117] S705, in response to a metadata bitmap write instruction for at least two target metadata bitmap regions of the storage region, determining the processing thread corresponding to the target metadata bitmap region respectively, and performing data write on the metadata bitmap in the target metadata bitmap region through the processing thread corresponding to the target metadata bitmap region.

[0118] Optionally, after the initialization or reconstruction of the metadata bitmap is completed, the method provided by the embodiment of the application can further include: in response to a read-write operation, determining the processing thread corresponding to the execution region accessed by the read-write operation, and performing data write on the metadata bitmap in the metadata bitmap region corresponding to the execution region through the processing thread corresponding to the execution region.

[0119] The execution region is a region that needs to be written by an IO request. When the host issues an IO request to write data, the mapping rule established by the embodiment shown in FIG. 8 is used to map the execution region corresponding to the IO request to the storage region, and the processing thread corresponding to the storage access is used to execute the write operation corresponding to the IO request. Figure 2

[0120] Exemplarily, the above method can be implemented in the following manner: in response to a read-write operation, determining the execution region accessed by the read-write operation; dividing the execution region accessed by the read-write operation in the same manner as the division of the storage space; mapping the execution region to the storage region, and determining the processing thread corresponding to the storage region as the processing thread corresponding to the execution region; and performing data write on the metadata bitmap in the metadata bitmap region corresponding to the execution region through the processing thread corresponding to the execution region.

[0121] In the above process, the execution region of the IO is divided according to the manner of dividing the storage space, that is, during the execution of the IO of the multi-thread host, the IO executed on other fibres follows the division manner of the metadata bitmap space, so as to ensure that the execution region accessed by the host IO and the metadata region updated by the background task triggered by the host IO are mapped to the same processing thread. Since the storage region and the processing thread are in one-to-one correspondence, there is no possibility that multiple threads operate the same region simultaneously, so there is no need to switch to a dedicated thread to ensure the order, and the metadata can be directly updated on the original thread of the execution IO.​

[0122] Figure 9 The execution flow diagram of the read-write operation triggering the background task process provided by the embodiment of the application is shown in the figure. The host IO (i.e., the read-write operation) calculates to determine the fibre corresponding to the execution function area, i.e., fibre x. The storage area corresponding to fibre x is the area in pack1, and start and end represent the start position and end position of the storage area, respectively. In response to the read-write operation, stripey (i.e., any one stripe) triggers the stripe background task, uses fiber x to execute the task, and updates the metadata corresponding to the stripe after the task is completed.

[0123] In the related art, the metadata update needs to be switched to the Master fibre first and then switched back, which has huge overhead. In the above scheme, there is no need to switch to a dedicated thread, which reduces such overhead, so that the response time of a single IO operation is shorter. On the other hand, the metadata operation is changed from serial processing to parallel processing, and the metadata update operation is evenly distributed to multiple CPU cores, which improves the throughput of the system and the resource utilization rate of the CPU.

[0124] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0125] Figure 10 The structure diagram of the metadata bitmap writing device provided by the embodiment of the application is shown in the figure. As shown in the figure, the metadata bitmap writing device 10 includes: Figure 10

[0126] The division module 101 is configured to divide the storage space of the disk array into at least two storage areas.

[0127] The allocation module 102 is configured to allocate a processing thread sequence to the storage area, the processing thread sequence including at least two processing threads, the processing threads being one-to-one mapped with metadata bitmap areas of the storage area, and the metadata bitmap areas being used to store metadata bitmaps of the stripes in the storage area.

[0128] The processing module 103 is configured to, in response to a metadata bitmap write instruction for at least two target metadata bitmap areas of the storage area, determine the processing threads corresponding to the target metadata bitmap areas, respectively, and execute data writing on the metadata bitmaps in the target metadata bitmap areas through the processing threads corresponding to the target metadata bitmap areas.

[0129] In a possible implementation, the division module 101 is specifically configured to:

[0130] ​Obtain disk configuration information of the disk array, the disk configuration information comprising at least one of a number of processing threads, a bitmap minimum storage length, and a stripe length;

[0131] Determine a region division length according to the disk configuration information;

[0132] Divide the storage space of the disk array into at least two storage regions according to the region division length.

[0133] In a possible implementation, the allocation module 102 is specifically configured to:

[0134] Number the N processing threads, determine a processing thread number corresponding to each processing thread, and the processing thread number is a positive integer from 1 to N;

[0135] Assign the N processing threads to the storage regions in sequence from 1 until all the N processing threads are assigned, and reassign the remaining storage regions to the processing threads from 1 until all the storage regions are assigned to the corresponding processing threads.

[0136] In a possible implementation, the processing module 103 is specifically configured to:

[0137] The processing thread traverses a task record table to determine a metadata bitmap write instruction, the task record table being used to indicate a change in ownership information of a stripe in the disk array, and the task record table comprising at least two change records;

[0138] Determine a target metadata bitmap region according to the metadata bitmap write instruction;

[0139] Determine a processing thread corresponding to the target metadata bitmap region, and perform data writing on a metadata bitmap in the target metadata bitmap region by the processing thread corresponding to the target metadata bitmap region.

[0140] In a possible implementation, the processing module 103 is further configured to:

[0141] Determine a start stripe number and an end stripe number of a stripe to be written according to the metadata bitmap write instruction;

[0142] Determine a storage region indicated by the change record according to the start stripe number and the end stripe number;

[0143] Determine a metadata bitmap region corresponding to the storage region indicated by the change record as the target metadata bitmap region.

[0144] In a possible implementation, the processing module 103 is specifically configured to:

[0145] For any one of the change record indications, the result of the ratio of the stripe number of the stripe to the region division length is rounded up to obtain a target serial number corresponding to the stripe;

[0146] The processing thread whose processing thread program number in the processing thread program sequence is same as the target serial number is determined as the processing thread corresponding to the metadata bitmap region.

[0147] In a possible implementation, the metadata bitmap writing device 10 is further configured to:

[0148] determine the number K of disk arrays, the number M of processor cores and the number N of processing threads, wherein each disk array corresponds to N processing threads, and N≤M;

[0149] allocate the first to Nth processor cores to the processing threads of the first disk array in sequence;

[0150] allocate the N+1th to Mth processor cores to the first to M-Nth processing threads of the subsequent disk array in sequence, and re-allocate the processor cores to the remaining processing threads starting from the first processor core in sequence until the processing threads of the K disk arrays are all allocated to the processor cores.

[0151] In a possible implementation, the metadata bitmap writing device 10 is further configured to:

[0152] in response to a read-write operation, determine an execution region accessed by the read-write operation;

[0153] divide the execution region accessed by the read-write operation using the same division manner as the storage space;

[0154] map the execution region to a storage region, and determine the processing thread corresponding to the storage region as the processing thread corresponding to the execution region;

[0155] perform data writing on the metadata bitmap in the metadata bitmap region corresponding to the execution region by the processing thread corresponding to the execution region.

[0156] In a possible implementation, the metadata bitmap writing device 10 is further configured to:

[0157] according to the metadata bitmap writing instruction, determine a first target stripe and a second target stripe that need to perform data writing;

[0158] determine a first target metadata bitmap region where the first target stripe is located and a second target metadata bitmap region where the second target stripe is located respectively through the first target stripe and the second target stripe;

[0159] According to the first target metadata bitmap area and the second target metadata bitmap area, a first bitmap area identifier of the first target metadata bitmap area and a second bitmap area identifier of the second target metadata bitmap area are determined respectively;

[0160] According to the processing line program sequence of the storage area and the first bitmap area identifier, a first processing thread corresponding to the first bitmap area identifier and a second processing thread corresponding to the second bitmap area identifier are determined;

[0161] The first target data is written into the first target strip and the second target data is written into the second target strip by triggering the background tasks through the first target strip and the second target strip respectively, so as to call the first processing thread and the second processing thread.

[0162] The features of the embodiments of the metadata bitmap flashing device can be referred to the related descriptions of the embodiments of the metadata bitmap flashing method, which will not be repeated here.

[0163] Figure 11 The structure schematic diagram of the electronic device provided in the present application is shown in the figure. Figure 11 As shown in the figure, the electronic device 11 provided in the present embodiment includes at least one processor 111 and a memory 112. Optionally, the electronic device 11 further includes a communication component 113. Wherein, the processor 111, the memory 112 and the communication component 113 are connected through a bus.

[0164] In the specific implementation process, the at least one processor 111 executes the computer execution instructions stored in the memory 112, so that the at least one processor 111 executes the metadata bitmap flashing method embodiments described above.

[0165] The specific implementation process of the processor 111 can be referred to the method embodiments described above, which has similar implementation principles and technical effects, and will not be repeated here.

[0166] In the above embodiments, it should be understood that the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC) and the like. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor and the like. The steps of the method disclosed in the present application can be directly embodied as the execution of the hardware processor, or executed by the combination of the hardware and software modules in the processor.

[0167] The memory can include a random access memory (RAM) and can also include a non-volatile memory (NVM), such as at least one disk memory.

[0168] The bus can be an industry standard architecture (ISA) bus, a peripheral component (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus.

[0169] Embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above metadata bitmap flashing method embodiments when running.

[0170] In an example embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0171] Embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps in any of the above metadata bitmap flashing method embodiments.

[0172] Embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above metadata bitmap flashing method embodiments.

[0173] Those skilled in the art will further realize that the mere concepts, teachings, and embodiments described herein are merely meant to provide an enabling description of the claimed application. Accordingly, modifications and / or additions, other than those explicitly described herein, can be obvious to those skilled in the art in the light of this disclosure. The claimed application is intended to embrace all such modifications and / or additions.

[0174] The metadata bitmap flashing method provided by the present application is described in detail above. The principles and implementation manners of the present application are described by using specific examples in this paper, and the above description of the embodiments is only applicable to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A metadata bitmap flashing method, characterized in that, The method comprises the following steps: dividing the storage space of the disk array into at least two storage regions; allocating a processing thread sequence to the storage regions, the processing thread sequence comprising at least two processing threads, the processing threads being one-to-one mapped with the metadata bitmap regions of the storage regions, and the metadata bitmap regions being used for storing the metadata bitmap of the stripe in the storage region; the one-to-one mapping of the processing threads with the metadata bitmap regions of the storage regions means that one processing thread is fixedly and exclusively responsible for the metadata bitmap operation of one or more storage regions; in response to a metadata bitmap write instruction for at least two target metadata bitmap regions of the storage region, determining the processing thread corresponding to the target metadata bitmap region respectively, and performing data write on the metadata bitmap in the target metadata bitmap region through the processing thread corresponding to the target metadata bitmap region; the step of dividing the storage space of the disk array into at least two storage regions comprises the following steps: obtaining the disk configuration information of the disk array, the disk configuration information comprising at least one of the number of processing threads, the minimum storage length of the bitmap, and the stripe length; determining the region division length according to the disk configuration information; dividing the storage space of the disk array into at least two storage regions according to the region division length; the step of determining the processing thread corresponding to the target metadata bitmap region respectively and performing data write on the metadata bitmap in the target metadata bitmap region through the processing thread corresponding to the target metadata bitmap region comprises the following steps: the processing thread traverses the task record table to determine the metadata bitmap write instruction, the task record table being used for indicating the change of the attribution information of the stripe in the disk array, and the task record table comprising at least two change records; determining the start stripe number and the end stripe number of the stripe to be written according to the metadata bitmap write instruction; determining the storage region indicated by the change record according to the start stripe number and the end stripe number; determining the metadata bitmap region corresponding to the storage region indicated by the change record as the target metadata bitmap region; for any one stripe indicated in the change record, taking the result of the ratio of the stripe number of the stripe to the region division length as an integer, to obtain the target serial number corresponding to the stripe; determining the processing thread in the processing thread sequence with the same processing thread number as the target serial number as the processing thread corresponding to the metadata bitmap region; performing data write on the metadata bitmap in the target metadata bitmap region through the processing thread corresponding to the target metadata bitmap region.

2. The metadata bitmap flashing method of claim 1, wherein, the step of allocating a processing thread sequence to the storage regions comprises the following steps: numbering N processing threads to determine the processing thread number corresponding to the processing thread, the processing thread number being a positive integer from 1 to N; allocating N processing threads to the storage areas in turn from 1 until N processing threads are all allocated, and re-allocating the processing threads to the remaining storage areas from 1 until all the storage areas are allocated to corresponding processing threads.

3. The metadata bitmap flashing method of claim 1, wherein, Before the step of dividing the storage space of the disk array into at least two storage areas, the method further comprises: determining the number K of disk arrays, the number M of processor cores, and the number N of processing threads, wherein each disk array corresponds to N processing threads, and N≤M; allocating the first to Nth processor cores to the processing threads of the first disk array in turn; allocating the N+1th to Mth processor cores to the first to M-Nth processing threads of the subsequent disk array in turn, and re-allocating the processor cores to the remaining processing threads from the first processor core in turn until the processing threads of the K disk arrays are all allocated to the processor cores.

4. The metadata bitmap flashing method of claim 1, wherein, The method further comprises: in response to a read-write operation, determining an execution area accessed by the read-write operation; dividing the execution area accessed by the read-write operation using the same division manner as the storage space; mapping the execution area to a storage area, and determining the processing thread corresponding to the storage area as the processing thread corresponding to the execution area; performing data writing on the metadata bitmap in the execution area by the processing thread corresponding to the execution area.

5. The metadata bitmap flashing method of claim 1, wherein, In response to a metadata bitmap write instruction for at least two target metadata bitmap areas of the storage area, determining the processing thread corresponding to each target metadata bitmap area, and performing data writing on the metadata bitmap in the target metadata bitmap area by the processing thread corresponding to the target metadata bitmap area, comprises: determining a first target stripe and a second target stripe that need to perform data writing according to the metadata bitmap write instruction; determining a first target metadata bitmap area where the first target stripe is located and a second target metadata bitmap area where the second target stripe is located according to the first target stripe and the second target stripe; determining a first bitmap area identifier of the first target metadata bitmap area and a second bitmap area identifier of the second target metadata bitmap area according to the first target metadata bitmap area and the second target metadata bitmap area; determining a first processing thread corresponding to the first bitmap area identifier and a second processing thread corresponding to the second bitmap area identifier according to the processing thread sequence of the storage area and the first bitmap area identifier; triggering a background task through the first target stripe and the second target stripe to call the first processing thread and the second processing thread to asynchronously write first target data to the first target stripe and second target data to the second target stripe.

6. An electronic device, comprising: comprises: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the metadata bitmap flushing method according to any one of claims 1 to 5.

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