Data reading processing method, multi-level cache processor architecture, processor, cache controller and equipment

Abstract

The invention provides a data reading processing method, a multi-level cache processor architecture, a processor, a cache controller and equipment, the method is applied to processor cache, and the method comprises the following steps: comparing a destination address of a read request sent by a request source with a destination address of a prefetch request stored in a first buffer area; the first buffer area is used for storing a request which does not hit the requested data in the processor cache; and under the condition of confirming that the read request and the prefetch request correspond to the same destination address, determining return data corresponding to the prefetch request and returned by the next-level storage as the return data of the read request. By applying the method in the processor cache, the efficiency of reading the data from the cache can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a data reading processing method, a multi-level cache processor architecture, a processor, a cache controller and a device. BACKGROUND

[0002] In the multi-level cache processor architecture, when a read / write request does not hit the required read / write data in a certain level cache, a buffer needs to be allocated for the request, the request is temporarily stored in the buffer, and a data request is sent to the next level cache.

[0003] In the above case, if a read / write request with the same destination address is subsequently received, the read / write request is blocked and a buffer is allocated for it, the read / write request is temporarily stored in the buffer allocated for it, and after the previous request is completed, the read / write request reenters the cache pipeline and rerequests data from the cache.

[0004] The above solution causes all requests entering the buffer to reenter the pipeline, affecting the data reading efficiency. SUMMARY

[0005] To solve the above technical problems, the present application provides a data reading processing method, a multi-level cache processor architecture, a processor, a cache controller and a device, which can improve the efficiency of reading data from the cache.

[0006] The first aspect of the present application provides a data reading processing method applied to a processor cache, the method comprising:

[0007] comparing the destination address of a read request sent by a request source with the destination address of a prefetch request stored in a first buffer; the first buffer is used to store a request that does not hit the requested data in the processor cache;

[0008] In the case where it is confirmed that the read request and the prefetch request correspond to the same destination address, the return data returned by the next level storage corresponding to the prefetch request is determined as the return data of the read request.

[0009] In some implementations, the method further comprises:

[0010] In the case where the prefetch request sent by the request source is received, the data corresponding to the prefetch request is queried from the local cache data of the processor cache;

[0011] In the case where it is confirmed that the data corresponding to the prefetch request does not exist in the local cache data, the first buffer is allocated for the prefetch request, the prefetch request is stored in the first buffer, and a data request is sent to the next level storage; the data request is used to request the data corresponding to the prefetch request.

[0012] In some implementations, upon confirming that the read request corresponds to the same destination address as the prefetch request, the method further comprises:

[0013] storing the read request to the first buffer.

[0014] In some implementations, storing the read request to the first buffer comprises:

[0015] replacing the prefetch request in the first buffer with the read request.

[0016] In some implementations, the method further comprises:

[0017] upon confirming that the data corresponding to the prefetch request does not exist in the local cache data, setting a request sending state machine and a backfill state machine to an active state; wherein the backfill state machine in the active state indicates that the data returned by the next level storage needs to be filled into the processor cache.

[0018] replacing the prefetch request in the first buffer with the read request comprises:

[0019] replacing the prefetch request in the first buffer with the read request, keeping the request sending state machine and the backfill state machine in the active state, and setting a data returning state machine to an active state; wherein the data returning state machine in the active state indicates that the data returned by the next level storage needs to be sent to the request source.

[0020] In some implementations, the method further comprises:

[0021] upon confirming that the data corresponding to the prefetch request does not exist in the local cache data, setting a request sending state machine and a backfill state machine to an active state; wherein the backfill state machine in the active state indicates that the data returned by the next level storage needs to be filled into the processor cache.

[0022] upon confirming that the read request corresponds to the same destination address as the prefetch request, the method further comprises:

[0023] storing the read request to a second buffer, setting a data returning state machine to an active state, and storing the prefetch request to a sub-buffer in the second buffer; wherein the data returning state machine in the active state indicates that the data returned by the next level storage needs to be sent to the request source.

[0024] upon receiving the returned data, comparing the request corresponding to the returned data with the requests in the sub-buffer;

[0025] in a case where it is confirmed that the return data corresponds to the request consistent with the request in the sub-buffer, writing the return data into the second buffer and releasing the first buffer, and determining the return data as the return data of the read request.

[0026] The second aspect of the present application provides a cache controller applied to a processor cache, the cache controller comprising:

[0027] a comparison unit configured to compare a destination address of a read request sent by a request source with a destination address of a prefetch request stored in a first buffer; the first buffer is configured to store a request for requested data that misses in the processor cache;

[0028] a response unit configured to, in a case where it is confirmed that the read request corresponds to the same destination address as the prefetch request, determine return data corresponding to the prefetch request returned by a next level storage as return data of the read request.

[0029] The third aspect of the present application provides a processor comprising a cache, the processor being configured to implement the above-mentioned data reading processing method, or the processor comprising the above-mentioned cache controller.

[0030] The fourth aspect of the present application provides a multi-level cache processor architecture comprising a multi-level cache, at least one cache in the multi-level cache being configured to implement the above-mentioned data reading processing method, or the multi-level cache processor architecture comprising the above-mentioned cache controller.

[0031] The fifth aspect of the present application provides a computer device comprising the above-mentioned cache controller, or comprising the above-mentioned processor, or comprising the above-mentioned multi-level cache processor architecture.

[0032] The data reading processing method provided by the present application can directly determine the return data returned by the next level storage corresponding to the prefetch request as the return data corresponding to the read request when the processor cache confirms that the prefetch request misses and stores the prefetch request into the first buffer, and then receives the read request sent by the request source, compares the destination address of the read request with the destination address of the prefetch request stored in the first buffer, and confirms that the destination addresses of the two are the same. The above-mentioned scheme can directly determine the return data returned by the next level storage corresponding to the prefetch request as the return data corresponding to the read request when the processor cache obtains the return data corresponding to the prefetch request, without restarting the read request to request data from the processor cache again, thereby improving the response efficiency of the read request and improving the efficiency of reading data from the cache by the processor. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only need to be drawn for the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of the provided drawings.

[0034] Figure 1 A schematic diagram of a multi-level cache processor architecture provided by an embodiment of the present application.

[0035] Figure 2 A flowchart of a data reading processing method provided by an embodiment of the present application.

[0036] Figure 3 A flowchart of another data reading processing method provided by an embodiment of the present application.

[0037] Figure 4 A structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0038] The embodiments of the present application are applicable to the application scenario of reading data from a cache by a processor. By adopting the technical solutions of the embodiments of the present application, the efficiency of reading data from a cache by a processor can be improved, and the number of buffer areas in the cache can be reduced.

[0039] In the hierarchy of computer storage systems, a cache is a high-speed small-capacity memory between a central processing unit and a main memory, which is composed of static memory chips (SRAM) and has a relatively small capacity but a speed higher than that of the main memory, close to the speed of the CPU.

[0040] The working principle of the cache is that when the CPU wants to read a data, it is first searched in the CPU cache. If found, it is immediately read and sent to the CPU for processing. If not found, it is read from the relatively slow memory and sent to the CPU for processing, and the data block where the data is located is also called into the cache, so that the reading of the entire block of data from the cache in the future is not necessary. Such a reading mechanism increases the hit rate of the CPU reading the cache, that is, the data to be read by the CPU next time is more likely to be in the CPU cache, and only a small amount of data needs to be read from the memory. This greatly saves the time of the CPU directly reading the memory, and also makes the CPU basically not need to wait when reading data.

[0041] The data in the cache is only a copy of part of the data in the memory, so when the CPU looks for data in the cache, it may not find it (because some data has not been copied from the memory to the cache), in which case the CPU will still read the data from the memory, which makes the data reading speed of the CPU relatively slower, but the CPU will copy the read data to the cache for the next use. Therefore, the more frequently the data is accessed, the longer it will exist in the cache. At the same time, as time changes, the data that is accessed most frequently will also change, so the data in the cache needs to be replaced frequently according to a certain algorithm, so that the data in the cache is always the data that is accessed most frequently.

[0042] The technical scheme of the embodiment of the present application is applicable to a multi-level cache processor architecture, which includes a plurality of levels of cache, such as two levels of cache, three levels of cache, four levels of cache, etc.

[0043] In the above multi-level cache, according to the distance of the cache from the processor core, the multi-level cache can be defined as a first level cache, a second level cache, a third level cache, etc. The closer the level of the cache, the closer the distance from the processor core, and the faster the speed of reading data from the processor core. Conversely, the farther the level of the cache, the farther the distance from the processor core, and the slower the speed of reading data from the processor core. For example, the speed of reading data from the first level cache is higher than that from the second level cache, and the speed of reading data from the second level cache is higher than that from the third level cache.

[0044] Generally, the closer the level of the cache, the higher the frequency of reading the stored data by the processor core, and the farther the level of the cache, the lower the frequency of reading the stored data by the processor core. Moreover, generally, the closer the level of the cache, the smaller the space, and the farther the level of the cache, the larger the space.

[0045] Figure 1 is a schematic diagram of a multi-level cache processor architecture provided by the embodiment of the present application, in which a three-level cache is exemplarily shown, including a first level cache L1, a second level cache L2, and a third level cache L3.

[0046] Among them, the first level cache L1 is divided into an instruction cache L1I and a data cache L1D, the instruction cache L1I is used to cache instructions, and the data cache L1D is used to cache data.

[0047] The instruction cache L1I and the data cache L1D included in the above first level cache L1 share the second level cache L2.

[0048] Referring to Figure 1As shown, in the multi-level cache processor architecture, a plurality of processor cores are included, for each processor core, a dedicated first level cache (including instruction cache L1I and data cache L1D) and a second level cache L2 are configured. The plurality of processor cores share a third level cache L3.

[0049] Continuing to refer to Figure 1 For the plurality of processor cores, different regions can also be divided, for each processor core in each region, a dedicated first level cache (including instruction cache L1I and data cache L1D) and a second level cache L2 are configured, and the processor cores in the region share a third level cache L3. The processor cores in the plurality of regions share the system main memory through the on-chip network.

[0050] In the above processor architecture, when a LOAD instruction misses the required read data in L1D, L1D will send a read request to L2 to read the data from L2. If the data is still not in L2, a read request is sent to L3 to read the data from L3. If the data is still not in L3, the data needs to be read from the main memory. In the above process, if the required read data is read in a certain level cache, the data is returned to the upper cache in turn until it is returned to the processor. For example, if the data is read from L2, the cache line where the data is located is returned to L1, and the cache line is stored in L1, and L1 returns the cache line to the processor.

[0051] Meanwhile, in the above multi-level cache data reading process, when a read-write request misses the required read-write data in a certain level cache, a buffer buffer area needs to be allocated for the request, and the request is temporarily stored in the buffer buffer area and requests data from the next level cache.

[0052] In the above case, if a subsequent read-write request with the same destination address is received, the read-write request is blocked and a buffer buffer area is allocated for it, and the read-write request is temporarily stored in the buffer buffer area allocated for it, and after the previous request is completed, the read-write request reenters the cache pipeline and re-reads the data from the cache.

[0053] For example, assuming that a first request for pre-fetching target data misses in the second level cache L2, that is, the required target data is not read from the second level cache L2, a buffer buffer area needs to be allocated for the first request in the second level cache L2, the first request is stored in the buffer buffer area, and the target data is requested from the third level cache L3, and the third level cache L3 returns the data. During the waiting process, if the second level cache L2 receives a second request with the same destination address as the first request, that is, the second request is also used to request the above target data, the second level cache L2 directly blocks the second request and allocates a buffer buffer area for the second request and stores the second request in the buffer buffer area.

[0054] When the third level cache L3 returns the above target data to the second level cache, the second level cache L2 first completes the response to the first request, and at the same time stores the target data locally in the second level cache L2. Then, the second request is restarted so that the second request re-enters the pipeline of the second level cache L2, so that the second request can hit the target data from the second level cache L2.

[0055] According to the above scheme, a buffer buffer area needs to be allocated in the cache for each miss request, and subsequent requests with the same destination address need to re-enter the pipeline, which affects the data reading efficiency.

[0056] In view of the above technical problems, the present application provides a data reading processing method, which can improve the efficiency of reading data from the cache by the processor.

[0057] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0058] The present application provides a data reading processing method, which can be applied to a processor cache, which can include Figure 1 Any cache in the multi-level cache processor architecture shown.

[0059] Referring to Figure 2 The data reading processing method provided by the embodiments of the present application includes:

[0060] S101, compare the read request destination address sent by the request source with the pre-fetch request destination address stored in the first buffer area.

[0061] Specifically, the request source refers to a higher-level cache or processor, processor core sending a read request to the processor cache. For example, for the first-level cache L1 shown in FIG. 1, the processor or processor core sends a read request to the first-level cache L1, and the processor or processor core is the request source of the read request. Figure 1 For the second-level cache L2 shown in FIG. 2, it receives the read request sent by the first-level cache L1, and thus the first-level cache L1 is the request source of the read request. Figure 1 For the third-level cache L3 shown in FIG. 3, it receives the read request sent by the second-level cache L2, and thus the second-level cache L2 is the request source of the read request. Figure 1

[0062] The first buffer is used to store a request for requested data that is not hit in the processor cache. Specifically, the first buffer refers to a buffer allocated for a prefetch request in a case where the prefetch request is received before the read request and the prefetch request does not hit prefetch data in the processor cache. The prefetch request is stored in the first buffer.

[0063] In some embodiments, when the processor cache receives a prefetch request sent by the request source, the processor cache queries the data corresponding to the prefetch request in the local cache data, that is, queries the data requested by the prefetch request in the local cache data.

[0064] If the data corresponding to the prefetch request is queried in the local cache data, the data is returned to the request source. If the data corresponding to the prefetch request is not queried in the local cache data, it can be confirmed that the data corresponding to the prefetch request does not exist in the local cache data. In this case, the processor cache allocates a first buffer for the prefetch request, stores the prefetch request in the first buffer, and sends a data request to the next-level storage to request the data corresponding to the prefetch request from the next-level storage.

[0065] The next-level storage refers to the next-level storage of the processor cache. For example, for the first-level cache L1 shown in FIG. 1, the next-level storage is the second-level cache L2, for the second-level cache L2, the next-level storage is the third-level cache L3, and for the third-level cache L3, the next-level storage is the system main memory. Figure 1

[0066] In some embodiments, one first buffer can be allocated for one prefetch request, or multiple first buffers can be shared by multiple prefetch requests. ​​

[0067] In the embodiment of the present application, when the processor cache receives the prefetch request, and confirms that the data corresponding to the prefetch request does not exist in the local cache data, and stores the prefetch request into the first buffer, in the process of waiting for the data returned by the next level storage, if the processor cache receives the read request sent by the request source, the destination address of the read request is compared with the destination address of the prefetch request in the first buffer, to determine whether the destination addresses of the two are the same, that is, to determine whether the read request and the prefetch request request the same data.

[0068] For example, in the architecture shown in FIG. 1, when the first level cache L1 sends a prefetch request to the second level cache L2, the second level cache L2 first queries the data corresponding to the prefetch request from the local cache data, if the corresponding data is not queried, the second level cache L2 allocates a first buffer for the prefetch request, then stores the prefetch request into the first buffer, and sends a request to the third level cache L3, to request the data corresponding to the prefetch request. Figure 1

[0069] In the process of waiting for the data returned by the third level cache L3, if the first level cache L1 sends a read request to the second level cache L2 again, the second level cache L2 compares the destination address of the read request with the destination address of the prefetch request in the first buffer, to determine whether the destination addresses of the two are the same.

[0070] S102, in the case of confirming that the read request and the prefetch request correspond to the same destination address, the return data corresponding to the prefetch request returned by the next level storage is determined as the return data of the read request.

[0071] Specifically, the processor cache can confirm that the read request and the prefetch request request the same data, in the case of confirming that the read request received and the prefetch request in the first buffer correspond to the same destination address.

[0072] When the next level storage returns the data corresponding to the prefetch request, the processor cache takes the returned data as the return data corresponding to the read request, that is, the data corresponding to the read request is obtained from the next level storage.

[0073] At this time, the processor cache can take the returned data as the return data of the read request, to complete the response to the read request, that is, the returned data is fed back to the request source sending the read request.

[0074] ​In addition, since the prefetch request stored in the first buffer also requests to obtain the data, the processor cache also takes the returned data as the returned data corresponding to the prefetch request, and fills the returned data into the processor cache, so that when subsequent other requests request the data from the processor cache, the data can be directly read from the processor cache locally.

[0075] It can be understood that, in the case that the above-mentioned prefetch request and the above-mentioned read request correspond to the same request source, the processor cache sends the above-mentioned returned data to the request source of the read request as the returned data corresponding to the read request, which is equivalent to returning the above-mentioned returned data to the request source of the prefetch request as the returned data corresponding to the prefetch request.

[0076] For the same target data, the request source sends a prefetch request to the processor cache to request the target data, in order to load the target data into the processor cache in advance before actually requesting the target data. Before the processor cache requests the target data from the next-level storage and returns the target data from the next-level storage, if the request source sends a read request to the processor cache to read the target data, the processor cache will block the read request and restart the read request after the prefetch is completed. In this case, when the next-level storage returns the target data corresponding to the prefetch request to the processor cache, the target data is directly taken as the returned data of the read request and fed back to the request source, which achieves the effect of the request source obtaining the target data, which is equivalent to achieving the purpose of the request source sending the prefetch request to the processor cache and achieving the purpose of the request source sending the read request to the processor cache. Moreover, compared with the conventional scheme, the embodiment scheme enables the read request to obtain the requested target data earlier.

[0077] As can be seen from the above description, in the case that the processor cache stores the prefetch request into the first buffer when confirming that the prefetch request is a miss, the data reading processing method provided by the embodiment compares the destination address of the read request sent by the request source with the destination address of the prefetch request stored in the first buffer when the read request is received again, and determines the data returned by the next-level storage corresponding to the above-mentioned prefetch request as the returned data corresponding to the above-mentioned read request when confirming that the destination addresses of the two are the same. The above-mentioned scheme can directly take the returned data as the returned data corresponding to the read request when the processor cache obtains the returned data corresponding to the prefetch request, without restarting the read request to request the data from the processor cache again, so as to improve the response efficiency of the read request and improve the efficiency of the processor reading data from the cache.

[0078] In another embodiment, referring to Figure 3As shown, the data reading processing method provided by the embodiment further performs step S202: in a case where it is confirmed that the read request and the prefetch request correspond to a same destination address, storing the read request to the first buffer.

[0079] Specifically, the processor cache can confirm that the read request and the prefetch request are used to request the same data in a case where it is confirmed that the received read request and the prefetch request in the first buffer correspond to a same destination address.

[0080] Since the prefetch request does not hit the requested data in the local cache data of the processor cache, according to a conventional processing idea, the processor cache should block the read request, and allocate a buffer for the read request to temporarily store the read request, and then read the read request from the buffer after the corresponding data is obtained from a next-level storage, restart the read request, and re-run the pipeline.

[0081] However, in the embodiment of the application, in a case where it is confirmed that the received read request and the prefetch request stored in the first buffer correspond to a same destination address, the processor cache no longer allocates a buffer for the read request, but directly stores the read request to the first buffer for storing the prefetch request, so that one buffer is saved compared with the conventional scheme.

[0082] In some embodiments, storing the read request to the first buffer can be storing the read request to a storage location in the first buffer different from the prefetch request.

[0083] Alternatively, in another embodiment, storing the read request to the first buffer can be replacing the prefetch request in the first buffer with the read request.

[0084] After performing the above step S202, the data reading processing method provided by the embodiment further includes step S203:

[0085] S203, in a case where return data corresponding to the prefetch request is obtained, determining the return data as return data of the read request.

[0086] Specifically, the processor cache can confirm that the read request and the prefetch request are used to request the same data in a case where it is confirmed that the received read request and the prefetch request in the first buffer correspond to a same destination address.

[0087] When the next level storage returns the data corresponding to the above-mentioned prefetch request, the processor cache takes the returned data as the returned data corresponding to the above-mentioned read request, that is, the data corresponding to the above-mentioned read request is obtained from the next level storage.

[0088] At this time, the processor cache can take the returned data as the returned data of the read request to complete the response to the read request, that is, the returned data is fed back to the request source sending the read request.

[0089] In addition, since the prefetch request stored in the first buffer also requests to obtain the data, the processor cache also takes the returned data as the returned data corresponding to the prefetch request, and fills the returned data into the processor cache, so that the data can be directly read from the local processor cache when the data is requested by subsequent other requests.

[0090] The data reading processing method provided in the embodiment can reduce the number of buffers in the processor cache while improving the efficiency of processing data read from the cache.

[0091] Figure 3 The steps S201 and S203 shown correspond to Figure 1 The steps S101 and S102 in the method embodiment can refer to the specific content of Figure 2 The corresponding introduction of the method embodiment is not repeated here.

[0092] In another embodiment, when the processor cache receives a prefetch request sent by a request source, the data corresponding to the prefetch request is queried from the local cache data of the processor cache.

[0093] If the data corresponding to the prefetch request is queried from the local cache data, the data is returned to the request source; if the data corresponding to the prefetch request is not queried from the local cache data, it can be confirmed that the data corresponding to the prefetch request does not exist in the local cache data, in which case the processor cache allocates a first buffer (buffer) for the prefetch request, stores the prefetch request to the first buffer (buffer), and sends a data request to the next level storage to request the data corresponding to the prefetch request from the next level storage.

[0094] In the above processing process, the processor cache sets the request sending state machine txreq and the backfill state machine fill, that is, the request sending state machine txreq and the backfill state machine fill are both set to an effective state. Wherein, the effective request sending state machine txreq indicates that the data is read from the next level storage, and the effective backfill state machine fill indicates that the data returned by the next level storage needs to be filled into the processor cache.

[0095] Based on the above operation, when the processor cache receives a read request sent by the request source, and determines that the read request corresponds to the same destination address as the prefetch request in the first buffer by comparing the destination address of the read request with the destination address of the prefetch request in the first buffer, the read request is used to replace the prefetch request in the first buffer.

[0096] At this time, the processor cache replaces the prefetch request in the first buffer with the read request, and retains the states of the request sending state machine txreq and the backfill state machine fill, that is, keeps the request sending state machine txreq and the backfill state machine fill in the active state, and sets the data return state machine fwd, that is, sets the data return state machine fwd to the active state, and the data return state machine fwd in the active state indicates that the data returned by the next level storage needs to be sent to the request source.

[0097] Based on the above operation, when the next level storage returns data to the processor cache, the processor cache detects the states of the above-mentioned state machines, and since the backfill state machine fill and the data return state machine fwd are both in the active state, the processor cache will perform the data backfill operation and the data return operation, that is, fill the returned data into the processor cache, and send the returned data to the request source, so as to complete the responses to the prefetch request and the read request at the same time.

[0098] In the above scheme, although the read request covers the prefetch request in the first buffer, the number of buffers is reduced, but the processor cache can complete the responses to the prefetch request and the read request through the states of the backfill state machine fill and the data return state machine fwd, and avoid missing the response processing of the expected request due to the read request covering the prefetch request.

[0099] In another embodiment, when the processor cache receives a prefetch request sent by the request source, the data corresponding to the prefetch request is queried from the local cache data of the processor cache.

[0100] If the data corresponding to the prefetch request is queried from the local cache data, the data is returned to the request source; if the data corresponding to the prefetch request is not queried from the local cache data, it can be confirmed that there is no data corresponding to the prefetch request in the local cache data, and in this case, the processor cache allocates a first buffer (buffer) for the prefetch request, stores the prefetch request to the first buffer (buffer), and sends a data request to the next level storage to request the data corresponding to the prefetch request from the next level storage.

[0101] In the above process, the processor cache sets the sending request state machine txreq and the backfill state machine fill, i.e., sets the sending request state machine txreq and the backfill state machine fill to be valid. The valid sending request state machine txreq indicates that the sending request state machine txreq sends a request to the next level storage to read data, and the valid backfill state machine fill indicates that the data returned by the next level storage needs to be filled into the processor cache.

[0102] Based on the above operation, when the processor cache receives a read request sent by a request source, and determines that the read request corresponds to a same destination address as a prefetch request in the first buffer by comparing a destination address of the read request with a destination address of the prefetch request in the first buffer, the processor cache allocates a second buffer for the read request, stores the read request in the second buffer, and allocates a sub-buffer in the second buffer, and stores the prefetch request in the first buffer in the sub-buffer. Meanwhile, the backfill state machine fill and the data return state machine fwd are set, i.e., the states of the backfill state machine fill and the data return state machine fwd are set to be valid. The valid data return state machine fwd indicates that the data returned by the next level storage needs to be sent to the request source.

[0103] When the processor cache receives the returned data sent by the next level storage, the request corresponding to the returned data is compared with the request in the sub-buffer in the second buffer.

[0104] If the request corresponding to the returned data is consistent with the request in the sub-buffer, i.e., corresponds to a same destination address, the processor cache writes the returned data into the second buffer, releases the first buffer, and determines the returned data as the returned data corresponding to the read request in the second buffer.

[0105] At this time, the processor cache detects the states of the above state machines. Since the backfill state machine fill and the data return state machine fwd are both valid, the processor cache performs the data backfill operation and the data return operation, i.e., fills the returned data into the processor cache and sends the returned data to the request source, thereby simultaneously completing the responses to the prefetch request and the read request.

[0106] The above scheme transfers the prefetch request to the second buffer allocated for the read request when determining that the read request corresponds to a same destination address as the prefetch request, and releases the first buffer used to store the prefetch request in time when receiving the returned data sent by the next level storage, thereby reducing the survival time of the first buffer and being beneficial to reducing the number of buffers in the processor cache.

[0107] Correspondingly, the application also provides a cache controller applied to a processor cache, in some embodiments, the processor cache can include Figure 1 any cache in the multi-level cache processor architecture shown.

[0108] The cache controller includes:

[0109] a comparison unit configured to compare a destination address of a read request sent by a request source with a destination address of a prefetch request stored in a first buffer; the first buffer is configured to store a request for requested data that is not hit in the processor cache;

[0110] a response unit configured to, in a case where it is confirmed that the read request and the prefetch request correspond to the same destination address, determine return data corresponding to the prefetch request returned by a next-level storage as return data of the read request.

[0111] In some implementations, the apparatus further includes:

[0112] a storage unit configured to, in a case where the prefetch request sent by the request source is received, query data corresponding to the prefetch request from local cache data;

[0113] in a case where it is confirmed that the data corresponding to the prefetch request does not exist in the local cache data, allocate the first buffer for the prefetch request, store the prefetch request to the first buffer, and send a data request to the next-level storage; the data request is configured to request the data corresponding to the prefetch request.

[0114] In some implementations, the storage unit is further configured to:

[0115] in a case where it is confirmed that the read request and the prefetch request correspond to the same destination address, store the read request to the first buffer.

[0116] In some implementations, the storage unit stores the read request to the first buffer, including:

[0117] replacing the prefetch request in the first buffer with the read request.

[0118] In some implementations, the storage unit is further configured to:

[0119] in a case where it is confirmed that the data corresponding to the prefetch request does not exist in the local cache data, set a request state machine and a backfill state machine to an active state; wherein the backfill state machine in the active state indicates that data returned by the next-level storage needs to be filled into the processor cache.

[0120] The storage unit replaces the prefetch request in the first buffer with the read request, including:

[0121] replacing the prefetch request in the first buffer with the read request, keeping the request sending state machine and the backfill state machine in an active state, and setting a data returning state machine to an active state; wherein the data returning state machine in the active state indicates that data returned by the next level storage needs to be sent to the request source.

[0122] In some implementations, the storage unit is further configured to:

[0123] setting the request sending state machine and the backfill state machine to the active state upon confirming that the data corresponding to the prefetch request does not exist in the local cache data; wherein the backfill state machine in the active state indicates that data returned by the next level storage needs to be filled into the processor cache.

[0124] upon confirming that the read request corresponds to the same destination address as the prefetch request, storing the read request to a second buffer, setting a data returning state machine to an active state, and storing the prefetch request to a sub-buffer in the second buffer; wherein the data returning state machine in the active state indicates that data returned by the next level storage needs to be sent to the request source.

[0125] The response unit is further configured to:

[0126] upon receiving the returned data, comparing the request corresponding to the returned data with the requests in the sub-buffer;

[0127] upon confirming that the request corresponding to the returned data is consistent with the request in the sub-buffer, writing the returned data to the second buffer and releasing the first buffer, and determining the returned data as the returned data of the read request.

[0128] The cache controller provided by the embodiment belongs to the same application concept as the data reading processing method provided by the above embodiments of the application, can execute the data reading processing method provided by any of the above embodiments of the application, and has the corresponding function modules and beneficial effects of the execution method. Technical details not described in detail in the embodiment can be referred to the specific processing content of the data reading processing method provided by the above embodiments of the application, which will not be described here.

[0129] The functions implemented by the above various units can be respectively implemented by the same or different processors, and the embodiments of the application are not limited.

[0130] It should be understood that the units in the above apparatus can be implemented in the form of processor calling software. For example, the apparatus includes a processor connected with a memory, the memory stores instructions, and the processor calls the instructions stored in the memory to implement any of the above methods or realize the functions of the units of the apparatus, wherein the processor can be a general processor such as CPU or microprocessor, and the memory can be an internal memory or an external memory of the apparatus. Alternatively, the units in the apparatus can be implemented in the form of hardware circuit, and the functions of part or all of the units can be realized by the design of the hardware circuit, which can be understood as one or more processors. For example, in one implementation, the hardware circuit is ASIC, and the functions of part or all of the units are realized by the design of the logical relationship of the elements in the circuit. For another example, in another implementation, the hardware circuit can be realized by PLD, and taking FPGA as an example, it can include a large number of logic gate circuits, and the connection relationship between the logic gate circuits is configured by a configuration file, so as to realize the functions of part or all of the units. All the units of the above apparatus can be realized in the form of processor calling software, or realized in the form of hardware circuit, or part of them are realized in the form of processor calling software, and the remaining part is realized in the form of hardware circuit.

[0131] In the embodiments of the present application, the processor is a circuit with signal processing capability. In one implementation, the processor can be a circuit with instruction reading and running capability, such as CPU, microprocessor, GPU, or DSP, etc. In another implementation, the processor can realize certain functions through the logical relationship of hardware circuit, which is fixed or can be reconfigured, such as ASIC or PLD implemented hardware circuit, such as FPGA, etc. In the reconfigurable hardware circuit, the process of the processor loading configuration document to realize hardware circuit configuration can be understood as the process of the processor loading instructions to realize the functions of part or all of the units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as a kind of ASIC, such as NPU, TPU, DPU, etc.

[0132] It can be seen that each unit in the above apparatus can be one or more processors (or processing circuits) configured to implement the above methods, such as CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0133] In addition, all or part of each unit in the above apparatus can be integrated together or can be independently implemented. In one implementation, the units are integrated together to be implemented in the form of a SOC. The SOC can include at least one processor for implementing the functions of any of the above methods or implementing the functions of the units of the apparatus. The at least one processor can be of different types, such as a CPU and an FPGA, a CPU and an artificial intelligence processor, a CPU and a GPU, and the like.

[0134] Another embodiment of the present application also provides a processor including a cache, the processor being configured to perform the data reading processing method according to any of the above embodiments, or the processor including the cache controller according to any of the above embodiments.

[0135] In another embodiment of the present application, a multi-level cache processor architecture is also provided, as shown in Figure 1 The multi-level cache processor architecture includes a first level cache L1, a second level cache L2, a third level cache L3, and a plurality of processor cores. For each of the processor cores, a dedicated first level cache L1 and a dedicated second level cache L2 are respectively configured, and the plurality of processor cores share the third level cache L3. At least one of the first level cache L1, the second level cache L2, and the third level cache L3 is configured to implement the data reading processing method according to any of the above embodiments, or the multi-level cache processor architecture includes the cache controller according to any of the above embodiments.

[0136] Another embodiment of the present application also provides a computer device including the cache controller according to any of the above embodiments, or including the processor according to any of the above embodiments, or including the multi-level cache processor architecture according to any of the above embodiments.

[0137] Another embodiment of the present application also provides an electronic device, as shown in Figure 4 The device includes:

[0138] a memory 200 and a processor 210;

[0139] The memory 200 is connected to the processor 210 and is configured to store programs.

[0140] The processor 210 is provided with a cache or a multi-level cache, and the processor 210 is configured to implement the data reading processing method according to any of the above embodiments by running the programs stored in the memory 200.

[0141] Specifically, the electronic device can further include a bus, a communication interface 220, an input device 230, and an output device 240.

[0142] The processor 210, the memory 200, the communication interface 220, the input device 230 and the output device 240 are connected to each other through a bus. Among them:

[0143] The bus can include a path for transmitting information between various components of the computer system.

[0144] The processor 210 can be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs of the present application. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a ready-to-use programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0145] The processor 210 can include a main processor, and can also include a baseband chip, a modem, etc.

[0146] The memory 200 stores programs for executing the technical solutions of the present application, and can also store operating systems and other key services. Specifically, the program can include program code, and the program code includes computer operation instructions. More specifically, the memory 200 can include read-only memory (ROM), other types of static storage devices that can store static information and instructions, random access memory (RAM), other types of dynamic storage devices that can store information and instructions, disk storage, flash, etc.

[0147] The input device 230 can include a device that receives data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer or a gravity sensor, etc.

[0148] The output device 240 can include a device that allows information to be output to a user, such as a display screen, a printer, a speaker, etc.

[0149] The communication interface 220 can include a device using any transceiver to communicate with other devices or communication networks, such as Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0150] The processor 210 executes the program stored in the memory 200 and calls other devices, which can be used to implement each step of any one of the data reading processing methods provided by the embodiments of the present application.

[0151] The embodiment of the present application also provides a chip, which comprises a processor and a data interface, the processor reads and runs a program stored on a memory through the data interface to execute the data reading processing method described in any of the above embodiments, and the specific processing process and advantages can be referred to the above description of the data reading processing method.

[0152] In addition to the above method and device, the embodiment of the present application can also be a computer program product, which comprises computer program instructions, the computer program instructions enable the processor to execute the steps of the data reading processing method described in any of the above embodiments of the present application when the computer program instructions are run by the processor.

[0153] The computer program product can be written in any combination of one or more programming languages to perform the operations of the embodiments of the present application, including object-oriented programming languages, such as Java, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0154] In addition, the embodiment of the present application can also be a storage medium, which stores a computer program, and the computer program enables the processor to execute the steps of the data reading processing method described in any of the above embodiments of the present application.

[0155] For each of the above method embodiments, in order to simply describe, it is expressed as a combination of a series of actions, but those skilled in the art should know that the present application is not limited to the order of the described actions, because according to the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0156] It should be noted that each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same and similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0157] The steps in the method of each embodiment of the present application can be adjusted, combined and reduced in sequence according to actual needs, and the technical features recorded in each embodiment can be replaced or combined.

[0158] The modules and sub-modules in the device and terminal of the embodiments of the present application can be combined, divided, and deleted according to actual needs.

[0159] In several embodiments provided by the present application, it should be understood that the disclosed terminal, device, and method can be implemented by other manners. For example, the terminal embodiments described above are only illustrative, for example, the division of the modules or sub-modules is only a logical function division, and actual implementation can have another division manner, for example, a plurality of sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed ones can be indirect coupling or communication connection through some interfaces, devices, or modules, which can be electrical, mechanical, or other forms.

[0160] The modules or sub-modules described as separate components can or can not be physically separated, and the components as modules or sub-modules can or can not be physical modules or sub-modules, that is, can be located in one place, or can be distributed to a plurality of network modules or sub-modules. Part or all of the modules or sub-modules can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0161] In addition, each functional module or sub-module in each embodiment of the present application can be integrated in one processing module, or each module or sub-module can exist physically, or two or more modules or sub-modules can be integrated in one module. The integrated module or sub-module can be realized in the form of hardware or software functional module or sub-module.

[0162] The skilled person can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software, or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in general terms in the above description. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0163] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, software units executed by a processor, or a combination of both. The software units can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the technical field.

[0164] Finally, it should be noted that, in the description above, relative terms such as first and second, etc. are merely used to distinguish one entity or action from another, without necessarily requiring or implying any such actual relationship or order between such entities or actions. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0165] The above description of disclosed embodiments provides enabling teaching for making or using the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data reading and processing method, characterized in that, Applied to processor cache, the method includes: The destination address of the read request sent by the request source is compared with the destination address of the prefetch request stored in the first buffer; the first buffer is used to store requests for data that were not hit in the processor cache. If it is confirmed that the read request and the prefetch request correspond to the same destination address, the return data returned by the next level storage corresponding to the prefetch request is determined as the return data of the read request.

2. The method according to claim 1, characterized in that, The method further includes: Upon receiving the prefetch request sent by the request source, the data corresponding to the prefetch request is queried from the local cache data of the processor cache; If it is confirmed that the data corresponding to the prefetch request does not exist in the local cache data, the first buffer is allocated for the prefetch request, the prefetch request is stored in the first buffer, and a data request is sent to the next level of storage; the data request is used to request the data corresponding to the prefetch request.

3. The method according to claim 1 or 2, characterized in that, If it is confirmed that the read request and the prefetch request correspond to the same destination address, the method further includes: The read request is stored in the first buffer.

4. The method according to claim 3, characterized in that, Storing the read request into the first buffer includes: The read request replaces the prefetch request in the first buffer.

5. The method according to claim 4, characterized in that, The method further includes: If it is confirmed that the data corresponding to the prefetch request does not exist in the local cache data, the request sending state machine and the backfilling state machine are set to the valid state; wherein, the backfilling state machine being in the valid state indicates that the data returned by the next level of storage needs to be filled into the processor cache; Replacing the prefetch request in the first buffer with the read request includes: Replace the prefetch request in the first buffer with the read request, keep the request sending state machine and the backfilling state machine in a valid state, and set the data return state machine to a valid state; wherein, the data return state machine being in a valid state indicates that the data returned by the next level of storage needs to be sent to the request source.

6. The method according to claim 1 or 2, characterized in that, The method further includes: If it is confirmed that the data corresponding to the prefetch request does not exist in the local cache data, the request sending state machine and the backfilling state machine are set to the valid state; wherein, the backfilling state machine being in the valid state indicates that the data returned by the next level of storage needs to be filled into the processor cache; If it is confirmed that the read request and the prefetch request correspond to the same destination address, the method further includes: The read request is stored in the second buffer, the data return state machine is set to a valid state, and the prefetch request is stored in a sub-buffer within the second buffer; wherein, the data return state machine being in a valid state indicates that the data returned by the next level of storage needs to be sent to the request source; Upon receiving the returned data, the request corresponding to the returned data is compared with the request in the sub-buffer; If it is confirmed that the request corresponding to the returned data is consistent with the request in the sub-buffer, the returned data is written to the second buffer and the first buffer is released, and the returned data is determined to be the returned data of the read request.

7. A cache controller, characterized in that, The cache controller is applied to the processor cache and includes: The comparison unit is used to compare the destination address of the read request sent by the request source with the destination address of the prefetch request stored in the first buffer; the first buffer is used to store requests for data that were not hit in the processor cache. The response unit is configured to, upon confirming that the read request and the prefetch request correspond to the same destination address, determine the return data corresponding to the prefetch request returned by the next level storage as the return data of the read request.

8. A processor, characterized in that, The processor includes a cache, and the processor is configured to implement the data read processing method as described in any one of claims 1 to 6, or the processor includes a cache controller as described in claim 7.

9. A multi-level cache processor architecture, characterized in that, The multi-level cache processor architecture includes a multi-level cache, wherein at least one level of the multi-level cache is configured to implement the data read processing method as described in any one of claims 1 to 6, or the multi-level cache processor architecture includes a cache controller as described in claim 7.

10. A computer device, characterized in that, It includes the cache controller as described in claim 7, or the processor as described in claim 8, or the multi-level cache processor architecture as described in claim 9.

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