Multi-pulse programming method and programming circuit of FeMFET memory cell

Abstract

The invention relates to a multi-pulse programming method and a multi-pulse programming circuit for a FeMFET (FeMFET) memory cell. The multi-pulse programming method of the FeMFET memory cell comprises the following steps: configuring the FeMFET memory cell to enter a write-in operation state; in response to the fact that the FeMFET storage unit enters a write-in operation state, at least two programming pulses are continuously applied to the FeMFET storage unit for programming, and all the programming pulses can enable the FeMFET storage unit to be programmed to a preset programming state; configuring the FeMFET memory cell to enter a read operation state; in response to the FeMFET memory cell entering a read operation state, reading a program state of the FeMFET memory cell to verify whether the FeMFET memory cell is programmed to a predetermined program state; repeating the above steps until the programming state of the FeMFET memory cell is verified to be a predetermined programming state or the predetermined maximum number of repetitions of the write-verification period; the write-in-verification period is to execute one round of the steps.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of non-volatile memory, in particular to a multi-pulse programming method and a programming circuit for FeMFET memory cells. BACKGROUND

[0002] With the increasing demand for density and performance of non-volatile memory, ferroelectric metal field effect transistor (FeMFET) memory has become an important development direction due to its high speed, low power consumption and high durability. However, the existing programming technology of ferroelectric metal field effect transistor (FeMFET) memory faces two major challenges: non-perfect writes and chaotic switching. Non-perfect writes result in partial write operation failure, and chaotic switching causes accidental writing of non-target states (such as writing a "1" state when the target is a "0" state) in the memory cell, which seriously reduces the write reliability.

[0003] To ensure data integrity, the existing technology adopts a write-verify cycle method for programming, which involves performing a verification operation after each write pulse. The specific process includes write setting (about 200 ns), programming single pulse application (about 20 ns), read setting (about 200 ns), and sensing verification (about 50 ns). If the verification fails, the entire process needs to be repeated.

[0004] This write-verify method requires repeating write setting and read setting after each failure, resulting in a large proportion of programming time being occupied by setting time in the entire process. The high frequency and high delay of setting operations in the entire programming process. SUMMARY

[0005] To solve the defects of the existing technology, the purpose of the present application is to provide a multi-pulse programming method and a programming circuit for FeMFET memory cells, which improves the efficiency of programming and reduces the programming delay.

[0006] To achieve the above-mentioned purpose, the present application provides a multi-pulse programming method for FeMFET memory cells, comprising: configuring the FeMFET memory cell to enter a write operation state; in response to the FeMFET memory cell entering the write operation state, continuously applying at least two programming pulses to the FeMFET memory cell for programming, each programming pulse being capable of programming the FeMFET memory cell to a predetermined programming state; configuring the FeMFET memory cell to enter a read operation state; in response to the FeMFET memory cell entering a read operation state, reading the programming state of the FeMFET memory cell to verify whether it is programmed to a predetermined programming state; repeating the above steps until the programming state of the FeMFET memory cell is verified to be the predetermined programming state or a predetermined maximum number of write-verify cycles is reached; the write-verify cycle is one round of the above steps.

[0007] Further, the method further comprises: based on the write success rate of a single programming pulse, setting the number of programming pulses so that the integrated write success rate in a predetermined number of write-verify cycles meets a predetermined write success rate.

[0008] Further, the specific step of setting the number of programming pulses based on the write success rate of a single programming pulse so that the integrated write success rate in a predetermined number of write-verify cycles meets a predetermined write success rate adopts the following formula: ; ; ; wherein K is the number of write-verify cycles, is the write success rate of a single programming pulse, is the number of programming pulses applied in one write-verify cycle, is the integrated write success rate after K cycles, is the write success rate of a single cycle, is the predetermined write success rate.

[0009] Further, the method further comprises: based on the write success rate of a single programming pulse and the chaotic switching probability, setting the number of programming pulses so that the integrated write success rate in a predetermined number of write-verify cycles meets a predetermined write success rate, and the specific step adopts the following formula: ; ; wherein K is the number of write-verify cycles, is the write success rate of a single programming pulse, is the number of programming pulses applied in one write-verify cycle, is the chaotic switching probability, is the integrated write success rate after K cycles, is the write success rate after the previous K-1 cycles, is the predetermined write success rate.

[0010] Further, the method further comprises: determining a minimum number of write-verify cycles satisfying a predetermined write success rate based on the number of programming pulses and the write success rate of a single programming pulse, according to the following formula: ; wherein K is the number of write-verify cycles, is the write success rate of a single programming pulse, is the number of programming pulses applied in one write-verify cycle, is the predetermined write success rate.

[0011] Further, the method further comprises: dynamically adjusting the number of programming pulses applied in each write-verify cycle based on the state of the FeMFET memory cell.

[0012] Further, the specific steps of configuring the FeMFET memory cell into a write operation state comprise: address decoding of the FeMFET memory cell, operation voltage generation, and pre-charging of the bit line.

[0013] Further, the specific steps of configuring the FeMFET memory cell into a read operation state comprise: address decoding of the FeMFET memory cell, operation voltage generation, pre-charging of the bit line, and configuring the multiplexer.

[0014] To achieve the above object, the present application further provides a programming circuit of a FeMFET memory cell, comprising: a memory array comprising a plurality of FeMFET memory cells; a write unit connected to the memory array and configured to apply programming pulses to selected FeMFET memory cells in the memory array for programming; a read unit connected to the memory array and configured to read the programming state of selected FeMFET memory cells in the memory array; a control unit connected to the write unit and the read unit and configured to: control the write unit and the read unit to perform the multi-pulse programming method of the FeMFET memory cell as described above.

[0015] Further, the write unit comprises a pulse generator configured to output programming pulses adapted to the FeMFET memory cell.

[0016] Further, the control unit disables the write unit and the read unit when a predetermined maximum number of repetitions of write-verify cycles is reached.

[0017] Further, the read unit comprises a sense amplifier coupled to a bit line of the memory array through a multiplexing switch.

[0018] Further, the read unit comprises a sense amplifier coupled to a bit line of the memory array through a multiplexing switch. Error correction logic unit, the error correction logic unit is connected with the read unit, is used in using ECC to verify the data integrity of read FeMFET storage unit.

[0019] Further, the control unit is further configured to dynamically adjust the number of programming pulses applied by the write unit within each write-verify cycle.

[0020] The multi-pulse programming method and programming circuit of the FeMFET storage unit provided by the present application adopt a single-cycle multi-pulse write-verify programming method, which can reduce the number of write-verify cycles, avoid high-frequency setup time, improve the write efficiency of the FeMFET storage unit, and reduce write delay.

[0021] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, and together with the embodiments of the present application, serve to explain the present application, and do not constitute a limitation on the present application. In the drawings: Figure 1 A write-verify cycle schematic diagram of the multi-pulse programming method of the FeMFET storage unit of the prior art; Figure 2 A success rate and delay test schematic diagram of the prior art under different single programming pulse write success rates; Figure 3 A flowchart schematic diagram of the multi-pulse programming method of the FeMFET storage unit of the embodiment 1 of the present application; Figure 4 A write-verify cycle schematic diagram of the multi-pulse programming method of the FeMFET storage unit of the embodiment 1 of the present application; Figure 5 A success rate and delay test schematic diagram of the embodiment 1 of the present application under a single programming pulse write success rate of 50%; Figure 6 A success rate and delay test schematic diagram of the embodiment 1 of the present application under chaotic interference; Figure 7 A structure schematic diagram of the programming circuit of the FeMFET storage unit of the embodiment 2 of the present application. DETAILED DESCRIPTION

[0023] The preferred embodiments of the present application will be described herein below with reference to the accompanying drawings; it should be understood that the preferred embodiments described herein are merely used to explain and illustrate the present application, and should not be used to limit the present application.

[0024] Embodiments of the present application will be described in more detail by referring to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms, and should not be interpreted as being limited to the embodiments set forth herein, but rather, these embodiments are provided to make the present application more thorough and complete. It should be understood that the drawings and embodiments of the present application are merely for exemplary purposes, and should not be used to limit the scope of protection of the present application.

[0025] The term “comprising” and variations thereof as used herein are open-ended, that is “including, but not limited to”. The term “based on” is “based, at least in part, on”. The term “one embodiment” means “at least one embodiment”; the term “another embodiment” means “at least one additional embodiment”; the term “some embodiments” means “at least some embodiments”.

[0026] It should be noted that the terms “first”, “second”, etc. mentioned in the present application are only used to distinguish different devices, components or parts, and are not used to limit the order or interdependence of the functions performed by these devices, components or parts.

[0027] It should be noted that the modification of “one”, “multiple” mentioned in the present application is illustrative and not restrictive, and those skilled in the art should understand that unless otherwise explicitly indicated in the context, it should be understood as “one or more”. “Multiple” should be understood as two or more.

[0028] Figure 1 Write-verify cycle schematic diagram of the programming method for the prior art storage unit; as shown in Figure 1 The entire method is performed in a write-verify cycle. In a write-verify cycle, during writing, first, a write operation is started (i.e. write setting), then a write programming pulse is generated to program. During verification, first, a read operation is started (i.e. read setting), then read sensing is performed. As shown in Figure 2As shown, in each write-verify cycle, time is needed for write operation start and read operation start, and when the write success rate of single pulse is not high, multiple verifications are often needed to write successfully, resulting in the entire write process being wasted in write operation start and read operation start. For example, when the write success rate of single programming pulse is only 50%, 8 write-verify cycles are needed to achieve a total success rate of 99.7% (3σ standard), wherein the write operation start time is 200 ns, the programming pulse programming time is 20 ns, the read operation start time is 200 ns, and the read sensing time is 50 ns, resulting in a delay of up to 8 × (200 + 20 + 200 + 50) = 3.76 μs. Among them, the time of write operation start and read operation start accounts for more than 85% of the total time, the programming efficiency is low, and the delay is large.

[0029] Figure 2 The success rate and delay test schematic diagram of the prior art under different write success rates of single programming pulse is as follows: Figure 2 As shown, when the write success rate of single programming pulse is 50%, 8 write-verify cycles are needed to achieve a total success rate of 99.7% (3σ standard), and the delay is 3.76 μs; when the write success rate of single programming pulse is 75%, 4 write-verify cycles are needed to achieve a total success rate of 99.7% (3σ standard), and the delay is 1.88 μs; when the write success rate of single programming pulse is 90%, 2 write-verify cycles are needed to achieve a total success rate of 99.7% (3σ standard), and the delay is 0.94 μs.

[0030] Therefore, the present application provides a multi-pulse programming method of FeMFET storage unit to improve programming efficiency and reduce programming delay.

[0031] Embodiment 1 In the embodiments of the present application, a multi-pulse programming method of FeMFET storage unit is provided, Figure 3 The flowchart of the multi-pulse programming method of FeMFET storage unit of Embodiment 1 of the present application is shown below, and the multi-pulse programming method of FeMFET storage unit of the present application will be described in detail below. Figure 3 The multi-pulse programming method of FeMFET storage unit of the present application is described in detail as follows: Step S101: configure the FeMFET storage unit to enter a write operation state; It can be understood that before writing operation is performed on the FeMFET storage unit, some configurations are needed to make the FeMFET storage unit enter the write operation state, such as preparing the write operation voltage to meet the needs of the FeMFET storage unit, address decoding to map the logical address to the physical FeMFET storage unit, and then configuring the potential line corresponding to the FeMFET storage unit to pre-charge.

[0032] In the embodiment, the FeMFET memory cell is a 2T1FC memory cell.

[0033] In some other embodiments, the FeMFET memory cell can also be a 1T1FC memory cell, a 2T2FC memory cell, and a 3T2FC FeMFET memory cell integrated with transistors and ferroelectric capacitors.

[0034] Step S102: in response to the FeMFET memory cell entering a write operation state, continuously applying at least two programming pulses to the FeMFET memory cell for programming; In the embodiment, four programming pulses are continuously applied to the FeMFET memory cell, and the pulse amplitude and bandwidth of each programming pulse can program the FeMFET memory cell to a predetermined programming state.

[0035] Step S103: configuring the FeMFET memory cell to enter a read operation state; It can be understood that before the FeMFET memory cell is read, some configurations are needed to make the FeMFET memory cell enter a read operation state, such as preparing read operation voltages to meet the needs of the FeMFET memory cell, address decoding to map logical addresses to physical FeMFET memory cells to configure pre-charging of the potential lines corresponding to the FeMFET memory cells, and setting multiplexers to send subsequent read signals to sensing circuits for sensing verification.

[0036] Step S104: in response to the FeMFET memory cell entering a read operation state, reading the programming state of the FeMFET memory cell to verify whether it is programmed to a predetermined programming state.

[0037] Step S105: repeating the above steps S101-S104 until the programming state of the FeMFET memory cell is verified to be a predetermined programming state or the predetermined maximum number of write-verify cycles is verified.

[0038] Figure 4 The write-verify cycle of the multi-pulse programming method of the FeMFET memory cell of Embodiment 1 of the present application is shown in the figure. Figure 4 As shown, the time of one write-verify cycle includes the time tWS of write operation start, the programming time (the product of the single programming pulse time tWP and the programming number m), the time tRS of read operation start, and the read sensing time tSEN.

[0039] In the embodiment, the time tWS of operation start is the time of configuring the FeMFET memory cell to enter a write operation state, which is 200 ns. In this embodiment, the programming time is the sum of the programming time of 4 single programming pulses (4 times tWP, tWP is 20 ns), which is 80 ns.

[0040] In this embodiment, the time tRS at which the read operation is initiated is the time at which the FeMFET memory cell is configured to enter the read operation state, which is 200 ns.

[0041] In this embodiment, the time (tSEN) for verification is 50 ns.

[0042] That is, the delay of one write-verify cycle is 530 ns.

[0043] Assuming that the write success rate of a single programming pulse is 50%, when writing is performed by the method of this embodiment, only 2 write-verify cycles are needed to ensure that the write success rate is not less than 99.7%, and the total delay is 1.06 μs, which is reduced by about 71% compared to the prior art.

[0044] In other embodiments, the number of programming pulses of each write-verify cycle can be dynamically adjusted according to the state of the FeMFET memory cell, such as the working environment and aging characteristics.

[0045] For example, if the initiation time of the write operation (tWS) = 200 ns, the duration of the single programming pulse (tWP) = 100 ns, the number of write pulses (m) = 4, the initiation time of the read operation (tRS) = 100 ns, and the time for read sensing (tSEN) = 150 ns, the time of one write-verify cycle is 850 ns. When writing is performed, a sequence of 4 short write pulses (write pulses, i.e., programming pulses) is applied. Each pulse polarizes the ferroelectric gate portion, thereby gradually approaching the target state. When read verification is performed, if the predetermined programming state is reached (verified based on the threshold or current window), the cycle ends; if the predetermined programming state is not reached, additional write pulses are applied in the next write-verify cycle, i.e., the number of write pulses (m) is increased, until verification ends.

[0046] It can be understood that the number of programming pulses can be set based on the write success rate of a single programming pulse, so that the comprehensive write success rate within a predetermined number of write-verify cycles meets a predetermined write success rate, and the formula is as follows: ; ; ; wherein K is the number of write-verify cycles, The write success rate for a single programming pulse. The number of programming pulses applied within a write-verify cycle. The overall write success rate after K cycles. This refers to the write success rate per cycle. This is the target write success rate.

[0047] Therefore, it can be concluded that when aiming to achieve a comprehensive write success rate greater than or equal to the predetermined write success rate within a predetermined number of K write-verification cycles... ,but: .

[0048] In other implementations, when the number of programming pulses and the write success rate of a single programming pulse are determined, the number of write-verification cycles required to achieve a predetermined write success rate can be determined using the following formula: .

[0049] Figure 5 This is a schematic diagram illustrating the success rate and latency test of Embodiment 1 of this application at a write success rate of 50% per programming pulse. Figure 5 As shown, when the write success rate of a single pulse is 50%, to achieve the predetermined write success rate of 99.7%, if the number of programming pulses m applied in one write-verify cycle is 2, it requires 4 write-verify cycles with a delay of 1.96μs. If the number of programming pulses m applied in one write-verify cycle is 4, it requires 2 write-verify cycles with a delay of 1.06μs.

[0050] Therefore, given a fixed write success rate for a single programming pulse, the more programming pulses applied within a write-verify cycle, the fewer write-verify cycles are required to achieve the predetermined write success rate, resulting in lower latency.

[0051] Understandably, the maximum number of write-verify cycles should be greater than the number of write-verify cycles required to achieve the predetermined write success rate.

[0052] In other implementations, due to the presence of chaotic switches, the number of programming pulses can be set based on the write success rate of a single programming pulse and the probability of chaotic switches, so that the overall write success rate within a predetermined number of write-verification cycles meets a predetermined write success rate. The specific steps are illustrated by the following formula: ; ; Where K is the number of write-verify cycles, the write success rate of a single programming pulse, the number of programming pulses applied in a write-verify cycle, the chaotic switching probability, the overall write success rate after the Kth cycle, the write success rate after the first K-1 cycles, the predetermined write success rate.

[0053] It can be understood that the higher the write success rate of a single programming pulse the smaller the number of programming pulses applied in a write-verify cycle, the smaller the number of write-verify cycles required to meet the predetermined write success rate; the greater the chaotic switching probability the greater the number of programming pulses applied in a write-verify cycle, the greater the number of write-verify cycles required to meet the predetermined write success rate.

[0054] Figure 6 The success rate and delay test schematic diagram of the multi-pulse programming method of the FeMFET storage unit of Embodiment 1 of the present application under chaotic interference is as shown in Figure 6 When the write success rate of a single pulse is 50% and the chaotic switching probability is 25%, in order to achieve a predetermined write success rate of 99.7%, if the number of programming pulses applied in a write-verify cycle m is 2, 5 write-verify cycles are required, with a delay of 2.45 μs; if the number of programming pulses applied in a write-verify cycle m is 3, 5 write-verify cycles are required, with a delay of 2.55 μs; if the number of programming pulses applied in a write-verify cycle m is 4, 5 write-verify cycles are required, with a delay of 2.65 μs.

[0055] Figure 6As shown, using prior art (m = 1): each write-verify cycle only applies 1 high-energy program pulse, due to variability or charge fluctuations, the write can fail, especially in a chaotic environment, as can be seen from the yellow curve (m = 1), even after 5 attempts, the success rate can only reach 90%, and slowly converges to 99.7%. While using the multi-pulse programming method (m = 3 or 4): in a single write-verify cycle, 3-4 smaller program pulses are applied to gradually polarize the ferroelectric gate for programming, which can reduce over-programming or under-programming, after only 3 write-verify cycles, the success rate is already over 99%, and reaches 3-sigma (99.7%) at the 4th write-verify. Therefore, when there is chaotic interference, increasing the number of program pulses m applied in the write-verify cycle can reduce the number of total write-verify cycles required and improve robustness, without significantly increasing the total write time.

[0056] It can be understood that the higher the number of program pulses m, the longer the programming time (tWP x m). The number of program pulses m and the predetermined maximum number of repetitions of write-verify must be set in combination with the speed, power consumption and reliability requirements, if the environment is stable (low F): a lower number of program pulses m (1-2) and a larger predetermined maximum number of repetitions are possible. If there is chaotic interference or strict reliability specifications (such as AI accelerators or military storage), using m = 3 or 4 can reduce the write failure rate and achieve 3σ success rate faster.

[0057] As shown in Figure 6 , the number of program pulses m = 3 or 4 significantly improves the write success rate of the FeMFET memory, especially under chaotic switching conditions.

[0058] The multi-pulse programming method of the FeMFET memory cell of Embodiment 1 of the present application improves the programming accuracy, uses multiple low-energy pulses to improve the control of the polarization state of the ferroelectric gate; reduces variability: helps to compensate for inter-cell variability and aging effects; improves durability, smaller pulses can reduce the stress on the ferroelectric memory cell and prolong the life of the device.

[0059] Embodiment 2 In the embodiments of the present application, a programming circuit for a FeMFET memory cell is also provided, Figure 7 The structure diagram of the programming circuit for the FeMFET memory cell of Embodiment 2 of the present application is shown in Figure 7 , the programming circuit comprises: The memory array 100 comprises a plurality of FeMFET memory cells 101; The write unit 200 is connected with the memory array 100 and configured to apply a programming pulse to the selected FeMFET memory cell 101 in the memory array 100 for programming. In the embodiment, the write unit 200 comprises a pulse generator 201, which is configured to output a programming pulse adapted to the FeMFET memory cell 101, i.e. a programming pulse with an amplitude and bandwidth adapted to the FeMFET memory cell 101.

[0060] The read unit 300 is connected with the memory array 100 and configured to read the programmed state of the selected FeMFET memory cell 101 in the memory array 100. In the embodiment, the read unit 300 comprises a sense amplifier 301, which is coupled to the bit line of the memory array 100 through a multiplexing switch.

[0061] The control unit 400 is connected with the write unit 200 and the read unit 300 and configured to: Control the write unit 200 and the read unit 300 to perform the multi-pulse programming method of the FeMFET memory cell as described above.

[0062] In the embodiment, the control unit 400 prohibits the write unit 200 and the read unit 300 from working when a predetermined maximum number of repetitions of the write-verify cycle is reached.

[0063] In the embodiment, the control unit 400 can dynamically adjust the number of programming pulses applied by the write unit in each write-verify cycle according to the state of the FeMFET memory cell 101, such as the working environment and aging characteristics.

[0064] In the embodiment, further comprising: The error correction logic unit 500 is connected with the read unit 300 and configured to verify the data integrity of the read FeMFET memory cell 101 using ECC.

[0065] It is to be understood that the above-described embodiments are merely preferred embodiments of the present application and are not used to limit the present application, and although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can make modifications to the technical solutions described in the foregoing embodiments or make equivalent replacements to some of the technical features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A multi-pulse programming method for a FeMFET memory cell, comprising: Configure the FeMFET memory cell to enter write operation state; In response to the FeMFET memory cell entering a write operation state, at least two programming pulses are continuously applied to the FeMFET memory cell for programming, and each programming pulse can program the FeMFET memory cell to a predetermined programming state. Configure the FeMFET memory cell to enter read operation state; In response to the FeMFET memory cell entering a read operation state, the programming state of the FeMFET memory cell is read to verify whether it has been programmed to the predetermined programming state; Repeat the above steps until the programming state of the FeMFET memory cell is verified to be a predetermined programming state or the predetermined maximum number of write-verification cycles is verified; the write-verification cycle is one round of the above steps.

2. The multi-pulse programming method for FeMFET memory cells according to claim 1, characterized in that, The method further includes: Based on the write success rate of a single programming pulse, the number of programming pulses is set so that the overall write success rate within a predetermined number of write-verification cycles meets the predetermined write success rate.

3. The multi-pulse programming method for FeMFET memory cells according to claim 2, characterized in that, The specific steps for setting the number of programming pulses based on the write success rate of a single programming pulse, so that the overall write success rate within a predetermined number of write-verification cycles meets the predetermined write success rate, are as follows: ； ； ； Where K is the number of write-verify cycles, The write success rate for a single programming pulse. The number of programming pulses applied within a write-verify cycle. The overall write success rate after K cycles. This refers to the write success rate per cycle. This is the target write success rate.

4. The multi-pulse programming method for FeMFET memory cells according to claim 1, characterized in that, The method further includes: Based on the write success rate of a single programming pulse and the probability of chaotic switching, the number of programming pulses is set to ensure that the overall write success rate within a predetermined number of write-verification cycles meets the predetermined write success rate. The specific steps are as follows: ； ； Where K is the number of write-verify cycles, The write success rate for a single programming pulse. The number of programming pulses applied within a write-verify cycle. For chaotic switching probability, The overall write success rate after the Kth cycle is given. The write success rate after the first K-1 cycles. This is the target write success rate.

5. The multi-pulse programming method for FeMFET memory cells according to claim 1, characterized in that, The method further includes: determining the minimum number of write-verification cycles to meet the predetermined write success rate based on the number of programming pulses and the write success rate of a single programming pulse, as shown in the following formula: ； Where K is the number of write-verify cycles, The write success rate for a single programming pulse. The number of programming pulses applied within a write-verify cycle. This is the target write success rate.

6. The multi-pulse programming method for FeMFET memory cells according to claim 1, characterized in that, The method further includes: The number of programming pulses applied in each write-verify cycle is dynamically adjusted based on the state of the FeMFET memory cell.

7. The multi-pulse programming method for FeMFET memory cells according to claim 1, characterized in that, The specific steps for configuring the FeMFET memory cell to enter the write operation state include: Address decoding, operating voltage generation, and precharge bit lines for FeMFET memory cells.

8. The multi-pulse programming method for FeMFET memory cells according to claim 1, characterized in that, The specific steps for configuring the FeMFET memory cell to enter the read operation state include: Address decoding, operating voltage generation, precharge bit line, and configuration multiplexer for FeMFET memory cells.

9. A programming circuit for a FeMFET memory cell, characterized in that, include: The memory array comprises multiple FeMFET memory cells; A write unit, connected to the memory array, is configured to apply programming pulses to selected FeMFET memory cells in the memory array for programming. A read unit, connected to the memory array, is configured to read the programming state of a selected FeMFET memory cell in the memory array; The control unit, connected to the writing unit and the reading unit, is configured as follows: The write unit and read unit are controlled to perform the multi-pulse programming method for the FeMFET memory cell according to any one of claims 1-8.

10. The programming circuit for the FeMFET memory cell according to claim 9, characterized in that, The write unit includes a pulse generator configured to output programming pulses adapted to the FeMFET memory cell.

11. The programming circuit for the FeMFET memory cell according to claim 9, characterized in that, The control unit disables the writing unit and the reading unit when the predetermined maximum number of repetitions of the write-verify cycle is reached.

12. The programming circuit for the FeMFET memory cell according to claim 9, characterized in that, The read unit includes a sensing amplifier that is coupled to the bit lines of the memory array via a multiplexer switch.

13. The programming circuit for the FeMFET memory cell according to claim 9, characterized in that, Also includes: An error correction logic unit, connected to the read unit, is used to verify the data integrity of the read FeMFET memory cell using ECC.

14. The programming circuit for the FeMFET memory cell according to claim 9, characterized in that, The control unit is also configured to dynamically adjust the number of programming pulses applied by the write unit within each write-verify cycle.

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