2T2FC ferroelectric storage unit and preparation method thereof

Abstract

The invention discloses a 2T2FC ferroelectric memory cell and a preparation method thereof, and the 2T2FC ferroelectric memory cell comprises a memory transistor; the source electrode of the control transistor is connected to the drain electrode of the storage transistor; one end of the first ferroelectric capacitor is connected with a first plate line, and the other end is coupled to the grid electrode of the storage transistor; one end of the second ferroelectric capacitor is connected with a second plate line, and the other end is coupled to the grid electrode of the storage transistor; a word line connected to the gate of the memory transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the memory transistor; a control line connected to the gate of the control transistor; the control transistor is configured to selectively enable or disable access to the memory transistor. By adopting one storage transistor and one control transistor, a storage path is separated from a control path, the reliability of data reading and writing is improved, meanwhile, the leakage current is reduced, and the memory is increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of ferroelectric memory, in particular to a 2T2FC ferroelectric memory cell and a preparation method thereof. BACKGROUND

[0002] Emerging AI (Artificial Intelligence) and neuromorphic computing architectures require memories with fast, non-volatile, in-memory computing capabilities. As a new type of non-volatile memory (NVM), ferroelectric memory (FRAM) can immediately capture and save critical data when the power is interrupted, which is very suitable for mission-critical data recording applications. Ferroelectric memory adopts a low-power and miniaturized design, which can provide instant non-volatility and almost unlimited durability without affecting speed or energy efficiency.

[0003] Existing ferroelectric memory mainly relies on ferroelectric field effect transistor (FeFET) architecture, which provides promising non-volatile characteristics. However, due to the polarization screening effect and process compatibility limitations of FeFET, it faces the problems of data retention degradation and scalability limitations. SUMMARY

[0004] In order to solve the defects of the prior art, the purpose of the present application is to provide a 2T2FC ferroelectric memory cell and a preparation method thereof, which can improve data retention and durability while being compatible with advanced CMOS process nodes by using two transistors and two ferroelectric capacitors.

[0005] To achieve the above purpose, the present application provides a 2T2FC ferroelectric memory cell, comprising: a storage transistor; a control transistor, the source of which is connected to the drain of the storage transistor; a first ferroelectric capacitor, one end of which is connected to a first plate line, and the other end of which is coupled to the gate of the storage transistor; a second ferroelectric capacitor, one end of which is connected to a second plate line, and the other end of which is coupled to the gate of the storage transistor; a word line connected to the gate of the storage transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the storage transistor; a control line connected to the gate of the control transistor; The control transistor is configured to selectively enable or disable access to the storage transistor.

[0006] Further, the polarization state of the ferroelectric capacitors is modulated by applying opposite polarity voltages to the first and second ferroelectric capacitors to switch the encoded logic state.

[0007] Further, when the 2T2FC ferroelectric memory cell is programmed to logic "1", a positive polarization voltage is applied to the first ferroelectric capacitor to make its polarization direction towards the storage transistor gate, while a negative polarization voltage is applied to the second ferroelectric capacitor to make its polarization direction away from the storage transistor gate.

[0008] Further, when the 2T2FC ferroelectric memory cell is programmed to logic "0", a negative polarization voltage is applied to the first ferroelectric capacitor to make its polarization direction away from the storage transistor gate, while a positive polarization voltage is applied to the second ferroelectric capacitor to make its polarization direction towards the storage transistor gate.

[0009] Further, after programming, the 2T2FC ferroelectric memory cell drives the word line, the control line, the bit line, the source line, the first plate line and the second plate line to 0V to prevent data degradation due to charge leakage of the ferroelectric capacitors.

[0010] Further, when the 2T2FC ferroelectric memory cell reads data: the control transistor is enabled by the control line; one of the first plate line and the second plate line is applied with a read voltage, while the other is kept at ground; a read bias voltage is applied to the bit line; the stored logic state is determined according to the detected drain current of the storage transistor.

[0011] Further, the logic state is determined according to that high current represents logic "1" and low current represents logic "0"; the high current refers to the detected drain current of the storage transistor when the gate voltage exceeds the threshold voltage and the channel forms a conductive path; the low current refers to the detected drain current of the storage transistor when the gate voltage is below the threshold voltage and the channel does not form a conductive path.

[0012] Further, after reading data, the 2T2FC ferroelectric memory cell discharges the word line, the control line, the bit line, the source line, the first plate line and the second plate line to 0V to eliminate residual gate charge and prevent data read interference or long-term data retention degradation.

[0013] To achieve the above object, the application further provides a preparation method of a 2T2FC ferroelectric memory cell, comprising the following steps: Depositing a gate oxide layer, a high dielectric constant dielectric layer and a gate metal layer on a silicon substrate in sequence to form a gate stack of a memory transistor and a control transistor respectively; Forming a source diffusion region and a drain diffusion region on the silicon substrate by ion implantation and activation respectively; Depositing an interlayer dielectric layer on the source diffusion region and the drain diffusion region respectively; Forming two ferroelectric capacitors symmetrically on both sides of the gate stack of the memory transistor; Connecting the two ferroelectric capacitors to a plate line.

[0014] Further, after forming the gate stack of the memory transistor and the control transistor, further comprising the steps of forming a word line and a control line.

[0015] Further, after depositing the interlayer dielectric layer, further comprising the steps of forming a bit line and a source line.

[0016] Further, the step of forming two ferroelectric capacitors symmetrically on both sides of the gate stack of the memory transistor further comprises: Depositing a TiN bottom electrode, a ferroelectric layer and a TiN top electrode on both sides of the gate metal layer in sequence to form a symmetric first ferroelectric capacitor and a second ferroelectric capacitor; wherein, The ferroelectric layer is formed by atomic layer deposition, and the TiN bottom electrode and the TiN top electrode are formed by plasma enhanced atomic layer deposition.

[0017] Further, the 2T2FC ferroelectric memory cell is patterned into a layout occupying an area of 8F², wherein F is the minimum feature size of a manufacturing process node.

[0018] To achieve the above object, the application further provides a 2T2FC ferroelectric memory cell obtained by the preparation method as described above.

[0019] To achieve the above object, the application further provides a memory array comprising a plurality of 2T2FC ferroelectric memory cells as described above.

[0020] Further, further comprising a write control unit configured to apply a multi-step hierarchical voltage to the plate line and the word line of the 2T2FC ferroelectric memory cell to selectively program a target cell and prevent interference with a half-selected cell.

[0021] To achieve the above object, the application further provides an AI chip comprising a memory array as described above.

[0022] The 2T2FC ferroelectric memory cell provided by the application realizes separation of a storage path and a control path by adopting one storage transistor and one control transistor, improves the reliability of data reading and writing, and reduces leakage current and increases internal memory.

[0023] Other features and advantages of the application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings: Figure 1 Structure schematic diagram of the 2T2FC ferroelectric memory cell according to the embodiments of the application; Figure 2 Schematic diagram of differential write logic value according to the embodiments of the application; Figure 3 Schematic diagram of read logic value according to the embodiments of the application; Figure 4 Flow chart of the preparation method of the 2T2FC ferroelectric memory cell according to the embodiments of the application; Figure 5 Schematic diagram of the active device region according to the embodiments of the application; Figure 6 Schematic diagram of the gate stack according to the embodiments of the application; Figure 7 Schematic diagram of the interlayer dielectric layer and contact hole formation according to the embodiments of the application; Figure 8 Schematic diagram of the bit line and source line contact formation according to the embodiments of the application; Figure 9 Schematic diagram of the patterned ferroelectric capacitor contact hole on the gate according to the embodiments of the application; Figure 10 Schematic diagram of the common bottom metal pad for generating the ferroelectric capacitor according to the embodiments of the application; Figure 11 Schematic diagram of the stack structure of the ferroelectric capacitor according to the embodiments of the application; Figure 12 Schematic diagram of the plate line generation according to the embodiments of the application; Figure 13 Schematic diagram of the first stage of writing "0" into the memory array according to some embodiments of the application; Figure 14 Schematic diagram of the second stage of writing "0" into the memory array according to some embodiments of the application; Figure 15Schematic diagram of a first phase for writing a "1" to a memory array according to some embodiments of the application; Figure 16 Schematic diagram of a second phase for writing a "1" to a memory array according to some embodiments of the application; Figure 17 Schematic diagram of a first phase for writing a "0" to a memory array according to some embodiments of the application; Figure 18 Schematic diagram of a second phase for writing a "0" to a memory array according to some embodiments of the application; Figure 19 Schematic diagram of a first phase for writing a "1" to a memory array according to some embodiments of the application; Figure 20 Schematic diagram of a second phase for writing a "1" to a memory array according to some embodiments of the application; Figure 21 Schematic diagram of a first phase for reading data from a memory array according to some embodiments of the application; Figure 22 Schematic diagram of a second phase for reading data from a memory array according to some embodiments of the application.

[0025] Reference signs: 401 - active device region; 402 - oxide; 403 - gate oxide; 404 - high-k dielectric; 405 - TiN gate electrode; 406 - source diffusion region; 407 - drain-source diffusion region; 408 - drain diffusion region; 409 - contact hole; 410 - common bottom metal pad; 411 - TiN bottom electrode; 412 - ferroelectric layer; 413 - TiN top electrode; 414, 415 - plate lines. DETAILED DESCRIPTION

[0026] The preferred embodiments of the present application will be described herein below with reference to the accompanying drawings; it should be understood, however, that the embodiments described herein are intended to be illustrative only and are presented by way of example only and are not intended to limit the present application since modifications and variations from the embodiments described herein will be apparent to those of ordinary skill in the art. It is also to be understood that the figures and embodiments are only meant to be illustrative and that the scope of the present application is not to be limited to the embodiments set forth herein.

[0027] Embodiments of the present application will be described below in greater detail with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is understood that the present application can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein, but rather, the embodiments are provided so as to more completely and thoroughly understand the present application. It is to be understood that the drawings and embodiments of the present application are merely for illustrative purposes and are not intended to limit the scope of the present application.

[0028] As used herein, the term "includes" and its variants are to be read as open-ended terms that mean "includes, but is not limited to." The term "based on" is to be cab interpreted as "based, at least in part, on." The term "one embodiment" does not preclude the existence of another embodiment. Likewise, the terms "another embodiment" and "some embodiments" do not preclude the existence of a same or identical embodiment. Other terms are to be construed similarly.

[0029] It should be noted that the terms "first", "second", and the like in the present application can be used to distinguish different apparatuses, components or parts, but not to limit the order or interdependence of the functions performed by these apparatuses, components or parts.

[0030] It should be noted that the terms "one", "multiple" mentioned in the present application are illustrative and not restrictive, and those skilled in the art should understand that "one or more" should be understood unless otherwise explicitly indicated in the context. "Multiple" should be understood as two or more.

[0031] The following terms can be mentioned in the present application: 2T2FC (two transistors and two ferroelectric capacitors) ferroelectric memory cell: a ferroelectric memory cell containing 2 transistors and 2 ferroelectric capacitors; CFA: first ferroelectric capacitor; CFB: second ferroelectric capacitor; PL (Plate Line): plate line, connecting the plate of the ferroelectric capacitor, used to transmit read-write voltage; ML (Metal Line): metal line, connecting the bottom electrode of the ferroelectric capacitor; CT (Control Transistor): control transistor, used to enable or disable access to the storage path; ST (Storage Transistor): storage transistor, as the main switch for storing and sensing the storage state; PLA: first plate line; PLB: second plate line; WL (Word Line): word line, connecting the gate of the storage transistor, used to control the conduction and cutoff of the storage transistor; BL (Bit Line): bit line, connecting the drain of the control transistor, used as a channel for data reading; SL (Source Line): source line, connecting the source of the storage transistor, used as a current loop or voltage reference line, cooperating with the bit line to complete data read-write operation; CL (Control Line): Control line, a wire connected to the gate of the control transistor, used to control the conduction and cutoff of the control transistor; +Vpp: Positive polarization voltage; -Vpp: Negative polarization voltage.

[0032] The related definitions of other terms will be given in the following description.

[0033] Embodiment 1 In the embodiments of the present application, a 2T2FC ferroelectric memory cell is provided, comprising: a storage transistor; a control transistor, the source of which is connected to the drain of the storage transistor; a first ferroelectric capacitor, one end of which is connected to a first plate line, and the other end of which is coupled to the gate of the storage transistor; a second ferroelectric capacitor, one end of which is connected to a second plate line, and the other end of which is coupled to the gate of the storage transistor; a word line connected to the gate of the storage transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the storage transistor; a control line connected to the gate of the control transistor; and the control transistor is configured to selectively enable or disable access to the storage transistor.

[0034] Figure 1 As shown in the structural schematic diagram of the 2T2FC ferroelectric memory cell according to the embodiments of the present application, Figure 1 As shown in the structural schematic diagram of the 2T2FC ferroelectric memory cell according to the embodiments of the present application,

[0035] In the embodiments of the present application, the storage transistor ST serves as an important switch for storing and sensing the storage state, and distinguishes the logic state by utilizing the threshold voltage change caused by ferroelectric polarization in the storage transistor ST. The control transistor CT is used to gate the access of the storage path and is configured to selectively enable or disable access to the storage transistor ST, which realizes the separation of the storage path and the control path, supports independent control of access and data retention, and suppresses leakage in standby and half-selected states. At the same time, the gate dielectric stress of a single transistor is reduced, thereby improving the durability and data retention capability of the memory cell. By using the storage transistor ST and the control transistor CT, a larger storage capacity is supported while reducing the leakage current.

[0036] In embodiments of the application, the logic state is switched by modulating the polarization state of the ferroelectric capacitors. By applying opposite polarity voltages to the two ferroelectric capacitors, the two ferroelectric capacitors are reversed polarized, resulting in different electric fields at the gate of the storage transistor ST to modulate the threshold voltage, which in turn affects the on current in the write operation. For example, to write a logic “1”, -Vpp is applied to PLB to polarize CFB upward (away from the storage transistor ST gate), and +Vpp is applied to PLA to polarize CFA downward (toward the storage transistor ST gate); to write a logic “0”, +Vpp is applied to PLB and -Vpp is applied to PLA to create opposite polarization states from writing a logic “1”. In reading data, a read voltage is applied to the plate line connected to one ferroelectric capacitor while the plate line connected to the other ferroelectric capacitor is grounded, and the current is passed through the storage transistor ST by activating the control line CL, and the storage logic state is determined based on the detected bit line current. For example, a high current level (channel on) or a low current level (channel off) reflects that the storage logic state based on the differential polarization condition is “1” or “0”. This differential polarization scheme improves noise immunity and reading accuracy, and is suitable for multi-bit storage levels for AI (artificial intelligence) related workloads.

[0037] Figure 2 A schematic diagram of differential write logic values according to embodiments of the application is shown in FIG. 1, where binary data is stored by differential polarization of two ferroelectric capacitors, involving applying high positive and negative voltage pulses to the plate lines (PLA and PLB) as follows: Figure 2 Write logic “0”: write “0” to CFB and +Vpp to PLB to polarize it downward; write “1” to CFA and -Vpp to PLA to polarize it upward.

[0038] Write logic “1”: write “1” to CFB and -Vpp to PLB to polarize it upward; write “0” to CFA and +Vpp to PLA to polarize it downward.

[0039] This dual ferroelectric capacitor configuration achieves high sensing margin by exploiting the threshold voltage shift induced by polarization in the storage transistor to distinguish logic states. The polarization state of the dual ferroelectric capacitors is maintained when power is off, achieving non-volatile storage.

[0040] In embodiments of the application, the 2T2FC ferroelectric memory cell can be accessed by a multi-step voltage approach to optimize the write operation, such as applying partial voltages in steps (e.g., ±2 / 3 Vpp, ±1 / 3 Vpp) to avoid write disturbance to unselected and half-selected cells in a large memory array.​

[0041] In embodiments of the application, to prevent data degradation due to charge leakage from CFA and CFB after write operation, a post-write zeroing scheme is adopted: all active terminals, i.e. word line WL, bit line BL, source line SL, first plate line PLA, second plate line PLB and control line CL, are driven to 0V. This state is maintained until the read operation to ensure all stored charges remain intact. This scheme eliminates capacitive memory effects that can affect subsequent read accuracy or induce long-term retention loss.

[0042] In embodiments of the application, the word line WL connected to the gate of the storage transistor ST (applied voltage less than 1.2V) is used for current sensing. High current (on) indicates a low effective threshold voltage due to polarization configuration, and low current (off) indicates a high threshold voltage due to reverse polarization configuration. When writing logic values, the two ferroelectric capacitors represent logic states “0” and “1” with opposite polarity. When reading data, the current through the storage transistor ST is detected, high current indicates logic “1”, and low current indicates logic “0”. High current refers to the drain current of the storage transistor ST when the gate voltage exceeds the threshold voltage and the channel forms a conductive path; low current refers to the drain current of the storage transistor ST when the gate voltage is below the threshold voltage and the channel does not form a conductive path. This current-based reading method is reliable, supports differential sensing, and can be extended to support multi-level cell (MLC) behavior.

[0043] In embodiments of the application, when the control line CL is activated, the control transistor CT is turned on, forming a current path from the bit line BL to the control transistor CT to the storage transistor ST to the source line SL. The degree of conduction of the storage transistor ST is determined by its gate voltage (modulated by the polarization state of the FeCAPs), which ultimately controls the current of the entire circuit.

[0044] In embodiments of the application, data reading of the 2T2FC ferroelectric memory cell is performed by the storage transistor ST for current-based sensing of the logic state, and the reading steps are as follows: Activate the control transistor CT by activating the control line CL; Apply a small read voltage (Vread) of 0.7V~0.9V to one of the plate lines (e.g. PLB); Ground the other plate line (e.g. PLA) to establish a voltage gradient; Float the gate of the storage transistor ST, which is affected by the net polarization state of CFA and CFB; A read bias voltage (0.2V to 0.7V in this embodiment) is applied to the bit line BL; According to the measured storage transistor ST drain current, the logic state is determined.

[0045] Figure 3 A schematic diagram for reading the logic value according to the embodiment of the present application is shown as follows: Figure 3 During reading, Vread (read voltage) is applied to the PLB, the PLA is grounded (0V), and the logic state "0" or "1" is read according to the drain current of the storage transistor ST by applying Vd (0.2V~0.7V) to the BL. During reading, the 2T2FC ferroelectric memory cell works as a ferroelectric field effect transistor (floating gate), and the drain current generated by gate modulation can be detected. High current is generated by +Vpp (on state), and low current is generated by -Vpp (off state), thereby determining the stored logic state.

[0046] In the embodiment of the present application, in order to prevent the data degradation caused by residual charge of the gate or floating node after reading the 2T2FC ferroelectric memory cell, a discharge scheme after reading is adopted: all active terminals, i.e. the word line WL, the bit line BL, the source line SL, the first plate line PLA, the second plate line PLB and the control line CL, are driven to 0V. The state is maintained for a certain time to ensure that all storage charges are neutralized. This scheme eliminates the capacitive memory effect that may affect subsequent reading or cause long-term retention loss.

[0047] In the embodiment of the present application, the 2T2FC ferroelectric memory cell is compatible with the standard CMOS back end of line (BEOL). The ferroelectric capacitor is designed to be stacked on the logic device, and can be realized using the materials and layers commonly used in the back end process, for example, the TiN electrode is formed by plasma enhanced atomic layer deposition (PEALD), and the ferroelectric HfZrO2 (HZO) layer is formed by atomic layer deposition (ALD) (as shown in Figure 1 ). Combined with the shallow trench isolation (STI) in the front end of line (FEOL) and the standard gate-first transistor process, the final cell occupies an area of 8F² (2F×4F), where F is the minimum feature size of the technology node. This makes the 2T2FC ferroelectric memory cell highly scalable and suitable for integration into CMOS nodes of 22nm, 14nm or even below 10nm.

[0048] In the embodiment of the present application, two ferroelectric capacitors are located on both sides of the gate of the storage transistor ST, and are both made of high-k ferroelectric material. The plate terminals at the top of the two ferroelectric capacitors are connected to the PLA and the PLB respectively, for transmitting the write and read voltages. ​

[0049] The 2T2FC ferroelectric memory cell of the embodiment of the present application has the following advantages: 1) Allows independent ferroelectric polarization of each ferroelectric capacitor, improves write reliability using differential polarization scheme, supports high-density in-memory computing operations, while improving noise immunity, read accuracy, and is suitable for multi-bit memory levels for AI (artificial intelligence) related workloads; 2) The following advantages are achieved by separating the storage path and the control path: Independent control of access and data retention; Leakage current is suppressed in standby and not fully selected states; Durability is improved due to reduced stress on the single gate dielectric layer; 3) Low power consumption and high reliability characteristics suitable for in-memory computing (CIM) and neuromorphic computing environments: The read gate function is implemented using an independent control transistor CT, which activates the 2T2FC ferroelectric memory cell only when explicitly accessed; Leakage current suppression is crucial for large arrays; Reduces inter-cell interference, especially when accessing partial cells; Improves durability as the programming voltage is distributed across two ferroelectric capacitors; 4) Compatible with standard CMOS back-end-of-line (BEOL) processes, only requires small-area ferroelectric capacitors to achieve high sensing margin, achieves a compact cell size (8F 2 ), suitable for neuromorphic and AI-centric memory architectures; 5) By utilizing two ferroelectric capacitors and independent storage and control transistors, the problem of scalability limitations and insufficient retention is solved, thereby improving data reliability, reducing read / write interference, and providing higher energy efficiency; The 2T2FC ferroelectric memory cell of the embodiment of the present application significantly improves reliability, especially in low-voltage or battery-constrained environments such as edge AI chips and IoT memory modules.

[0050] Embodiment 2 In the embodiment of the present application, a preparation method of a 2T2FC ferroelectric memory cell is provided, comprising the following steps: depositing a gate oxide layer, a high dielectric constant dielectric layer and a gate metal layer on a silicon substrate in sequence to form a gate stack of a storage transistor and a control transistor; forming a source diffusion region and a drain diffusion region on the silicon substrate by ion implantation and activation; depositing an interlayer dielectric layer on the source diffusion region and the drain diffusion region; forming two ferroelectric capacitors symmetrically on both sides of the gate stack of the storage transistor; and connecting the two ferroelectric capacitors to a plate line.

[0051] Figure 4 A flow chart of a method for fabricating a 2T2FC ferroelectric memory cell according to an embodiment of the present application is shown in FIG. 2. The method will be described in detail below with reference to FIG. 2. Figure 4 A method for fabricating a 2T2FC ferroelectric memory cell according to an embodiment of the present application is described in detail.

[0052] First, in step 201, active areas are defined and isolated on a silicon substrate using shallow trench isolation (STI).

[0053] In an embodiment of the present application, this step includes: on the silicon substrate, first defining a shallow trench isolation area by photolithography, and then forming a STI (Shallow Trench Isolation) trench with a preset depth in the shallow trench isolation area by dry etching (such as HBr / Cl2 plasma). The trench separates a plurality of active device areas 401 on the silicon substrate, thereby defining an isolation area around the active device areas 401 on the silicon substrate to prevent leakage and parasitic coupling.

[0054] In step 202, the surface of the silicon substrate is pretreated.

[0055] In an embodiment of the present application, this step includes: depositing an oxide 402 (such as SiO2, by HDP-CVD) in the formed trench to fill the trench; and removing the excess material by chemical mechanical polishing (CMP) to leave a flat surface. As shown in FIG. 3, the oxide 402 is deposited in the trench to form a plurality of active device areas 401 on the silicon substrate. Figure 5

[0056] In step 203, a gate stack of a storage transistor and a control transistor is generated on the active device area.

[0057] In an embodiment of the present application, this step includes: Growth or deposition of two gate oxide layers 403: growth of a gate oxide on the active device area 401, such as a silicon oxynitride gate medium (SiON gate oxide), with a high-k (improving high-K medium interface state); ​Depositing high-k dielectric and TiN gate metal, forming gate stack: on the two gate oxide layers 403, high-k dielectric layer 404 and TiN gate electrode 405 (TiN Gate) are generated by atomic layer deposition (ALD), forming gate stack, and the storage transistor gate and control transistor gate are formed by lithography + dry etching; The patterned storage transistor gate forms word line (WL), and the patterned control transistor gate forms control line (CL); Ion implantation and annealing are performed to form N+ source diffusion region 406, drain-source diffusion region 407 (as storage transistor drain and control transistor source) and drain diffusion region 408, and thermal annealing activates the dopant and forms a low resistance junction. As Figure 6 As shown, two gate stacks of gate oxide layer 403, high-k dielectric layer 404 and TiN gate electrode 405 are sequentially grown on active device area 401, and word line (WL) and control line (CL) are formed, N+ source diffusion region 406, drain-source diffusion region 407 and drain diffusion region 408 are formed by ion implantation, and finally high temperature annealing is performed to activate the dopant and form a low resistance junction.

[0058] In step 204, bit lines and source lines are generated on the drain and source diffusion regions.

[0059] In an embodiment of the present application, the step includes: depositing an interlayer dielectric layer (InterLayer Dielectric, ILD) on the source diffusion region 406 and the drain diffusion region 408 and etching a contact hole, respectively connecting the source diffusion region 406 and the drain diffusion region 408, filling the contact hole with a conductive metal (such as tungsten W or copper Cu), and forming a source line (SL) and a bit line (BL).

[0060] As Figure 7 and 8 As shown, an interlayer dielectric layer (ILD) is deposited on the source diffusion region 406 and the drain diffusion region 408, and a source line (SL) and a bit line (BL) are respectively formed on the interlayer dielectric layer.

[0061] In an embodiment of the present application, step 204 further includes: ILD deposition: depositing an oxide (such as SiO2) above the source diffusion region 406, the drain-source diffusion region 407 and the drain diffusion region 408, and planarizing by CMP to generate an interlayer dielectric layer; Contact hole formation: photolithography is performed on the interlayer dielectric layer, and etching to the source diffusion region 406 and the drain diffusion region 408 forms a contact hole; Metal filling: filling the contact hole with a conductive metal to form a source line (SL) and a bit line (BL).

[0062] In step 205, ferroelectric capacitors are generated on both sides of the storage transistor gate.

[0063] In embodiments of the present application, the step includes: A ferroelectric capacitor contact hole 409 is patterned on the storage transistor gate and filled with conductive material, as shown in FIG. 4B; a common bottom metal pad 410 of the ferroelectric capacitor is formed above the contact hole 409, as shown in FIG. 4C; a TiN bottom electrode 411 is deposited on the common bottom metal pad 410 in sequence, a ferroelectric layer 412 is grown, and a TiN top electrode 413 is deposited, as shown in FIG. 4D; the ferroelectric layer 412 is activated by annealing to form a ferroelectric domain, completing the stacked structure of the two ferroelectric capacitors. Figure 9 Figure 10 Figure 11

[0064] Specifically, by aligning the storage transistor gate on both sides through photolithography, the ILD is etched to the gate to form a deep hole; the TiN bottom electrode 411 is deposited on the deep hole through plasma-enhanced ALD (PEALD); the HfZrO2 ferroelectric thin film is deposited through ALD to form the ferroelectric layer 412; the TiN top electrode 413 is deposited through ALD, and finally the electrode pattern is defined by photolithography stripping.

[0065] In step 206, metal wiring is performed.

[0066] In embodiments of the present application, the metal wiring layer is used to connect the independent plate lines PLA and PLB to the CFA and CFB; the metalization and patterning define the word lines (WL) and control lines (CL) and connect to the transistor gate. As shown in FIG. 4E, the plate lines 414 and 415, i.e., PLA and PLB, are formed on the TiN top electrode 413 through the interconnection metal layer; the word lines WL, control lines CL, and other wiring layers, such as the bit lines BL and source lines SL, are connected through vias. Figure 12

[0067] Further, it also includes depositing a SiN (silicon nitride) etching stop layer, connecting the TiN top electrode 413 of the ferroelectric capacitor through a via by photolithography; etching a trench + electroplating copper to form the plate lines and word lines.

[0068] In step 207, back-end integration is completed.

[0069] In embodiments of the present application, the last step is to perform the passivation and planarization required by the semiconductor back-end process (BE) for packaging, completing the integration of the 2T2FC ferroelectric memory cell. The 2T2FC ferroelectric memory cell is patterned into a layout occupying an area of 8F², where F is the minimum feature size of the manufacturing process node. Further, the step includes: Dimension verification: 2F x 4F (= 8F 2 ​​​​Layout (e.g., 14nm node: lateral gate length 28nm × vertical metal pitch 56nm); Deposit passivation layer: Deposit SiN passivation layer and open pad windows.

[0070] The fabrication method of the 1T2FC ferroelectric memory cell in this application embodiment enables the 1T2FC ferroelectric memory cell to be seamlessly integrated onto standard CMOS logic devices, ensuring high density scalability, compatibility with 28nm, 22nm and more advanced nodes, and full compatibility with CMOS back-end processes, thereby supporting high-density and high-performance system-on-chip (SoC) applications.

[0071] Example 3 In an embodiment of this application, a memory array is provided, including a plurality of 2T2FC ferroelectric memory cells as described above.

[0072] In the embodiments of this application, the control transistors of multiple 2T2FC ferroelectric memory cells share a control line (CL) for control, and two ferroelectric capacitors share a plate line (PLA, PLB) between rows or columns.

[0073] In the embodiments of this application, the memory array is accessed using a multi-step voltage method. By applying multi-step graded voltages to the board lines and word lines of the 2T2FC ferroelectric memory cell, the target cell is selectively programmed and interference with the half-selected cell is prevented.

[0074] In a memory array, a half-selected cell refers to a memory cell that is only selected by column strobe (word line WL activated) or row strobe (bit line BL activated) during read and write operations, but is not fully selected. Such cells are in a state of potential interference.

[0075] The following section uses a 3×4 memory array as an example to explain the multi-step voltage access method in detail from the perspectives of the write and read processes.

[0076] Figure 13 to Figure 16 As an example of writing to this memory array, firstly, "0" is written to the 2T2FC ferroelectric memory cell in the memory array, in two stages: Phase 1, such as Figure 13 As shown, WL(1) is 0V, WL(2-4) is 2 / 3Vpp applied; all BL and SL are 0V; CL(1) is Vdd applied, CL(2-4) is 0V; PLA(1-3) is 1 / 3Vpp applied; PLB(2) is Vpp applied, PLB(1) and PLB(3) are 1 / 3Vpp applied; The second stage, such as Figure 14 As shown, PLB(1-3) is applied with -1 / 3Vpp, PLA(2) is applied with -Vpp, PLA(1) and PLA(3) are applied with -1 / 3Vpp, and WL(2-4) is applied with -2 / 3Vpp.

[0077] To write a "1" to a 2T2FC ferroelectric memory cell in the memory array, there are two stages: In the first stage, as shown in Figure 15 , WL(l) is applied with OV, WL(2-4) is applied with 2 / 3 Vpp; all BLs and SLs are OV; CL(l) is applied with Vdd, CL(2-4) is applied with OV; PLB(l-3) is applied with 1 / 3 Vpp; PLA(2) is applied with Vpp, PLA(l) and PLA(3) are applied with 1 / 3 Vpp. In the second stage, as shown in Figure 16 , PLA(l-3) is applied with -1 / 3 Vpp, PLB(2) is applied with -Vpp, PLB(l) and PLB(3) are applied with -1 / 3 Vpp, and WL(2-4) is applied with -2 / 3 Vpp.

[0078] Figure 17 to Figure 20 For another write example of the memory array, first, to write a "0" to a 2T2FC ferroelectric memory cell in the memory array, there are two stages: In the first stage, as shown in Figure 17 , only WL(l) is applied with -1 / 2 Vpp, the rest of WL(2-4) is OV, all BLs and SLs are OV; CL(l) is applied with Vdd, CL(2-4) is OV; PLB(2) is applied with 1 / 2 Vpp, the rest of plate lines are OV. In the second stage, as shown in Figure 18 , WL(l) is applied with 1 / 2 Vpp, PLA(2) is applied with -1 / 2 Vpp, PLB(2) is OV.

[0079] To write a "1" to a 2T2FC ferroelectric memory cell in the memory array, there are two stages: In the first stage, as shown in Figure 19 , WL(l) is applied with -1 / 2 Vpp, PLA(2) is applied with 1 / 2 Vpp, PLB(2) is OV. In the second stage, as shown in Figure 20 , WL(l) is applied with 1 / 2 Vpp, PLB(2) is applied with -1 / 2 Vpp, PLA(2) is OV.

[0080] Figure 21 to Figure 22 For a read example of the memory array, the read process is divided into two stages: In the first stage, as shown in Figure 21As shown, only WL(1) applies Vdd, the rest of WL(2-4) is 0V; BL(2) applies Vdd, the rest of BL is 0V; CL(1) applies Vdd, CL(2-4) is 0V; PLB(2) applies Vread, the rest of plate lines are connected to 0V; Vread < Vc, Vd = 0.2V-0.7V(<Vdd); In the second stage, PLA(2) applies Vread, and PLB(2) is connected to 0V; Vread < Vc, Vd = 0.2V-0.7V(<Vdd).

[0081] Wherein, Vc represents the coercive voltage, defined as the minimum voltage required to flip the direction of ferroelectric domain polarization; in the polarization-voltage (P-V) hysteresis loop, Vc is the voltage at which the polarization value crosses zero during voltage scanning. It marks the inflection point of the switching between the following two states of the ferroelectric material: positive remanent polarization +Pr (after applying +V>Vc), and negative remanent polarization-Pr (after applying-V<-Vc).

[0082] Further, the memory array of the present application further comprises a write control unit configured to apply a multi-step grading voltage to the plate line and the word line of the 2T2FC ferroelectric memory cell, so as to selectively program the target cell and prevent interference with the half-selected cell.

[0083] Embodiment 4 In the embodiments of the present application, an AI chip is provided, which comprises the memory array as described above. The AI chip adopting the memory array has the characteristics of low power consumption and high reliability.

[0084] Those skilled in the art can understand that the above description is only preferred embodiments of the present application and is not used to limit the present application, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A 2T2FC ferroelectric memory cell, characterized in that, include: Storage transistors; A control transistor, the source of which is connected to the drain of the storage transistor; A first ferroelectric capacitor, one end of which is connected to a first plate line, and the other end of which is coupled to the gate of the storage transistor; The second ferroelectric capacitor has one end connected to the second plate line and the other end coupled to the gate of the storage transistor; Word lines are connected to the gate of the storage transistor; Bit lines are connected to the drain of the control transistor; The source line is connected to the source of the storage transistor; The control line is connected to the gate of the control transistor; The control transistor is configured to selectively enable or disable access to the storage transistor.

2. The 2T2FC ferroelectric memory unit according to claim 1, characterized in that, By applying voltages of opposite polarity to the first and second ferroelectric capacitors, the polarization state of the ferroelectric capacitors is modulated to switch the coded logic state.

3. The 2T2FC ferroelectric memory cell according to claim 1, characterized in that, When the 2T2FC ferroelectric memory cell is written with logic "1", a positive polarization voltage is applied to the first ferroelectric capacitor so that its polarization direction is toward the gate of the memory transistor, and a negative polarization voltage is applied to the second ferroelectric capacitor so that its polarization direction is away from the gate of the memory transistor.

4. The 2T2FC ferroelectric memory unit according to claim 1, characterized in that, When the 2T2FC ferroelectric memory cell is written with logic "0", a negative polarization voltage is applied to the first ferroelectric capacitor so that its polarization direction is away from the gate of the memory transistor, and a positive polarization voltage is applied to the second ferroelectric capacitor so that its polarization direction is towards the gate of the memory transistor.

5. The 2T2FC ferroelectric memory cell according to claim 3 or 4, characterized in that, After the 2T2FC ferroelectric memory cell performs the write logic, it drives the word line, the control line, the bit line, the source line, the first board line, and the second board line to 0V to prevent charge leakage from the ferroelectric capacitor from causing data degradation.

6. The 2T2FC ferroelectric memory cell according to claim 1, characterized in that, When the 2T2FC ferroelectric storage unit reads data: The control transistor is activated via the control line; Apply a read voltage to one of the first board line and the second board line, while keeping the other of the first board line and the second board line grounded; Apply a read bias voltage to the bit line; The stored logic state is determined based on the detected drain current of the storage transistor.

7. The 2T2FC ferroelectric memory cell according to claim 6, characterized in that, The basis for determining the logic state is: high current represents logic "1", and low current represents logic "0". The high current refers to the drain current detected by the storage transistor when the gate voltage exceeds the threshold voltage and a conductive path is formed in the channel. The low current refers to the drain current detected by the storage transistor when the gate voltage is lower than the threshold voltage and the channel has not formed a conductive path.

8. The 2T2FC ferroelectric memory unit according to claim 6, characterized in that, After reading data, the 2T2FC ferroelectric memory cell drives the word line, control line, bit line, source line, first board line, and second board line to 0V for discharge to eliminate residual gate charge and prevent data read interference or long-term data retention degradation.

9. A method for fabricating a 2T2FC ferroelectric memory cell, characterized in that, Includes the following steps: A gate oxide layer, a high dielectric constant dielectric layer, and a gate metal layer are sequentially deposited on a silicon substrate to form the gate stacks of the storage transistor and the control transistor, respectively. Source diffusion regions and drain diffusion regions are formed on the silicon substrate by ion implantation and activation, respectively. Interlayer dielectric layers are deposited in the source diffusion region and the drain diffusion region, respectively; Two ferroelectric capacitors are symmetrically formed on both sides of the gate stack of the storage transistor; Connect the two ferroelectric capacitors to the plate wires.

10. The method for preparing the 2T2FC ferroelectric memory cell according to claim 9, characterized in that, After the formation of the gate stack of the memory transistor and the control transistor, the steps of forming word lines and control lines are also included.

11. The method for preparing the 2T2FC ferroelectric memory cell according to claim 9, characterized in that, Following the deposition of the interlayer medium layer, the steps of forming bit lines and source lines are further included.

12. The method for preparing the 2T2FC ferroelectric memory cell according to claim 9, characterized in that, The step of symmetrically forming two ferroelectric capacitors on both sides of the gate stack of the storage transistor further includes: On both sides of the gate metal layer, a TiN bottom electrode, a ferroelectric layer, and a TiN top electrode are sequentially deposited to form a symmetrical first ferroelectric capacitor and a second ferroelectric capacitor; wherein... The ferroelectric layer is formed by atomic layer deposition, and the TiN bottom electrode and the TiN top electrode are formed by plasma-enhanced atomic layer deposition.

13. The method for preparing the 2T2FC ferroelectric memory cell according to claim 9, characterized in that, The 2T2FC ferroelectric memory cell is patterned into a layout occupying an area of ​​8F², where F is the minimum feature size of the manufacturing process node.

14. A 2T2FC ferroelectric memory cell obtained by the preparation method according to any one of claims 9-13.

15. A memory array, characterized in that, It includes the 2T2FC ferroelectric memory cell as described in any one of claims 1-8.

16. The memory array according to claim 15, characterized in that, It also includes a write control unit configured to apply multi-step graded voltages to the board lines and word lines of the 2T2FC ferroelectric memory cell to selectively program target cells and prevent interference with semi-selected cells.

17. An AI chip, characterized in that, Includes the memory array described in any one of claims 15-16.

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