A 2T2FC ferroelectric memory cell and its fabrication method

Abstract

This application discloses a 2T2FC ferroelectric memory cell and its fabrication method. The 2T2FC ferroelectric memory cell includes: a storage transistor; a control transistor, the source of which is connected to the drain of the storage transistor; a first ferroelectric capacitor, one end of which is connected to a first plate line and the other end coupled to the gate of the storage transistor; a second ferroelectric capacitor, one end of which is connected to a second plate line and the other end coupled to the gate of the storage transistor; a word line connected to the gate of the storage transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the storage transistor; and a control line connected to the gate of the control transistor. The control transistor is configured to selectively enable or disable access to the storage transistor. This application achieves separation of the storage path and the control path by employing one storage transistor and one control transistor, improving the reliability of data read / write operations while reducing leakage current and increasing memory capacity.

Description

Technical Field

[0001] This application relates to the field of ferroelectric memory technology, and in particular to a 2T2FC ferroelectric memory cell and its fabrication method. Background Technology

[0002] Emerging AI (Artificial Intelligence) and neuromorphic computing architectures require memory with fast, non-volatile, and in-memory computing capabilities. Ferroelectric RAM (FRAM), as a novel type of non-volatile memory (NVM), can immediately capture and save critical data during power interruptions, making it ideal for mission-critical data logging applications. FRAM employs a low-power, miniaturized design, providing instant non-volatility and near-infinite durability without compromising speed or energy efficiency.

[0003] Existing ferroelectric memories mainly rely on the ferroelectric field-effect transistor (FeFET) architecture, which provides promising non-volatile characteristics. However, due to the polarization shielding effect and process compatibility limitations of FeFET, they face problems such as degraded data retention and scalability limitations. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this application is to provide a 2T2FC ferroelectric memory cell and its fabrication method. By employing two transistors and two ferroelectric capacitors, the data retention and durability are improved while remaining compatible with advanced CMOS process nodes.

[0005] To achieve the above objectives, this application provides a 2T2FC ferroelectric memory cell, comprising:

[0006] Storage transistors;

[0007] A control transistor, the source of which is connected to the drain of the storage transistor;

[0008] A first ferroelectric capacitor, one end of which is connected to a first plate line, and the other end of which is coupled to the gate of the storage transistor;

[0009] The second ferroelectric capacitor has one end connected to the second plate line and the other end coupled to the gate of the storage transistor;

[0010] Word lines are connected to the gate of the storage transistor;

[0011] Bit lines are connected to the drain of the control transistor;

[0012] The source line is connected to the source of the storage transistor;

[0013] The control line is connected to the gate of the control transistor;

[0014] The control transistor is configured to selectively enable or disable access to the storage transistor.

[0015] Furthermore, by applying voltages of opposite polarity to the first ferroelectric capacitor and the second ferroelectric capacitor, the polarization state of the ferroelectric capacitor is modulated to switch the coded logic state.

[0016] Furthermore, when the 2T2FC ferroelectric memory cell writes a logic "1", a positive polarization voltage is applied to the first ferroelectric capacitor so that its polarization direction is toward the gate of the memory transistor, and a negative polarization voltage is applied to the second ferroelectric capacitor so that its polarization direction is away from the gate of the memory transistor.

[0017] Furthermore, when the 2T2FC ferroelectric memory cell is written with logic "0", a negative polarization voltage is applied to the first ferroelectric capacitor so that its polarization direction is away from the gate of the memory transistor, and a positive polarization voltage is applied to the second ferroelectric capacitor so that its polarization direction is towards the gate of the memory transistor.

[0018] Furthermore, after writing logic, the 2T2FC ferroelectric memory cell drives the word line, the control line, the bit line, the source line, the first board line, and the second board line to 0V to prevent charge leakage from the ferroelectric capacitor from causing data degradation.

[0019] Furthermore, when the 2T2FC ferroelectric storage unit reads data:

[0020] The control transistor is activated via the control line;

[0021] Apply a read voltage to one of the first board line and the second board line, while keeping the other of the first board line and the second board line grounded;

[0022] Apply a read bias voltage to the bit line;

[0023] The stored logic state is determined based on the detected drain current of the storage transistor.

[0024] Furthermore, the basis for determining the logic state is: high current represents logic "1", and low current represents logic "0".

[0025] The high current refers to the drain current detected by the storage transistor when the gate voltage exceeds the threshold voltage and a conductive path is formed in the channel;

[0026] The low current refers to the drain current detected by the storage transistor when the gate voltage is lower than the threshold voltage and the channel has not formed a conductive path.

[0027] Furthermore, after reading data, the 2T2FC ferroelectric memory cell drives the word line, the control line, the bit line, the source line, the first board line, and the second board line to 0V for discharge to eliminate residual gate charge and prevent data read interference or long-term data retention degradation.

[0028] To achieve the above objectives, this application also provides a method for fabricating a 2T2FC ferroelectric memory cell, comprising the following steps:

[0029] A gate oxide layer, a high dielectric constant dielectric layer, and a gate metal layer are sequentially deposited on a silicon substrate to form the gate stacks of the storage transistor and the control transistor, respectively.

[0030] Source diffusion regions and drain diffusion regions are formed on the silicon substrate by ion implantation and activation, respectively.

[0031] Interlayer dielectric layers are deposited in the source diffusion region and the drain diffusion region, respectively;

[0032] Two ferroelectric capacitors are symmetrically formed on both sides of the gate stack of the storage transistor;

[0033] Connect the two ferroelectric capacitors to the plate wires.

[0034] Furthermore, after forming the gate stack of the memory transistor and the control transistor, the step of forming word lines and control lines is also included.

[0035] Furthermore, following the deposition of the interlayer medium layer, the steps of forming bit lines and source lines are also included.

[0036] Furthermore, the step of symmetrically forming two ferroelectric capacitors on both sides of the gate stack of the storage transistor further includes:

[0037] On both sides of the gate metal layer, a TiN bottom electrode, a ferroelectric layer, and a TiN top electrode are sequentially deposited to form a symmetrical first ferroelectric capacitor and a second ferroelectric capacitor; wherein...

[0038] The ferroelectric layer is formed by atomic layer deposition, and the TiN bottom electrode and the TiN top electrode are formed by plasma-enhanced atomic layer deposition.

[0039] Furthermore, the 2T2FC ferroelectric memory cell is patterned into a layout occupying an area of ​​8F², where F is the minimum feature size of the manufacturing process node.

[0040] To achieve the above objectives, this application also provides a 2T2FC ferroelectric memory cell prepared according to the preparation method described above.

[0041] To achieve the above objectives, this application also provides a memory array comprising a plurality of 2T2FC ferroelectric memory cells as described above.

[0042] Furthermore, it also includes a write control unit configured to apply multi-step graded voltages to the board lines and word lines of the 2T2FC ferroelectric memory cell to selectively program target cells and prevent interference with semi-selected cells.

[0043] To achieve the above objectives, this application also provides an AI chip, including the memory array described above.

[0044] The 2T2FC ferroelectric memory cell provided in this application achieves separation of the storage path and the control path by using one storage transistor and one control transistor, which improves the reliability of data reading and writing, while reducing leakage current and increasing memory.

[0045] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0046] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings:

[0047] Figure 1 This is a schematic diagram of the 2T2FC ferroelectric memory cell structure according to an embodiment of this application;

[0048] Figure 2 This is a schematic diagram of differential write logic values ​​according to an embodiment of this application;

[0049] Figure 3 This is a schematic diagram illustrating the reading logic value according to an embodiment of this application;

[0050] Figure 4 This is a flowchart illustrating the fabrication method of the 2T2FC ferroelectric memory cell according to an embodiment of this application.

[0051] Figure 5 This is a schematic diagram of the active device area according to an embodiment of this application;

[0052] Figure 6 This is a schematic diagram of the gate stack according to an embodiment of this application;

[0053] Figure 7 This is a schematic diagram of the formation of the interlayer dielectric layer and contact holes according to an embodiment of this application;

[0054] Figure 8 This is a schematic diagram showing the contact formation of bit lines and source lines according to an embodiment of this application;

[0055] Figure 9 This is a schematic diagram of the contact hole of a patterned ferroelectric capacitor on the gate according to an embodiment of this application;

[0056] Figure 10 This is a schematic diagram of the common bottom metal pad for generating a ferroelectric capacitor according to an embodiment of this application;

[0057] Figure 11 This is a schematic diagram of the stacked structure of a ferroelectric capacitor according to an embodiment of this application;

[0058] Figure 12 This is a schematic diagram of the generated board lines according to an embodiment of this application;

[0059] Figure 13 This is a schematic diagram of the first stage of writing "0" to a memory array according to some embodiments of this application;

[0060] Figure 14 This is a schematic diagram of the second stage of writing "0" to a memory array according to some embodiments of this application;

[0061] Figure 15 This is a schematic diagram of the first stage of writing "1" into a memory array according to some embodiments of this application;

[0062] Figure 16 This is a schematic diagram of the second stage of writing "1" into a memory array according to some embodiments of this application;

[0063] Figure 17 This is a schematic diagram of the first stage of writing "0" to a memory array according to other embodiments of this application;

[0064] Figure 18 This is a schematic diagram of the second stage of writing "0" to a memory array according to other embodiments of this application;

[0065] Figure 19 This is a schematic diagram of the first stage of writing "1" into a memory array according to other embodiments of this application;

[0066] Figure 20 This is a schematic diagram of the second stage of writing "1" into a memory array according to other embodiments of this application;

[0067] Figure 21 This is a schematic diagram of the first stage of reading data from a memory array according to other embodiments of this application;

[0068] Figure 22 This is a schematic diagram of the second stage of reading data from a memory array according to other embodiments of this application.

[0069] Figure label:

[0070] 401 - Active device area; 402 - Oxide; 403 - Gate oxide layer; 404 - High-k dielectric layer; 405 - TiN gate electrode; 406 - Source diffusion region; 407 - Drain-source diffusion region; 408 - Drain diffusion region; 409 - Contact hole; 410 - Common bottom metal pad; 411 - TiN bottom electrode; 412 - Ferroelectric layer; 413 - TiN top electrode; 414, 415 - Board lines. Detailed Implementation

[0071] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application.

[0072] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0073] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0074] It should be noted that the terms "first" and "second" may be used in this application only to distinguish different devices, components or parts, and are not used to define the order of functions performed by these devices, components or parts or their interdependence.

[0075] It should be noted that the terms "one" and "more" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.

[0076] The following terms may be used in this application:

[0077] 2T2FC (two transistors and two ferroelectric capacitors) ferroelectric memory cell: A ferroelectric memory cell containing two transistors and two ferroelectric capacitors;

[0078] CFA: First Ferroelectric Capacitor;

[0079] CFB: Second ferroelectric capacitor;

[0080] PL (Plate Line): The plate line connects the plates of a ferroelectric capacitor and is used to transmit read / write voltage.

[0081] ML (Metal Line): A metal wire that connects to the bottom electrode of a ferroelectric capacitor;

[0082] CT (Control Transistor): A control transistor used to enable or disable access to the memory path;

[0083] ST (Storage Transistor): A storage transistor that serves as the primary switch for storing and sensing storage states;

[0084] PLA: First Plate Line;

[0085] PLB: Second Plate Line;

[0086] WL (Word Line): A word line is a wire that connects to the gate of a storage transistor and is used to control the switching on and off of the storage transistor.

[0087] BL (Bit Line): The wire connecting the drain of the control transistor, used as a channel for data reading;

[0088] SL (Source Line): The source line is the wire that connects to the source of the storage transistor. It serves as a current loop or voltage reference line and works with the bit line to complete data read and write operations.

[0089] CL (Control Line): The control line is a wire that connects to the gate of the control transistor and is used to control the turn-on and turn-off of the control transistor.

[0090] +Vpp: Positive polarization voltage;

[0091] -Vpp: Negative polarization voltage.

[0092] Definitions for other terms will be provided in the following description.

[0093] Example 1

[0094] In an embodiment of this application, a 2T2FC ferroelectric memory cell is provided, comprising: a memory transistor; a control transistor, the source of which is connected to the drain of the memory transistor; a first ferroelectric capacitor, one end of which is connected to a first plate line and the other end of which is coupled to the gate of the memory transistor; a second ferroelectric capacitor, one end of which is connected to a second plate line and the other end of which is coupled to the gate of the memory transistor; a word line connected to the gate of the memory transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the memory transistor; and a control line connected to the gate of the control transistor. The control transistor is configured to selectively enable or disable access to the memory transistor.

[0095] Figure 1 This is a schematic diagram of the 2T2FC ferroelectric memory cell structure according to an embodiment of this application, as shown below. Figure 1 As shown, the 2T2FC ferroelectric memory cell of this application includes a storage transistor ST, a control transistor CT coupled to the storage transistor ST, and two planar ferroelectric capacitors (FeCAPs), namely a first ferroelectric capacitor CFA and a second ferroelectric capacitor CFB. One end of CFA and CFB is coupled to the gate of the storage transistor ST, and the other end is connected to the first board line PLA and the second board line PLB, respectively. The source of the control transistor CT is connected to the drain of the storage transistor ST, the drain is connected to the bit line BL, and the gate is connected to the control line CL. The gate of the storage transistor ST is connected to the word line WL, and the source is connected to the source line SL.

[0096] In the embodiments of this application, the storage transistor ST serves as a crucial switch for storing and sensing storage states. It distinguishes logic states by utilizing the threshold voltage change caused by ferroelectric polarization within the storage transistor ST. The control transistor CT is used to gate access to the storage path and is configured to selectively enable or disable access to the storage transistor ST, achieving separation between the storage path and the control path. This supports independent control access and data retention, suppressing leakage in standby and semi-selected states. Simultaneously, the reduced stress on the gate dielectric of individual transistors improves the durability and data retention capability of the storage cell. By employing the storage transistor ST and the control transistor CT, larger storage capacities are supported while reducing leakage current.

[0097] In the embodiments of this application, the polarization state of ferroelectric capacitors is modulated to switch the encoding logic state. By applying voltages of opposite polarities to two ferroelectric capacitors, the two capacitors are reverse polarized, thereby generating different electric fields at the gate of the storage transistor ST to modulate the threshold voltage and thus affect the conduction current during the write operation. For example, when writing logic "1", -Vpp is applied to PLB, causing CFB to polarize upward (away from the gate of the storage transistor ST), and +Vpp is applied to PLA, causing CFA to polarize downward (towards the gate of the storage transistor ST); when writing logic "0", +Vpp is applied to PLB and -Vpp is applied to PLA, producing a polarization state opposite to that of writing logic "1". When reading data, a read voltage is applied to the board line connected to one ferroelectric capacitor, while the board line connected to the other ferroelectric capacitor is grounded. Current flows through the storage transistor ST by activating the control line CL, and the storage logic state is determined based on the detected bit line current. For example, a high current level (channel on) or a low current level (channel off) reflects that the storage logic state based on differential polarization conditions is "1" or "0". This differential polarization scheme improves noise immunity and read accuracy, and is suitable for multi-bit storage levels of AI (artificial intelligence) related workloads.

[0098] Figure 2 This is a schematic diagram of the differential write logic value according to an embodiment of this application, such as... Figure 2 As shown, storing binary data via differential polarization of two ferroelectric capacitors involves applying high positive and negative voltage pulses to the plate lines (PLA and PLB), and the writing method is as follows:

[0099] Write logic "0": Write "0" to CFB, and PLB is polarized downward by applying +Vpp; write "1" to CFA, and PLA is polarized upward by applying -Vpp.

[0100] Write logic "1": Write "1" to CFB, and PLB is polarized upward by applying -Vpp; write "0" to CFA, and PLA is polarized downward by applying +Vpp.

[0101] This configuration of biferroelectric capacitors achieves high perception margin by utilizing the shift in threshold voltage induced by polarization in the storage transistor to distinguish logic states. The polarization state of the biferroelectric capacitor is maintained when power is off, achieving non-volatile storage.

[0102] In the embodiments of this application, the 2T2FC ferroelectric memory cell can be accessed in a multi-step voltage manner to optimize the write operation, such as applying partial voltages in steps (e.g., ±2 / 3Vpp, ±1 / 3Vpp) to avoid writing interference to unselected and semi-selected cells in a large memory array.

[0103] In the embodiments of this application, to prevent data degradation caused by charge leakage in the CFA and CFB after writing to the 2T2FC ferroelectric memory cell, a post-write zeroing scheme is adopted: all active terminals, namely word line WL, bit line BL, source line SL, first board line PLA, second board line PLB, and control line CL, are driven to 0V. This state is maintained before the read operation to ensure that all stored charges remain intact. This scheme eliminates capacitive memory effects that may affect the accuracy of subsequent reads or lead to long-term retention loss.

[0104] In the embodiments of this application, the word line WL (with an applied voltage of less than 1.2V) connected to the gate of the storage transistor ST is used for current sensing. A high current (on) indicates a polarization configuration resulting in a low effective threshold voltage, while a low current (off) indicates a reverse polarization configuration resulting in a high threshold voltage. When writing logic values, two ferroelectric capacitors with opposite polarities represent logic states "0" and "1". When reading data, the current through the storage transistor ST is detected; a high current represents logic "1", and a low current represents logic "0". The high current refers to the drain current of the storage transistor ST when the gate voltage exceeds the threshold voltage and a conductive path is formed in the channel; the low current refers to the drain current of the storage transistor ST when the gate voltage is below the threshold voltage and a conductive path is not formed in the channel. This current-based readout method is reliable, supports differential sensing, and can be scaled to support multi-level cell (MLC) behavior.

[0105] In the embodiments of this application, when the control line CL is activated, the control transistor CT is turned on, forming a current path from bit line BL → control transistor CT → storage transistor ST → source line SL. The conduction level of the storage transistor ST is determined by its gate voltage (modulated by the polarization state of FeCAPs), ultimately controlling the current of the entire circuit.

[0106] In the embodiments of this application, data reading from the 2T2FC ferroelectric memory cell is performed by current-based sensing-based logic state determination through the storage transistor ST. The reading steps are as follows:

[0107] Enable the control transistor CT by activating the control line CL;

[0108] Apply a small read voltage (Vread) of 0.7V to 0.9V to one of the board lines (such as PLB);

[0109] Ground another board line (such as PLA) to establish a voltage gradient;

[0110] The gate of the floating storage transistor ST is affected by the net polarization state of CFA and CFB;

[0111] Apply a read bias voltage (0.2V to 0.7V in this embodiment) to the bit line BL.

[0112] The logic state is determined based on the measured drain current of the storage transistor ST.

[0113] Figure 3 This is a schematic diagram illustrating the reading logic value according to an embodiment of this application, such as... Figure 3 As shown:

[0114] During reading, Vread (read voltage) is applied to PLB while PLA is kept grounded (0V). Vd (0.2V~0.7V) is applied to BL, and the logic state "0" or "1" is read based on the drain current of the storage transistor ST. During reading, the 2T2FC ferroelectric memory cell operates as a ferroelectric field-effect crystal (floating gate), which can detect the drain current generated by gate modulation. +Vpp generates a high current (conduction state), and -Vpp generates a low current (cutoff state), thereby determining the stored logic state.

[0115] In the embodiments of this application, to prevent data degradation caused by residual charge on the gate or floating node after reading the 2T2FC ferroelectric memory cell, a post-read discharge scheme is adopted: all active terminals, namely word line WL, bit line BL, source line SL, first board line PLA, second board line PLB, and control line CL, are driven to 0V. This state is maintained for a certain period of time to ensure that all stored charges are neutralized. This scheme eliminates the capacitive memory effect that may affect subsequent readings or cause loss of long-term retention force.

[0116] In the embodiments of this application, the 2T2FC ferroelectric memory cell is compatible with standard CMOS back-end of line (BEOL) processes. Ferroelectric capacitors are designed to be stacked on top of logic devices and can be implemented using materials and layers commonly found in back-end processes, such as forming TiN electrodes via plasma-enhanced atomic layer deposition (PEALD) and forming ferroelectric HfZrO2 (HZO) layers via atomic layer deposition (ALD). Figure 1 Combining shallow trench isolation (STI) in the front end of line (FEOL) process with standard gate-first transistor technology, the final cell occupies an area of ​​8F² (2F×4F), where F is the minimum feature size of the technology node. This makes the 2T2FC ferroelectric memory cell highly scalable, suitable for integration into CMOS nodes below 22nm, 14nm, and even 10nm.

[0117] In the embodiments of this application, two ferroelectric capacitors are located on both sides of the gate of the storage transistor ST, and both are made of high-k ferroelectric material. The plate terminals at the top of the two ferroelectric capacitors are connected to PLA and PLB respectively to transmit write and read voltages.

[0118] The 2T2FC ferroelectric memory cell of this application embodiment has the following advantages:

[0119] 1) Allows each ferroelectric capacitor to be independently polarized, improves write reliability with differential polarization scheme, supports high-density in-memory computing operations, and improves noise immunity and read accuracy, making it suitable for multi-bit storage levels for AI (artificial intelligence) related workloads.

[0120] 2) The separation of storage path and control path achieves the following advantages:

[0121] Independent control over access and data retention;

[0122] Suppress leakage current in standby and incompletely selected states;

[0123] Durability is improved due to reduced stress in individual gate dielectric layers;

[0124] 3) It features low power consumption and high reliability, making it suitable for in-memory computing (CIM) and neuromorphic computing environments:

[0125] The independent control transistor CT is used to realize the read gating function, so that the 2T2FC ferroelectric memory cell is activated only when explicitly accessed;

[0126] Leakage current suppression is crucial for large arrays;

[0127] This reduces interference between cells, especially when accessing only some cells;

[0128] Durability is improved because the programming voltage is distributed across two ferroelectric capacitors;

[0129] 4) Compatible with standard CMOS back-end processes, requiring only small-area ferroelectric capacitors to achieve high sensing margin, resulting in a compact cell size (8F). 2 ), applicable to neuromorphic and AI-centric memory architectures;

[0130] 5) By utilizing two ferroelectric capacitors and independent storage and control transistors, the problems of scalability limitations and insufficient holding force are solved, thereby improving data reliability, reducing read / write interference, and providing higher energy efficiency;

[0131] The 2T2FC ferroelectric memory cell of this application embodiment significantly improves reliability, especially in low-voltage or battery-constrained environments (such as edge AI chips and IoT memory modules).

[0132] Example 2

[0133] In the embodiments of this application, a method for fabricating a 2T2FC ferroelectric memory cell is provided, comprising the following steps: sequentially depositing a gate oxide layer, a high dielectric constant dielectric layer, and a gate metal layer on a silicon substrate to form gate stacks of a memory transistor and a control transistor, respectively; forming a source diffusion region and a drain diffusion region on the silicon substrate by ion implantation and activation; depositing an interlayer dielectric layer in the source diffusion region and the drain diffusion region, respectively; symmetrically forming two ferroelectric capacitors on both sides of the gate stack of the memory transistor; and connecting the two ferroelectric capacitors to a board line.

[0134] Figure 4 The following is a flowchart of the fabrication method of the 2T2FC ferroelectric memory cell according to an embodiment of this application, with reference to... Figure 4 The preparation method of the T2FC ferroelectric memory cell in Embodiment 2 of this application is described in detail.

[0135] First, in step 201, active areas are defined and isolated on the silicon substrate using shallow trench isolation (STI).

[0136] In embodiments of this application, the step includes: firstly, defining a shallow trench isolation region on a silicon substrate using photolithography, and then forming an STI (Shallow Trench Isolation) trench of a predetermined depth by dry etching (such as HBr / Cl2 plasma) on the shallow trench isolation region. Multiple active device regions 401 are isolated on the silicon substrate through these trenches, thereby defining an isolation region around the active device regions 401 on the silicon substrate to prevent leakage and parasitic coupling.

[0137] In step 202, the surface of the silicon substrate is pretreated.

[0138] In embodiments of this application, the step includes: depositing oxide 402 (such as SiO2, by high-density plasma chemical vapor deposition (HDP-CVD)) in the formed trench to fill the trench; and removing excess material by chemical mechanical polishing (CMP) to retain a flat surface. Figure 5 As shown, multiple active device regions 401 are formed on a silicon substrate by depositing oxide 402 in the trench.

[0139] In step 203, a stack of gates for storage transistors and control transistors is generated on the active device region.

[0140] In embodiments of this application, this step includes:

[0141] Two gate oxide layers 403 are grown or deposited: gate oxide, such as silicon oxynitride gate oxide, is grown on the active device region 401, which has a high dielectric constant (high-k) (improving the interface states of high-k dielectric).

[0142] Depositing a high-k dielectric layer and a TiN gate metal layer to form a gate stack: On two gate oxide layers 403, a high-k dielectric layer 404 and a TiN gate electrode 405 are generated by atomic layer deposition (ALD) to form a gate stack. The gate of the storage transistor and the gate of the control transistor are formed by photolithography and dry etching.

[0143] Patterned memory transistor gates form word lines (WL), and patterned control transistor gates form control lines (CL).

[0144] Ion implantation and annealing are performed to form N+ source diffusion region 406, drain-source diffusion region 407 (serving as the drain of the storage transistor and the source of the control transistor), and drain diffusion region 408. Thermal annealing activates doping and forms a low-resistance junction. Figure 6 As shown, two gate stacks, namely gate oxide layer 403, high-k dielectric layer 404 and TiN gate electrode 405, are sequentially grown on the active device region 401 to form word line (WL) and control line (CL). N+ source diffusion region 406, drain-source diffusion region 407 and drain diffusion region 408 are formed by ion implantation. Finally, high-temperature annealing is performed to activate the dopant and form a low-resistance junction.

[0145] In step 204, bit lines and source lines are generated on the drain and source diffusion regions.

[0146] In the embodiments of this application, the step includes: depositing an interlayer dielectric (ILD) on the source diffusion region 406 and the drain diffusion region 408 and etching contact holes to connect the source diffusion region 406 and the drain diffusion region 408 respectively, and filling the contact holes with a conductive metal (such as tungsten W or copper Cu) to form a source line (SL) and a bit line (BL).

[0147] like Figure 7 and 8As shown, interlayer dielectric layers (ILDs) are deposited in the source diffusion region 406 and the drain diffusion region 408, respectively, and source lines (SLs) and bit lines (BLs) are formed on the interlayer dielectric layers, respectively.

[0148] In the embodiments of this application, step 204 further includes:

[0149] ILD deposition: An oxide (such as SiO2) is deposited above the source diffusion region 406, the drain source diffusion region 407 and the drain diffusion region 408, and then planarized by CMP to generate an interlayer dielectric layer;

[0150] Contact hole formation: Photolithography is performed on the interlayer dielectric layer to etch to the source diffusion region 406 and the drain diffusion region 408 to form contact holes;

[0151] Metal filling: The contact holes are filled with conductive metal to form source lines (SL) and bit lines (BL).

[0152] In step 205, ferroelectric capacitors are generated on both sides of the gate of the storage transistor.

[0153] In embodiments of this application, this step includes:

[0154] Ferroelectric capacitor contact holes 409 are patterned on the gate of the storage transistor and filled with a conductive material, such as... Figure 9 As shown; a common bottom metal pad 410 for the ferroelectric capacitor is formed above the contact hole 409, as... Figure 10 As shown; a TiN bottom electrode 411 is sequentially deposited, a ferroelectric layer 412 is grown, and a TiN top electrode 413 is deposited on a common bottom metal pad 410, as follows. Figure 11 As shown, the ferroelectric layer 412 is activated by annealing to form ferroelectric domains, thus completing the stacked structure of two ferroelectric capacitors.

[0155] Specifically, the ILD is etched to the gate of the storage transistor by photolithography to align both sides of the gate, forming a deep hole; a TiN bottom electrode 411 is deposited on the deep hole by plasma-enhanced ALD (PEALD); a ferroelectric layer 412 is formed by depositing a HfZrO2 ferroelectric thin film by ALD; a TiN top electrode 413 is deposited by ALD; and finally, the electrode pattern is defined by photolithography.

[0156] In step 206, metal wiring is performed.

[0157] In embodiments of this application, a metal wiring layer is used to connect independent board lines PLA and PLB to CFA and CFB; metallization and patterning define word lines (WL) and control lines (CL) and connect them to the transistor gate. Figure 12As shown, board lines 414 and 415, namely PLA and PLB, are formed on the TiN top electrode 413 through interconnect metal layers; word lines WL, control lines CL and other wiring layers, such as bit lines BL and source lines SL, are connected through vias.

[0158] Furthermore, it also includes: depositing a SiN (silicon nitride) etching stop layer, connecting the TiN top electrode 413 of the ferroelectric capacitor through photolithographic vias; etching trenches and electroplating copper to form board lines and word lines.

[0159] In step 207, the backend integration is completed.

[0160] In the embodiments of this application, passivation and planarization required for semiconductor back-end (BE) packaging are performed last to complete the integration of the 2T2FC ferroelectric memory cells. The 2T2FC ferroelectric memory cells are patterned into a layout occupying an area of ​​8F², where F is the minimum feature size of the manufacturing process node. Further, this step includes:

[0161] Size verification: Confirmed by electron beam testing as 2F×4F (=8F) 2 Layout (e.g., 14nm node: lateral gate length 28nm × vertical metal pitch 56nm);

[0162] Deposit passivation layer: Deposit SiN passivation layer and open pad windows.

[0163] The fabrication method of the 1T2FC ferroelectric memory cell in this application embodiment enables the 1T2FC ferroelectric memory cell to be seamlessly integrated onto standard CMOS logic devices, ensuring high density scalability, compatibility with 28nm, 22nm and more advanced nodes, and full compatibility with CMOS back-end processes, thereby supporting high-density and high-performance system-on-chip (SoC) applications.

[0164] Example 3

[0165] In an embodiment of this application, a memory array is provided, including a plurality of 2T2FC ferroelectric memory cells as described above.

[0166] In the embodiments of this application, the control transistors of multiple 2T2FC ferroelectric memory cells share a control line (CL) for control, and two ferroelectric capacitors share a plate line (PLA, PLB) between rows or columns.

[0167] In the embodiments of this application, the memory array is accessed using a multi-step voltage method. By applying multi-step graded voltages to the board lines and word lines of the 2T2FC ferroelectric memory cell, the target cell is selectively programmed and interference with the half-selected cell is prevented.

[0168] In a memory array, a half-selected cell refers to a memory cell that is only selected by column strobe (word line WL activated) or row strobe (bit line BL activated) during read and write operations, but is not fully selected. Such cells are in a state of potential interference.

[0169] The following section uses a 3×4 memory array as an example to explain the multi-step voltage access method in detail from the perspectives of the write and read processes.

[0170] Figures 13 to 16 As an example of writing to this memory array, firstly, "0" is written to the 2T2FC ferroelectric memory cell in the memory array, in two stages:

[0171] Phase 1, such as Figure 13 As shown, WL(1) is 0V, WL(2-4) is 2 / 3Vpp applied; all BL and SL are 0V; CL(1) is Vdd applied, CL(2-4) is 0V; PLA(1-3) is 1 / 3Vpp applied; PLB(2) is Vpp applied, PLB(1) and PLB(3) are 1 / 3Vpp applied;

[0172] The second stage, such as Figure 14 As shown, PLB(1-3) is applied with -1 / 3Vpp, PLA(2) is applied with -Vpp, PLA(1) and PLA(3) are applied with -1 / 3Vpp, and WL(2-4) is applied with -2 / 3Vpp.

[0173] Writing a "1" to the 2T2FC ferroelectric memory cell in the memory array is done in two stages:

[0174] Phase 1, such as Figure 15 As shown, WL(1) is applied with 0V, WL(2-4) is applied with 2 / 3Vpp; all BL and SL are 0V; CL(1) is applied with Vdd, CL(2-4) is applied with 0V; PLB(1-3) is applied with 1 / 3Vpp; PLA(2) is applied with Vpp, PLA(1) and PLA(3) are applied with 1 / 3Vpp;

[0175] The second stage, such as Figure 16 As shown, PLA(1-3) is applied with -1 / 3Vpp, PLB(2) is applied with -Vpp, PLB(1) and PLB(3) are applied with -1 / 3Vpp, and WL(2-4) is applied with -2 / 3Vpp.

[0176] Figures 17 to 20 As another example of writing to this memory array, firstly, "0" is written to the 2T2FC ferroelectric memory cell in the memory array, in two stages:

[0177] Phase 1, such as Figure 17As shown, only WL(1) is given -1 / 2Vpp, while the rest of WL(2-4) are 0V, and all BL and SL are 0V; CL(1) is given Vdd, and CL(2-4) are 0V; PLB(2) is given 1 / 2Vpp, and the rest of the board wires are connected to 0V;

[0178] The second stage, such as Figure 18 As shown, WL(1) is applied with 1 / 2Vpp, PLA(2) is applied with -1 / 2Vpp, and PLB(2) is connected to 0V.

[0179] Writing a "1" to the 2T2FC ferroelectric memory cell in the memory array is done in two stages:

[0180] Phase 1, such as Figure 19 As shown, WL(1) is applied with -1 / 2Vpp, PLA(2) is applied with 1 / 2Vpp, and PLB(2) is connected to 0V;

[0181] The second stage, such as Figure 20 As shown, WL(1) is applied with 1 / 2Vpp, PLB(2) is applied with -1 / 2Vpp, and PLA(2) is connected to 0V.

[0182] Figures 21 to 22 For an example of reading from this memory array, the reading process consists of two stages:

[0183] Phase 1, such as Figure 21 As shown, only WL(1) is given Vdd, while the rest of WL(2-4) are 0V; BL(2) is given Vdd, while the rest of BL are 0V; CL(1) is given Vdd, while CL(2-4) are 0V; PLB(2) is given Vread, while the rest of the board wires are connected to 0V; Vread < Vc, Vd = 0.2V-0.7V <Vdd);

[0184] In the second stage, PLA(2) applies Vread, and PLB(2) is connected to 0V; Vread < Vc, Vd = 0.2V - 0.7V. <Vdd)。

[0185] Here, Vc represents the coercive voltage, defined as the minimum voltage required to reverse the polarization direction of ferroelectric domains; in the polarization-voltage (PV) hysteresis loop, Vc is the voltage at which the polarization value crosses zero during the voltage scan. It marks the inflection point where ferroelectric materials switch between two states: positive remanent polarization +Pr (after applying +V>Vc), and negative remanent polarization -Pr (after applying -V<-Vc).

[0186] Furthermore, the memory array of this application also includes a write control unit configured to apply multi-step graded voltages to the board lines and word lines of the 2T2FC ferroelectric memory cell to selectively program target cells and prevent interference with half-selected cells.

[0187] Example 4

[0188] In the embodiments of this application, an AI chip is provided, including the memory array described above. AI chips employing this memory array feature low power consumption and high reliability.

[0189] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A 2T2FC ferroelectric memory cell, characterized by, comprising: a storage transistor; a control transistor, whose source is connected to the drain of the storage transistor; a first ferroelectric capacitor, one end of which is connected to a first plate line, and the other end of which is coupled to the gate of the storage transistor; a second ferroelectric capacitor, one end of which is connected to a second plate line, and the other end of which is coupled to the gate of the storage transistor; a word line, which is connected to the gate of the storage transistor; a bit line, which is connected to the drain of the control transistor; a source line, which is connected to the source of the storage transistor; a control line, which is connected to the gate of the control transistor; the control transistor is configured to selectively enable or disable access to the storage transistor; by applying voltages of opposite polarity to the first ferroelectric capacitor and the second ferroelectric capacitor, the polarization state of the ferroelectric capacitor is modulated to switch the encoded logic state.

2. The 2T2FC ferroelectric memory cell of claim 1, wherein, When the 2T2FC ferroelectric memory cell writes a logic "1", a positive polarization voltage is applied to the first ferroelectric capacitor, so that its polarization direction is towards the gate of the storage transistor, while a negative polarization voltage is applied to the second ferroelectric capacitor, so that its polarization direction is away from the gate of the storage transistor.

3. The 2T2FC ferroelectric memory cell of claim 1, wherein, When the 2T2FC ferroelectric memory cell writes a logic "0", a negative polarization voltage is applied to the first ferroelectric capacitor, so that its polarization direction is away from the gate of the storage transistor, while a positive polarization voltage is applied to the second ferroelectric capacitor, so that its polarization direction is towards the gate of the storage transistor.

4. The 2T2FC ferroelectric memory cell of claim 2 or 3, wherein, After the 2T2FC ferroelectric memory cell writes a logic, the word line, the control line, the bit line, the source line, the first plate line and the second plate line are all driven to 0V to prevent data degradation caused by charge leakage of the ferroelectric capacitor.

5. The 2T2FC ferroelectric memory cell of claim 1, wherein, When the 2T2FC ferroelectric memory cell reads data: the control transistor is enabled through the control line; one of the first plate line and the second plate line is applied with a read voltage, and the other of the first plate line and the second plate line is kept at ground; a read bias voltage is applied to the bit line; the stored logic state is determined according to the detected drain current of the storage transistor.

6. The 2T2FC ferroelectric memory cell of claim 5, wherein, The basis for determining the logic state is that high current represents logic "1" and low current represents logic "0"; the high current refers to the detected drain current of the storage transistor when the gate voltage exceeds the threshold voltage and the channel forms a conductive path; the low current refers to the detected drain current of the storage transistor when the gate voltage is lower than the threshold voltage and the channel does not form a conductive path.

7. The 2T2FC ferroelectric memory cell of claim 5, wherein, After the 2T2FC ferroelectric memory cell reads data, the word line, the control line, the bit line, the source line, the first plate line and the second plate line are all discharged to 0V to eliminate residual gate charge, so as to prevent data read interference or long-term data retention degradation.

8. A method of fabricating a 2T2FC ferroelectric memory cell, comprising: comprising the following steps: depositing a gate oxide layer, a high dielectric constant dielectric layer and a gate metal layer on a silicon substrate in sequence to form a gate stack of a storage transistor and a control transistor, respectively; forming a source diffusion region and a drain diffusion region on the silicon substrate by ion implantation and activation, respectively; depositing an interlayer dielectric layer on the source diffusion region and the drain diffusion region, respectively; forming two ferroelectric capacitors symmetrically on both sides of the gate stack of the memory transistor; connecting the two ferroelectric capacitors to plate lines.

9. The method of claim 8, wherein the 2T2FC ferroelectric memory cell is formed by: After the step of forming the gate stack of the memory transistor and the control transistor, further comprising the steps of forming word lines and control lines.

10. The method of claim 8, wherein the 2T2FC ferroelectric memory cell is formed by: After the step of depositing the interlayer dielectric layer, further comprising the steps of forming bit lines and source lines.

11. The method of fabricating a 2T2FC ferroelectric memory cell of claim 8, wherein, The step of forming two ferroelectric capacitors symmetrically on both sides of the gate stack of the memory transistor, further comprising: on both sides of the gate metal layer, sequentially depositing a TiN bottom electrode, a ferroelectric layer and a TiN top electrode to form a symmetric first ferroelectric capacitor and a second ferroelectric capacitor; wherein, the ferroelectric layer is formed by atomic layer deposition, and the TiN bottom electrode and the TiN top electrode are formed by plasma enhanced atomic layer deposition.

12. The method of fabricating a 2T2FC ferroelectric memory cell of claim 8, wherein, The 2T2FC ferroelectric memory cell is patterned into a layout occupying an 8F2area, where F is the minimum feature size of a manufacturing process node.

13. A 2T2FC ferroelectric memory cell prepared according to the preparation method of any one of claims 8 to 12.

14. A memory array, comprising: A memory array comprising a plurality of 2T2FC ferroelectric memory cells according to any one of claims 1 to 7.

15. The memory array of claim 14, wherein, Further comprising a write control unit configured to apply a multi-step staged voltage to the plate lines and the word lines of the 2T2FC ferroelectric memory cell to selectively program target cells and prevent disturb half-selected cells.

16. An AI chip, comprising: A memory array comprising the 2T2FC ferroelectric memory cell of any one of claims 14 to 15.

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