Memory test circuit, memory controller and microprocessor architecture

Abstract

The invention provides a memory test circuit, a memory controller and a microprocessor architecture, and is applied to the technical field of computers, the circuit comprises a configuration module and a memory access module, the configuration module is used for storing mode configuration information, and any one of a plurality of preset test modes is specified as a target test mode through the mode configuration information; the memory access module responds to the test request and sends an access request for testing the memory to the memory controller according to the target test mode, so that the memory controller accesses the memory according to the obtained access request, the circuit tests the memory according to the configured target test mode, an operating system does not need to participate in the test process, and the test efficiency is improved. Compared with the prior art, the time consumed for starting the operating system can be saved, the memory testing efficiency is improved, meanwhile, the access request for testing the memory is directly provided by the memory testing circuit and no longer depends on network-on-chip transmission, other interference factors can be avoided, and therefore the accuracy of a testing result is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a memory test circuit, a memory controller and a microprocessor architecture. BACKGROUND

[0002] In modern computer technology, memory is used for data caching to realize efficient data interaction with the processor, and the health status of the memory directly determines the overall performance and stability of the computer system. If the memory fails and causes the loss of cached data, it will not only cause the overall performance of the system to decline, but also may cause various errors and affect the normal operation of the computer system. Therefore, ensuring that the memory is fully tested before use ensures the reliability of the memory, which is the key to ensuring the normal operation of the system.

[0003] The related technology tests the memory through a dedicated memory test software, that is, after the operating system is loaded, the memory test software is started, and the preset test operation is executed by the memory test software and the test result is fed back. The memory is tested through software, the operation process is simple, and the test algorithm is various, but the running of the memory test software depends on the normal loading of the operating system, and the operating system must be loaded before the memory test is carried out, which undoubtedly reduces the test efficiency, and at the same time, the test process needs to be executed by the processor, and the memory read-write request generated by the processor based on the memory test software needs to pass through the network on chip before reaching the memory, which process is easy to introduce other interference factors, resulting in low accuracy of the test result. SUMMARY

[0004] The purpose of the embodiment of the present application is to provide a memory test circuit, a memory controller and a microprocessor architecture to improve the memory test efficiency and the accuracy of the test result.

[0005] In a first aspect, the present application provides a memory test circuit applied to memory testing in the post-silicon debug process of a microprocessor architecture, the microprocessor architecture further comprising a memory controller and a memory, the memory test circuit comprising a configuration module and a memory access module, wherein

[0006] The configuration module is configured to store mode configuration information, and the mode configuration information is configured to specify any one of a plurality of preset test modes for testing the performance of the memory as a target test mode;

[0007] The memory access module is configured to determine the target test mode according to the mode configuration information in response to a test request, and send an access request for testing the memory to the memory controller according to the target test mode, so that the memory controller accesses the memory according to the access request.

[0008] Based on the above, the memory test circuit provided in the application is applied to memory test in a post-silicon debug process of a microprocessor architecture, the microprocessor architecture further includes a memory controller and a memory, the memory test circuit includes a configuration module and a memory access module, the configuration module is configured to store mode configuration information, and any one of a plurality of preset test modes is specified as a target test mode through the mode configuration information, the memory access module is configured to send an access request for testing the memory to the memory controller according to the target test mode in response to a test request, so that the memory controller accesses the memory according to the obtained access request. Compared with the related art in which a dedicated memory test software is used to test the memory, the application provides a memory test circuit, the memory is tested according to the configured target test mode, the test process does not need to involve an operating system, and whether the operating system is started or not does not affect the test process, so that the time required for starting the operating system can be saved, and the memory test efficiency is improved. At the same time, the access request for testing the memory is directly provided by the memory test circuit, and no longer depends on network transmission on chip, so that other interference factors can be avoided, and the accuracy of the test result is improved.

[0009] In an optional implementation, the access request includes a write request and a read request, and any of the preset test modes includes a test behavior mode, a test address mode, and a test data mode.

[0010] The memory access module includes:

[0011] a test control module configured to generate an enable signal according to the test behavior mode in the target test mode;

[0012] a first address generation module configured to generate a first target memory address according to the test address mode in the target test mode in response to the enable signal;

[0013] a first data generation module configured to generate target test data according to the test data mode in the target test mode in response to the enable signal;

[0014] a second address generation module configured to generate a second target memory address according to the test address mode in the target test mode in response to the enable signal;

[0015] The test control module is further configured to send a write request for testing the memory to the memory controller based on the first target memory address and the target test data, or send a read request for testing the memory to the memory controller based on the second target memory address.

[0016] The memory test circuit provided in the application, the memory access module includes a test control module, a first address generation module, a first data generation module, and a second address generation module. The test control module can control the enable state of the first address generation module, the second address generation module, and the first data generation module, independently control the generation of the memory address and the test data, and control the process flexibly to meet the test requirements of different preset test modes in the actual test process. Meanwhile, the target test mode is determined based on the mode configuration information, and the target memory address and the target test data are obtained based on the target test mode, that is, the user can configure the target test mode, configure the specific target memory address and the target test data, and realize the test on the specific memory address and the memory data, so that the test process is more targeted and meets the demand of the targeted test in the actual application.

[0017] In an optional implementation, the access request includes a write request and a read request, the write request includes a first target memory address and target test data, and the read request includes a second target memory address.

[0018] The memory test circuit further includes:

[0019] The preprocessing module is configured to convert the target test data into a plurality of processed data recognizable by the memory controller, send each processed data to the memory according to the first target memory address, and obtain the memory data in the memory according to the second target memory address.

[0020] The memory test circuit provided in the application adds a preprocessing module. According to the actual test requirement, the memory access module can initiate a write request to the memory or a read request to the memory. The preprocessing module converts the test data in the write request into a plurality of processed data, so that the memory can successfully receive and store the processed data. Correspondingly, the preprocessing module obtains the memory data in the memory according to the second target memory address, realizes the acquisition of the memory data, and not only verifies the reliability of the memory response to the read request, but also uses the obtained memory data to verify the correctness of the data stored in the memory, thereby providing basic data for the memory test.

[0021] In an optional implementation, the memory test circuit further includes:

[0022] The data verification module is configured to verify the memory data fed back by the memory and the memory address to which the memory data belongs.

[0023] The memory testing circuit provided in this application adds a data verification module. The data verification module can verify the memory data returned by the memory and the memory address to which the memory data belongs, to determine whether the memory meets the application requirements in terms of the location of the stored data and the reliability of the stored data. At the same time, the verification results can be obtained directly through the data verification module, so testers no longer need to determine the memory performance based on the response of write and read requests, saving testers' manpower and improving testing efficiency.

[0024] In one optional implementation, the memory testing circuit further includes:

[0025] The test result caching module is used to store the verification results of the data verification module.

[0026] The memory testing circuit provided in this application adds a test result caching module. By storing the verification results through the test result caching module, unified management of the verification results can be achieved, which facilitates further analysis of memory performance and helps to improve memory testing efficiency.

[0027] In one optional implementation, any of the preset test modes includes a test behavior mode, a test address mode, and a test data mode, wherein,

[0028] The test behavior modes include any one of the following: write-only mode, write-then-read mode, and read-write interleaved mode;

[0029] The test address mode includes any one of the following: randomly generated memory address, custom memory address, or generating a memory address starting from any address of the memory and according to a preset step size;

[0030] The test data mode includes any one of the following: randomly generated test data, custom test data, and test data generated according to a preset data generation algorithm.

[0031] In the memory testing circuit provided in this application, any preset test method is characterized by three dimensions: test behavior mode, test address mode, and test data mode. The test behavior mode, test address mode, and test data mode each include multiple implementation methods. By combining different specific implementation methods, different preset test modes can be obtained to meet different testing needs and help to achieve full and comprehensive testing of memory.

[0032] In one alternative implementation, the memory test circuit is positioned adjacent to the memory controller.

[0033] In the memory test circuit provided in the application, the memory test circuit is arranged adjacent to the memory controller, the memory access path is shorter, the memory access efficiency is effectively improved, and meanwhile, the shorter memory access path can reduce the probability of interference factors introduced by the memory access path in the memory access process, and help to further improve the reliability of the test result.

[0034] In a second aspect, the application provides a memory controller, comprising: a master module, wherein,

[0035] The master module comprises:

[0036] The memory test circuit provided in any of the embodiments of the first aspect of the application is used to initiate an access request to the memory in a post-silicon debug memory test process.

[0037] The scheduling module is configured to schedule the obtained access request according to a preset scheduling rule.

[0038] The memory controller provided in the application integrates the memory test circuit, tests the memory through the memory test circuit, and does not need the operating system to participate in the test process, and whether the operating system is started or not does not affect the test process, so that the time required for starting the operating system can be saved, the memory test efficiency is improved, and meanwhile, the access request for testing the memory is directly provided by the memory test circuit, and does not depend on the on-chip network transmission, so that other interference factors can be avoided, and the accuracy of the test result is improved.

[0039] In an optional embodiment, the master module further comprises:

[0040] The second conversion module is configured to convert an access request initiated by other control modules in a microprocessor architecture to which the memory controller belongs into a protocol;

[0041] The gating module has a first input end, a second input end and an output end;

[0042] The first input end is configured to receive the access request output by the second conversion module after conversion;

[0043] The second input end is connected with the memory test circuit to receive the access request of the memory test circuit;

[0044] The output end is connected with the scheduling module;

[0045] The gating module is configured to connect the first input end and the output end, and / or connect the second input end and the output end.

[0046] In the memory controller provided in this application, the main control module is also provided with a gating module. By connecting different transmission paths through the gating module, it can be ensured that the memory test circuit does not affect the normal operation of the memory controller in the microprocessor architecture. At the same time, memory testing can also be completed. When both the first input terminal and the second input terminal are connected to the output terminal, the response capability of the memory under high-frequency access scenarios can be further verified.

[0047] Thirdly, this application provides a microprocessor architecture, including: a memory controller, memory, and a memory test circuit as provided in any embodiment of the first aspect of this application, wherein...

[0048] The memory test circuit, the memory controller, and the memory are connected in sequence.

[0049] During the memory testing process of the microprocessor architecture after silicon debugging, the memory testing circuit sends an access request to the memory controller to test the memory.

[0050] The memory controller accesses the memory according to the access request. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A structural block diagram of a memory testing circuit provided in an embodiment of this application;

[0053] Figure 2 A structural block diagram of another memory test circuit provided in an embodiment of this application;

[0054] Figure 3 A structural block diagram of another memory test circuit provided in the embodiments of this application;

[0055] Figure 4 A structural block diagram of another memory testing circuit provided in the embodiments of this application;

[0056] Figure 5 A flowchart illustrating the memory testing process using the memory testing circuit provided in the embodiments of this application;

[0057] Figure 6 A structural block diagram of a memory controller provided in an embodiment of this application;

[0058] Figure 7Another structure block diagram of a memory controller provided by an embodiment of the present application is provided.

[0059] Figure 8 A schematic diagram of a microprocessor architecture provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of the present application.

[0061] Modern microprocessor architectures usually include multiple components, such as processor cores, video processing units, memory controllers, peripheral controllers, and the like. Some of the components generate intermediate data in operation, but they do not have enough space to store the data. Most of the data caches in the microprocessor architecture are implemented through memory. Therefore, memory is one of the core components of the microprocessor architecture, and its health status directly determines the overall performance and stability of the system. Memory failure can cause cache data loss, which not only leads to system performance degradation, but also causes various errors, and even hardware damage. Therefore, ensuring that the memory is fully tested before use and ensuring its reliability is the key to ensuring the normal operation of the system.

[0062] The related art tests the memory through dedicated memory test software, such as MemTest86, Memtest64, Stress-ng, and the like. The memory test software contains multiple test algorithms, can provide comprehensive test scenarios, and has a simple test process without complex operations. Only the memory test software needs to be started under the operating system, and then the test result reported by the memory test software can be waited for. However, the operation of the memory test software depends on the normal loading of the operating system, and the operating system must be loaded before the memory test is carried out, which undoubtedly reduces the test efficiency. At the same time, the test process needs to be executed by the processor, and the memory read / write request generated by the processor based on the memory test software needs to pass through the network on chip before reaching the memory. This process is easy to introduce other interference factors, resulting in low accuracy of the test result.

[0063] To solve the above problems, the present application provides a memory test circuit, which directly generates an access request for testing the memory. The test process does not need the participation of the operating system, and whether the operating system is started or not does not affect the test process. Therefore, the time-consuming required for starting the operating system can be saved, and the memory test efficiency is improved. At the same time, the access request for testing the memory is directly provided by the memory test circuit, and no longer depends on the network on chip transmission, which can avoid causing other interference factors, thereby improving the accuracy of the test result.

[0064] Based on the above content, reference is made toFigure 1 The memory test circuit provided by the embodiments of the present application comprises a configuration module 10 and a memory access module 20. The configuration module 10 is connected to the memory access module 20. The memory access module 20 is further connected to a memory through a memory controller.

[0065] First of all, it should be pointed out that the memory test circuit provided by the embodiments of the present application is applied to memory testing in a post-silicon debug process of a microprocessor architecture. The memory test circuit is integrated in the microprocessor architecture and exists as a hardware component of the microprocessor architecture. In combination with Figure 1 As shown in the figure, the microprocessor architecture further comprises a memory controller and a memory. Of course, the microprocessor architecture can further comprise other components, such as the aforementioned processor core, peripheral controller, etc. For details, please refer to the related art, which will not be described one by one here. As a possible implementation, the memory test circuit provided by each embodiment of the present application is arranged adjacent to the memory controller. In this way, the memory access path of the memory test circuit is shorter, which effectively improves the memory access efficiency. At the same time, shortening the memory access path can also reduce the probability of introducing interference factors in the memory access process, which helps to further improve the reliability of the test results.

[0066] In the memory test circuit provided by the embodiments of the present application, the configuration module 10 is configured to store mode configuration information. The mode configuration information is used to specify any one of a plurality of preset test modes for testing the performance of the memory as a target test mode.

[0067] In an optional implementation, any preset test mode provided by the present application comprises a test behavior mode, a test address mode and a test data mode. In other words, any preset test mode is represented by three dimensions of the test behavior mode, the test address mode and the test data mode. The test behavior mode is used to indicate the way of initiating an access request to the memory. The test address mode is used to indicate the way of determining any memory address in the memory. The test data mode is used to indicate the way of generating test data.

[0068] In actual application, the test behavior mode comprises any one of a write-only mode, a write-then-read mode and a read-write interleaving mode. The write-only mode refers to continuous write operation on the memory. The write-then-read mode refers to continuous write operation on the memory first, followed by continuous read operation. The read-write interleaving mode refers to alternating read operation and write operation on the memory.

[0069] The test address mode includes any one of the following: randomly generating a memory address, defining a memory address, and generating a memory address starting from any address of the memory and according to a preset step. The randomly generating a memory address refers to generating a random number by using a pseudo-random number generator, and determining a memory address based on the random number. The defining a memory address refers to that a user can select one or more memory addresses according to a test requirement. The generating a memory address starting from any address of the memory and according to a preset step can also be defined as generating a continuous address, that is, generating a memory address starting from any address of the memory and according to a preset step in an accumulated manner.

[0070] The test data mode includes any one of the following: randomly generating test data, defining test data, and generating test data according to a preset data generation algorithm. The randomly generating test data refers to generating a random number by using a pseudo-random number generator, and using the random number as test data. The defining test data refers to that a user can configure test data according to a test requirement, and if the user defines multiple test data, the test data can be used in a loop in a test process. The memory test circuit provided in the embodiment of the application supports multiple preset data generation algorithms, including but not limited to the following algorithms:

[0071] 1. repeat: the generated test data is completely consistent, and the same test data is repeatedly provided;

[0072] 2. seqinc: the generated test data is 1 greater than the previous data, and different test data is provided in an accumulated manner;

[0073] 3. inv: the generated test data is the inverse of the previous test data, that is, different test data is provided by using an inverse operation;

[0074] 4. shift: the generated test data is a shift operation on the previous test data. Taking 4-bit test data as an example, if the initial configuration is 4'b0001, the generated test data should be 4'b0001, 4'b0010, 4'b0100, 4'b1000, 4'b0001, and so on.

[0075] 5. shiftinv: the test data generation adds an inverse operation in the shift operation process. Taking 4-bit test data as an example, if the initial configuration is 4'b0001, the generated test data is 4'b0001, 4'b1110, 4'b0010, 4'b1101, 4'b0100, 4'b1011, 4'b1000, 4'b0111, 4'b0001, 4'b1110, and so on.

[0076] It can be understood that the above test behavior mode, test address mode and test data mode can be combined in various ways, such as the test behavior mode selecting the write-only mode, the test address mode selecting the custom memory address, and the test data mode selecting the randomly generated test data, or the test behavior mode selecting the write-then-read mode, the test address mode selecting the randomly generated memory address, and the test data mode selecting the custom test data, and of course, there are other combination modes, which will not be listed one by one here. Any combination mode and corresponding preset test mode, in other words, the user can select different test behavior modes, test address modes and test data modes in the configuration module 10 to obtain the corresponding target test mode.

[0077] Based on the above, as an optional implementation, the configuration module 10 can configure a corresponding register for each test behavior mode, each test address mode and each test data mode, that is, configure a corresponding enable state bit. Different values are written in the register to represent whether the corresponding mode is selected, that is, whether it is in the enabled state. Specifically, a first value, such as 1, represents that the corresponding mode is selected (i.e., enabled), and a second value, such as 0, represents that the corresponding mode is not selected (i.e., disabled). Of course, in actual applications, the configuration module 10 can also use other ways to represent whether any of the above modes is selected by the user, which will not be described one by one here. Without departing from the core idea of the present application, it also belongs to the scope of protection of the present application.

[0078] The memory test circuit provided in the present application is characterized by three dimensions of test behavior mode, test address mode and test data mode, and the test behavior mode, test address mode and test data mode each include multiple implementation modes. Different preset test modes can be obtained by combining different specific implementation modes, which can meet different test requirements and help to fully and comprehensively test the memory. In actual applications, different combination modes can achieve different tests with different emphases, which will be described in the subsequent content, and will not be described here.

[0079] It can be understood that in the process of testing the memory, some scenarios only need to test part of the memory space in the memory. If not distinguished, each test is implemented in the form of traversing all the memory space, which will inevitably seriously reduce the test efficiency. Based on this, as an optional implementation, the configuration module 10 can also be used to store space configuration information, which specifies the to-be-tested memory space in the memory through the space configuration information. Specifically, the space configuration information can include a start address and a capacity of the to-be-tested memory space, and the combination of the two can uniquely determine the specific location of the to-be-tested memory space in the memory. The start address can be any address in the memory specified by the user, and if the user does not specify, an address in the memory can be randomly selected as the start address. Through the space configuration information, targeted testing of part of the memory space in the memory can be realized, meeting the demand of testing part of the memory space in the memory in actual application. At the same time, by specifying the to-be-tested memory space, the task amount of the test process can also be effectively reduced, further improving the test efficiency.

[0080] Of course, the configuration module 10 can also be used to store other configuration information, which will be described in detail in combination with subsequent embodiments, and will not be described here.

[0081] The memory access module 20 is mainly used to control the progress of the test process. Specifically, the memory access module 20 responds to the test request, queries the mode configuration information stored in the configuration module 10, and determines a target test mode from the plurality of preset test modes according to the mode configuration information. Further, the memory access module 20 sends an access request for testing the memory to the memory controller according to the target test mode, and the memory controller accesses the memory according to the access request, thereby completing the test of the memory according to the response of the memory to the access request.

[0082] As described above, in the related art, the execution of the memory test software depends on the processor and the operating system loaded thereon. In order to eliminate the dependence of the test process on the processor, the aforementioned test request for starting the test process should also be avoided to be issued by the processor. Based on this, as a possible implementation, the test request can be generated by the firmware of the microprocessor architecture. In the process of starting the microprocessor architecture or loading the corresponding firmware in other application scenarios, the test request is generated, and then the test of the memory is completed. In this way, the influence of the test process on the processor core and the operating system can be eliminated, thereby improving the test efficiency. Of course, the test request can also be triggered by the user in a conventional manner, which will not be described here.

[0083] In summary, the memory test circuit provided by the embodiment of the present application, the configuration module is configured to store mode configuration information, and any one of the plurality of preset test modes is specified as a target test mode through the mode configuration information. The memory access module sends an access request for testing the memory to the memory controller according to the target test mode, so that the memory controller accesses the memory according to the obtained access request. Compared with the related art, the memory is tested based on the dedicated memory test software. The memory test circuit provided by the embodiment of the present application tests the memory according to the configured target test mode. The test process does not need to involve the operating system. Whether the operating system is started or not does not affect the test process. Therefore, the time required for starting the operating system can be saved, and the memory test efficiency is improved. At the same time, the access request for testing the memory is directly provided by the memory test circuit, and no longer depends on the network-on-chip transmission. Other interference factors can be avoided, thereby improving the accuracy of the test result.

[0084] It can be understood that the access request for the memory includes a write request and a read request. In actual application, the memory access module needs to issue a write request and a read request according to the target test mode. Based on this, another memory test circuit is provided in the embodiment of the present application, which is described with reference to Figure 2 On the basis of the foregoing embodiment, the embodiment of the present application provides an optional implementation manner of the memory access circuit. Specifically, the memory access module 20 includes a test control module 210, a first address generation module 220, a first data generation module 230, and a second address generation module 240.

[0085] As shown in Figure 2 , the test control module 210 is connected to the first address generation module 220, the first data generation module 230, and the second address generation module 240, respectively. Further, the test control module 210, the first address generation module 220, the first data generation module 230, and the second address generation module 240 are also connected to the configuration module 10. For clearer display of the specific structure of the memory access module 20, the connection relationship between the configuration module 10 and each constituent module in the memory access module 20 is indicated by an arrow in Figure 2 .

[0086] Based on the above connection relationship, the test control module 210 is mainly used for controlling the access request during the test of the memory, and is responsible for the generation and switching of the read request and the write request. Specifically, the test control module 210 responds to the test request, accesses the configuration module 10, and obtains the mode configuration information of the configuration module 10. The target test mode is determined according to the mode configuration information, and an enable signal is generated according to the test behavior mode in the target test mode.

[0087] The first address generation module 220, in response to the obtained enable signal, acquires the target test mode indicated by the mode configuration information in the configuration module 10, and generates a first target memory address according to the test address mode in the target test mode. Correspondingly, the first data generation module 230, in response to the obtained enable signal, acquires the target test mode indicated by the mode configuration information in the configuration module 10, and generates target test data according to the test data mode in the target test mode. The second address generation module 240, in response to the obtained enable signal, acquires the target test mode indicated by the mode configuration information in the configuration module 10, and generates a second target memory address according to the test address mode in the target test mode.

[0088] Regarding the address generation module (including the first address generation module 220, the second address generation module 240, and other address generation modules provided in subsequent embodiments), it needs to be explained that: if the test address mode is a continuous address mode, the address generation module will generate a corresponding address each time it receives an enable signal, and after generating an address, the address will be adjusted based on a preset step size at the next address generation; if the test address mode is to generate a random memory address, the address generation module will generate a random address each time it receives an enable signal; if the test address mode is a user-defined memory address, according to the number of user-defined memory addresses, the address generation module selects one from the user-defined memory addresses in response to the current enable signal each time it receives an enable signal, and selects other user-defined memory addresses in a polling manner when receiving subsequent enable signals, for example: the user-defined addresses are A, B, and C, then the generated addresses are A, B, C, A, … each time an enable signal is received.

[0089] Regarding the data generation module (including the first data generation module 230 and other data generation modules provided in subsequent embodiments), in addition to generating target test data according to the test data mode described above, the generation of target test data may also depend on other configuration information, such as data variation bit width, initial data, etc. Of course, these configuration information is also stored by the configuration module 10. The following takes the memory test circuit with an external data bit width of 256 bits as an example to explain the role of data variation bit width, initial data, and test data mode in generating target test data.

[0090] A. The data variation bit width is 32 bits, the initial data is 32'h1, the preset data generation algorithm is selected as seqinc, and the form of the target test data output by the data generation module is:

[0091]

[0092] B, the data change bit width is 64 bits, the initial data is 64'h1, the preset data generation algorithm is selected shift, and the form of the target test data output by the data generation module is:

[0093]

[0094] The process of generating target test data by using other preset data generation algorithms can be implemented by referring to the above content, and will not be described one by one here.

[0095] The test control module 210 obtains the first target memory address and the target test data, generates a write request based on the first target memory address and the target test data, and sends the write request to the memory controller, or generates a read request based on the second target memory address and sends the read request to the memory controller.

[0096] It can be understood that according to the foregoing content, the test behavior mode in the target test mode is used to indicate the way of initiating an access request to the memory, and based on this, the test control module 210 outputs an enable signal based on the test behavior mode of the target test mode, which is also matched with the requirement of the test behavior mode. Taking the write-only mode as an example, the write-only mode will perform continuous write operations on the memory, and based on this, the test control module 210 will continuously send enable signals to the first address generation module 220 and the first data generation module 230, so that the first address generation module 220 continuously generates the first target memory address according to the test address mode in the target test mode, and correspondingly, the first data generation module 230 continuously generates the target test data according to the test data mode in the target test mode. The test control module 210 generates a corresponding write request according to the obtained first target memory address and target test data after sending each enable signal, so as to continuously output the write request according to the write-only mode. The control process of other target test modes is similar, and will not be described one by one here.

[0097] It should be noted that the number of times of sending the access request by the memory access module 20 is determined by the to-be-tested memory space and the data amount of each access, and the test control module 210 is further used to determine the number of times of generating the enable signal (i.e., the number of times of accessing the memory) based on this. In actual application, all memory addresses of the to-be-tested memory space are traversed, so as to achieve the purpose of comprehensively testing the to-be-tested memory space.

[0098] It also needs to be explained that each address generation module described in the present application has the same logical design, based on which, when each address generation module generates memory addresses according to the same test address mode, the corresponding addresses when completely copying the write request can be ensured, and the final address verification is realized, such as in the write request generation process, under the action of the enable signal, the address generated by the address generation module is A, B, C, D…, then in the read request generation process, under the action of the enable signal, the address generated by the address generation module is also A, B, C, D…. Correspondingly, each data generation module described in the present application also has the same logical design, when generating target test data according to the same test data mode, the target test data generated by different data generation modules is the same, and finally data verification is realized based on this. As for the specific process of address verification and data verification, it will be expanded in the subsequent embodiments, which will not be described here.

[0099] In summary, in the memory test circuit provided by the embodiments of the present application, the memory access module includes a test control module, a first address generation module, a first data generation module, and a second address generation module. The test control module can control the enable state of the first address generation module, the second address generation module, and the first data generation module, independently control the generation of memory addresses and test data, and the control process is flexible, which can meet the test requirements of different preset test modes in actual test process. At the same time, since the target test mode is determined based on the mode configuration information, and the target memory address and the target test data are obtained based on the target test mode, that is, the user can configure the target test mode, configure the specific target memory address and the target test data, and realize the test for specific memory address and memory data, so that the test process is more targeted, and meets the demand of targeted test in actual application.

[0100] Further, the embodiments of the present application provide another memory test circuit, which combines Figure 3 As shown in the foregoing embodiments, the memory test circuit provided by the embodiments of the present application further includes a preprocessing module 30, a data verification module 40, and a test result cache module 50.

[0101] The preprocessing module 30 is connected with the memory access module 20, the data verification module 40, and the memory controller, the data verification module 40 is further connected with the test result cache module 50.

[0102] The preprocessing module 30 is connected in series between the memory access module 20 and the memory controller, and is configured to preprocess data exchanged between the memory test circuit and the memory controller, so that the processed data matches the data format of the data receiving party. Specifically, when the memory access module 20 sends target test data to the memory controller through a write request, the preprocessing module 30 is configured to convert the target test data into data recognizable by the memory controller. Correspondingly, when the memory access module 20 obtains memory data fed back by the memory controller through a read request, the preprocessing module 30 is configured to convert the obtained memory data into data recognizable by the data verification module 40. Of course, the memory test circuit and the memory controller will also transmit memory addresses, and the preprocessing module 30 does not process the memory addresses transmitted by both parties.

[0103] As mentioned above, the access request sent by the memory test circuit to the memory controller includes a write request and a read request, wherein the write request includes a first target memory address and target test data, and the read request includes a second target memory address. Based on this, for the write request, the preprocessing module 30 converts the target test data into a plurality of processed data recognizable by the memory controller, and sends each processed data to the memory according to the first target memory address. Specifically, the preprocessing module 30 sends the first target memory address and the plurality of processed data obtained by conversion to the memory controller, and the memory controller stores each preprocessing data in the memory according to the obtained first target memory address. Further, for the read request, the preprocessing module 30 sends the read request carrying the second target memory address to the memory controller, the memory controller obtains the memory data in the memory according to the second target memory address, and feeds back the obtained memory data to the preprocessing module 30, and the preprocessing module 30 converts the obtained memory data into data recognizable by the memory test circuit. As can be known from the subsequent content, the memory data fed back by the memory controller will be used for data verification, therefore, the preprocessing module 30 specifically converts the memory data into data recognizable by the data verification module 40.

[0104] Specifically, it is assumed that the data bit width of the memory test data generated by the memory test circuit is 256 bits, and these data are divided into a plurality of processed data and transmitted in multiple times in the preprocessing module. The specific division process is related to the data bit width of the data port of the memory controller. For example, if the data port bit width is 64 bits, the target test data of 256 bits needs to be divided into 4 parts, and the preprocessing module supports the same internal data exchange for each 64-bit data, that is, the position of each bit of the original data can be determined.

[0105] For example, when the target test data is {4{64'h1}}, the positions of 0 and 3 in the 64-bit data are exchanged, and then the processed data becomes {4{64'h8}}, that is, the data is changed from 'b0001 to 'b1000.

[0106] It can be seen that, for actual test requirements, the preprocessing module converts the test data in the write request into a plurality of processed data, so that the memory can successfully receive and store the obtained processed data. Correspondingly, the preprocessing module obtains the memory data in the memory according to the second target memory address, and realizes the acquisition of the memory data. Not only can the reliability of the memory responding to the read request be verified, but also the obtained memory data can be used for verifying the correctness of the data stored in the memory, thereby providing basic data for memory testing.

[0107] Further, the data verification module 40 is configured to verify the memory data fed back by the memory and the memory address to which the memory data belongs. The specific verification process will be described in detail in the subsequent content, which is not described here.

[0108] In order to facilitate the storage of the verification result, the test result cache module 50 is arranged in the memory test circuit. In actual application, when the memory test circuit initiates a read request to the memory, the data verification module 40 verifies the information fed back by the memory controller, and the obtained verification result can be stored in the test result cache module 50. In particular, the error address, the error data, and the corresponding correct address and correct data identified in the verification process can be directly obtained by the test result cache module 50 when analyzing the performance of the memory subsequently. By storing the verification result through the test result cache module, the unified management of the verification result can be realized, which provides convenience for further analyzing the performance of the memory, and helps to improve the efficiency of memory testing.

[0109] The composition of the data verification module will be described in detail below in combination with FIG. 4. Figure 4 As a possible implementation manner, the data verification module 40 includes a third address generation module 410, a second data generation module 420, and a comparison module 430.

[0110] The third address generation module 410 and the second data generation module 420 are respectively connected with the preprocessing module 30, and the comparison module 430 is respectively connected with the third address generation module 410, the second data generation module 420, the preprocessing module 30, and the test result cache module 50. Figure 4

[0111] ​The third address generating module 410 generates a third target memory address according to the test address pattern in the target test pattern in response to the memory controller feeding back the memory data (in other words, in response to the preprocessing module 30 receiving the memory data). As described above, the address generating modules provided by the embodiments of the present application are implemented based on the same logic, and the third target memory address generated by the third address generating module 410 according to the test address pattern in the target test pattern is necessarily the same as the second target memory address generated by the second address generating module 240 according to the test address pattern in the target test pattern, that is, the third target memory address provided by the third address generating module 410 is the correct memory address.

[0112] Correspondingly, the second data generating module 420 generates reference data according to the test data pattern in the target test pattern in response to the memory controller feeding back the memory data (in other words, in response to the preprocessing module 30 receiving the memory data). As described above, the data generating modules provided by the embodiments of the present application are implemented based on the same logic, and the reference data generated by the second data generating module 420 according to the test data pattern in the target test pattern is necessarily the same as the target test data generated by the first data generating module 230 according to the test data pattern in the target test pattern.

[0113] The comparison module 430 acquires the third target memory address provided by the third address generating module 410, the reference data provided by the second data generating module 420, and the memory data fed back by the preprocessing module 30 and the memory address to which the memory data belongs. The comparison module 430 further performs comparison and verification on the obtained data. If the third target memory address is consistent with the memory address to which the memory data belongs, and the reference data is also consistent with the memory data, it can be concluded that the memory correctly performs the access request. Conversely, if the third target memory address is inconsistent with the memory address to which the memory data belongs, and / or the reference data is inconsistent with the memory data, it can be determined that the memory does not correctly respond to the access request.

[0114] Further, the comparison module 430 sends the verification result to the test result caching module 50 for storage.

[0115] To sum up, the memory test circuit provided in the application, the third address generation module generates a third target memory address according to the test address pattern in the target test pattern, and the second data generation module generates reference data according to the test data pattern in the target test pattern. By setting this way, the third target memory address obtained can be consistent with the memory address of the write request sent by the memory access module, and the reference data obtained can be consistent with the test data carried in the write request sent by the memory access module, in other words, by setting this way, correct memory address and reference data can be obtained, which can be used as the basis for subsequent verification. If the third target memory address is consistent with the memory address of the memory data, it means that the memory address used when the memory stores data is correct, and correspondingly, if the reference data is consistent with the memory data, it can be determined that the memory data is reliable, thereby achieving the purpose of testing the performance of the memory.

[0116] The above provides various optional implementation modes of the memory test circuit, and the basic flow of memory testing based on the memory test circuit provided in the application is further introduced below, referring to Figure 5 As shown in the figure, the test flow can include the following steps.

[0117] S100, configure the memory test circuit.

[0118] Referring to the related content of the configuration module in the foregoing embodiments, before performing the memory test, the configuration module needs to be configured according to the test requirements, such as setting the start address of the to-be-tested memory space, the capacity of the to-be-tested memory space, the required target test module, and the execution order of each target test module.

[0119] As an optional implementation mode, after the above configuration operation is completed, the configuration module is notified that all configurations have been completed, and waits for the configuration processing state returned by the configuration module. When the configuration module completes the cache processing of the foregoing configuration information, feedback notification information indicating that the configuration is successful, so that the subsequent steps can be further executed.

[0120] As can be known from the working process of the memory test circuit in the foregoing embodiments, all the configuration information stored in the configuration module is open to all the logic modules in the memory test circuit, and each logic module obtains the configuration information required by itself according to the running requirements.

[0121] S110, generate a test request.

[0122] For the generation process of the test request, the related content of the foregoing embodiments can be referred to for implementation, which will not be repeated here.

[0123] S120, the memory test circuit responds to the test request and tests the memory.

[0124] After obtaining the test request, the memory test circuit tests the memory in response to the test request. The specific test process can refer to the related content of the foregoing embodiments, which will not be repeated here.

[0125] In an optional embodiment, if a check exception occurs during the test of the memory, new access requests can be stopped first, and the ongoing access requests can be executed until they are completed. After the access requests are processed, an error state of the exception is fed back to the test control module. After receiving the error state, the test control module directly ends all tests and reports the exception.

[0126] As described above, the preset test mode provided in the application is represented by three dimensions of a test behavior mode, a test address mode and a test data mode. The test behavior mode, the test address mode and the test data mode each include a plurality of optional specific modes. Different preset test modes can be obtained by combining different specific modes, and the memory can be tested according to the test process described above. It should be noted that different preset test modes can be used to test different performances of the memory. Before being described in detail, the related knowledge of the memory test is introduced.

[0127] 1. Test pressure in the continuous address mode:

[0128] The scheduling of the access request by the memory controller needs to meet the timing requirements of JEDEC (Joint Electron Device Engineering Council, a leading standard organization in the microelectronics industry), that is, after the memory controller sends a request, the CMD delay (request delay) specified in the protocol needs to be met, and then the next request can be sent. The protocol specifies the sending interval between different requests. The higher the interval, the lower the bandwidth utilization, and the less time the data transmission port is used for data transmission, and the lower the test pressure. Therefore, the smaller the request interval, the higher the proportion of the data transmission state, and the greater the pressure on the data transmission port. The minimum request switching form defined in the JEDEC protocol is the request of the same direction and different BG (Bank Group). In a specific scenario, continuous transmission on the data transmission port can be achieved.

[0129] Therefore, when stress testing is required, it is generally necessary to configure the preset test mode of the memory test circuit provided in the present application as the first-write-after-reading mode + continuous address mode (i.e., taking any address of the memory as the starting address and generating the memory addresses according to the preset step size), and the test data mode can be optional. The reason is that, on the one hand, the first-write-after-reading mode makes the request buffer of the memory controller have only one type of request most of the time, greatly reducing the test stress caused by the switching of the request direction; on the other hand, the continuous address mode makes the memory access addresses change in an incremental form. Taking binary as an example, the address will constantly increase from a certain bit, 'b00, 'b01, 'b10, 'b11, 'b00, and so on. At this time, if these bits are mapped to the BG positions, the requests in the memory controller will be requests of the same direction and different BGs, which belongs to the optimal form in the JEDEC protocol. At this time, the maximum test bandwidth can be obtained, and the test stress on the data transmission port will also be the maximum.

[0130] 2. Serial-to-parallel conversion in the memory controller:

[0131] The data transmission port of the memory runs at a very high clock frequency during operation, but such a high-speed clock is difficult to apply in the design of components within the microprocessor architecture, therefore, the concept of clock ratio is introduced in the design of the memory controller, i.e., the ratio of the running clock inside the memory controller to the working clock of the memory data transmission port. To ensure consistent bandwidth before and after, the data bit width under different clocks needs to be adjusted.

[0132] Taking DDR5 as an example, its data transmission port is 32 bits, and the working frequency is 3200 MHz. When the ratio is 1:4, the memory controller working clock is 800 MHz, and the data bit width of the memory controller to the outside is 256 bits. Although the clock frequencies are different, the total amount of data transmission in the same time is consistent. Therefore, for the data transmission port of the memory, the large bit width data from the memory controller is transmitted through multiple small bit width data transmissions.

[0133] 3. Data storage of the memory:

[0134] In the related art, one memory particle does not have the above-mentioned data bit width, therefore, the memory generally expands the bit width through multiple memory particles. Taking DDR5 32 bits and X8 particles as an example, the 32-bit data bit width provided by the memory to the outside is stored in 4 X8 DDR5 memory particles. For each memory particle, the 32-bit data corresponds to the same address, and each address in the memory particle can store 8-bit data.

[0135] Based on the above basic knowledge, the following for several representative pre-set test mode, brief introduction of its can mainly test the memory performance.

[0136] 1, test the memory fast initialization ability.

[0137] When the target test mode is selected as the write-only mode + any address of the memory as the starting address and generate memory address according to the preset step (i.e. continuous address) mode (test data mode is arbitrarily selected), the memory test circuit provided by the embodiment of the application sends the write request of the same direction (i.e. all write requests), continuous address (continuous BG cutting) and arbitrary target test data to the memory controller. This memory behavior does not require complex scheduling operation for the memory controller, can minimize bandwidth waste and accelerate the initialization process.

[0138] 2, test the scheduling reliability of the memory controller.

[0139] When the target test mode is selected as the read-write interleaving mode + randomly generating memory address (test data mode is arbitrarily selected), the memory test circuit sends the memory behavior of read-write direction interleaving and complex address form to the memory controller. For the memory controller, there are complex access requests of different directions and different memory addresses in the access request buffer. In this case, the scheduling of the memory controller becomes very complex, and the execution of the access request involves all the cases in the protocol, so the reliability test of the scheduling of the memory controller to the access request can be realized.

[0140] 3, test the stability of the memory data transmission port.

[0141] For the stability test of the memory data transmission port, the test pressure must be ensured first: when the target test mode is selected as the write-then-read mode + any address of the memory as the starting address and generate memory address according to the preset step (i.e. continuous address) mode (test data mode is arbitrarily selected), the memory test circuit only sends the memory controller the memory request (write request / read request) of the same direction (all write requests), continuous address (continuous BG cutting) in a period of time. At this time, the bandwidth utilization of the memory is at a high level, i.e. the stability of the memory data transmission port in the data transmission process can be verified based on the continuous transmission state.

[0142] In addition, different target test data generation modes are selected, and whether the data transmission port can overcome the interference of the transmitted data on the transmission process can be verified. For example, the target test data is all 1 or all 0 data, which can make the data transmission port in a similar transmission state for a long time; the values of adjacent bit positions of the target test data are opposite, which can make adjacent bits in the data transmission port in opposite transmission states for a long time; when the shift algorithm is used to generate the target test data, reliable alternate transmission of the data transmission port is required; when the inv algorithm is used to generate the target test data, reliable alternate inversion of the data transmission port is required; when a random number is used as the target test data, the data transmission port can flexibly adjust the transmitted data (that is, flexibly adjust the level information). Of course, other target test data generation modes can also be selected, and enumeration is not repeated here. For the stress test of the memory data transmission port, the data transmission port is required to be in a working state for a long time, and the more rich the flip form of the port level is, the better. The memory test circuit provided in the embodiment of the application can well meet the test requirement.

[0143] 4. Test the storage reliability of the memory.

[0144] For the storage reliability test of the memory, specific test data is generally written into the memory, and whether the read memory data is correct is judged. To minimize the test time and maximize the test pressure, when the memory test circuit provided in the embodiment of the application is used for the storage reliability test of the memory, the target test mode can be selected as: the first write and then read mode + the mode of generating memory addresses (that is, continuous addresses) from any address of the memory as a starting address according to a preset step size (the test data mode is selected arbitrarily). Based on the storage mode of the memory for data, the configuration of data generation is completed, and an example is as follows:

[0145] ① Configure the memory space to be tested, write repeated test data (for example, 32{8’b1}) into the memory space, read the memory data stored in the memory after the test data is written, and perform 8 rounds of tests on the storage results of different bit positions.

[0146] ② Configure the memory space to be tested, write pseudo-random data into the memory space, and test the storage of the data by the memory.

[0147] When the storage reliability of the memory is tested, the form of the written data is extremely relevant to the effectiveness of the test. The memory test circuit provided in the embodiment of the application can provide multiple test data generation modes to meet the test requirements.

[0148] Further, the embodiment of the application further provides a memory controller, which is described with reference to Figure 6As shown, the memory controller provided by the embodiment includes a master module 100 and a first conversion module 200, wherein the master module 100 includes the memory test circuit 101 and the scheduling module 102 provided by any of the preceding embodiments of the present application.

[0149] The memory test circuit 101 and the scheduling module 102 are integrated in the master module 100, the memory test circuit 101 is connected with the scheduling module 102, the output end of the scheduling module 102 serves as the output end of the master module 100, and is connected with the first conversion module 200.

[0150] The memory test circuit 101 is used to initiate an access request to the memory in the memory test process of the microprocessor architecture post-silicon debug. It can be understood that the access request output by the memory test circuit 101 first reaches the scheduling module 102. The scheduling module 102 schedules the access request according to a preset scheduling rule, determines the timing of sending the access request, and finally sends the access request to the first conversion module 200. The preset scheduling rule can include various implementation manners, for example, the scheduling order can be determined according to the time when the access request arrives, and for another example, the scheduling order can also be determined according to the priority of the access request, and the specific implementation of the preset scheduling rule can refer to related technologies, which will not be described one by one here.

[0151] In actual application, the memory controller and the memory can support different data transmission specifications, therefore, it is necessary to convert the access request provided by the scheduling module 102 into an access request recognizable by the memory through the first conversion module 200, and then further send it to the memory, so that the memory can accurately respond to the access request.

[0152] In summary, the memory controller provided by the embodiment of the present application integrates the memory test circuit inside, tests the memory through the memory test circuit, and the test process does not need to involve the operating system, and whether the operating system is started or not does not affect the test process, so the time-consuming required for starting the operating system can be saved, and the memory test efficiency is improved. At the same time, the access request for testing the memory is directly provided by the memory test circuit, and no longer depends on the network-on-chip transmission, which can avoid causing other interference factors, thereby improving the accuracy of the test result.

[0153] In an alternative embodiment, the present application provides another memory controller, as shown in Figure 7 As shown, the memory test circuit provided by the embodiment includes a master module 100 and a first conversion module 200, wherein the master module 100 includes the memory test circuit 101 and the scheduling module 102 provided by any of the preceding embodiments of the present application.

[0154] In actual application, the memory controller can be integrated in the microprocessor architecture to process the access request initiated by other control modules in the microprocessor architecture, usually, the access request is transmitted through a standard bus, because of the difference in supporting data transmission specification, the memory controller performs protocol conversion on the access request sent by other control modules, based on this, the second conversion module 104 is arranged in the master control module 100, the access request sent by other control modules in the microprocessor architecture is cached through the second conversion module 104, and the obtained access request is converted according to the protocol supported by the memory controller.

[0155] The gating module 103 has a first input end, a second input end and an output end, which are connected with the second conversion module 104, the memory test circuit 101 and the scheduling module 102 respectively. Figure 7 As shown in the figure, the first input end is connected with the second conversion module 104, used for receiving the access request output by the second conversion module 104 after conversion; the second input end is connected with the memory test circuit 101, used for receiving the access request output by the memory test circuit 101; and the output end is connected with the scheduling module 102.

[0156] In actual application, the gating module 103 can be configured to connect the first input end and the output end to output the access request of the second conversion module 104 to the next stage, and / or connect the second input end and the output end to output the access request of the memory test circuit 101 to the next stage.

[0157] It can be understood that the present application actually provides three configuration schemes of the gating module 103, in the case of connecting the first input end and the output end, only the access request from other control modules is allowed to enter, which is suitable for the scene of non-memory test, and the passage between the memory test circuit 101 and the scheduling module 102 can be closed; in the case of connecting the second input end and the output end, only the access request from the memory test circuit is allowed to enter, which is suitable for the memory test scene, the memory test process can be avoided from being disturbed by the access request from other control modules, and the memory test can be carried out without starting the operating system, thereby improving the test efficiency; in the case of connecting the first input end and the second input end with the output end at the same time, the access request of other control modules and the memory test circuit 101 is allowed to enter, so that the memory controller can not only normally respond to the running demand of the microprocessor architecture, but also can test the memory to further verify the response ability of the memory in the high-frequency access scene.

[0158] Further, the memory test circuit can be integrated in the master control module, which can shorten the access path, ensure the consistency of access behavior, and make the access request directly reach the memory, thereby improving the test efficiency.

[0159] The present application also provides a microprocessor architecture, as shown in Figure 8As shown, specifically comprises: the memory test circuit 101, the memory controller 300 and the memory 400 provided by any one of the preceding embodiments of the present application, wherein,

[0160] The memory test circuit 101, the memory controller 300 and the memory 400 are connected in sequence;

[0161] The memory test circuit 101 sends an access request for testing the memory 400 to the memory controller 300 in the memory test process of the silicon post-debug of the microprocessor architecture.

[0162] The memory controller 300 accesses the memory 400 according to the access request to test the memory 400.

[0163] Those skilled in the art can understand that the disclosed content of the present disclosure can have various modifications and improvements. For example, the various devices or components described above can be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0164] In addition, although the present disclosure makes various references to certain units in the system according to the embodiments of the present disclosure, however, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0165] Flowcharts are used in the present disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or subsequent steps do not necessarily proceed in sequence. Instead, various steps can be processed in reverse order or simultaneously. Other operations can also be added to these processes.

[0166] Those skilled in the art can understand that all or part of the steps in the above method can be requested by the relevant hardware through a computer program, which can be stored in a computer readable storage medium such as a read-only memory. Alternatively, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.

[0167] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0168] The foregoing is a summary of the disclosure, and is not to be considered as limiting its scope. While several exemplary embodiments of the disclosure have been described, it will be apparent to those of ordinary skill in the art that many modifications are possible without departing from the teachings of the disclosure, which are intended to be limited only by the claims. Accordingly, all such modifications are intended to be included within the scope of the disclosure as defined in the following claims. It is to be understood that the above description is illustrative of the disclosure and is not to be considered limiting in any way. Modifications to the disclosed embodiments, as well as other embodiments, are intended to be within the scope of the claims. The disclosure is defined by the claims and their equivalents.

Claims

1. A memory testing circuit, characterized in that, This memory testing circuit is applied during the post-silicon debugging process of microprocessor architectures. The microprocessor architecture also includes a memory controller and memory. The memory testing circuit includes a configuration module and a memory access module. The configuration module is used to store mode configuration information, which is used to specify any one of a plurality of preset test modes for testing memory performance as the target test mode. In response to a test request, the memory access module determines the target test mode based on the mode configuration information and sends a test memory access request to the memory controller according to the target test mode, so that the memory controller accesses the memory according to the access request.

2. The memory testing circuit according to claim 1, characterized in that, The access request includes a write request and a read request, and any of the preset test modes includes a test behavior mode, a test address mode, and a test data mode. The memory access module includes: The test control module is used to generate an enable signal according to the test behavior pattern in the target test mode; The first address generation module is used to respond to the enable signal and generate a first target memory address according to the test address pattern in the target test mode; The first data generation module is used to respond to the enable signal and generate target test data according to the test data pattern in the target test mode. The second address generation module is used to respond to the enable signal and generate a second target memory address according to the test address pattern in the target test mode. The test control module is further configured to: send a write request to the memory controller to test the memory based on the first target memory address and the target test data, or send a read request to the memory controller to test the memory based on the second target memory address.

3. The memory testing circuit according to claim 1, characterized in that, The access request includes a write request and a read request. The write request includes a first target memory address and target test data. The read request includes a second target memory address. The memory testing circuit also includes: The preprocessing module is used to convert the target test data into multiple processed data that can be recognized by the memory controller, send each of the processed data to the memory according to the first target memory address, and obtain the memory data in the memory according to the second target memory address.

4. The memory testing circuit according to claim 3, characterized in that, The memory testing circuit also includes: The data verification module is used to verify the memory data returned by the memory and the memory address to which the memory data belongs.

5. The memory testing circuit according to claim 4, characterized in that, The memory testing circuit also includes: The test result caching module is used to store the verification results of the data verification module.

6. The memory testing circuit according to claim 1, characterized in that, Any of the preset test modes includes a test behavior mode, a test address mode, and a test data mode, wherein, The test behavior modes include any one of the following: write-only mode, write-then-read mode, and read-write interleaved mode; The test address mode includes any one of the following: randomly generated memory address, custom memory address, or generating a memory address starting from any address of the memory and according to a preset step size; The test data mode includes any one of the following: randomly generated test data, custom test data, and test data generated according to a preset data generation algorithm.

7. The memory testing circuit according to any one of claims 1 to 6, characterized in that, The memory test circuit is located adjacent to the memory controller.

8. A memory controller, characterized in that, include: The main control module, among which, The main control module includes: The memory test circuit as described in any one of claims 1 to 7 is used to initiate an access request to the memory during memory testing in post-silicon debugging. The scheduling module is used to schedule access requests according to preset scheduling rules.

9. The memory controller according to claim 8, characterized in that, The main control module also includes: The second conversion module is used to convert the access requests initiated by other control modules in the microprocessor architecture to which the memory controller belongs into protocols. The gating module has a first input terminal, a second input terminal, and an output terminal; The first input terminal is used to receive the access request output by the second conversion module after conversion; The second input terminal is connected to the memory test circuit to receive access requests from the memory test circuit; The output terminal is connected to the scheduling module; The gating module is configured to connect the first input terminal and the output terminal, and / or connect the second input terminal and the output terminal.

10. A microprocessor architecture, characterized in that, include: The memory controller, the memory, and the memory test circuit as described in any one of claims 1 to 7, wherein, The memory test circuit, the memory controller, and the memory are connected in sequence. During the memory testing process of the microprocessor architecture after silicon debugging, the memory testing circuit sends an access request to the memory controller to test the memory. The memory controller accesses the memory according to the access request.

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