Memory test circuit, memory controller and microprocessor architecture

Abstract

The invention provides a memory test circuit, a memory controller and a microprocessor architecture, which are applied to the technical field of computers, the circuit is used for the memory test in the post-silicon debugging process of the microprocessor architecture, the circuit comprises a configuration module, a process control module and a plurality of test modules, each test module carries at least one memory test algorithm, and the process control module is connected with the configuration module. The configuration module stores module configuration information, and the process control module responds to a test instruction, determines target test modules according to the module configuration information and controls each target test module to send an access request of a test memory according to a memory test algorithm carried by the target test module. According to the method, the time consumed for starting the operating system can be saved, the memory testing efficiency is improved, meanwhile, the access request for testing the memory is directly provided by the memory testing circuit and no longer depends on network-on-chip transmission, other interference factors can be avoided, and therefore the accuracy of a testing result is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a memory test circuit, a memory controller and a microprocessor architecture. BACKGROUND

[0002] In modern computer technology, the health status of memory directly determines the overall performance and stability of the computer system, therefore, ensuring that the memory is fully tested before use ensures the reliability of the memory, which is the key to guarantee the normal operation of the system.

[0003] The related art tests the memory through a dedicated memory test software, such as the memtester software, which contains multiple test algorithms and can provide comprehensive test scenarios, and the test process is simple and does not require complex operations, however, as a software under the Linux system, the memtester must be run after the operating system is loaded, which undoubtedly reduces the test efficiency, at the same time, the memory read / write request generated by the processor based on the memory test software needs to pass through the network on chip before reaching the memory, which process is easy to introduce other interference factors, resulting in low accuracy of the test results. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a memory test circuit, a memory controller and a microprocessor architecture to improve the memory test efficiency and the accuracy of the test results.

[0005] In a first aspect, the present application provides a memory test circuit applied to memory testing in the silicon post-debugging process of a microprocessor architecture, the microprocessor architecture further comprising a memory controller and a memory, the memory test circuit comprising a configuration module, a process control module and a plurality of test modules, wherein,

[0006] Each of the test modules is equipped with at least one memory test algorithm;

[0007] The configuration module is configured to store module configuration information, the module configuration information being used to specify at least one target test module in the plurality of test modules;

[0008] The process control module is configured to determine the at least one target test module according to the module configuration information in response to a test instruction, and control each of the target test modules to send an access request for testing the memory to the memory controller according to the memory test algorithm equipped by itself, so that the memory controller accesses the memory according to the access request.

[0009] Based on the above, the memory test circuit provided by the application is applied to memory test in a post-silicon debug process of a microprocessor architecture, the microprocessor architecture further comprises a memory controller and a memory, the memory test circuit comprises a configuration module, a process control module and a plurality of test modules, each test module carries at least one memory test algorithm, the configuration module stores module configuration information, at least one target test module is specified in the plurality of test modules through the module configuration information, the process control module determines the target test module according to the module configuration information and controls each target test module to send an access request for testing the memory according to the memory test algorithm carried by the target test module, so as to realize the test of the memory. Based on this, the circuit tests the memory according to the configured target test module, and the test process does not need to involve the operating system, and whether the operating system is started or not does not affect the test process, so that the time required for starting the operating system can be saved, and the memory test efficiency is improved. At the same time, the access request for testing the memory is directly provided by the memory test circuit, and no longer depends on the on-chip network transmission, so that other interference factors can be avoided, thereby improving the accuracy of the test result.

[0010] Further, the application provides a plurality of test modules, and a user can select at least one target test module from the plurality of test modules, so as to meet different test requirements and help to realize comprehensive test of the memory.

[0011] In an optional embodiment, the target test module comprises a plurality of target test modules, the configuration module further stores module sequence information, and the memory test circuit further comprises a test sequencing module, wherein,

[0012] The test sequencing module is configured to sequence each target test module according to the module sequence information.

[0013] The process control module is specifically configured to control each target test module to send an access request for testing the memory to the memory controller according to the memory test algorithm carried by the target test module in sequence according to the sequencing result of the test sequencing module.

[0014] In the memory test circuit provided by the application, the configuration module further stores module sequence information, and a test sequencing module is further added, each target test module is sequenced according to the module sequence information by the test sequencing module, and the process control module controls each target test module to test the memory according to the sequencing result of the test sequencing module. Therefore, the execution sequence of each test mode can be configured according to actual test requirements, so that the memory can be more comprehensively tested.

[0015] In an optional embodiment, the memory test circuit further comprises:

[0016] The first gating module has at least one test input end and one test output end.

[0017] Each of the test inputs is connected with one of the test modules, and the test outputs are in communication connection with the memory controller;

[0018] The first gating module is configured to sequentially connect the test inputs connected with the target test modules with the test outputs according to the sorting result.

[0019] In the memory test circuit provided in the application, the first gating module is newly added, and the respective connection between the test modules and the memory can be realized through the first gating module. In this way, the simultaneous access of two or more test modules to the memory can be avoided, the memory access error can be avoided, and the accuracy of the test result can be ensured.

[0020] In an optional implementation, any of the test modules comprises:

[0021] a behavior control module configured to generate an enable signal according to a memory test algorithm corresponding to the test module;

[0022] a write request generation module configured to generate a write request for the memory in response to the enable signal;

[0023] a read request generation module configured to generate a read request for the memory in response to the enable signal.

[0024] In the memory test circuit provided in the application, the memory access module comprises the behavior control module, the write request generation module and the read request generation module. The enable state of the write request generation module and the read request generation module can be controlled through the behavior control module, the generation of the write request and the read request can be independently controlled, the control process is flexible, and the test requirements of different test algorithms in the actual test process can be met.

[0025] In an optional implementation, the test module further comprises:

[0026] a data verification module configured to verify memory data fed back by the memory in response to the read request and a memory address to which the memory data belongs.

[0027] In the memory test circuit provided in the application, the data verification module is additionally arranged in the test module. The memory data fed back by the memory and the memory address to which the memory data belongs can be verified through the data verification module, the position of the memory data stored in the memory and whether the reliability of the memory data meets the application requirements are determined, and at the same time, the verification result can be directly obtained through the data verification module, the performance of the memory does not have to be determined by the tester according to the response of the write request and the read request, the manpower of the tester is saved, and the test efficiency is improved.

[0028] In an alternative implementation, the test circuit further comprises:

[0029] a test result cache module configured to store the check results fed back by the test modules.

[0030] The memory test circuit provided by the application adds a test result cache module in the test module, stores the check results through the test result cache module, and thus can realize unified management of the check results, provide convenience for further analysis of the memory performance, and help improve the memory test efficiency.

[0031] In an alternative implementation, the memory test circuit is arranged adjacent to the memory controller.

[0032] In the memory test circuit provided by the application, the memory test circuit is arranged adjacent to the memory controller, the memory access path is shorter, the memory access efficiency is effectively improved, and meanwhile, the shorter memory access path can reduce the probability of interference factors introduced by the memory access path in the memory access process, and thus help further improve the reliability of the test results.

[0033] In a second aspect, the application provides a memory controller, comprising a master control module and the memory test circuit provided by any of the embodiments of the first aspect of the application, wherein,

[0034] the memory test circuit is connected to the master control module;

[0035] the memory test circuit initiates, in a post-silicon debug memory test process, an access request for testing the memory to the memory through the master control module.

[0036] The memory controller provided by the application integrates the memory test circuit, tests the memory through the memory test circuit, and does not need to involve the operating system in the test process, so that the test process is not affected by whether the operating system is started or not, and thus the time consumption required for starting the operating system can be saved, the memory test efficiency is improved, and meanwhile, the access request for testing the memory is directly provided by the memory test circuit, and does not depend on the on-chip network transmission, so that other interference factors can be avoided, and thus the accuracy of the test results is improved.

[0037] In an alternative implementation, the memory controller provided by the second aspect of the application further comprises:

[0038] a second gating module having a first gating input end, a second gating input end and a target output end;

[0039] the first gating input end is configured to receive an access request initiated by other control modules in a microprocessor architecture to which the memory controller belongs to the memory;

[0040] The second gating input end is connected with the memory test circuit to receive an access request of the memory test circuit.

[0041] The target output end is connected with the master module.

[0042] The second gating module is configured to connect the first gating input end and the target output end, or connect the second gating input end and the target output end.

[0043] The memory controller provided by the present application adds a second gating module, and the isolation of the memory test circuit can be realized through the second gating module. When the memory controller is running, the memory test circuit will not affect the running process of the memory controller. When the memory is tested, other control modules will not affect the test process, and the reliability and accuracy of the obtained test results are ensured.

[0044] In a third aspect, the present application provides a microprocessor architecture, comprising: a memory controller, a memory, and a memory test circuit provided by any one of the first aspect of the present application, wherein,

[0045] The memory test circuit, the memory controller and the memory are connected in sequence.

[0046] The memory test circuit sends an access request for testing the memory to the memory controller in a memory test process of post-silicon debugging of the microprocessor architecture.

[0047] The memory controller accesses the memory according to the access request. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0049] Figure 1 A structural block diagram of a memory test circuit provided by the embodiments of the present application is provided.

[0050] Figure 2 A structural block diagram of a test module provided by the embodiments of the present application is provided.

[0051] Figure 3 A structural block diagram of another memory test circuit provided by the embodiments of the present application is provided.

[0052] Figure 4 A structural block diagram of another memory test circuit provided by the embodiments of the present application is provided.

[0053] Figure 5 Another structure block diagram of a memory test circuit provided by an embodiment of the present application is provided;

[0054] Figure 6 A flow chart of a memory test process performed by the memory test circuit provided by an embodiment of the present application is provided;

[0055] Figure 7 A structure block diagram of a memory controller provided by an embodiment of the present application is provided;

[0056] Figure 8 Another structure block diagram of a memory controller provided by an embodiment of the present application is provided;

[0057] Figure 9 A schematic diagram of a microprocessor architecture provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative labor fall within the scope of the present application.

[0059] Modern microprocessor architectures usually include multiple components, such as processor cores, video processing units, memory controllers, peripheral controllers, etc. Some of the components will generate intermediate data during work, but they do not have enough space to store these data. Most of the data caches in the microprocessor architecture are implemented through memory. Therefore, memory is one of the core components of the microprocessor architecture, and its health status directly determines the overall performance and stability of the system. Memory failure can cause cache data loss, which not only leads to system performance degradation, but also can cause various errors, and even hardware damage. Therefore, ensuring that the memory is fully tested before use and ensuring its reliability is the key to ensuring the normal operation of the system.

[0060] The related art tests the memory through a dedicated memory test software, such as a memtester software, which contains various test algorithms, can provide a comprehensive test scene, and has a simple test process without complex operations. Only the memory test software needs to be started under the operating system, and then the test result reported by the memory test software can be waited for. However, as a software under the Linux system, the memtester must be run after the operating system is loaded, which leads to that the operating system must be loaded before the memory test is carried out, and the memory test time is occupied, which undoubtedly reduces the test efficiency. Meanwhile, the memory access request generated by the processor based on the memory test software has a source of the processor core, and the memory access request initiated by the processor core needs to pass through the network on chip before reaching the memory, which easily introduces other interference factors, leading to low accuracy of the test result.

[0061] To solve the above problems, the present application provides a memory test circuit, which initiates an access request to the memory through the memory test circuit. The test process does not need the participation of the operating system, and whether the operating system is started or not does not affect the test process. Therefore, the time required for starting the operating system can be saved, and the memory test efficiency is improved. Meanwhile, the access request for testing the memory is directly provided by the memory test circuit, and no longer depends on the network on chip transmission, which can avoid causing other interference factors, thereby improving the accuracy of the test result.

[0062] Based on the above content, referring to Figure 1 , the memory test circuit provided by the embodiments of the present application comprises a configuration module 10, a process control module 20 and a plurality of test modules, Figure 1 , wherein the test module 1, the test module 2 and the test module N are shown, and N≥2.

[0063] First of all, it should be pointed out that the memory test circuit provided by the embodiments of the present application is applied to the memory test in the silicon post-debugging process of the microprocessor architecture. The memory test circuit is integrated in the microprocessor architecture and exists as a hardware component of the microprocessor architecture. As shown in Figure 1 , the microprocessor architecture further comprises a memory controller and a memory. Of course, the microprocessor architecture can further comprise other components, such as the aforementioned processor core and peripheral controller, and the specific components can be referred to the related art, which will not be described here. As a possible implementation, the memory test circuit provided by each embodiment of the present application is adjacent to the memory controller. In this way, the memory access path of the memory test circuit is shorter, which effectively improves the memory access efficiency. Meanwhile, shortening the memory access path can also reduce the probability of introducing interference factors in the memory access process, which helps to further improve the reliability of the test result.

[0064] In combination with Figure 1As shown, the configuration module 10 is connected with the process control module 20, and the process control module 20 is connected with each test module respectively, and meanwhile, the configuration module 10 is also connected with each test module respectively, to more clearly show the constitution of the memory test circuit and the connection relationship between the modules provided by the embodiment of the present application, Figure 1 The connection relationship between each test module and the configuration module 10 and the process control module 20 is indicated by a bidirectional arrow. Further, each test module is also connected with a memory controller, and the connection relationship between the two is also indicated by a bidirectional arrow. The memory controller is connected with the memory, and can write data into the memory or read the data stored in the memory.

[0065] The memory test circuit provided by the embodiment of the present application includes multiple test modules, each of which is equipped with at least one memory test algorithm. Each memory test algorithm can initiate an access request to the memory according to a preset test logic, so as to test the actual performance of the memory according to the response of the memory to the access request. Of course, the test processes of different memory test algorithms are different, and the test purposes are also different. The purpose of setting multiple test modules is to provide more memory test algorithms, so as to comprehensively test the memory, and of course, it is also helpful to meet different test requirements. The specific process of testing the memory by each memory test algorithm will be described in detail in the subsequent content, which is not described here.

[0066] The configuration module 10 is used to store module configuration information, by which at least one target test module can be specified in the aforementioned multiple test modules. It can be understood that in actual application, different users may have different test requirements for the memory in different scenarios. By setting the configuration module 10, the user can select one or more of the multiple test modules as the target test module according to his own test requirements, and can also exclude unnecessary test items to avoid repeated testing or irrelevant testing, which can not only meet different test requirements, but also significantly improve the test efficiency.

[0067] In an optional embodiment, a register group can be set in the configuration module 10, and the register group includes multiple registers. Each test module corresponds to a register, that is, the register is used as the enable flag of each test module. Specifically, when the register is configured as a first value, such as 1, it indicates that the test module corresponding to the register is enabled, that is, it is configured as the target test module. On the contrary, when the register is configured as a second value, such as 0, it indicates that the test module corresponding to the register is disabled, that is, it is not configured as the target test module. Of course, the module configuration information can also be stored and recorded by other ways, which will not be listed one by one here, and as long as it does not exceed the core idea of the present application, it also belongs to the protection range of the present application.

[0068] It can be understood that in the process of testing the memory, some scenarios only need to test part of the memory space in the memory. If not distinguished, each test is implemented in the way of traversing all the memory space, which will inevitably reduce the test efficiency. Based on this, as an optional implementation, the configuration module 10 can also be used to store space configuration information, which specifies the to-be-tested memory space in the memory through the space configuration information. Specifically, the space configuration information can include a start address and a capacity of the to-be-tested memory space, and the combination of the two can uniquely determine the specific location of the to-be-tested memory space in the memory, wherein the start address can be any address in the memory specified by the user, and if the user does not specify, an address in the memory can be randomly selected as the start address. Through the space configuration information, targeted testing of part of the memory space in the memory can be realized, meeting the demand of testing part of the memory space in the memory in actual application. At the same time, by specifying the to-be-tested memory space, the task amount of the test process can also be effectively reduced, further improving the test efficiency.

[0069] Further, in an optional implementation, the partial memory test algorithm requires that the to-be-tested memory space be divided into two parts. Assuming that the start address is 0x0 and the capacity of the to-be-tested memory space is 2M, the to-be-tested memory space needs to be divided into space A: 0x0~0x0+1M and space B: 0x400~0x400+1M. The division process of the to-be-tested memory space can also be completed by the configuration module. In this way, the user only needs to configure two parameters, the start address and the capacity of the to-be-tested memory space, in actual application, and the division process is automatically completed by the memory test circuit, which can reduce the workload of the user.

[0070] Of course, the configuration module 10 can also be used to store other configuration information, which will be described in detail in combination with subsequent embodiments, and will not be described here.

[0071] The process control module 20 is mainly used to control the progress of the test process. Specifically, the process control module 20 responds to the test instruction, queries the module configuration information stored in the configuration module 10, and determines the corresponding target test module in each test module according to the module configuration information. It can be one or more, which is determined by the user's choice. Further, the process control module 20 controls the target test module to send an access request for testing the memory to the memory controller according to the memory test algorithm carried by the target test module, and the memory controller accesses the memory according to the access request, thereby completing the test of the memory according to the response of the memory to the access request. As an optional implementation, the process control module 20 can activate each target test module by sending an enable signal to each target test module. Of course, the control of each target test module to execute the memory test algorithm can also be realized by other ways, which will not be described here, and it is also within the scope of protection of the present application without going beyond the core idea of the present application.

[0072] As described above, in the related art, when testing the memory by the memory testing software, the execution of the memory testing software depends on the processor and the operating system loaded thereon. In order to eliminate the dependence of the testing process on the processor, the aforementioned test instruction for starting the testing process should also be avoided to be issued by the processor. Based on this, as a possible implementation, the test instruction can be generated by the firmware of the microprocessor architecture, and the test instruction is generated in the process of starting the microprocessor architecture or loading the corresponding firmware in other application scenarios, and then the testing of the memory is completed. In this way, the influence of the testing process on the processor core and the operating system can be avoided, thereby improving the testing efficiency. Of course, the test instruction can also be triggered by the user in a conventional manner, which will not be described here.

[0073] In summary, the circuit according to the target test module configured by the present application tests the memory, and the testing process does not need the participation of the operating system. Whether the operating system is started or not does not affect the testing process, so the time-consuming required for starting the operating system can be saved, and the memory testing efficiency is improved. At the same time, the access request for testing the memory is directly provided by the memory testing circuit, and no longer depends on the on-chip network transmission, which can avoid causing other interference factors, thereby improving the accuracy of the test results.

[0074] Further, the present application provides a plurality of test modules, and the user can select at least one of the plurality of test modules as a target test module, thereby meeting different testing requirements and helping to realize the comprehensive testing of the memory.

[0075] In the memory testing circuit provided by the embodiments of the present application, the physical implementations of the test modules are basically similar, and the difference is only that the specific memory testing algorithms carried are different. The optional implementation of the test module will be introduced below in conjunction with the drawings. Figure 2

[0076] The test module provided by the embodiments of the present application includes a behavior control module, a write request generation module, and a read request generation module. As a possible implementation, the test module can also include a data verification module.

[0077] ​Specifically, the behavior control module is configured to generate an enable signal according to the memory test algorithm corresponding to the test module, and the behavior control module is connected to the process control module as an input port of the test module. After the process control module determines the target test module according to the module configuration information of the configuration module, the process control module sends a control signal to the target test module. The behavior control module in the test module receiving the corresponding control signal further generates an enable signal according to the memory test algorithm carried by the behavior control module. It can be understood that for any memory test algorithm, the process of testing the memory usually involves multiple memory accesses. Therefore, the behavior control module needs to generate multiple enable signals according to the test rules of the memory test algorithm during the process, each enable signal corresponding to one write access or read access, and the set of all read accesses and write accesses, i.e. the complete test process of the memory test algorithm.

[0078] The write request generation module is connected to the behavior control module and receives the enable signal of the behavior control module. Meanwhile, the write request generation module is also connected to the memory controller through the communication bus. In response to the obtained enable signal, the write request generation module generates a write request for the memory and sends the write request to the memory controller through the communication bus.

[0079] Similar to the connection relationship of the write request generation module, the read request generation module is connected to the behavior control module and is connected to the memory controller through the communication bus. In response to the enable signal sent by the behavior control module, the read request generation module generates a read request for the memory and sends the read request to the memory controller through the communication bus.

[0080] Based on the above, it can be understood that for any memory test algorithm, the write request and read request initiated by the memory test algorithm can be many. The memory controller accesses the memory according to the obtained write request and read request. If the memory can correctly respond to the write request and read request, it can be determined that the memory performance is reliable, otherwise it can be determined that the memory may have a fault.

[0081] Further, in order to more efficiently determine the response of the memory to the aforementioned read request and write request, the test module further comprises a data verification module. The data verification module verifies the memory data fed back by the memory in response to the read request and the memory address to which the memory data belongs.

[0082] Based on the hardware architecture of the test module described above, the memory test algorithm carried by the test module is briefly described below. For the specific implementation process of each memory test algorithm, please refer to the related technical implementation, which will not be described here.

[0083] 1. Stuck address: first generate continuous write request, address from the start address, with 0x8 as address step. Data bit width is 64bit, data form is corresponding address, corresponding address negation alternation, complete data write of the whole memory space to be tested, that is, if the current write value is corresponding address value, then the next address write data is the negation result of corresponding address value; generate continuous read request, address from the start address, with 0x8 as step. When the test module receives the read data, it will perform verification.

[0084] 2. Random value: first generate a 64bit random number, and perform write data operation on space A and space B obtained by dividing the memory space to be tested according to the content described in the foregoing embodiment, specifically, first generate continuous write request, and the write data process is staggered between space A and space B, the data written in the corresponding addresses of space A and space B are consistent, complete data write of the whole memory space to be tested; further, generate continuous read request, the read data process is also staggered between space A and space B; when the test module receives the read data, it will compare the consistency of the read data returned by space A and space B.

[0085] 3. Compare XOR\SUB\MUL\DIV\AND\OR: generate a random data, alternately read the data in the corresponding addresses of the foregoing space A and space B, perform XOR\SUB\MUL\DIV\AND\OR operation on the read data and the generated random number, write the new data obtained by operation back to the corresponding addresses of space A and space B, complete data write of the whole memory space to be tested. Generate continuous read request, address is space A and space B alternately; when the test module receives the read data, it will compare the consistency of the read data returned by space A and space B.

[0086] 4. Sequential increment: generate a 64bit random number and a 64bit count value (initial value is 0), add the random number and the count value, and write them to the corresponding addresses of space A and space B respectively. The count value will be incremented with the address step, and the process will be repeated until the data write of all the memory space to be tested is completed. After data write is completed, further read the data in the corresponding addresses of space A and space B, perform data comparison, and then repeat the process until the data comparison of all the memory space to be tested is completed.

[0087] 5、Solid bits: The algorithm alternately writes data into the aforementioned space A and space B, and the data in each space alternates between all 0s and all Is. After the data is written, the algorithm reads the data in the corresponding addresses of space A and space B, compares the data, and then repeats the process until the data comparison of all the memory spaces to be tested is completed. The data writing sequence is switched, and the data in each space alternates between all Is and all 0s, and then the test is performed again.

[0088] 6、Block sequential: The initial data is 0x0. First, continuous write requests are generated, and the addresses alternate between space A and space B. The data in a single space alternates between all 0s, and the corresponding addresses in the two spaces are written with the same data, completing the data writing of the entire memory space to be tested. Continuous read requests are generated, and the addresses alternate between space A and space B. When the test module receives the read data, it compares the read data returned by space A and space B. After the above behavior is executed, the data form in the memory space to be tested is changed, and the data is increased by {8{8'b1}} every round, a total of 256 rounds are executed.

[0089] 7、Checker board: First, continuous write requests are generated, and the addresses alternate between space A and space B. The data in a single space alternates between all 5s and all a, and the corresponding addresses in the two spaces are written with the same data, completing the data writing of the entire memory space to be tested. Continuous read requests are generated, and the addresses alternate between space A and space B. When the module receives the read data, it compares the read data returned by space A and space B. After the above behavior is executed, the data form in the space is changed, i.e., all a and all 5 alternately, and then executed again.

[0090] 8、Bit spread: First, generate the initial data 0x3, then generate continuous write requests, and the addresses alternate between space A and space B. The data in a single space is 0x3, and the corresponding addresses in the two spaces are written with the same data, completing the data writing of the entire memory space to be tested. Further, continuous read requests are generated, and the addresses alternate between space A and space B. When the test module receives the read data, it compares the read data returned by space A and space B. After the above behavior is executed, the data form in the space is changed, and the data is shifted left by 1 bit every round, a total of 64 rounds are executed.

[0091] 9. Bit flip: define an initial data 0x1, first generate continuous write request, address is space A, B alternately, the data form in single space is initial data, initial data negation alternately, write the same data in corresponding address in two spaces, complete data write in whole memory space to be tested; further generate continuous read request, address is space A, B alternately; when the test module receives read data, compare read data returned by space A, B. After the above behavior is executed, change the data form in space, initial data is left shifted by 1 bit per round, and a total of 64 rounds are executed.

[0092] 10. Walking ones: define an initial data 0x1, first generate continuous write request, address is space A, B alternately, the data form in single space is initial data, initial data negation alternately, write the same data in corresponding address in two spaces, complete data write in whole memory space to be tested; generate continuous read request, address is space A, B alternately; when the test module receives read data, compare read data returned by space A, B. After the above behavior is executed, change the data form in space, initial data is left shifted by 1 bit per round, and a total of 64 rounds are executed.

[0093] 11. Walking zeros: define an initial data 0Xffffffff_fffffffe, first generate continuous write request, address is space A, B alternately, the data form in single space is initial data, initial data negation alternately, write the same data in corresponding address in two spaces, complete data write in whole memory space to be tested; generate continuous read request, address is space A, B alternately; when the test module receives read data, compare read data returned by space A, B. After the above behavior is executed, change the data form in space, initial data is left shifted by 1 bit per round, and a total of 64 rounds are executed.

[0094] 12. 8-bit writes: first generate continuous write request, address behavior is region A, B alternately, but address step is different, generate a random number, generate a 64-bit write request to region A address, and generate 8 8-bit write requests to region B, the address step of space A is 0x8 and the address step of space B is 0x1. The data of corresponding addresses in space A and B is consistent, that is, the same 64-bit data can be completed in one write operation in space A, and 8 times in space B to complete, complete data write in whole memory space to be tested; generate continuous read request, address is space A, B alternately; when the test module receives read data, compare read data returned by space A, B. Then exchange the write form of space A, B and perform a round of test again.

[0095] 13、16-bit writes: first generate continuous write requests, the address behavior alternates between space A and space B, but the address steps are different, generate a random number, generate a 64-bit write request for the address of space A, and correspondingly generate four 16-bit write requests for the address of region B, the address step of space A is 0x8 and the address step of space B is 0x2. The data corresponding to the addresses of space A and space B are consistent, that is, the same 64-bit data can be completed in one write operation in space A, and four times in space B to complete the data write of the entire memory space to be tested; generate continuous read requests, the address alternates between space A and space B; when the module receives the read data, it will compare the read data returned by space A and space B. Then exchange the write form of space A and space B, and perform a round of testing again.

[0096] Of course, in actual application, other memory test algorithms can also be carried in the test module, which will not be described one by one here. It should be noted that if the execution process of any memory test algorithm carried by the test module depends on pre-configuration data, the required configuration data can be stored in the configuration module, and the test module can obtain the required configuration data by accessing the configuration module.

[0097] In the memory test circuit provided in the foregoing embodiment, multiple test modules are provided, and each test module carries at least one memory test algorithm. The user can select one or more test modules as target test modules according to the test requirements of the user, compared with the test process of the related art which can only traverse all test algorithms, the memory test circuit provided in the present application can make the test process more flexible, realize the targeted test of the memory, and effectively improve the test efficiency.

[0098] It can be understood that in actual application, the user can configure multiple target test modules and hope to specify the execution order of each target test module by himself. To meet this demand, another memory test circuit is provided in the embodiment of the present application, as shown in Figure 3 The memory test circuit provided in the embodiment of the present application further comprises a test sequencing module 30 on the basis of the foregoing embodiment.

[0099] In the memory test circuit provided in the embodiment of the present application, the configuration module 10 further stores module sequence information, the module sequence information is used to indicate the order of executing each target test module, the test sequencing module 30 is connected with the configuration module 10 and the process control module 20 respectively, the test sequencing module 30 accesses the configuration module 10 and obtains the module sequence information stored therein, and then sequences each target test module according to the module sequence information.

[0100] Referring to the storage mode of the aforementioned module configuration information, a register group for storing module sequence information can also be provided in the configuration module, the register group including a plurality of registers, each register corresponding to a test module, and when a user selects a target test module in the configuration module, the user configures the execution sequence in the register corresponding to the target test module for storing module sequence information, such as configuring a specific execution serial number, etc. Of course, the execution sequence of the test module can also be represented by other methods, which will not be described in detail here. It can be understood that the configuration process described here is completed before the specific memory test is performed.

[0101] Based on the above configuration, the test sequencing module 30 accesses the configuration module 10, first determines the target test module according to the module configuration information, then accesses the register corresponding to each target test module for storing module sequence information, obtains the execution sequence corresponding to each target test module, and then sorts each target test module according to the execution sequence from the first to the last to obtain the corresponding sorting result.

[0102] The process of the test sequencing module 30 sorting each target test module can be implemented in various ways. As a possible implementation, a module identifier uniquely representing each test module can be created, based on which the test sequencing module 30 can sort each target test module according to the bubble sort algorithm. According to the foregoing, the test sequencing module 30 obtains the serial number corresponding to each target test module, then performs bubble sort according to the serial number, determines the smallest serial number, and stores the module identifier of the target test module corresponding to the smallest serial number in a predetermined buffer area. Then, the remaining target test modules are sorted again, the smallest serial number in the remaining target test modules is determined, and the module identifier of the target test module corresponding to the smallest serial number is stored in the aforementioned buffer area again. This process is repeated until all module identifiers of the target test modules are stored in the buffer area in the order from small to large according to the serial number, and the sorting result is obtained. By assigning a unique module identifier to each test module, the test sequencing module sequentially stores the module identifiers of each target test module according to the module sequence information, which can achieve the sorting of each target test module, and the operation is simple. Moreover, since the module identifier uniquely corresponds to the test module, the accuracy of the sorting result can be ensured.

[0103] Of course, the test sequencing module 30 can also sort each target test module according to the module sequence information by other methods, which will not be described in detail here. In the case of not exceeding the core idea of the present application, it also belongs to the scope of protection of the present application.

[0104] As for the triggering of the test sequencing module 30, there can be multiple implementation manners, in an optional implementation, the process control module 20 can be configured to output an enabling signal to the test sequencing module 30 in response to the test instruction, and the test sequencing module 30 can be configured to perform the aforementioned sequencing work on the target test modules in response to the obtained enabling signal. In another optional implementation, the test sequencing module 30 can also be configured to directly obtain the test instruction and perform the sequencing work on the target test modules in response to the test instruction.

[0105] Further, the process control module 20 can be configured to sequentially control each target test module to send the access request for testing the memory to the memory controller according to the sequencing result provided by the test sequencing module 30. As for the specific process of the process control module 20 controlling any target test module to test the memory, the related content of the foregoing embodiments can be referred to, and will not be repeated here.

[0106] In summary, the memory testing circuit provided by the embodiment allows the user to specify the target test modules, and further allows the user to specify the execution order of each test module according to the actual testing requirement. The test sequencing module can be configured to sequence the target test modules according to the module order information, and the process control module can be configured to sequentially control each target test module to test the memory according to the sequencing result of the test sequencing module. In this way, the execution order of each test module can be configured according to the actual testing requirement, so that the memory can be tested more comprehensively. Compared with the related art in which each test algorithm can only be executed in a fixed order, the testing process is more flexible.

[0107] It can be understood that although the memory testing circuit includes multiple test modules, only one test module can send the access request to the memory controller at the same time. The process control module can be configured to sequentially control each target test module to execute the memory testing algorithm carried by the target test module according to the sequencing result, so as to effectively avoid the situation that two or more test modules simultaneously send the access request to the memory controller. Based on this, the embodiment of the present application provides another memory controller which ensures the reliable execution of the foregoing process in hardware. Referring to Figure 4 The memory testing circuit provided by the embodiment of the present application further includes a first gating module 40.

[0108] In combination with Figure 4As shown, the first gating module 40 includes at least one test input end and one test output end, each test input end is connected with a test module, and the test output end is in communication connection with the memory controller. Based on the foregoing connection relationship, the first gating module 40 sequentially connects the test input end connected with each target test module and the test output end according to the sorting result of the test sorting module 30, and it can be understood that in the case that the test input end connected with any target test module and the test output end are connected, the access request of the target test module can be output to the memory controller through the first gating module 40.

[0109] In an optional embodiment, the first gating module 40 can be implemented by a MUX (Multiplexer), and the specific control process of gating can be implemented by the process control module 20, that is, the process control module 20 is connected with the gating control end of the first gating module 40, and the process control module 20 sequentially sends a gating signal to the first gating module 40 according to the sorting result provided by the test sorting module 30, so as to connect different test input ends and test output ends, and realize that only one target test module outputs an access request at any moment. As for the specific gating control implementation of the MUX, it can be implemented by referring to related technologies, which will not be described in detail here.

[0110] In another optional embodiment, the first gating module 40 can also obtain the sorting result of the test sorting module 30, and the process control module 20 sequentially sends an enable signal to the first gating module 40 according to the obtained sorting result, and the first gating module 40 obtains each enable signal, that is, switches the connection relationship between the test input end and the test output end according to the sorting result, so as to sequentially connect each target test module and the memory controller according to the sorting result, and complete the test of the memory.

[0111] In summary, in the memory test circuit provided in the embodiment of the present application, the first gating module is newly added, and the respective connection between each test module and the memory can be realized through the first gating module. In this way, it can be avoided that two or more test modules simultaneously access the memory, causing memory access errors, and the accuracy of the test result is ensured.

[0112] As described above, the data verification module is also integrated in any test module, and the memory data fed back in response to the read request of the memory and the memory address to which the memory data belongs are verified. Based on this, in order to facilitate storage of the verification result, a test result cache module can also be arranged in the memory test circuit, which is combined with the data verification module to store the verification result of each test module in the test result cache module. Figure 5As shown, the test result cache module 50 is connected with each test module (refer to the foregoing content, and the connection relationship is represented by a bidirectional arrow), and in actual application, when any test module initiates an access request to the memory as a target test module, the obtained verification result can be stored in the test result cache module 50, in particular, the error address, the error data and the corresponding correct address and correct data recognized in the verification process, and when the memory performance is analyzed subsequently, the verification result can be directly obtained through the test result cache module 50, the verification result is stored through the test result cache module, unified management of the verification result can be realized, which provides convenience for further analysis of the memory performance, and helps to improve the memory test efficiency.

[0113] The foregoing content provides various optional implementation manners of the memory test circuit, and the basic flow of memory test based on the memory test circuit provided in the present application is further introduced below, referring to Figure 6 As shown, the test flow can include the following steps.

[0114] S100, configuring the memory test circuit.

[0115] Referring to the related content about the configuration module in the foregoing embodiments, before the memory test is performed, the configuration module needs to be configured according to the test requirement, for example, the start address of the to-be-tested memory space, the capacity of the to-be-tested memory space, the required target test module and the execution order of each target test module.

[0116] As an optional implementation manner, after the foregoing configuration operation is completed, the configuration module is notified that all configurations have been completed, and the configuration processing state returned by the configuration module is waited for, when the configuration module completes the cache processing of the foregoing configuration information, the notification information indicating that the configuration is successful is fed back, and the subsequent step can be further executed.

[0117] S110, generating a test instruction.

[0118] The generation process of the test instruction can be implemented by referring to the related content of the foregoing embodiments, which is not repeated here.

[0119] S120, the memory test circuit tests the memory in response to the test instruction.

[0120] After the test instruction is obtained, the memory test circuit tests the memory in response to the test instruction, and the specific test process can be referred to the related content of the foregoing embodiments, which is not repeated here.

[0121] In an alternative embodiment, if any test module has a check exception during the test of the memory, the output of new access requests can be stopped first, and the ongoing access requests can be executed until they are completed, and then the abnormal error state is fed back to the process control module. After the process control module receives the error state, all tests are directly ended, and the exception is reported. Correspondingly, if the test process is successful, after the test of a target test module is completed, the test process of other target test modules is continued until all target test modules are traversed, and the test of the memory is completed.

[0122] Further, the embodiment of the application further provides a memory controller, as shown in Figure 7 The memory controller provided by the embodiment comprises a master module 101 and the memory test circuit 102 provided by any of the foregoing embodiments.

[0123] The memory test circuit 102 is connected with the master module 101. During the memory test process in the post-silicon debugging stage, the memory test circuit 102 sends an access request for testing the memory to the master module 101. The master module 101 receives and caches the access request, schedules the access request, determines the timing of sending the access request to the memory, and finally sends the access request to the memory to complete the test of the memory.

[0124] As described above, the memory test circuit provided by the embodiment of the application is used for the post-silicon test of the microprocessor architecture. The process of testing the memory by the memory test circuit should not affect the normal operation of the microprocessor architecture. Correspondingly, the memory test circuit should not be affected by other control modules in the microprocessor architecture during the test of the memory. Therefore, the embodiment of the application provides another memory controller.

[0125] As shown in Figure 8 On the basis of the foregoing embodiment, the memory controller provided by the embodiment further comprises a second gating module 104.

[0126] The second gating module 104 comprises a first gating input end, a second gating input end and a target output end. As shown in Figure 8 The first gating input end is used for receiving an access request initiated by other control modules 103 (such as a processor, a peripheral controller and the like) in the microprocessor architecture to which the memory controller belongs. The second gating input end is connected with the memory test circuit 102 to receive the access request of the memory test circuit 102. The target output end is connected with the master module 101.

[0127] Based on the foregoing connection relationship, the second gating module 104 is configured to: in the case that the microprocessor architecture is normally running, connect the first gating input end and the target output end, so that the other control modules 103 in the microprocessor architecture can normally send access requests to the memory through the master module 101, at this time, the memory test circuit 102 can be regarded as being in a dormant or idle state; or in the case that the memory needs to be tested, connect the second gating input end and the target output end, so that the memory test circuit 102 can send an access request for testing the memory to the master module 101, and complete the testing of the memory.

[0128] In actual application, the second gating module can also be implemented based on MUX. As for the specific configuration of the second gating module, reference can be made to the foregoing configuration process of the first gating module, that is, the selection of different connection paths is completed by the preset firmware in the microprocessor architecture startup process or other application scenarios, which will not be described here in detail.

[0129] The memory controller provided by the embodiment of the present application can realize the isolation of the memory test circuit through the second gating module. When the memory controller is running, the memory test circuit will not affect the running process of the memory controller. When the memory is tested, the other control modules will also not affect the testing process, thereby ensuring the reliability and accuracy of the obtained test results.

[0130] Further, as a possible implementation manner, the memory test circuit can be integrated near the master module, which on the one hand reduces the interaction path, and on the other hand, the second gating module has a simple structure and can effectively shield the access requests of the other control modules in the memory testing process.

[0131] Figure 8 The memory controller also includes a conversion module 105, the input end of the conversion module 105 is connected with the master module 101, and the output end is connected with the memory (not shown in the figure). Through the conversion module 105, the access request output by the master module can be converted into an access request recognizable by the memory, so that the memory can correctly respond to the obtained access request.

[0132] The present application also provides a microprocessor architecture, which is shown in Figure 9 Specifically, the microprocessor architecture includes: a memory controller 201, a memory 202, and the memory test circuit 102 provided by any one of the foregoing embodiments.

[0133] The memory test circuit 102, the memory controller 201, and the memory 202 are connected in sequence.

[0134] The memory test circuit 102 sends an access request for testing the memory 202 to the memory controller 201 in the memory testing process of the silicon post-debugging of the microprocessor architecture.

[0135] The memory controller 201 accesses the memory 202 in accordance with an access request to test the memory 202.

[0136] Those skilled in the art will appreciate that the disclosure disclosed herein is susceptible to variations and modifications other than those specifically described. It is to be understood that the disclosure disclosed herein includes all such variations and modifications. For example, the various devices or components described above can be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0137] In addition, while a variety of units in the system according to embodiments of the disclosure are made various references, any number of different units can be used and run on the client and / or server. The units are illustrative only, and different aspects of the system and method can use different units.

[0138] Flowcharts have been used in the present disclosure to illustrate the steps of the methods according to embodiments of the disclosure. It should be understood that the preceding or following steps do not necessarily proceed in order. Instead, various steps can be processed in reverse order, or at the same time. Other operations can also be added to these processes.

[0139] Those of ordinary skill in the art can understand that all or part of the steps in the above method can be instructed by a computer program to relevant hardware, and the program can be stored in a computer readable storage medium, such as a read-only memory. Alternatively, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.

[0140] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0141] The above is a description of the present disclosure and should not be considered as a limitation. Although several exemplary embodiments of the present disclosure are described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is a description of the present disclosure and should not be considered as a limitation. Although several exemplary embodiments of the present disclosure are described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. The present disclosure is limited by the claims and their equivalents.

Claims

1. A memory testing circuit, characterized in that, This is applied to memory testing during the post-silicon debugging process of microprocessor architectures; the microprocessor architecture also includes a memory controller and memory, and the memory testing circuit includes a configuration module, a process control module, and multiple test modules, wherein... Each of the test modules is equipped with at least one memory testing algorithm; The configuration module is used to store module configuration information, and the module configuration information is used to specify at least one target test module among the plurality of test modules; The process control module responds to the test command, determines the at least one target test module according to the module configuration information, and controls each target test module to send an access request to the memory controller according to its own memory test algorithm, so that the memory controller accesses the memory according to the access request.

2. The memory testing circuit according to claim 1, characterized in that, The target test module includes multiple modules, the configuration module also stores module order information, and the memory test circuit further includes a test sorting module, wherein... The test sorting module is used to sort each of the target test modules according to the module order information; The process control module is specifically used to control each target test module to send a test memory access request to the memory controller according to its own memory test algorithm, based on the sorting result of the test sorting module.

3. The memory testing circuit according to claim 2, characterized in that, The memory testing circuit also includes: The first gating module has at least one test input terminal and one test output terminal; Each of the test input terminals is connected to one of the test modules, and the test output terminal is communicatively connected to the memory controller; The first selection module is configured to connect the test input terminals of each target test module to the test output terminals in sequence according to the sorting result.

4. The memory testing circuit according to claim 1, characterized in that, Any of the aforementioned test modules includes: The behavior control module is used to generate an enable signal according to the memory test algorithm corresponding to this test module. A write request generation module is used to generate a write request to the memory in response to the enable signal; A read request generation module is used to generate a read request for the memory in response to the enable signal.

5. The memory testing circuit according to claim 4, characterized in that, The testing module also includes: The data verification module is used to verify the memory data returned by the memory in response to the read request and the memory address to which the memory data belongs.

6. The memory testing circuit according to claim 5, characterized in that, The memory testing circuit also includes: The test result caching module is used to store the verification results returned by each of the test modules.

7. The memory testing circuit according to any one of claims 1 to 6, characterized in that, The memory test circuit is located adjacent to the memory controller.

8. A memory controller, characterized in that, include: The main control module and the memory testing circuit as described in any one of claims 1 to 7, wherein, The memory testing circuit is connected to the main control module; During the post-silicon debugging memory testing process, the memory testing circuit initiates an access request to the memory through the main control module to test the memory.

9. The memory controller according to claim 8, characterized in that, Also includes: The second gating module has a first gating input terminal, a second gating input terminal, and a target output terminal; The first strobe input is used to receive access requests from other control modules in the microprocessor architecture to which the memory controller belongs to the memory access request. The second strobe input terminal is connected to the memory test circuit to receive access requests from the memory test circuit; The target output terminal is connected to the main control module; The second gating module is configured to either connect the first gating input terminal and the target output terminal, or connect the second gating input terminal and the target output terminal.

10. A microprocessor architecture, characterized in that, include: The memory controller, the memory, and the memory test circuit as described in any one of claims 1 to 7, wherein, The memory test circuit, the memory controller, and the memory are connected in sequence. During the memory testing process of the microprocessor architecture after silicon debugging, the memory testing circuit sends an access request to the memory controller to test the memory. The memory controller accesses the memory according to the access request.

Images