Monocrystalline silicon wafer layer fault ring lossless identification method
By combining SP7 testing and laser defect detection with thermal oxidation corrosion technology, the problem of identifying layer faults in monocrystalline silicon wafers has been solved, achieving non-destructive testing and efficient quality monitoring, which is suitable for large-scale production.
Patent Information
- Application Number
- CN202511007691.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-22
- Publication Date
- 2025-11-04
AI Technical Summary
Existing technologies struggle to efficiently identify stacking fault loops in monocrystalline silicon wafers, particularly OISF loops. The inability of existing technologies to effectively identify and process stacking fault loops leads to product waste and complicated testing.
By employing the SP7 testing method, combined with laser defect detection and thermal oxidation corrosion technology, and analyzing the particle distribution map of silicon wafers, stacking fault rings can be identified, avoiding heat treatment and corrosion inspection and saving inspection steps.
It enables non-destructive identification of layer faults and loops in monocrystalline silicon wafers, simplifies the testing process, reduces product waste, and is suitable for quality monitoring in large-scale production.
Smart Images
Figure CN120895490A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of monocrystalline silicon wafer technology, and in particular to a non-destructive method for identifying stacking fault loops in monocrystalline silicon wafers. Background Technology
[0002] For monocrystalline silicon wafers, different intrinsic defects will form due to the influence of crystal growth conditions such as thermal field and pulling speed, depending on the type and concentration of doping. When the silicon wafer is thermally oxidized, the intrinsic stacking fault micro-defect region partially manifests as cyclic oxidation-induced stacking faults, i.e., OISF (Oxidation-Induced Stacking Faults) rings. The location of OISF rings in the crystal corresponds to a fixed critical value V / G, where V is the pulling speed and G is the temperature gradient at the solid-liquid interface. Material manufacturers typically perform corrosion testing on the native micro-defects inside the crystal to detect OISF rings induced by intrinsic stacking fault oxidation. Furthermore, intrinsic stacking fault rings can also induce stacking fault defects after epitaxy.
[0003] Common defects in silicon single crystals mainly include stacking faults, dislocations, and vortices. For some defects, such as vacancy-type defects (COP), laser defect detection and analysis can be performed directly on native silicon wafers. However, some defects, especially OISF, require high-temperature oxidation induction before testing.
[0004] Conventional etching detection methods are complex, the etching solution is polluting, and the etched silicon wafer is unusable, making it difficult to characterize the defect level of the entire crystal ingot. Intrinsic stacking faults cannot be characterized without etching or epitaxy, and routine inspections during the front-end polishing process often fail to detect any abnormalities. Products with OISF rings do not meet quality requirements and must be scrapped, resulting in significant losses. Therefore, it is necessary to design a non-destructive method for identifying stacking fault rings on single-crystal silicon wafers. Summary of the Invention
[0005] The technical problem to be solved by this invention is to provide a non-destructive method for identifying stacking fault loops in monocrystalline silicon wafers. This method pre-identifies stacking faults in monocrystalline silicon wafers and has the advantages of convenient operation and good operational stability. It only uses SP7 testing to avoid heat treatment and corrosion inspection, saving processing time, reducing inspection steps, and avoiding product waste. Moreover, when necessary, it can perform non-destructive full inspection of the entire silicon wafer ingot, which is suitable for comprehensive monitoring of ingot quality and product quality in large-scale production. It also has a verification step, making the overall method more reliable and accurate.
[0006] The technical solution adopted by this invention to solve its technical problem is: to provide a method for non-destructive identification of stacking fault rings in a single-crystal silicon wafer, comprising the following steps:
[0007] Step 1: Prepare silicon wafer samples. A group of samples are numbered and connected to form adjacent wafers. The cleaned silicon wafer samples are subjected to the same chemical polishing treatment to obtain polished silicon wafer samples. The purpose is to completely remove the surface damage and contamination introduced by the previous processing steps and eliminate interference in subsequent tests.
[0008] Step 2: Laser defect detection is performed on the silicon wafer sample using the Ketech particle size analyzer SP7 test; the measurement threshold is 15nm or 19nm, that is, the smallest defect size to be measured is 15nm or 19nm.
[0009] Step 3: After laser defect detection, analyze the particle detection results to determine the degree and location of stacking fault defects within the crystal rod;
[0010] Step 4: Identify densely distributed point defects with ring-like features from the particle test defect distribution map. These densely distributed point defects with ring-like features are suspected stacking fault loops. Then, measure the inner radius r1 and outer radius r2 of the stacking fault loop from the particle test defect distribution map. In the Ketech particle analyzer, reset the wafer detection radius to the inner diameter r1 and only detect the area between r1 and r2. Point defects with the particle density at the center of the particle map are vacancy-type point defects. Compare the particle density of the area with radius r1 with the particle density of the ring-like area between r1 and r2. If the density of the ring-like area is twice or more than twice the density of the central vacancy defect, then the silicon wafer sample has a stacking fault loop defect; otherwise, the silicon wafer sample does not have a stacking fault loop defect.
[0011] Alternatively, in step four: Export the test results with defect coordinates from the SP7 instrument of the Ketech particle analyzer, extract the X-axis in the radial range of the silicon wafer, use the X-axis of the defect point distribution as the abscissa, and the Y-axis of the number of defects as the ordinate; analyze the defects with defect coordinates between -10mm and +10mm in the Y-axis, and construct a histogram of defect distribution within a diameter range of ±20mm, and analyze the radial particle distribution histogram; Condition 1: The radial distribution of the silicon wafer shows a symmetrical distribution trend; Condition 2: There is a significantly higher density in the annular region than in the center, and the particle density is significantly higher than in the center region, and the particle number drops sharply after passing through the annular region; Condition 3: Furthermore, the ratio of the number of micro-defect particles corresponding to each group of test points to the average number of micro-defect particles in its central region is greater than 2; If all three conditions are met simultaneously, the silicon wafer sample has a stacking fault ring defect; otherwise, if any one condition is not met, the silicon wafer sample does not have a stacking fault ring defect.
[0012] As a supplement to the technical solution described in this invention, the following verification steps five to eight are also included:
[0013] Step 5: Perform a post-thermal oxidation corrosion test on the silicon wafer sample that has undergone laser defect detection;
[0014] Step 6: Microscopic examination of the front side of the silicon wafer sample after thermal oxidation and etching; observation of the morphology of strip-shaped oxygen precipitates (OISF) under the microscope, and confirmation of the distribution and results of intrinsic stacking fault rings on the polished wafer by the morphology and distribution of strip-shaped oxygen precipitates (OISF);
[0015] Step 7: Select an adjacent silicon wafer sample that has undergone laser defect detection for epitaxial growth; the epitaxial layer thickness is 15nm or more, the epitaxial layer thickness is 20μm, and the resistivity is 0.002~1000Ω; after epitaxial growth, perform particle testing to identify the stacking fault distribution on the epitaxial wafer.
[0016] Step 8: The results of epitaxial layer fault rings and thermal oxidation etching are correlated with the test results of substrate SP7 laser defect detection particles. Based on the OISF distribution on the silicon wafer after thermal oxidation etching and the morphology of strip-shaped oxygen precipitates OISF under a microscope, the position and distribution of the epitaxial layer fault rings and the position and distribution of the layer fault rings identified by substrate SP7 testing are determined.
[0017] As a supplement to the technical solution described in this invention, the specific content of step five is as follows: the thermal oxidation temperature range is from 800℃ to 1000℃; the process is as follows: standby, opening the furnace door, loading, closing the furnace door, constant temperature, heating, heat preservation, heat treatment, cooling and unloading; during oxidation, in order to ensure the effect of oxidation induction, it is preferable to introduce high-purity oxygen and 18M pure water steam at a flow rate of 3±0.5L / min; after oxidation, the temperature is slowly reduced to 800℃ at a rate of 3℃ / min; the oxidized silicon wafer is slowly pulled out of the furnace at a speed of 200mm / min; in order to reduce the shrinkage and deformation of the silicon wafer caused by the huge temperature difference, the furnace exit speed must be slow; wait for about 30 minutes, and let the silicon wafer cool naturally to room temperature in a clean laminar flow environment.
[0018] As a supplement to the technical solution described in this invention, the corrosion test after thermal oxidation is preferably performed at a temperature of 1000°C for 8 hours, the corrosion solution is Secco solution, the corrosion time is 30 minutes, and densely distributed annular corrosion pits are visible on the surface after corrosion. Microscopic examination of the annular corrosion pits shows typical OISF morphological characteristics.
[0019] As a supplement to the technical solution described in this invention, in step seven, the silicon wafer epitaxial growth includes atmospheric pressure and reduced pressure growth methods, and the epitaxial layer thickness is preferably 20 μm. The stacking faults induced by intrinsic stacking fault loops on the surface of the epitaxial wafer are characterized by particle testing after epitaxial growth, or the intrinsic stacking fault loops are characterized by the etching results of the epitaxial wafer.
[0020] Beneficial effects: This invention relates to a non-destructive method for identifying stacking fault loops in monocrystalline silicon wafers. This method allows for pre-identification of stacking faults in monocrystalline silicon wafers, offering advantages such as ease of operation and high stability. It utilizes only the SP7 test, avoiding heat treatment and corrosion inspection, thus saving processing time, simplifying inspection procedures, and preventing product waste. Furthermore, it allows for non-destructive full inspection of the entire silicon wafer ingot when necessary, making it suitable for comprehensive monitoring of ingot quality and product quality during large-scale production. The invention also includes a verification step, making the overall method more reliable and accurate. Attached Figure Description
[0021] Figure 1 This is a step diagram of the present invention;
[0022] Figure 2 This is a particle test result diagram of laser defect detection of silicon wafers after epitaxial growth as described in this invention;
[0023] Figure 3 This is a particle test result diagram of SP7 laser defect detection on a polished silicon wafer sample with a measurement threshold of 19nm as described in this invention;
[0024] Figure 4 This is a microscopic morphology observation image of the front side after thermal oxidation corrosion as described in this invention;
[0025] Figure 5 This is a particle test result diagram of SP7 laser defect detection for the inner diameter of stacking fault rings with a measurement threshold of 15nm, as described in this invention.
[0026] Figure 6 This is a particle test result diagram of SP7 laser defect detection of stacking fault rings with a measurement threshold of 15nm, from the inner diameter to the outer diameter.
[0027] Figure 7 This is a histogram showing the distribution of the number of defects in the Y direction within ±10 mm of a particle measured by the SP7 laser defect detection method of the present invention, with a diameter of 300 mm. Detailed Implementation
[0028] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.
[0029] The embodiments of the present invention relate to a non-destructive method for identifying stacking fault loops in a single-crystal silicon wafer, such as... Figure 1-7 As shown, there are two embodiments, taking a lightly doped silicon single crystal P-type circular silicon wafer with a diameter of 300 mm as an example.
[0030] Example 1 includes the following steps:
[0031] Step 1: Prepare silicon wafer samples. A group of samples are numbered and connected to form adjacent wafers. The cleaned silicon wafer samples are subjected to the same chemical polishing treatment to obtain polished silicon wafer samples. The purpose is to completely remove the surface damage and contamination introduced by the previous processing steps and eliminate interference in subsequent tests.
[0032] Step 2: Perform laser defect detection on silicon wafer samples. Preferably, use KLA-Tencor (i.e., KLA particle size analyzer) for SP7 testing. The measurement threshold is 15nm or 19nm, that is, the minimum defect size to be measured is 15nm or 19nm.
[0033] Step 3: After laser defect detection, analyze the particle detection results to determine the degree and location of stacking fault defects within the crystal rod;
[0034] Step 4: Identify densely distributed point defects with ring-shaped features from the particle test defect distribution map. These densely distributed point defects with ring-shaped features are suspected stacking fault loops. Then, measure the inner radius r1 and outer radius r2 of the stacking fault loop from the particle test defect distribution map. In the Ketech particle analyzer, reset the wafer detection radius to the inner diameter r1 and only detect the area between r1 and r2. Point defects with the particle density at the center of the particle map are vacancy-type point defects. Compare the particle density of the area with radius r1 with the particle density of the ring-shaped area between r1 and r2. If the density of the ring-shaped area is twice or more than twice the density of the central vacancy defect, then the silicon wafer sample has a stacking fault loop defect; otherwise, the silicon wafer sample does not have a stacking fault loop defect.
[0035] Step four is illustrated using r1 as 100 μm and r2 as 110 μm as an example. Based on the location of the undetermined stacking fault ring, the SP7 detection area is shielded. The detection radius ranges from 100 μm to 110 μm for rings (see...). Figure 6 Based on the number of detected particles and the area of the ring, where the number of detected particles is 3972, the particle density D1 in the stacking fault ring is calculated as D1 = 3972 / (3.14 * (110^2 - 100^2)). Based on the location of the undetermined stacking fault ring, the SP7 detection area is shielded, with the detection radius within 100 μm of the wafer center. Based on the particle MAP (see...),... Figure 5 The number of defects and the area of the detection circle are used to calculate the particle density D2 in the intrinsic defects of the vacancy COP; the Ratio = D1 / D2 is calculated. If the Ratio is greater than 2, then the silicon wafer product has a stacking fault ring defect.
[0036] Example 2 includes the following steps:
[0037] Step 1: Prepare silicon wafer samples. A group of samples are numbered and connected to form adjacent wafers. The cleaned silicon wafer samples are subjected to the same chemical polishing treatment to obtain polished silicon wafer samples. The purpose is to completely remove the surface damage and contamination introduced by the previous processing steps and eliminate interference in subsequent tests.
[0038] Step 2: Perform laser defect detection on silicon wafer samples. Preferably, use KLA-Tencor (i.e., KLA particle size analyzer) for SP7 testing. The measurement threshold is 15nm or 19nm, that is, the minimum defect size to be measured is 15nm or 19nm.
[0039] Step 3: After laser defect detection, analyze the particle detection results to determine the degree and location of stacking fault defects within the crystal rod;
[0040] Step 4: Export the test results with defect coordinates from the SP7 particle analyzer of Ketech (TFF, Klarf, CSV, etc. formats). In the test file of the 300mm round silicon wafer, extract the X-axis radial range of the silicon wafer from 0-300mm. Plot the X-axis of defect point distribution as the abscissa and the Y-axis of the number of defects as the ordinate. Analyze the defects with defect coordinates between -10mm and +10mm in the Y-axis and construct a histogram of defect distribution within a diameter range of ±20mm (see...). Figure 7 The spacing between adjacent defect distribution histogram regions in the X direction does not exceed 20mm. The smaller the spacing, such as 10mm or 5mm, the more detailed the distribution of the corresponding micro-defect particles is, and the easier it is to see the changing pattern of the number of micro-defect particles. Analysis of the radial particle distribution histogram is performed. Condition 1: The radial distribution of the silicon wafer shows a symmetrical distribution trend. Condition 2: There is a number density in the annular region that is significantly higher than that in the center, and it is significantly higher than that in the center region. After passing through the annular region, the number of particles drops sharply. Condition 3: Furthermore, the ratio of the number of micro-defect particles corresponding to each group of test points to the average number of micro-defect particles shown in the center region is greater than 2. If all three conditions are met, the silicon wafer sample has a stacking fault ring defect. Conversely, if any one condition is not met, the silicon wafer sample does not have a stacking fault ring defect.
[0041] Both of the above embodiments also include verification steps five through eight. These verification steps re-authenticate the judgment results of steps one through four, making the overall method more reliable. Once the accuracy of the judgments in steps one through four is confirmed, only steps one through four need to be used.
[0042] Step 5: Perform a post-thermal oxidation corrosion test on the silicon wafer samples that have undergone laser defect detection; the thermal oxidation temperature range is from 800℃ to 1000℃; the process is as follows: standby, opening the furnace door, loading, closing the furnace door, constant temperature, heating, holding, heat treatment, cooling and unloading; during oxidation, to ensure the effect of oxidation induction, it is preferable to introduce high-purity oxygen and 18M pure water vapor at a flow rate of 3±0.5L / min; after oxidation, slowly cool down to 800℃ at a rate of 3℃ / min; slowly pull the oxidized silicon wafer out of the furnace at a speed of 200mm / min; to reduce the shrinkage and deformation of the silicon wafer caused by the huge temperature difference, the furnace exit speed must be slow; wait for about 30 minutes for the silicon wafer to cool naturally to room temperature in a clean laminar flow environment;
[0043] Step Six: Microscopic examination of the front side of the silicon wafer sample after thermal oxidation and etching; observation of the morphology of the strip-shaped oxygen precipitates (OISF) under the microscope. (See attached image for OISF morphology). Figure 4 ) and distribution (see appendix) Figure 3 Confirm the distribution and results of intrinsic stacking fault loops on the polished wafer;
[0044] Step 7: Select an adjacent silicon wafer sample that has undergone laser defect detection for epitaxial growth; the epitaxial layer thickness should be 15 nm or more, with a thickness of 20 μm and a resistivity of 0.002–1000 Ω; after epitaxial growth, perform particle testing to identify the stacking fault distribution on the epitaxial wafer (see Appendix). Figure 2 );
[0045] Step 8: The results of epitaxial layer fault rings and thermal oxidation etching are correlated with the particle test results of SP7 laser defect detection on the substrate. Based on the OISF distribution on the silicon wafer after thermal oxidation etching and the microscopic observation of the strip-shaped oxygen precipitates OISF morphology (see Appendix)... Figure 4 The location and distribution of layer fault loops after epitaxy were determined, and the location and distribution of layer fault loops were identified by substrate SP7 testing.
[0046] The corrosion test after thermal oxidation is preferably performed at a temperature of 1000℃ for 8 hours. The corrosion solution is Secco solution, and the corrosion time is 30 minutes. After corrosion, densely distributed annular corrosion pits are visible on the surface. Microscopic examination of the annular corrosion pits shows typical OISF morphological characteristics.
[0047] In step seven, the silicon wafer epitaxial growth includes atmospheric pressure and reduced pressure growth methods. The epitaxial layer thickness is preferably 20 μm. The stacking faults induced by intrinsic stacking fault loops on the surface of the epitaxial wafer are characterized by particle testing of the wafer after epitaxial growth, or the intrinsic stacking fault loops are characterized by the etching results of the epitaxial wafer.
[0048] The silicon wafer products mentioned above include silicon wafers with different doping levels, different resistivities, and different doping elements, including phosphorus, arsenic, antimony, and boron.
[0049] This invention provides pre-identification of stacking faults in monocrystalline silicon wafers, offering advantages such as ease of operation and high stability. It utilizes only the SP7 test, eliminating the need for heat treatment and corrosion inspection, thus saving processing time, simplifying inspection procedures, and preventing product waste. Furthermore, it allows for non-destructive full inspection of the entire silicon wafer ingot when necessary, making it suitable for comprehensive monitoring of ingot quality and product quality during large-scale production. The invention also includes verification steps, further enhancing the reliability and accuracy of the overall method.
[0050] In the description of this invention, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this invention and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this invention; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.
[0051] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.
[0052] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this invention.
[0053] The above provides a detailed description of a non-destructive identification method for layer fault rings in single-crystal silicon wafers. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and its core ideas. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A non-destructive method for identifying stacking fault rings in a single-crystal silicon wafer, characterized in that: The following steps are included: Step 1: Prepare silicon wafer samples. A group of samples are numbered and connected to form adjacent wafers. The cleaned silicon wafer samples are subjected to the same chemical polishing treatment to obtain polished silicon wafer samples. The purpose is to completely remove the surface damage and contamination introduced by the previous processing steps and eliminate interference in subsequent tests. Step 2: Laser defect detection is performed on the silicon wafer sample using the Ketech particle size analyzer SP7 test; the measurement threshold is 15nm or 19nm, that is, the smallest defect size to be measured is 15nm or 19nm. Step 3: After laser defect detection, analyze the particle detection results to determine the degree and location of stacking fault defects within the crystal rod; Step 4: Identify densely distributed point defects with ring-like features from the particle test defect distribution map. These densely distributed point defects with ring-like features are suspected stacking fault loops. Then, measure the inner radius r1 and outer radius r2 of the stacking fault loop from the particle test defect distribution map. In the Ketech particle analyzer, reset the wafer detection radius to the inner diameter r1 and only detect the area between r1 and r2. Point defects with the particle density at the center of the particle map are vacancy-type point defects. Compare the particle density of the area with radius r1 with the particle density of the ring-like area between r1 and r2. If the density of the ring-like area is twice or more than twice the density of the central vacancy defect, then the silicon wafer sample has a stacking fault loop defect; otherwise, the silicon wafer sample does not have a stacking fault loop defect. Alternatively, in step four: Export the test results with defect coordinates from the SP7 instrument of the Ketech particle analyzer, extract the X-axis in the radial range of the silicon wafer, use the X-axis of the defect point distribution as the abscissa, and the Y-axis of the number of defects as the ordinate; analyze the defects with defect coordinates between -10mm and +10mm in the Y-axis, and construct a histogram of defect distribution within a diameter range of ±20mm, and analyze the radial particle distribution histogram; Condition 1: The radial distribution of the silicon wafer shows a symmetrical distribution trend; Condition 2: There is a significantly higher density in the annular region than in the center, and the particle density is significantly higher than in the center region, and the particle number drops sharply after passing through the annular region; Condition 3: Furthermore, the ratio of the number of micro-defect particles corresponding to each group of test points to the average number of micro-defect particles in its central region is greater than 2; If all three conditions are met simultaneously, the silicon wafer sample has a stacking fault ring defect; otherwise, if any one condition is not met, the silicon wafer sample does not have a stacking fault ring defect.
2. The method for non-destructive identification of stacking fault rings in a single-crystal silicon wafer according to claim 1, characterized in that: It also includes the following verification steps five through eight: Step 5: Perform a post-thermal oxidation corrosion test on the silicon wafer sample that has undergone laser defect detection; Step 6: Microscopic examination of the front side of the silicon wafer sample after thermal oxidation and etching; observation of the morphology of strip-shaped oxygen precipitates (OISF) under the microscope, and confirmation of the distribution and results of intrinsic stacking fault rings on the polished wafer by the morphology and distribution of strip-shaped oxygen precipitates (OISF); Step 7: Select an adjacent silicon wafer sample that has undergone laser defect detection for epitaxial growth; the epitaxial layer thickness is 15nm or more, the epitaxial layer thickness is 20μm, and the resistivity is 0.002~1000Ω; after epitaxial growth, perform particle testing to identify the stacking fault distribution on the epitaxial wafer. Step 8: The results of epitaxial layer fault rings and thermal oxidation etching are correlated with the test results of substrate SP7 laser defect detection particles. Based on the OISF distribution on the silicon wafer after thermal oxidation etching and the morphology of strip-shaped oxygen precipitates OISF under a microscope, the position and distribution of the epitaxial layer fault rings and the position and distribution of the layer fault rings identified by substrate SP7 testing are determined.
3. The method for non-destructive identification of stacking fault rings in a single-crystal silicon wafer according to claim 2, characterized in that: The specific details of step five are as follows: the thermal oxidation temperature range is from 800℃ to 1000℃; the process is as follows: standby, opening the furnace door, loading, closing the furnace door, constant temperature, heating, holding, heat treatment, cooling and unloading; during oxidation, to ensure the effect of oxidation induction, it is preferable to introduce high-purity oxygen and 18M pure water steam at a flow rate of 3±0.5L / min; after oxidation, the temperature is slowly reduced to 800℃ at a rate of 3℃ / min; the oxidized silicon wafer is slowly pulled out of the furnace at a speed of 200mm / min; to reduce the shrinkage and deformation of the silicon wafer caused by the huge temperature difference, the furnace exit speed must be slow. Wait about 30 minutes for the silicon wafer to cool naturally to room temperature in a clean laminar flow environment.
4. The method for non-destructive identification of stacking fault rings in a single-crystal silicon wafer according to claim 3, characterized in that: The corrosion test after thermal oxidation is preferably performed at a temperature of 1000℃ for 8 hours. The corrosion solution is Secco solution, and the corrosion time is 30 minutes. After corrosion, densely distributed annular corrosion pits are visible on the surface. Microscopic examination of the annular corrosion pits shows typical OISF morphological characteristics.
5. The method for non-destructive identification of stacking fault rings in a single-crystal silicon wafer according to claim 2, characterized in that: In step seven, the silicon wafer epitaxial growth includes atmospheric pressure and reduced pressure growth methods. The epitaxial layer thickness is preferably 20 μm. The stacking faults induced by intrinsic stacking fault loops on the surface of the epitaxial wafer are characterized by particle testing of the wafer after epitaxial growth, or the intrinsic stacking fault loops are characterized by the etching results of the epitaxial wafer.