Curvilinear processing method for semiconductor devices and semiconductor device layouts

Abstract

The application discloses a semiconductor device and a curve processing method of a semiconductor device layout. The semiconductor device comprises a metal interconnection layer; a metal coverage area of the metal interconnection layer is a closed area formed by a plurality of boundary lines with different directions and connected by transition lines; the transition line between two adjacent boundary lines is a curve determined according to the intersection relationship of the two boundary lines, and the opening direction of the curve and the intersection point of the two boundary lines are located on the two sides of the curve. The end points of the related lines forming the metal interconnection layer are taken as processing objects, and the transition lines are used for transition at the positions where the related lines change direction, so that the overall coverage adjustment of each angle is realized, the inradius of all concave corner positions is increased as much as possible, the stress distribution concentration effect at each concave corner is weakened, the crack formation is avoided, the metal electromigration, the connected lines or the broken lines and other phenomena are eliminated, the product quality is obviously improved, and the chip life is prolonged.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to semiconductor devices and a method for processing curves in semiconductor device layouts. Background Technology

[0002] Semiconductor integrated circuits are widely used in consumer electronics, communication technology, automotive industry, medical and aerospace fields, playing an irreplaceable role in modern life. Different integrated circuit chips undergo corresponding reliability tests and have different pass / fail standards depending on their application. For example, the lifespan of consumer electronics is 5-10 years, while automotive electronics require a lifespan of no less than 15 years. Furthermore, automotive chips have higher packaging standards, such as using ceramic packaging; chips operating in high humidity environments must pass humidity sensitivity testing (HSM).

[0003] In the reliability testing of semiconductor integrated circuits, the metal interconnect layer and post-interconnect test (PIT) are crucial. As the outermost layer of the chip interconnect structure, the metal interconnect layer directly undertakes the functions of signal transmission, power management, packaging, and connectivity. Its electrical characteristics (including resistance, current carrying capacity, and parasitic capacitance) and physical integrity (such as resistance to electromigration and resistance to mechanical stress) are core factors affecting the long-term reliability of the device. PIT testing not only includes electrical testing but also stress testing (such as high temperature and humidity, and temperature cycling) to assess the failure risk of the metal layer under extreme environments.

[0004] The inventors, through a comprehensive analysis of the test results of existing semiconductor devices, discovered that potential defects in the metal interconnect layer (such as cracks and interface delamination) may lead to premature metal electromigration, bridging, or breakage during reliability testing, thereby reducing chip lifespan. Summary of the Invention

[0005] This application provides a semiconductor device, a method for processing the curve of a semiconductor device layout, an electronic device, and a storage medium. It solves the technical problem that potential defects (such as cracks and interface delamination) in the metal interconnect layer of existing semiconductor devices may lead to premature metal electromigration, bridging, or breakage during reliability testing, thereby reducing chip lifespan.

[0006] In a first aspect, embodiments of this application provide a semiconductor device, which includes a metal interconnect layer;

[0007] The metal-covered area of ​​the metal interconnect layer is a closed region formed by connecting multiple boundary lines with different directions through transition lines;

[0008] The transition line between two adjacent boundary lines is a curve determined by the intersection relationship of the two boundary lines. The opening direction of the curve and the intersection point of the two boundary lines are located on both sides of the curve.

[0009] The transition lines are either circular or elliptical.

[0010] Wherein, the gap of the circular arc is greater than a preset first threshold value, and the diameter of the circular arc is equal to the first threshold value; the gap of the elliptical arc is less than or equal to the preset first threshold value, the length of the minor axis of the elliptical arc is equal to the width of the gap, and the length of the major axis of the elliptical arc is greater than the width of the gap.

[0011] The thickness of the metal interconnect layer is between 20,000 and 40,000 angstroms, and the width of the wiring in the metal interconnect layer is greater than 2 micrometers.

[0012] Secondly, embodiments of this application provide a method for curve processing of semiconductor device layouts, the method comprising:

[0013] The optical proximity effect correction tool is used to filter the line endpoints of the metal interconnect layer of the layout to be processed, resulting in multiple line endpoints to be processed. The closed area formed by the lines between the line endpoints to be processed is the metal coverage area of ​​the metal interconnect layer.

[0014] Curves are added to the endpoints of the lines to be processed to obtain the target layout. The curves connect two lines and are tangent to the corresponding two lines.

[0015] The process involves adding curves based on the endpoints of the lines to be processed to obtain the target layout, including:

[0016] The layout to be processed is enlarged to obtain the enlarged layout;

[0017] Add curves to the enlarged layout based on the endpoints of the lines to be processed to obtain the intermediate layout;

[0018] The intermediate layout is scaled down to obtain a target layout of the same size as the layout to be processed.

[0019] Among them, the optical proximity effect correction tool is used to screen the line endpoints of the metal interconnect layers in the layout to be processed, resulting in multiple line endpoints to be processed, including:

[0020] The optical proximity correction tool is used to extract the line endpoints of the metal interconnect layer of the layout to be processed, resulting in multiple initial line endpoints;

[0021] Based on the optical proximity effect correction tool, the endpoints corresponding to the step positions in the initial line endpoints are filtered out to obtain multiple initial line endpoints.

[0022] The curve can be either a circular arc or an elliptical arc.

[0023] Thirdly, embodiments of this application provide an electronic device, which includes a processor and a memory;

[0024] The memory is used to store computer programs and transfer them to the processor;

[0025] The processor is used to execute a curve-based processing method for semiconductor device layout, as described in the second aspect, according to instructions in a computer program.

[0026] Fourthly, embodiments of this application provide a storage medium for storing computer-executable instructions, which, when executed by a computer processor, are used to perform a curve-based processing method for a semiconductor device layout as described in the second aspect.

[0027] This application discloses a semiconductor device, a method, apparatus, and storage medium for curve-based processing of semiconductor device layouts. The semiconductor device includes a metal interconnect layer; the metal-covered area of ​​the metal interconnect layer is a closed region formed by connecting multiple boundary lines with different directions via transition lines; the transition line between two adjacent boundary lines is a curve determined based on the intersection relationship of the two boundary lines, with the curve's opening direction and the intersection point of the two boundary lines located on both sides of the curve. Taking the endpoints of the relevant lines forming the metal interconnect layer as the processing object, curves are used for transition at the points where the relevant lines change direction, achieving comprehensive coverage adjustment for each angle. This maximizes the inscribed circle radius at all concave corner positions, reduces stress concentration at each concave corner, avoids crack formation, eliminates metal electromigration, bridging, or breakage, significantly improves product quality, and extends chip lifespan. Attached Figure Description

[0028] Figure 1 A schematic diagram of the photoresist morphology simulated by an optical proximity effect model at the concave corner of the metal interconnect layer.

[0029] Figure 2 This is a schematic diagram of a crack at a concave corner.

[0030] Figure 3 This is a schematic diagram illustrating how related technologies correct the position of the concave corner.

[0031] Figure 4 For use Figure 3 A schematic diagram of the photoresist morphology at the concave corner of a semiconductor device produced by the correction method.

[0032] Figure 5 This is a schematic diagram of stress distribution at the concave corner location and a schematic diagram of stress distribution changes before and after correction of the concave corner location in related technologies.

[0033] Figure 6A flowchart illustrating a method for processing a curved layout of a semiconductor device provided in this application embodiment.

[0034] Figures 7-9 This is a schematic diagram of the gaps involved in gap width measurement.

[0035] Figure 10 This is a schematic diagram of a specific semiconductor layout processing procedure.

[0036] Figure 11 This diagram illustrates the effect of isosceles right triangle treatment of the concave corner position and the treatment according to the embodiments of this application on the gap.

[0037] Figure 12 This is a schematic diagram of crack distribution in the metal interconnect layer in related technologies.

[0038] Figure 13 This is a schematic diagram showing the processing result of a curve-type processing method for a semiconductor device layout provided in an embodiment of this application.

[0039] Figure 14 This is a schematic diagram of the photoresist morphology at a concave corner position after processing by a curve-type processing method for a semiconductor device layout provided in an embodiment of this application.

[0040] Figure 15 This is a schematic diagram of a step at a concave angle and a non-right-angle position.

[0041] Figure 16 This is a schematic diagram comparing the effects of treating the concave corner with an isosceles right triangle and the treatment according to the embodiments of this application.

[0042] Figure 17 This is a schematic diagram showing the processing result of the convex corner.

[0043] Figure 18 This is a schematic diagram illustrating the adjustment of the transition line.

[0044] Figure 19 This is a schematic diagram of a semiconductor device layout processing apparatus provided in an embodiment of this application.

[0045] Figure 20 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0046] The following description and accompanying drawings fully illustrate specific embodiments of this application to enable those skilled in the art to practice them. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. The scope of embodiments of this application includes the entire scope of the claims and all available equivalents of the claims. In this document, each embodiment may be referred to individually or collectively by the term "invention," which is merely for convenience and is not intended to automatically limit the scope of the application to any single invention or inventive concept if more than one invention is disclosed. Relational terms such as "first" and "second" are used herein only to distinguish one entity or operation from another, without requiring or implying any actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed. The various embodiments in this document are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the structures, products, etc., disclosed in the embodiments, since they correspond to the disclosed parts, the descriptions are relatively simple; relevant details can be found in the method section.

[0047] Aluminum is a primary material for metal interconnect layers, offering advantages such as low cost, simple processing, and compatibility with earlier silicon device processes (e.g., bipolar devices). It is widely used in integrated circuit manufacturing at process nodes of 0.18 micrometers and above. Aluminum-processed chips are extensively used in critical fields such as consumer electronics, automotive, medical, and aerospace. For aluminum-processed integrated circuits, a range of reliability tests are available, including resistance and humidity sensitivity testing, post-interconnect test (PIT), and mechanical reliability testing.

[0048] The inventors, through a comprehensive analysis of the test results of existing semiconductor devices, discovered that potential defects in the metal interconnect layer (such as cracks and interface delamination) may lead to premature metal electromigration, bridging, or breakage during reliability testing, thereby reducing chip lifespan.

[0049] The inventors conducted in-depth research into the causes of this problem in existing semiconductor devices. In the chip manufacturing process, the later the process flow, the thicker the aluminum layer and the larger the linewidth. At the metal interconnect layer, the linewidth typically reaches 1.5 micrometers or more, and the thickness typically reaches 10,000 to 40,000 angstroms. The photolithography process for the metal interconnect layer generally uses an I-line lithography machine with a wavelength of 365 nanometers. Because the design size of the metal interconnect layer is much larger than the I-line wavelength (more than 3 times), the photoresist morphology at the concave corners is close to a right angle (e.g., ...). Figure 1 (As shown). After etching, the pattern is transferred to the metal interconnect layer. The concave corners of the metal interconnect layer are also close to right angles after etching, and the radius of the inscribed circle is small.

[0050] The stress distribution at the concave corner of aluminum metal during the etching process is similar to that at the corner of a stepped axis. The inscribed circle of a near-right-angle concave corner is very small, resulting in a large stress concentration factor at the stepped axis corner. Due to physical bombardment, chemical corrosion, material structure changes, and interfacial stress between the subsequent passivation dielectric layer and the metal layer during etching, residual tensile stress forms on the metal surface. At the concave corner, this stress concentration effect easily leads to… Figure 2 The crack shown.

[0051] The inventors analyzed existing technical approaches to solving problems such as cracks and interface delamination and found that existing solutions to stress concentration effects involve placing a device such as... at the concave corner. Figure 3 The isosceles right triangle is shown in the dashed box. This method optimizes the design structure to make the concave corners of the final etched metal interconnect layer rounded. The rounded concave corner morphology is as follows: Figure 4 As shown in the dashed box, the stress concentration effect weakens as the radius of its inscribed circle increases. A comparison of the stress distribution at the concave corner before and after the rounding with the stress distribution at the corner of the stepped shaft reveals the following: Figure 5 As shown in the diagram. The left side presents the stress distribution when the concave corner is a right angle (i.e., before the shape becomes rounded), with the inscribed circle at the concave corner being a gray shaded area. The middle side presents the step axial angle stress concentration factor obtained from the stress concentration handbook. The right side presents the stress distribution when an isosceles right triangle is added to the concave corner (i.e., after the shape becomes rounded), with the inscribed circle at the concave corner being a gray shaded area. The solid lines represent the structural boundary, the dashed lines within the solid lines represent the stress distribution, and the dashed circles represent the inscribed circles at the concave corner.

[0052] The inventor based on Figure 3 and Figure 4 Further analysis of existing semiconductor devices reveals that when using isosceles right triangles for topography adjustment at concave corners in gaps, these triangles are typically placed by selecting specific sides through an optical proximity correction menu, which is quite complex. Special patterns require specific code for processing, and incomplete adjustments to the layout are the underlying cause of reduced chip lifespan.

[0053] Based on the initial observed problems and the analysis of their underlying causes, the inventors proposed a semiconductor device comprising a metal interconnect layer. The metal-covered area of ​​the interconnect layer is a closed region formed by connecting multiple boundary lines with different directions via transition lines. The transition line between two adjacent boundary lines is a curve determined by the intersection relationship of the two boundary lines, with the curve's opening direction and the intersection point of the two boundary lines located on opposite sides of the curve. By focusing on the endpoints of the relevant lines forming the metal interconnect layer, curves are used for transitions at the points where the relevant lines change direction, achieving comprehensive coverage and adjustment at every angle. This maximizes the radius of the inscribed circle at all concave corners, reduces stress concentration at each concave corner, prevents crack formation, eliminates metal electromigration, striations, or breaks, significantly improves product quality, and extends chip lifespan.

[0054] This application provides a semiconductor device and a curve-based processing method for semiconductor device layouts. The curve-based processing method is used to correct the layout to be processed. The layout to be processed is a design drawing created by a designer as a production reference for the semiconductor device. Designers, unlike production technicians, do not have complete knowledge of the manufacturing process details. If a semiconductor device is manufactured precisely according to the design drawing, it can achieve the corresponding function and ensure product quality. However, errors, large or small, in the manufacturing process details may lead to discrepancies between the manufactured semiconductor device and the design drawing, affecting product quality. To eliminate such errors, the layout to be processed needs to be corrected according to the manufacturing process details. Only semiconductor devices manufactured according to the corrected design drawing can achieve the intended design function while ensuring product quality.

[0055] In this application embodiment, considering that the final product form of a semiconductor device is determined by the corresponding design drawing used as a production reference, and that the design drawing used as a production reference originates from the curve processing method of the semiconductor device layout, the curve processing method of the semiconductor device layout and the embodiments of the semiconductor device are comprehensively described. While describing the semiconductor device layout using the curve processing method as the framework, the implementation details of the curve processing method of the semiconductor device layout and its impact on the product form of the semiconductor device are described, and the detailed description of the embodiments of the semiconductor device is completed accordingly.

[0056] Please refer to Figure 6 This is a flowchart of a method for processing a curve-type layout of a semiconductor device provided in an embodiment of this application, as shown below. Figure 6 As shown, the method for processing the curve of the semiconductor device layout includes, but is not limited to, steps S110-S120:

[0057] Step S110: Based on the optical proximity effect correction tool, the line endpoints of the metal interconnect layer of the layout to be processed are screened to obtain multiple line endpoints to be processed. The closed area formed by the lines between the line endpoints to be processed is the metal coverage area of ​​the metal interconnect layer.

[0058] Optical proximity correction tools are primarily used in semiconductor manufacturing to compensate for pattern distortion during photolithography, ensuring that the chip circuitry matches the design. In this embodiment, based on the standard verification rule format (SVRF) statement in the optical proximity effect menu, all line endpoints in the layout to be processed that may involve concave corners can be filtered.

[0059] In practical implementation, an optical proximity correction effect model can be established based on parameters such as wavelength, numerical aperture, illumination conditions, film material thickness, and corresponding refractive index and extinction coefficient of the actual photolithography process, as well as the online measured linewidth. Among these, the online measured linewidth involves dense lines (…). Figure 7 Isolated lines Figure 8 ) and gap endpoint to endpoint graphics ( Figure 9 ) and corresponding gap diagrams (for Figures 7-9 (Simply invert the lines in the diagram). Black lines represent opaque lines.

[0060] For metal interconnect layers, the metal-covered areas are composed of Figures 7-9 The text is a jumbled mess of lines, seemingly unrelated and nonsensical. It appears to be a collection of fragments from various sources, possibly related to a computer program or a document. A coherent translation is impossible without the full context.

[0061] Step S120: Add curves based on the endpoints of the lines to be processed to obtain the target layout. The curves connect two lines and are tangent to the corresponding two lines.

[0062] For the selected line endpoints, curves are added according to the set curve parameters. For the concave and convex corner positions in the layout to be processed, designed and drawn strictly according to horizontal and vertical alignment, adding curves ensures that the radius of the inscribed circle at any position in the target layout is greater than the radius of the inscribed circle at any position in the layout to be processed, and that the minimum width of the gap in the metal interconnect layer is greater than the preset strut threshold. The resulting semiconductor device, because it uses the endpoints of the lines forming the metal interconnect layer as the processing object, uses curves to transition at the points where the lines change direction, achieving comprehensive coverage adjustment for each angle. This maximizes the radius of the inscribed circle at all concave corner positions, reduces the stress concentration effect at each concave corner, avoids crack formation, eliminates metal electromigration, struts, or breaks, significantly improves product quality, and extends chip lifespan. The curve can be, for example, an arc. The radius of the arc is determined by the width of the gap where the line is located, ensuring that there are no struts under the support of the actual production process.

[0063] Based on the target layout obtained by the above-described curve-based processing method for semiconductor device layout, the semiconductor device provided in this embodiment can be manufactured. The semiconductor device provided in this embodiment includes a metal interconnect layer; the metal-covered area of ​​the metal interconnect layer is a closed region formed by connecting multiple boundary lines with different directions through transition lines; the transition line between two adjacent boundary lines is a curve determined according to the intersection relationship of the two boundary lines, and the opening direction of the curve and the intersection point of the two boundary lines are located on both sides of the curve. The shape of the transition line can be an arc. The metal-covered area corresponding to the transition line is implemented based on an etching process.

[0064] In one optional implementation, a target layout is obtained by adding curves based on the endpoints of the lines to be processed, including: enlarging the layout to be processed to obtain an enlarged layout; adding curves to the enlarged layout based on the endpoints of the lines to be processed to obtain an intermediate layout; and shrinking the intermediate layout to obtain a target layout of the same size as the layout to be processed.

[0065] Since the smoothing layout function is based on optical proximity correction, the optical proximity effect is weak for large-sized graphics. Therefore, software processing the layout may limit the maximum smoothable side length (e.g., less than 1 micrometer). Based on the embodiments of this application, the size of the graphics in the layout that need adjustment can be increased first (e.g., ...). Figure 10 The gray-filled area on the left side is first expanded by 0.42 micrometers, and then smoothed to a certain size (e.g.) Figure 10 The diagonal line and gray-filled area in the middle, with a smooth curved edge of 0.8 micrometers), are then reduced by 0.42 micrometers to the original size (e.g., Figure 10By filling the diagonal line area on the right side of the layout, a smoothing effect greater than 1 micrometer (approximately 1.22 micrometers) can be achieved. When the layout gap d is less than 2.44 micrometers, optical proximity correction software is used. Figure 10 The enlargement operation shown generates a small gap with a width less than 1.6 micrometers. For such small gaps, the optical proximity correction software can independently generate a quarter-ellipse with a minor axis of d / 2 and an arbitrary major axis (typically, the major axis of such an ellipse is d / 2 to 3d / 2), see [link to documentation]. Figure 11 As shown in (b), compared to the traditional isosceles right triangle (see...), Figure 11 (a) has the advantage of being closer to the design dimensions, that is Figure 11 In the middle, Db is less than Da (the photoresist morphology of the black solid line is obtained through...). Figure 2 The optical proximity effect model shown is obtained through simulation.

[0066] Overall, the gap of the circular arc is greater than the preset first threshold value (e.g., 2.44 micrometers as described above), and the diameter of the circular arc is equal to the first threshold value; the gap of the elliptical arc is less than or equal to the preset first threshold value, the length of the minor axis of the elliptical arc is equal to the width of the gap, and the length of the major axis of the elliptical arc is greater than the width of the gap.

[0067] Because the inscribed circle radius of a convex corner is larger than that of a concave corner, the stress concentration effect is stronger at the concave corner. Metal-level cracks are also found at the concave corners during post-interconnect testing of the chip. Since the optical proximity effect is more pronounced at large sizes, manifested in smoother photoresist morphology and etched patterns at the endpoints, and a smaller inscribed circle area, the stress concentration effect is even stronger. Therefore, cracks often appear at large gap corners, as shown in the specific distribution... Figure 12 As shown.

[0068] More broadly, for thicker aluminum interconnect layers and wider aluminum gaps, larger concave areas may need to be filled to address greater stress issues. Assuming the area of ​​the curve to be filled and the edge of the original layout is X (X > 1 micrometer), and the area of ​​the intermediate transition curve and the edge of the enlarged transition layout is Y (Y < 1 micrometer), then the layout needs to be enlarged by (XY) micrometers, smoothed by Y micrometers, and then reduced by (XY) micrometers back to its original size. This allows for the creation of arbitrary curve-filled layouts larger than 1 micrometer.

[0069] In another alternative implementation, the line endpoints of the metal interconnect layer of the layout to be processed are screened based on the optical proximity correction tool to obtain multiple line endpoints to be processed, including: extracting line endpoints of the metal interconnect layer of the layout to be processed based on the optical proximity correction tool to obtain multiple initial line endpoints; and filtering out the endpoints corresponding to the step positions among the initial line endpoints based on the optical proximity correction tool to obtain multiple initial line endpoints.

[0070] Concave corner graphics in the layout typically appear at gaps and corners. Through the processing described in this application, curved corner filling can be completed at the concave corners of various types of graphics in one step. (See...) Figure 13 The diagonal line fills the area. Based on this embodiment, only the diagonals are filled, without affecting the length of the longer side. Specifically, this is manifested as follows: Figure 13 The diagonal fill area coincides with the edge of the original layout on its long side. The filled pattern is transferred to the etched metal layer via the photoresist pattern after photolithography. Compared to the original 90-degree layout, the radius of the inscribed circle at the concave corner of the metal layer is increased, reducing stress concentration effects. Figure 14 The solid black line representing the photoresist topography (simulated topography of the curved layout) has a larger inscribed circle radius at the concave corner than the gray line representing the photoresist topography (simulated topography of the 90-degree concave corner layout). Since curved layouts do not require edge selection, they effectively avoid the risk of concave corners not being selected due to steps or arbitrary angles. For example, by filtering out endpoints corresponding to step positions in the initial line, it is possible to achieve selection of such... Figure 15 The step position processing shown can be directly implemented for angles other than 90°.

[0071] As verified, such as Figure 16 As shown in (a), an exemplary representation is presented at the concave corner, simultaneously adding an isosceles right triangle according to the prior art and performing curved processing according to the embodiments of this application. If an isosceles right triangle is added according to the prior art, the length of the right-angled side of the isosceles right triangle is not less than 0.8 micrometers, that is, the area of ​​the isosceles right triangle is not less than 0.32 square micrometers (the formula for calculating the area of ​​an isosceles right triangle is 1 / 2 * 0.8 * 0.8 square micrometers). If the curved processing method in the embodiments of this application is used, the length of the edge between the added curved pattern and the original pattern is also 0.8 micrometers, then the area of ​​the added curved pattern is smaller than the area of ​​the isosceles right triangle, which will... Figure 16The concave corner in (a) will be magnified as shown in (b). It is obvious that the area enclosed by the dashed box after the curve is processed is smaller than the area of ​​the gray area. In fact, the area enclosed by the curve is not smaller than the area of ​​the gray area. Taking the example where the area enclosed by the curved pattern equals the area of ​​the gray region, assuming the radius of the inscribed circle of the curved pattern is r, the area of ​​the curved pattern is r² - π / 4 * r², approximately 0.2146 r². Further calculations show that the length of contact between the curved pattern and the original pattern is 1.22 micrometers. Compared to adding an isosceles right triangle, the contact length between the curved pattern and the original pattern is greater than the length of the right-angled side of the isosceles right triangle (0.8 micrometers). Correspondingly, the curve of the enclosed area after the curved pattern must be closer to the concave corner to control the enclosed area to equal the area of ​​the gray region. In other words, the distance between the concave and convex corners (i.e., the Dc2c value) when adding the curved pattern must be greater than the distance when adding an isosceles right triangle. The relationship between these distances is shown in [the relevant section]. Figure 16 As shown in (c), it is clear that the curved processing method in the embodiments of this application has a lower risk of cracking. When the smooth length at the concave corner of the curved pattern is greater than 900 nanometers and the minimum gap size is greater than 2 micrometers, stress-induced cracks can be avoided for aluminum thicknesses of 20,000 to 40,000 angstroms.

[0072] For concave corner layouts, adding a curved layout with a minimum thickness of 1.22 micrometers can reduce stress at the concave corner, thus preventing crack formation. Adding a concave corner increases the area of ​​the top metal layer, causing a slight change in the equivalent resistance of this layer. If the product has high resistance requirements for the top metal layer, the slight change in resistance caused by adding a concave corner can be partially offset by removing the curved layout at the convex corner. Convex corner graphics typically appear at lines and their corners. A smooth layout file can be used to complete curved corner cutting at the convex corners of various types of graphics in one step. See [link to relevant documentation]. Figure 17 The specific length of the edge of the convex curve layout relative to the original layout can be obtained by referring to the ratio of the concave and convex corners of that layer or through group experiments. Generally, the edge length of the convex curve is between 0.4 and 2 times the length of the concave corner. Figure 17 This also indicates that convex and concave corners can be set separately. Convex corner graphics in a layout typically appear at lines and their corners. Through the embodiments of this application, curved corner cutting can be completed at the convex corners of various types of graphics in one step, and the processed result is as follows... Figure 17 As shown. In the actual implementation, the convex and concave corners can also be set separately. In actual manufacturing processes, Figure 17 The convex corner design can be applied to compressive stress design, reducing the stress concentration effect at the convex corner by smoothing the corner position. Since curved layouts do not require edge selection, the risk of convex corners not being selected due to steps or arbitrary angles at the corners can be effectively avoided.

[0073] This application proposes using curve processing of the layout to reduce stress concentration and prevent cracks. Conventional corner-filling methods add isosceles right triangles by selecting edges. If required by production departments or designers, the layout after curve processing can also be converted into traditional isosceles right triangles. For a specific conversion method using a concave corner as an example, please refer to [reference needed]. Figure 18 The process involves creating a rectangle by edging the curve-filled graphic, then using edge selection and distance filtering on the rectangle to convert it into a conventional right-angled triangle fill pattern. In other words, based on the smooth pattern obtained in this embodiment, an edge-filled rectangle (thick black box) is formed in the smooth pattern area. Then, the edge of the edge-filled rectangle is selected (thick black line), and finally, the endpoints of the selected edge are connected to achieve the commonly used concave corner filling process (thick black triangle).

[0074] Overall, based on the smoothing layout function in the optical proximity effect menu, the corners of the layout are rounded into curves. Layout smoothing can be independently set to five types: concave corners, convex corners, line endpoints, and gap endpoints. The smoothing parameter settings, including the smoothing length and endpoint edge smoothing length, can be independently set for different types of graphics. Small steps can also be ignored, effectively avoiding the inability to select the corresponding angle due to small steps near the corners of the layout. This application's embodiments propose design schemes for different types of graphics and processing methods for special graphics. The simulation of the photoresist morphology uses an optical proximity effect model that matches the actual process.

[0075] Please refer to Figure 19 This is a schematic diagram of the structure of a semiconductor device layout processing apparatus provided in an embodiment of this application, as shown below. Figure 19 As shown, the semiconductor device layout processing apparatus includes an endpoint processing unit 210 and a curve addition unit 220.

[0076] The endpoint processing unit 210 is used to screen the line endpoints of the metal interconnect layer of the layout to be processed based on the optical proximity effect correction tool to obtain multiple line endpoints to be processed. The closed area formed by the lines between the line endpoints to be processed is the metal coverage area of ​​the metal interconnect layer. The curve adding unit 220 is used to add curves according to the line endpoints to be processed to obtain the target layout. The curve connects two lines and is tangent to the corresponding two lines.

[0077] Based on the above embodiments, the curve adding unit 220 includes:

[0078] The magnification processing module is used to magnify the layout to be processed, thereby obtaining an enlarged layout.

[0079] The curve processing module is used to add curves to the enlarged layout based on the endpoints of the lines to be processed, so as to obtain an intermediate layout.

[0080] The scaling-down module is used to scale down the intermediate layout to obtain a target layout of the same size as the layout to be processed.

[0081] The endpoint processing unit 210 includes:

[0082] The endpoint extraction module is used to extract the line endpoints of the metal interconnect layers of the layout to be processed based on the optical proximity effect correction tool, so as to obtain multiple initial line endpoints;

[0083] The endpoint filtering module is used to filter out endpoints corresponding to step positions in the initial line endpoints based on the optical proximity effect correction tool, thereby obtaining multiple initial line endpoints.

[0084] The curve is a circular arc.

[0085] The radius of the arc is determined by the width of the gap between the lines.

[0086] The semiconductor device layout processing apparatus provided in this application embodiment is included in an electronic device and can be used to execute the curve processing method of the corresponding semiconductor device layout provided in the above embodiment, and has corresponding functions and beneficial effects.

[0087] Figure 20 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 20 As shown, the electronic device includes a processor 510 and a memory 520. In one possible form of the electronic device, it may also include an input device 530, an output device 540, and a communication device 550. The number of processors 510 in the electronic device can be one or more. Figure 20 Taking a processor 510 as an example; the processor 510, memory 520, input device 530, output device 540, and communication device 550 in the electronic device can be connected via a bus or other means. Figure 20 Taking the example of a connection between China and Israel via a bus.

[0088] The memory 520, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the curve-type processing method for the semiconductor device layout in the embodiments of this application. The processor 510 executes various functional applications and data processing of the electronic device by running the software programs, instructions, and modules stored in the memory 520, thereby implementing the aforementioned curve-type processing method for the semiconductor device layout.

[0089] The memory 520 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 520 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 520 may further include memory remotely located relative to the processor 510, which can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0090] Input device 530 can be used to receive network configuration information. Output device 540 may include electronic devices such as a display screen.

[0091] The aforementioned electronic device can be used to perform curve processing methods for any semiconductor device layout, possessing corresponding functions and beneficial effects.

[0092] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and equipment can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0093] Furthermore, embodiments of this application also provide a storage medium containing computer-executable instructions. When executed by a computer processor, the computer-executable instructions are used to perform relevant operations in the curve-type processing method of semiconductor device layout provided in any embodiment of this application, and have corresponding functions and beneficial effects.

[0094] Those skilled in the art will understand that embodiments of this application may be provided as methods, systems, or computer program products.

[0095] Therefore, this application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, produce implementations of the flowchart... Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0096] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory. Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0097] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0098] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0099] The above specific embodiments have further detailed the purpose, technical solution, and beneficial effects of this application. It should be understood that the above are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application for those skilled in the art.

Claims

1. A semiconductor device, characterized in that, Includes metal interconnect layers; The metal-covered area of ​​the metal interconnect layer is a closed area formed by connecting multiple boundary lines with different directions through transition lines. The transition line between two adjacent boundary lines is a curve determined based on the intersection relationship of the two boundary lines, and the opening direction of the curve and the intersection point of the two boundary lines are located on both sides of the curve. The layout of the semiconductor device is obtained by processing it in the following way: The optical proximity correction tool is used to extract the line endpoints of the metal interconnect layer of the layout to be processed, resulting in multiple initial line endpoints; Based on the optical proximity effect correction tool, the endpoints corresponding to the step positions in the initial line endpoints are filtered out to obtain multiple line endpoints to be processed. The closed area formed by the lines between the line endpoints to be processed is the metal coverage area of ​​the metal interconnect layer. A curve is added based on the endpoints of the lines to be processed to obtain the target layout. The curve connects two lines and is tangent to the corresponding two lines.

2. The semiconductor device according to claim 1, characterized in that, The transition line is either a circular arc or an elliptical arc.

3. The semiconductor device according to claim 2, characterized in that, The gap of the circular arc is greater than a preset first threshold value, and the diameter of the circular arc is equal to the first threshold value; the gap of the elliptical arc is less than or equal to the preset first threshold value, the length of the minor axis of the elliptical arc is equal to the width of the gap, and the length of the major axis of the elliptical arc is greater than the width of the gap.

4. The semiconductor device according to claim 1 or 2, characterized in that, The thickness of the metal interconnect layer is 20,000 to 40,000 angstroms, and the width of the wiring in the metal interconnect layer is greater than 2 micrometers.

5. The semiconductor device according to claim 1, characterized in that, The step of adding curves based on the endpoints of the lines to be processed includes: The layout to be processed is enlarged to obtain an enlarged layout; Based on the endpoints of the lines to be processed, curves are added to the enlarged layout to obtain an intermediate layout; The intermediate layout is scaled down to obtain a target layout of the same size as the layout to be processed.

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