Semiconductor device

Abstract

A semiconductor device includes: an active pattern on a substrate, the substrate including a cell array region and extension regions, the extension regions being located on opposite sides of the cell array region in a first direction; a bit line structure extending in a first direction on the active pattern; and spacer structures on sidewalls of the bit line structures in a second direction, the second direction being perpendicular to the first direction. A first thickness of a first portion of the spacer structure on the extension region of the substrate in the second direction is greater than a second thickness of a second portion of the spacer structure on the cell array region of the substrate in the second direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0058259, filed on May 2, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various exemplary embodiments of this disclosure relate to semiconductor devices. More specifically, the various exemplary embodiments of this disclosure relate to DRAM devices. Background Technology

[0004] DRAM devices may include bit line structures and spacers covering the sidewalls of the bit line structures. During the anisotropic etching process that forms the spacers, the relatively weaker ends of the bit line structures may be damaged. Summary of the Invention

[0005] Various example embodiments provide a semiconductor device with improved electrical characteristics.

[0006] According to various exemplary embodiments conceived in this invention, a semiconductor device includes: an active pattern on a substrate, the substrate including a cell array region and an extension region located on opposite sides of the cell array region along a first direction; a bit line structure extending on the active pattern along the first direction; and a spacer structure on a sidewall of the bit line structure along a second direction perpendicular to the first direction. A first thickness of a first portion of the spacer structure on the extension region of the substrate in the second direction is greater than a second thickness of a second portion of the spacer structure on the cell array region of the substrate in the second direction.

[0007] According to various exemplary embodiments conceived in this invention, a semiconductor device includes: an active pattern on a substrate, the substrate including a cell array region and an extension region located on opposite sides of the cell array region along a first direction; a bit line structure extending on the active pattern along the first direction; and a spacer structure on the sidewalls of the bit line structure along a second direction perpendicular to the first direction. A first portion of the spacer structure on the extension region of the substrate includes a first spacer, a second spacer, a third spacer, an insulating layer, and a fourth spacer sequentially stacked on the sidewalls of the bit line structure along the second direction, and a second portion of the spacer structure on the cell array region of the substrate includes a first spacer, a second spacer, a third spacer, and a fourth spacer sequentially stacked on the sidewalls of the bit line structure along the second direction.

[0008] According to various example embodiments of the inventive concept, a semiconductor device can include: an active pattern on a substrate, the substrate including a cell array region and an extension region, the extension region being located at opposite sides of the cell array region in a first direction, the active pattern being spaced apart from each other in the first direction and a second direction perpendicular to the first direction; and a bit line structure, and each bit line structure including: an extension portion extending in the first direction on the cell array region of the substrate and overlapping with a center portion of the active pattern arranged in the first direction; a pad portion on the extension region of the substrate, the pad portion contacting an end portion of the extension portion in the first direction; a spacer structure on a sidewall of the bit line structure, respectively; and a contact plug structure on an end portion of the active pattern, respectively. A width of the pad portion of each bit line structure in the second direction is greater than a width of the extension portion of each bit line structure in the second direction, and a first thickness of a first portion of each spacer structure on the extension region of the substrate in the second direction is greater than a second thickness of a second portion of each spacer structure on the cell array region of the substrate in the second direction.

[0009] In a method of manufacturing a semiconductor device according to various example embodiments of the inventive concept, a spacer layer can be formed on sidewalls of a bit line, a portion of the spacer layer on a relatively weak end portion of the bit line structure can be covered, and an anisotropic etching can be performed only on an exposed portion of the spacer layer. That is, an anisotropic etching process can not be performed on the spacer layer on the end portion of the bit line structure, and thus, the end portion of the bit line structure can not be damaged.

[0010] Alternatively, an insulating layer can be additionally formed on the end portion of the bit line structure before the anisotropic etching of the spacer layer. Accordingly, the end portion of the bit line structure can be protected by the additionally formed insulating layer during the anisotropic etching process of the spacer layer. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figures 1-64 is a plan view and cross-sectional views illustrating a method of manufacturing a semiconductor device according to various example embodiments.

[0012] Figures 65-92 is a plan view and cross-sectional views illustrating a method of manufacturing a semiconductor device according to various example embodiments. DETAILED DESCRIPTION

[0013] The above and other aspects and features of the semiconductor device and the method of manufacturing the same according to various example embodiments will be more apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the semiconductor device and the method of manufacturing the same according to various example embodiments. It is to be understood that the terms "first", "second", and / or "third" and the like, if any, used herein, are merely used to differentiate one element, component, region, layer and / or section from another element, component, region, layer and / or section, but do not limit the elements, components, regions, layers and / or sections. The first element, component, region, layer or section discussed below could be termed the second or third element, component, region, layer or section without departing from the teachings of the inventive concept.

[0014] Figures 1-64 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to various example embodiments.

[0015] Specifically, Figures 1-2 , Figure 5 , Figure 8 , Figure 15 , Figure 20 , Figure 33 , Figure 38 , Figure 43 , Figure 48 , Figure 52 , Figure 55 , Figure 59 and Figure 63 are plan views, Figure 3 , Figure 6 , Figure 9 , Figure 12 , Figure 16 , Figure 18 , Figure 21 , Figure 25 , Figure 29 , Figure 34 , Figure 39 , Figure 44 , Figure 49 , Figure 56 and Figure 60 are cross-sectional views taken along lines A-A' of the corresponding plan views, Figure 10 , Figure 13 , Figure 17 , Figure 19 , Figure 22 , Figure 26 , Figure 30 , Figure 35 , Figure 40 , Figure 45 , Figure 50 , Figure 53 , Figure 57 and Figure 61 are cross-sectional views taken along lines B-B' of the corresponding plan views, Figure 11 ,Figure 14 Figure 23 Figure 27 Figure 31 Figure 36 Figure 41 Figure 46 Figure 51 Figure 54 Figure 58 Figure 62 Figure 64 are cross-sectional views taken along lines C-C' of the corresponding plan views, Figure 24 Figure 28 Figure 32 Figure 37 Figure 42 Figure 47 are cross-sectional views taken along lines D-D' of the corresponding plan views, and Figure 4 Figure 7 are cross-sectional views taken along lines E-E' of the corresponding plan views.

[0016] Hereinafter, in the specification (not necessarily in the claims), two directions substantially parallel to the upper surface of the substrate 100 and substantially perpendicular to each other can be referred to as a first direction D1 and a second direction D2, respectively, and a direction substantially parallel to the upper surface of the substrate 100 and having an acute angle with respect to the first direction D1 and an obtuse angle with respect to the second direction D2 can be referred to as a third direction D3. A direction substantially perpendicular to the upper surface of the substrate 100 can be referred to as a vertical direction. Each of the first direction D1, the second direction D2, and the third direction D3 can not only represent the direction shown in the drawing but also represent a direction opposite to the direction.

[0017] Referring to Figures 1-4 The first active pattern 101 and the second active pattern 105 can be formed on the substrate 100 including the first region I, the second region II, and the third region III.

[0018] The substrate 100 can include silicon, germanium, silicon germanium, or a Group III-V compound semiconductor such as GaP, GaAs, GaSb, or the like. However, example embodiments are not limited thereto. In various example embodiments, the substrate 100 can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0019] ​​​​​​​​​​​​​​​​​The first region I of the substrate 100 can be a cell array region on which a memory cell is formed, and the second region II of the substrate 100 can be an extension region on which an upper contact plug that transmits an electrical signal to the memory cell is formed. The first region I and the second region II can collectively form a cell region. The third region III of the substrate 100 surrounding the first region I and the second region II of the substrate 100 can be a peripheral circuit region on which a peripheral circuit pattern for driving the memory cell is formed. In various example embodiments, the second region II of the substrate 100 can surround the first region I of the substrate 100, or can be formed on an opposite side in the second direction D2 of the first region I of the substrate 100. In various example embodiments, the third region III of the substrate 100 can surround the first region I and the second region II of the substrate 100.

[0020] The first active pattern 101 and the second active pattern 105 can be formed by removing an upper portion of the substrate 100 to form a recess structure. The first active pattern 101 can extend in the third direction D3 on the first region I and the second region II of the substrate 100, and a plurality of first active patterns 101 can be spaced apart from each other in each of the first direction D1 and the second direction D2 on the first region I and the second region II of the substrate 100. Some of the first active patterns 101 on the second region II of the substrate 100 can be dummy active patterns. In addition, a plurality of second active patterns 105 can be spaced apart from each other in each of the first direction D1 and the second direction D2 on the third region III of the substrate 100.

[0021] The recess structure can include a first recess 102, a second recess 104, and a third recess 106. The first recess 102 can be formed between the first active patterns 101 spaced apart from each other by a relatively small distance on the first region I and the second region II of the substrate 100, the second recess 104 can be formed between the first active patterns 101 spaced apart from each other by a relatively large distance on the first region I and the second region II of the substrate 100, and the third recess 106 can be formed on the third region III of the substrate 100 or between the second region II and the third region III of the substrate 100.

[0022] In various example embodiments, the width and / or depth of the third recess 106 can be greater than the width and / or depth of the second recess 104, and the width and / or depth of the second recess 104 can be greater than the width and / or depth of the first recess 102.

[0023] An isolation structure 110 can be formed to cover sidewalls of the first active pattern 101 and the second active pattern 105.

[0024] In various example embodiments, the isolation structure 110 can include a first isolation pattern 112, a second isolation pattern 114, and a third isolation pattern 116 sequentially stacked on the inner wall of the third recessed portion 106. However, the first isolation pattern 112 and the second isolation pattern 114 can be formed in the second recessed portion 104 having a width smaller than that of the third recessed portion 106, and the first isolation pattern 112 can be formed in the first recessed portion 102 having a width smaller than that of the second recessed portion 104.

[0025] Each of the first isolation pattern 112 and the third isolation pattern 116 can include an oxide, for example, silicon oxide, and the second isolation pattern 114 can include an insulating nitride, for example, silicon nitride.

[0026] Referring to Figures 5-7 An etching process can be performed on the first active pattern 101 on the first region I of the substrate 100 and the isolation structure 110 to form a fourth recessed portion 40.

[0027] In various example embodiments, during the etching process, the first active pattern 101 including a semiconductor material can be etched less than the isolation structure 110 including an insulating material due to etching selectivity. Accordingly, the fourth recessed portion 40 can have a recessed upper surface on the upper surface of the first active pattern 101.

[0028] A first gate insulating layer and a first conductive layer can be sequentially stacked on the inner wall of the fourth recessed portion 40 and the upper surfaces of the first active pattern 101 and the second active pattern 105 and the isolation structure 110, planarization can be performed on the first gate insulating layer and the first conductive layer until the upper surfaces of the first active pattern 101, the second active pattern 105, and the isolation structure 110 are exposed, and an upper portion of the first conductive layer can be removed through, for example, an etch-back process. The planarization process can include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0029] A first gate insulating pattern 120 can be formed on the inner wall of the fourth recessed portion 40 through the planarization process, and a first conductive pattern 140 can be formed on the first gate insulating pattern 120 through the etch-back process to fill a lower portion of the fourth recessed portion 40.

[0030] The second conductive pattern 150 can be formed on the first conductive pattern 140, the first gate mask layer can be formed on the second conductive pattern 150, the first and second active patterns 101 and 105, and the isolation structure 110 to fill the fourth recessed portion 40, and the first gate mask layer can be planarized until the upper surfaces of the first and second active patterns 101 and 105 and the isolation structure 110 are exposed, so that the first gate mask 160 can be formed to fill the upper portion of the fourth recessed portion 40. The first and second conductive patterns 140 and 150 can collectively form a gate electrode, and a first barrier pattern can also be formed between the first gate insulating pattern 120 and the first conductive pattern 140.

[0031] The first gate insulating pattern 120 can include an oxide, e.g., silicon oxide, the first barrier pattern can include a metal nitride, e.g., titanium nitride, tantalum nitride, or the like, the first conductive pattern 140 can include a metal, a metal nitride, a metal silicide, doped polysilicon, or the like, the second conductive pattern 150 can include doped polysilicon, and the first gate mask 160 can include a nitride, e.g., silicon nitride. However, example embodiments are not limited thereto.

[0032] The first gate insulating pattern 120, the first barrier pattern, the first conductive pattern 140, the second conductive pattern 150, and the first gate mask 160 in the fourth recessed portion 40 can collectively form a first gate structure 170. In various example embodiments, the first gate structure 170 can extend in the first direction D1 on the first region I of the substrate 100, and a plurality of first gate structures 170 can be spaced apart from each other in the second direction D2.

[0033] Referring to Figures 8-11 The insulating layer structure 210 can be formed on the first region I, the second region II, and the third region III of the substrate 100, and a portion of the insulating layer structure 210 on the third region III of the substrate 100 can be removed.

[0034] For example, a thermal oxidation process can be performed on the second active pattern 105 on the third region III of the substrate 100 to form a second gate insulating layer 220.

[0035] The insulating layer structure 210 can be patterned, and the first active pattern 101, the isolation structure 110, and the first gate mask 160 of the first gate structure 170 can be partially etched using the patterned insulating layer structure 210 as an etching mask to form a first opening 230.

[0036] In various example embodiments, the patterned insulating layer structure 210 can have a circular or elliptical shape in a plan view, and a plurality of the insulating layer structures 210 can be spaced apart from each other in the first direction D1 and the second direction D2 on the first region I of the substrate 100. Each of the insulating layer structures 210 can overlap opposite end portions of the first active pattern 101 in the third direction D3 in the vertical direction. In various example embodiments, the insulating layer structure 210 remaining on the second region II of the substrate 100 can have a rectangular shape in a plan view.

[0037] Referring to Figures 12-14 A third conductive layer 240, a second barrier layer 250, a fourth conductive layer 260, and a second mask layer 270 can be sequentially stacked on the upper surfaces of the insulating layer structure 210, the first active pattern 101 exposed by the first opening 230 on the first and second regions I and II of the substrate 100, the isolation structure 110, and the first gate structure 170, and on the second gate insulating layer 220 and the isolation structure 110 on the third region III of the substrate 100, which can collectively form a conductive structure layer. The third conductive layer 240 can fill the first opening 230.

[0038] The third conductive layer 240 can include doped polysilicon, the second barrier layer 250 can include metal nitride silicon, e.g., titanium silicon nitride, the fourth conductive layer 260 can include metal, e.g., tungsten, and the second mask layer 270 can include nitride, e.g., silicon nitride. However, example embodiments are not limited thereto.

[0039] Referring to Figures 15-17 The conductive structure layer can be patterned to form a second gate structure 330 on the third region III of the substrate 100.

[0040] The second gate structure 330 can include a second gate insulating pattern 280, a third conductive pattern 290, a second barrier pattern 300, a fourth conductive pattern 310, and a second gate mask 320 sequentially stacked in a vertical direction substantially perpendicular to an upper surface of the substrate 100, and the third conductive pattern 290, the second barrier pattern 300, and the fourth conductive pattern 310 can collectively form a second gate electrode.

[0041] The second gate structure 330 can at least partially overlap the second active pattern 105 in the vertical direction on the third region III of the substrate 100.

[0042] A portion of the conductive structure layer on an edge portion of the second region II of the substrate 100 adjacent to the third region III of the substrate 100 can also be removed, and thus the insulating layer structure 210 and the upper surfaces of the first active pattern 101, the isolation structure 110, and the first gate structure 170 exposed by the first opening 230 can also be partially exposed.

[0043] A first spacer structure can be formed on the sidewall of the second gate structure 330, and a second spacer structure can be formed on the sidewall of the conductive structure layer remaining on the first region I and the second region II of the substrate 100. The first spacer structure can include a first spacer 340 and a third spacer 350 stacked on the sidewall of the second gate structure 330 in a horizontal direction substantially parallel to the upper surface of the substrate 100, and the second spacer structure can include a second spacer 345 and a fourth spacer 355 stacked on the sidewall of the conductive structure layer in the horizontal direction.

[0044] The first spacer 340 and the second spacer 345 can be formed by forming a first spacer layer on the substrate 100 to cover the conductive structure layer and the second gate structure 330, and anisotropically etching the first spacer layer. The third spacer 350 and the fourth spacer 355 can be formed by forming a second spacer layer on the substrate 100 to cover the conductive structure layer, the second gate structure 330, and the first spacer 340 and the second spacer 345, and anisotropically etching the second spacer layer.

[0045] The first spacer 340 and the second spacer 345 can include a nitride, for example, silicon nitride, and the third spacer 350 and the fourth spacer 355 can include an oxide, for example, silicon oxide.

[0046] However, the structure of the first spacer structure and the second spacer structure can not be limited thereto, and each of the first spacer structure and the second spacer structure can include a single spacer or more than two spacers sequentially stacked.

[0047] A first etch stop layer 360 can be formed on the substrate 100 to cover the conductive structure layer, the second gate structure 330, the first spacer structure and the second spacer structure, and the isolation structure 110. The first etch stop layer 360 can include an insulating nitride, for example, silicon nitride.

[0048] Referring to Figure 18 and Figure 19A first insulating intermediate layer 370 of a sufficient height can be formed on the first etching stop layer 360, the first insulating intermediate layer 370 can be planarized until the upper surfaces of the second gate structure 330 and the portions of the first etching stop layer 360 on the conductive structure layer are exposed, and a capping layer 380 can be formed on the first insulating intermediate layer 370 and the first etching stop layer 360.

[0049] Accordingly, the first insulating intermediate layer 370 can fill spaces between the first spacer structures on the sidewalls of the second gate structure 330 and spaces between the first spacer structures on the sidewalls of the second gate structure 330 and the second spacer structures on the sidewalls of the conductive structure layer.

[0050] The first insulating intermediate layer 370 can include an oxide, for example, silicon oxide, and the capping layer 380 can include a nitride, for example, silicon nitride. However, example embodiments are not limited thereto.

[0051] Referring to Figures 20-24 Portions of the capping layer 380 on the first and second regions I and II of the substrate 100 can be etched to form a capping pattern 385, and the first etching stop layer 360, the second mask layer 270, the fourth conductive layer 260, the second barrier layer 250, and the third conductive layer 240 can be sequentially etched using the capping pattern 385 as an etching mask.

[0052] In various example embodiments, the capping pattern 385 can extend in the second direction D2 on the first and second regions I and II of the substrate 100, and a plurality of capping patterns 385 can be formed to be spaced apart from each other in the first direction D1. The capping layer 380 can remain on the third region III of the substrate 100 and a portion of the second region II of the substrate 100 adjacent thereto.

[0053] By the etching process, on the first and second regions I and II of the substrate 100, the fifth conductive pattern 245, the third barrier pattern 255, the sixth conductive pattern 265, the second mask 275, the first etching stop pattern 365, and the capping pattern 385 can be sequentially stacked on the first opening 230, and the third insulating pattern 205, the fifth conductive pattern 245, the third barrier pattern 255, the sixth conductive pattern 265, the second mask 275, the first etching stop pattern 365, and the capping pattern 385 can be sequentially stacked on the second insulating layer 190 of the insulating layer structure 210 outside the first opening 230.

[0054] Hereinafter, the sequentially stacked fifth conductive pattern 245, the third barrier pattern 255, the sixth conductive pattern 265, the second mask 275, the first etching stop pattern 365, and the capping pattern 385 can be referred to as a bit line structure 395.

[0055] In various example embodiments, the bit line structures 395 can extend in the second direction D2 over the first region I and the second region II of the substrate 100, and the plurality of bit line structures 395 can be spaced apart from each other in the first direction D1.

[0056] A first bit line structure of the bit line structures 395 can be formed to include a first extension portion and a first pad portion. The first extension portion can be formed to extend in the second direction D2 over the first region I of the substrate 100 and the second region II of the substrate 100 adjacent thereto, and the first pad portion can be formed to extend in the second direction D2 from a right end of the first extension portion in the second direction D2 over the second region II of the substrate 100 adjacent to the third region III of the substrate 100. A width of the first pad portion in the first direction D1 can be greater than a width of the first extension portion in the first direction D1.

[0057] A second bit line structure of the bit line structures 395 can be formed to include a second extension portion and a second pad portion. The second extension portion can be formed to extend in the second direction D2 over the first region I of the substrate 100 and the second region II of the substrate 100 adjacent thereto, and the second pad portion can be formed to extend in the second direction D2 from a left end of the first extension portion in the second direction D2 over the second region II of the substrate 100 adjacent to the third region III of the substrate 100. A width of the second pad portion in the first direction D1 can be greater than a width of the second extension portion in the first direction D1.

[0058] In various example embodiments, the first bit line structures and the second bit line structures can be alternately and repeatedly formed in the first direction D1.

[0059] In the drawing, a portion of the second region II of the substrate 100 in which the first pad portions of the first bit line structures are formed, and the first region I and the third region III of the substrate 100 adjacent thereto in the second direction D2 are shown.

[0060] In various example embodiments, the first pad portions of the first bit line structures can be aligned with each other in the first direction D1, and right ends of the second extension portions of the second bit line structures in the second direction D2 can be aligned with each other in the first direction D1. The right ends of the first extension portions of the first bit line structures in the second direction D2 can be closer to the third region III of the substrate 100 than the right ends of the second extension portions of the second bit line structures in the second direction D2. That is, on the portion of the second region II of the substrate 100 in which the first pad portions of the first bit line structures are formed, the first bit line structures can extend longer in the second direction D2 than the second bit line structures.

[0061] Similarly, the second pad portions of the second bit line structures can be aligned with each other in the first direction D1, and left ends of the first extension portions of the first bit line structures in the second direction D2 can be aligned with each other in the first direction D1. The left ends of the second extension portions of the second bit line structures in the second direction D2 can be closer to the third region III of the substrate 100 than the left ends of the first extension portions of the first bit line structures in the second direction D2. That is, the second bit line structures can extend longer than the first bit line structures in the second direction D2 on a portion of the second region II of the substrate 100 on which the second pad portions of the second bit line structures are formed.

[0062] The second gate structure 330, the first and second spacer structures, a portion of the insulating layer structure 210, and the isolation structure 110 can remain on the third region III of the substrate 100 and on a portion of the second region II of the substrate 100 adjacent thereto. Further, the cap layer 380 can remain on a portion of the first etch stop layer 360 on an upper surface of the second gate structure 330 and the first insulating intermediate layer 370.

[0063] Referring to Figures 25-28 The fifth spacer layer 400 and the sixth spacer layer 410 can be sequentially formed on the bit line structures 395 and the cap layer 380 on the substrate 100, and the fourth insulating layer 420 can be formed on the sixth spacer layer 410.

[0064] The fifth spacer layer 400 can further cover sidewalls of the third insulating pattern 205 between the second insulating layer 190 and the bit line structures 395, and the fourth insulating layer 420 can fill the first openings 230.

[0065] The fifth spacer layer 400 can include an insulating nitride, e.g., silicon nitride, the sixth spacer layer 410 can include an oxide, e.g., silicon oxide, or a carbonate, e.g., silicon carbonate, and the fourth insulating layer 420 can include an insulating nitride, e.g., silicon nitride. However, example embodiments are not limited thereto.

[0066] Referring to Figures 29-32 The fourth insulating layer 420 can be etched by an etching process.

[0067] In various example embodiments, the etching process can be performed by a wet etching process using an etching solution including phosphoric acid (H3PO4), and other portions of the fourth insulating layer 420 except for a portion thereof in the first openings 230 can be removed. Accordingly, a majority of an entire surface of the sixth spacer layer 410, i.e., an entire surface except for a portion in the first openings 230, can be exposed, and the portion of the fourth insulating layer 420 remaining in the first openings 230 can form a fourth insulating pattern 425.

[0068] In various example embodiments, the fourth insulating layer 420 can remain on the second and third regions II and III of the substrate 100 between the first pad portions of the first bit line structure adjacent to each other in the first direction D1. The portions of the fourth insulating layer 420 remaining between the first pad portions of the first bit line structure can be referred to as a fifth insulating pattern 427.

[0069] Referring to Figures 33-37 A seventh spacer layer 430 can be formed on the exposed surface of the sixth spacer layer 410, the fourth insulating pattern 425 in the first opening 230, and the fifth insulating pattern 427.

[0070] The seventh spacer layer 430 can include an oxide, for example, silicon oxide. In various example embodiments, the seventh spacer layer 430 and the portions of the sixth spacer layer 410 that can contact the seventh spacer layer 430 can merge with each other and can not be distinguished from each other.

[0071] A photoresist structure 10 can be formed on the second and third regions II and III of the substrate 100. Accordingly, the portions of the seventh spacer layer 430 on the second and third regions II and III of the substrate 100 can be covered, except for the portions of the seventh spacer layer 430 on the first region I of the substrate 100.

[0072] In various example embodiments, the photoresist structure 10 can include a mold layer, an anti-reflection layer, and a photoresist pattern sequentially stacked on the second and third regions II and III of the substrate 100. The mold layer can include, but is not limited to, for example, a spin-on hard mask (SOH), an amorphous carbon layer (ACL), etc., the anti-reflection layer can include, for example, silicon oxynitride, and the photoresist pattern can include, for example, a photoresist material whose chemical properties can change in response to light.

[0073] Referring to Figures 38-42 The seventh spacer layer 430 can be anisotropically etched.

[0074] Accordingly, the seventh spacer layer 430 can be formed on the surface of the sixth spacer layer 410 and the upper surface of the fourth insulating pattern 425 to cover the sidewalls of the extended portions of the bit line structure 395.

[0075] A dry etching process can be performed to form a second opening 440 exposing the upper surface of the first active pattern 101. The upper surface of the isolation structure 110 and the upper surface of the first gate mask 160 can also be exposed through the second opening 440.

[0076] Through the dry etching process, portions of the fifth spacer layer 400 and the sixth spacer layer 410 on the cap pattern 385 and the second insulating layer 190 can be removed, and thus the fifth spacer 405 and the sixth spacer 415 sequentially stacked on the sidewall of the bit line structure 395 can be formed. The fifth spacer 405 can cover the sidewall of the bit line structure 395.

[0077] Further, during the dry etching process, the first insulating layer 180 and the second insulating layer 190 can be partially removed, so that the first insulating pattern 185 and the second insulating pattern 195 can be left under the bit line structure 395. The first insulating pattern 185, the second insulating pattern 195, and the third insulating pattern 205 sequentially stacked under the bit line structure 395 can collectively form an insulating pattern structure 215.

[0078] Portions of the seventh spacer layer 430 on the second region II and the third region III of the substrate 100 can be covered by the photoresist structure 10, and thus can not be exposed during the anisotropic etching process. Accordingly, the first thickness T1 of the seventh spacer layer 430 can be greater than the second thickness T2 of the seventh spacer 435 exposed to the anisotropic etching process.

[0079] Similarly, on the second region II and the third region III of the substrate 100, portions of the first insulating layer 180 and the second insulating layer 190 and the fifth spacer layer 400 and the sixth spacer layer 410 under the seventh spacer layer 430 can be covered by the photoresist structure 10, thereby remaining without being exposed to the anisotropic etching process. That is, on the second region II of the substrate 100, the first insulating layer 180 and the second insulating layer 190, and the fifth spacer layer 400, the sixth spacer layer 410, and the seventh spacer layer 430 can be sequentially stacked in a vertical direction on the upper surface of the first active pattern 101 and the isolation structure 110.

[0080] Referring to Figures 43-47 The photoresist structure 10 can be removed, thereby exposing the seventh spacer layer 430 on the second region II and the third region III of the substrate 100.

[0081] In various example embodiments, the photoresist structure 10 can be removed by performing, for example, an ashing process.

[0082] Subsequently, an eighth spacer layer can be formed on the upper surface of the cap pattern 385, portions of the upper surfaces of the fifth and sixth spacers 405 and 415, the outer sidewall of the seventh spacer 435, portions of the upper surface of the fourth insulating pattern 425, and the upper surfaces of the first active pattern 101, the isolation structure 110, and the first gate mask 160 exposed by the second opening 440 on the first region I of the substrate 100, and the upper surfaces of the fifth insulating pattern 427 and the surface of the seventh spacer layer 430 on the second and third regions II and III of the substrate 100.

[0083] Subsequently, an eighth spacer layer can be formed on the upper surface of the cap pattern 385, portions of the upper surfaces of the fifth and sixth spacers 405 and 415, the outer sidewall of the seventh spacer 435, portions of the upper surface of the fourth insulating pattern 425, and the upper surfaces of the first active pattern 101, the isolation structure 110, and the first gate mask 160 exposed by the second opening 440 on the first region I of the substrate 100, and the upper surfaces of the fifth insulating pattern 427 and the surface of the seventh spacer layer 430 on the second and third regions II and III of the substrate 100.

[0084] In various example embodiments, on the second region II of the substrate 100, a width in the first direction D1 between the first pad portions of the first bit line structure adjacent to each other in the first direction D1 can be smaller than a width in the first direction D1 between the first extension portion of the first bit line structure and the second extension portion of the second bit line structure adjacent to each other in the first direction D1. Accordingly, the ninth spacers 457 at the opposite sidewalls of the first pad portions of the first bit line structure adjacent to each other in the first direction D1 can merge with each other. That is, the ninth spacers 457 can be formed to fill the space between the first pad portions of the first bit line structure adjacent to each other in the first direction D1.

[0085] The fifth, sixth, seventh, and eighth spacers 405, 415, 435, and 455 sequentially stacked in the horizontal direction from the sidewall of the bit line structure 395 on the first region I of the substrate 100 can be referred to as a third spacer structure 465, and the fifth, sixth, seventh, and ninth spacers 400, 410, 430, and 457 sequentially stacked in the horizontal direction from the sidewall of the bit line structure 395 on the second region II of the substrate 100 can be referred to as a fourth spacer structure 467.

[0086] As shown above, a first thickness T1 of the seventh spacer layer 430 on the sidewall of the bit line structure 395 at the second region II of the substrate 100 can be greater than a second thickness T2 of the seventh spacer 435 on the sidewall of the bit line structure 395 at the first region I of the substrate 100. Accordingly, a third thickness of the fourth spacer structure 467 on the sidewall of the bit line structure 395 at the second region II of the substrate 100 in a horizontal direction can be greater than a fourth thickness of the third spacer structure 465 on the sidewall of the bit line structure 395 at the first region I of the substrate 100 in the horizontal direction.

[0087] Referring to Figures 48-51 A lower contact plug layer can be formed to fill the second openings 440 on the first and second regions I and II of the substrate 100, and the lower contact plug layer, the cap layer 380, the cap pattern 385, and upper portions of the third and fourth spacer structures 465 and 467 can be planarized until upper surfaces of the cap pattern 385 are exposed to form the first contact plugs 475.

[0088] The first contact plugs 475 can extend in the second direction D2 between the bit line structures 395 adjacent to each other in the first direction D1 on the first and second regions I and II of the substrate 100, and a plurality of the first contact plugs 475 can be spaced apart from each other in the first direction D1. Each of the first contact plugs 475 can contact an upper surface of an end portion of the first active pattern 101 in the third direction D3 extending in the third direction D3 on the first region I of the substrate 100.

[0089] In contrast, on the second region II of the substrate 100, each of the first contact plugs 475 can overlap the end portion of the first active pattern 101 in the third direction D3 in the vertical direction, but not contact due to the first and second insulating layers 180 and 190 and the fifth, sixth, and seventh spacer layers 400, 410, and 430. Accordingly, the first active pattern 101 on the second region II of the substrate 100 can be a dummy active pattern as shown above.

[0090] In various example embodiments, the first contact plugs 475 extending in the second direction D2 along the sidewall of the second bit line structure in the first direction D1 can meet the right end of the second bit line structure in the second direction D2 and merge with each other.

[0091] In various example embodiments, the ninth spacers 457 can fill spaces between the first pad portions of the first bit line structures adjacent to each other in the first direction D1, and thus, the first contact plugs 475 can not be formed between the first pad portions of the first bit line structures.

[0092] Referring to Figures 52-54An etch mask with third openings can be formed on the cap layer 380, the bit line structure 395, and the first contact plug 475, each of the third openings can extend along the first direction D1 and spaced apart from each other in the second direction D2, and an etching process can be performed on the first contact plug 475 using the etch mask to form the fourth openings 445.

[0093] In various example embodiments, on the first region I of the substrate 100, the third openings can overlap the first gate structure 170 in the vertical direction, and the fourth openings 445 can expose the upper surface of the first gate mask 160 of the first gate structure 170. On the second region II of the substrate 100, the third openings can be spaced apart from each other in the second direction D2 at the same interval as in the first region I of the substrate 100, and the fourth openings 445 can expose the upper surface of the seventh spacer layer 430 on the second region II of the substrate 100. With the formation of the fourth openings 445, the first contact plug 475 extending along the second direction D2 can be divided into a plurality of portions spaced apart from each other in the second direction D2.

[0094] After the etch mask is removed, a fence pattern 480 can be formed to fill the fourth openings 445. The plurality of fence patterns 480 can be spaced apart from each other in the second direction D2 between the bit line structure 395 on the first region I and the second region II of the substrate 100. The fence pattern 480 can include insulating nitride, for example, silicon nitride.

[0095] As shown above, the third thickness of the fourth spacer structure 467 on the second region II of the substrate 100 can be greater than the fourth thickness of the third spacer structure 465 on the first region I of the substrate 100. Accordingly, the first width of the first contact plug 475 in the first direction D1 on the second region II of the substrate 100 can be less than the second width of the first contact plug 475 in the first direction D1 on the first region I of the substrate 100. Similarly, the third width of the fence pattern 480 in the first direction D1 on the second region II of the substrate 100 can be less than the fourth width of the fence pattern 480 in the first direction D1 on the first region I of the substrate 100.

[0096] In various example embodiments, the fifth width of the first contact plug 475 in the first direction D1 between the right end of the first extended portion of the first bit line structure in the second direction D2 and the right end of the second extended portion of the second bit line structure in the second direction D2 can be greater than the first width or the second width of the first contact plug 475 in the first direction D1 to the left of the right end of the second extended portion of the second bit line structure in the second direction D2.

[0097] As shown above, the first contact plug 475 and the fence pattern 480 can be alternately and repeatedly arranged along the second direction D2, and can be formed by forming a lower contact plug layer extending along the second direction D2 between the bit line structures 395, planarizing the lower contact plug layer to form the first contact plug 475, forming fourth openings 445 spaced apart from each other in the second direction D2 through the first contact plug 475, and filling the fourth openings 445 by the fence pattern 480, although example embodiments are not limited thereto.

[0098] Alternatively, the first contact plug 475 and the fence pattern 480 can be alternately and repeatedly arranged along the second direction D2, and can be formed by forming a fence layer extending along the second direction D2 between the bit line structures 395, forming fifth openings spaced apart from each other in the second direction D2 through the fence layer to divide the fence layer into the fence pattern 480, forming a lower contact plug layer on the fence layer to fill the fifth openings, and planarizing the lower contact plug layer to form the first contact plug 475.

[0099] Alternatively, the first contact plug 475 and the fence pattern 480 can be alternately and repeatedly arranged along the second direction D2, and can be formed by forming a sacrificial layer including an oxide (e.g., silicon oxide) and extending along the second direction D2 between the bit line structures 395, forming the fence pattern 480 spaced apart from each other in the second direction D2 through the sacrificial layer, removing the sacrificial layer to form sixth openings, forming a lower contact plug layer to fill the sixth openings, and planarizing the lower contact plug layer to form the first contact plug 475.

[0100] Thereafter, an upper portion of the first contact plug 475 can be removed to expose upper portions of the third spacer structure 465 and the fourth spacer structure 467 on sidewalls of the bit line structure 395.

[0101] An ohmic contact pattern 500 can be formed on the exposed upper surface of the first contact plug 475. In various example embodiments, the ohmic contact pattern 500 can be formed by forming a first metal layer on the cap pattern 385, the cap layer 380, the third spacer structure 465 and the fourth spacer structure 467, the fence pattern 480, and the first contact plug 475, heat-treating the first metal layer, and removing unreacted portions of the first metal layer. The ohmic contact pattern 500 can include a metal silicide, e.g., cobalt silicide, nickel silicide, titanium silicide, etc. However, example embodiments are not limited thereto.

[0102] Referring to Figures 55-58A seventh opening 520 can be formed through a portion of the cap pattern 385 on a portion of the second region II of the substrate 100 adjacent to the third region III of the substrate 100, and the first etching stop layer 360, the second mask 275, the sixth conductive pattern 265, and the third barrier pattern 255 to expose the fifth conductive pattern 245.

[0103] In various example embodiments, a plurality of the seventh openings 520 can be spaced apart from each other in the first direction D1 on the second region II of the substrate 100.

[0104] A fourth barrier layer can be formed on the cap pattern 385, the third spacer structure 465, the fence pattern 480, and the ohmic contact pattern 500 on the first region I of the substrate 100, and on the cap layer 380, the cap pattern 385, the fourth spacer structure 467, sidewalls of the seventh openings 520, and the fifth conductive pattern 245, the third barrier pattern 255, the sixth conductive pattern 265, and the second mask 275 exposed by the seventh openings 520 on the second region II and the third region III of the substrate 100. A second metal layer can be formed on the fourth barrier layer to fill spaces between the bit line structures 395, between the bit line structures 395 and the seventh openings 520.

[0105] Subsequently, a planarization process can be performed on the second metal layer, the fourth barrier layer, the cap pattern 385, the third spacer structure 465, the fence pattern 480, and the first etching stop pattern 365 on the first region I of the substrate 100, and on the cap layer 380, the cap pattern 385, the fourth spacer structure 467, the fence pattern 480, and the first etching stop pattern 365 on the second region II and the third region III of the substrate 100 until an upper surface of the second mask 275 is exposed.

[0106] Through the planarization process, the second metal layer and the fourth barrier layer can be transformed into a first metal pattern 545 on the first region I of the substrate 100 and the second region II of the substrate 100 adjacent thereto, respectively, and a fourth barrier pattern 535 covering a lower surface of the first metal pattern 545. The first metal pattern 545 and the fourth barrier pattern 535 can collectively form a second contact plug 549. In various example embodiments, a plurality of the second contact plugs 549 can be spaced apart from each other in the first direction D1 and the second direction D2 on the first region I of the substrate 100 and the second region II of the substrate 100 adjacent thereto, and can be arranged in a lattice pattern in a plan view.

[0107] The first contact plug 475, the ohmic contact pattern 500, and the second contact plug 549 on the first region I of the substrate 100 and the second region II adjacent thereto can collectively form a contact plug structure.

[0108] Corresponding to the first contact plug 475, a first width of the contact plug structure on the second region II of the substrate 100 in the first direction D1 can be smaller than a second width of the contact plug structure on the first region I of the substrate 100 in the first direction D1.

[0109] In various example embodiments, corresponding to the first contact plug 475, a fifth width of the contact plug structure between the right end of the first extension portion of the first bit line structure in the second direction D2 and the right end of the second extension portion of the second bit line structure in the second direction D2 in the first direction D1 can be greater than the first width or the second width of the contact plug structure left of the right end of the second extension portion of the second bit line structure in the second direction D2 in the first direction D1.

[0110] By the planarization process, the second metal layer and the fourth barrier layer can be transformed into a second metal pattern 560 within the seventh opening 520 and a fifth barrier pattern 550 covering a lower surface of the second metal pattern 560, respectively. The second metal pattern 560 and the fifth barrier pattern 550 can collectively form an upper contact plug 570. In various example embodiments, a plurality of upper contact plugs 570 can be spaced apart from each other in the first direction D1 on the second region II of the substrate 100 adjacent to the third region III of the substrate 100. The upper contact plug 570 can contact the fifth conductive pattern 245, the third barrier pattern 255, and the sixth conductive pattern 265, and accordingly, can apply an electrical signal to the bit line structure 395.

[0111] Referring to Figures 59-62 A fifth conductive layer can be formed on the cap pattern 385, the third spacer structure 465, the fence pattern 480, and the contact plug structure on the first region I of the substrate 100, and on the cap layer 380, the cap pattern 385, the fourth spacer structure 467, the fence pattern 480, the contact plug structure, and the upper contact plug 570 on the second region II and the third region III of the substrate 100. The fifth conductive layer can include a metal (e.g., tungsten) or a metal nitride (e.g., titanium nitride). However, example embodiments are not limited thereto.

[0112] Subsequently, the fifth conductive layer can be patterned, and a third contact plug 580 and an upper wiring 585 can be formed. The third contact plug 580 can be formed on and electrically connected to the contact plug structure, and the upper wiring 585 can be formed on and electrically connected to the upper contact plug 570.

[0113] In various example embodiments, a plurality of third contact plugs 580 can be spaced apart from each other in the first direction D1 and the second direction D2 on the first region I of the substrate 100, and can be arranged in a honeycomb pattern in a plan view. The third contact plug 580 can have a circular, elliptical, or polygonal shape in the plan view.

[0114] In various example embodiments, the plurality of upper wiring lines 585 can be spaced apart from each other in the first direction D1 on the second region II of the substrate 100.

[0115] The second insulating intermediate layer 590 can be formed to cover sidewalls of the third contact plug 580 and the upper wiring line 585. The second insulating intermediate layer 590 can include an oxide (e.g., silicon oxide) or an insulating nitride (e.g., silicon nitride). However, example embodiments are not limited thereto.

[0116] Referring to Figure 63 and Figure 64 The capacitor 670 can be formed to contact the upper surface of the third contact plug 580 on the first region I of the substrate 100.

[0117] Specifically, the second etching stop layer 630 and a molding layer can be sequentially formed on the third contact plug 580 and the second insulating intermediate layer 590, and the second etching stop layer 630 and the molding layer can be partially etched to form a ninth opening partially exposing the upper surface of the third contact plug 580. The second etching stop layer 630 can include an insulating nitride (e.g., silicon nitride). However, example embodiments are not limited thereto.

[0118] A lower electrode layer can be formed on the exposed upper surface of the third contact plug 580 and the molding layer to fill the ninth opening, and the lower electrode layer can be planarized until the upper surface of the molding layer is exposed to separate the lower electrode layer into nodes. Thereafter, the molding layer can be removed by, for example, a wet etching process. Accordingly, the lower electrode 640 having a column shape can be formed on the exposed upper surface of the third contact plug 580. Alternatively, the lower electrode 640 can be formed to have a cylindrical shape. The lower electrode can include, for example, a metal, a metal nitride, a metal silicide, doped polysilicon, etc. However, example embodiments are not limited thereto.

[0119] A dielectric layer 650 and an upper electrode 660 can be sequentially formed on a surface of the lower electrode 640 and an upper surface of the second etching stop layer 630 to form a capacitor 670 including the lower electrode 640, the dielectric layer 650, and the upper electrode 660 on the first region I of the substrate 100.

[0120] The dielectric layer 650 can include, for example, a metal oxide, and the upper electrode 660 can include, for example, a metal, a metal nitride, a metal silicide, doped polysilicon, etc. However, example embodiments are not limited thereto.

[0121] A contact plug and an upper wiring line can also be formed on the substrate 100 to be electrically connected to the first gate structure 170 and the second gate structure 330, the bit line structure 395, the capacitor 670, etc., thereby completing the manufacture of the semiconductor device.

[0122] As shown above, the seventh spacer layer 430 can be formed on the bit line structure 395 on the first region I and the second region II of the substrate 100, the photoresist structure 10 can be formed on the seventh spacer layer 430 on the second region II and the third region III of the substrate 100, and an anisotropic etching process can be performed only on the exposed portion of the seventh spacer layer 430 on the first region I of the substrate 100 to form the seventh spacer 435.

[0123] The anisotropic etching process can not be performed on the portion of the seventh spacer layer 430 on the sidewall of the bit line structure 395 on the second region II of the substrate 100, and thus the seventh spacer layer 430 can not be damaged. Accordingly, damage to the bit line structure 395 can be prevented or reduced by the intact seventh spacer layer 430, so that the semiconductor device can have improved electrical characteristics.

[0124] Figures 65-92 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to various example embodiments. Specifically, Figure 65 , Figure 70 and Figure 75 are plan views, Figure 66 , Figure 71 , Figure 76 , Figure 79 , Figure 82 , Figure 85 and Figure 89 are cross-sectional views taken along lines A-A' of the corresponding plan views, Figure 67 , Figure 72 , Figure 77 , Figure 80 , Figure 83 , Figure 86 and Figure 90 are cross-sectional views taken along lines B-B' of the corresponding plan views, Figure 68 , Figure 73 , Figure 78 , Figure 81 , Figure 87 and Figure 91 are cross-sectional views taken along lines C-C' of the corresponding plan views, and Figure 69 , Figure 74 , Figure 84 , Figure 88 and Figure 92 are cross-sectional views taken along lines D-D' of the corresponding plan views. The method can include substantially the same or similar processes as those shown with reference to Figures 1-64 , and thus a repeated explanation thereof is omitted here.

[0125] Referring to Figures 65-69 , the same or similar processes as those shown with reference to Figures 1-28The processes shown are substantially the same or similar. Subsequently, a sacrificial spacer layer 900 may be formed on the fourth insulating layer 420. The sacrificial spacer layer 900 may include oxides, such as silicon oxide.

[0126] Reference Figures 70-74 It can be executed and referenced. Figures 33-37 The processes shown are basically the same or similar.

[0127] That is, photoresist structures 10 can be formed on the second region II and the third region III of the substrate 100. Accordingly, except for a portion of the sacrificial spacer layer 900 on the first region I of the substrate 100, portions of the sacrificial spacer layer 900 on the second region II and the third region III of the substrate 100 can be covered by the photoresist structures 10.

[0128] Reference Figures 75-78 This can remove the exposed portion of the sacrificial spacer layer 900 on the first region I of the substrate 100.

[0129] In various example embodiments, the sacrificial spacer layer 900 can be removed by a wet etching process using an etching solution comprising hydrofluoric acid (HF).

[0130] A portion of the sacrificial spacer layer 900 on the second region II and the third region III of the substrate 100 can be covered by the photoresist structure 10 and therefore not exposed to the wet etching process. Accordingly, the sacrificial spacer layer 900 can remain on the second region II and the third region III of the substrate 100 without being removed.

[0131] Reference Figures 79-81 It can be executed and referenced. Figures 43-47 The processes shown are basically the same or similar.

[0132] That is, the photoresist structure 10 can be removed, thereby exposing the sacrificial spacer layer 900 on the second region II and the third region III of the substrate 100. In various example embodiments, the photoresist structure 10 can be removed by performing an ashing process and / or a stripping process.

[0133] Executable and referenced Figures 29-32 The processes shown are substantially the same or similar. Accordingly, most of the entire surface of the sixth spacer layer 410 (i.e., the entire surface except for the portion in the first opening 230) can be exposed, and the portion of the fourth insulating layer 420 retained in the first opening 230 can form the fourth insulating pattern 425.

[0134] With reference Figures 29-32The process is different, and the portions of the fourth insulating layer 420 formed on the second region II and the third region III of the substrate 100 covered by the sacrificial spacer layer 900 can be retained instead of being removed.

[0135] Reference Figures 82-84 The portion of the sacrificial spacer layer 900 on the second region II and the third region III of the substrate 100 can be removed, and the remaining portion of the fourth insulating layer 420 on the second region II and the third region III can be exposed accordingly.

[0136] In various example embodiments, the sacrificial spacer layer 900 can be removed by a wet etching process using an etching solution comprising hydrofluoric acid (HF).

[0137] Reference Figures 85-88 It can be executed and referenced. Figures 33-42 The processes shown are basically the same or similar.

[0138] A seventh spacer layer 430 can be formed on the surface of the sixth spacer layer 410 on the first region I of the substrate 100, on the upper surface of the fourth insulating pattern 425, and on the upper surface of the fourth insulating pattern 425 on the second region II and the third region III of the substrate 100, and the seventh spacer layer 430 can be anisotropically etched. Accordingly, a seventh spacer 435 can be formed on the surface of the sixth spacer layer 410 and on the upper surface of the fourth insulating layer 420, at the sidewall of the bit line structure 395 on the first region I of the substrate 100.

[0139] With reference Figures 33-42 Different processes are shown, and the photoresist structure 10 may not be formed on the second region II and the third region III of the substrate 100. Accordingly, the seventh spacer layer 430 can be transformed into a tenth spacer 437 covering the sidewalls of the bit line structure 395 on the second region II and the third region III of the substrate 100 by an anisotropic etching process.

[0140] Reference Figures 89-92 It can be executed and referenced. Figures 43-47 Figures 43-47 The processes shown are basically the same or similar.

[0141] That is, an eighth spacer 455 can be formed covering the outer wall of the seventh spacer 435 formed from the sidewall of the bit line structure 395 on the first region I of the substrate 100 in the first direction D1, and a ninth spacer 457 can be formed covering the outer wall of the tenth spacer 437 formed from the sidewall of the bit line structure 395 on the second region II of the substrate 100.

[0142] The fifth spacer layer 400 and the sixth spacer layer 410, the fourth insulating layer 420, and the tenth spacer 437 and the ninth spacer 457 sequentially stacked in the horizontal direction from the sidewall of the bit line structure 395 on the second region II of the substrate 100 can collectively form a fifth spacer structure 477.

[0143] In various example embodiments, the fifth spacer structure 477 can further include the fourth insulating layer 420 compared to the third spacer structure 465 having a total of four layers (i.e., the fifth spacer 405, the sixth spacer 415, the seventh spacer layer 435, and the eighth spacer 455), thereby having a total of five layers.

[0144] In the method of forming a semiconductor device, the fourth insulating layer 420 can be formed on the sidewall of the bit line structure 395, the photoresist structure 10 can be formed to cover the second region II and the third region III of the substrate 100, and the fourth insulating layer 420 on the first region I of the substrate 100 can be etched to form the fourth insulating pattern 425. The fourth insulating layer 420 can remain on the second region II and the third region III of the substrate 100. Accordingly, the remaining portion of the fourth insulating layer 420 can protect the right end of the second bit line structure during the anisotropic etching process of the seventh spacer layer 430.

[0145] While the inventive concept has been shown and described with reference to various example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A semiconductor device comprising: active patterns on a substrate, the substrate including a cell array region and an extension region, the extension region being located on opposite sides of the cell array region along a first direction; bit line structures extending on the active patterns along the first direction; and spacer structures on sidewalls of the bit line structures along a second direction, the second direction being perpendicular to the first direction, and wherein a first thickness of a first portion of the spacer structures on the extension region of the substrate in the second direction is greater than a second thickness of a second portion of the spacer structures on the cell array region of the substrate in the second direction. the spacer structures include a first spacer, a second spacer, a third spacer, and a fourth spacer sequentially stacked on the sidewalls of the bit line structures along the second direction.

2. The semiconductor device of claim 1, wherein, a third thickness of the third spacer in the second direction in the first portion of the spacer structures is greater than a fourth thickness of the third spacer in the second direction in the second portion of the spacer structures.

3. The semiconductor device of claim 2, wherein, each of the first spacer and the fourth spacer includes insulating nitride, and each of the second spacer and the third spacer includes oxide.

4. The semiconductor device of claim 2, wherein, 5. The semiconductor device according to claim 2, further comprising: insulating patterns on outer sidewalls of the second spacer, and wherein the third spacer and the fourth spacer are on the insulating patterns. the insulating patterns include insulating nitride.

6. The semiconductor device of claim 5, wherein, the spacer structures include:

7. The semiconductor device of claim 1, wherein, a first spacer, a second spacer, and a third spacer sequentially stacked on the sidewalls of the bit line structures along the second direction, and each of the first spacer and the third spacer includes insulating nitride, and the second spacer includes oxide.

8. The semiconductor device according to claim 1, wherein a plurality of active patterns are spaced apart from each other in the first direction and the second direction, contact plug structures respectively contact end portions of the active patterns, and a width of each of the contact plug structures along the second direction on the extension region of the substrate is less than a width of each of the contact plug structures along the second direction on the cell array region of the substrate.

9. A semiconductor device comprising: active patterns on a substrate, the substrate including a cell array region and an extension region, the extension region being located on opposite sides of the cell array region along a first direction; bit line structures extending on the active patterns along the first direction; and spacer structures on sidewalls of the bit line structures along a second direction, the second direction being perpendicular to the first direction, and wherein a first portion of the spacer structures on the extension region of the substrate includes a first spacer, a second spacer, a third spacer, an insulating layer, and a fourth spacer sequentially stacked on the sidewalls of the bit line structures along the second direction, and ​ ​ A second portion of the spacer structure on the cell array region of the substrate includes the first spacer, the second spacer, the third spacer, and the fourth spacer sequentially stacked on a sidewall of the bit line structure along the second direction.

10. The semiconductor device according to claim 9, further comprising: an insulating pattern on a lower outer sidewall of the second spacer on the cell array region of the substrate, wherein the third spacer and the fourth spacer are on the insulating pattern, and the insulating layer and the insulating pattern include the same material as each other.

11. The semiconductor device of claim 10, wherein, Each of the first spacer and the fourth spacer, the insulating layer, and the insulating pattern includes insulating nitride, and each of the second spacer and the third spacer includes oxide.

12. A semiconductor device, comprising: active patterns on a substrate, the substrate including a cell array region and an extension region located on opposite sides of the cell array region along a first direction, the active patterns being spaced apart from each other in the first direction and a second direction perpendicular to the first direction; bit line structures each including: an extension portion extending along the first direction on the cell array region of the substrate and overlapping a center portion of the active pattern arranged along the first direction, and a pad portion on the extension region of the substrate, the pad portion contacting an end portion of the extension portion along the first direction, spacer structures on sidewalls of the bit line structures, respectively, and contact plug structures on end portions of the active patterns, respectively, wherein a width of the pad portion of each of the bit line structures in the second direction is greater than a width of the extension portion of each of the bit line structures in the second direction, and a first thickness of a first portion of each of the spacer structures on the extension region of the substrate in the second direction is greater than a second thickness of a second portion of each of the spacer structures on the cell array region of the substrate in the second direction.

13. The semiconductor device according to claim 12, wherein a first end and a second end of the extension portion of each of the bit line structures are located on opposite sides of the extension portion along the first direction, the pad portion of a first bit line structure of the bit line structures contacts the first end of the extension portion, and the pad portion of a second bit line structure of the bit line structures contacts the second end of the extension portion, and wherein the first bit line structure and the second bit line structure of the bit line structures are alternately arranged along the second direction.

14. The semiconductor device of claim 12, wherein, a width of each of the contact plug structures along the second direction on the cell array region of the substrate is greater than a width of each of the contact plug structures along the second direction on the extension region of the substrate.

15. The semiconductor device of claim 12, wherein, Each of the spacer structures includes a first spacer, a second spacer, a third spacer, and a fourth spacer sequentially stacked on a sidewall of each of the bit line structures along the second direction.

16. The semiconductor device of claim 15, wherein, Each of the first and fourth spacers includes insulating nitride, and each of the second and third spacers includes oxide.

17. The semiconductor device of claim 15, wherein, A first thickness of the third spacer in a first portion of the spacer structure on the extension region of the substrate in the second direction is greater than a second thickness of the third spacer in a second portion of the spacer structure on the cell array region of the substrate in the second direction.

18. The semiconductor device of claim 15, wherein, The first portion of each of the spacer structures further includes an insulating layer between the second and third spacers.

19. The semiconductor device of claim 18, wherein, The second portion of each of the spacer structures further includes an insulating pattern at a lower outer sidewall of the second spacer, The third and fourth spacers of each of the spacer structures are on the insulating pattern, and The insulating layer and the insulating pattern include the same material.

20. The semiconductor device of claim 19, wherein, The insulating layer and the insulating pattern include insulating nitride. The insulating layer and the insulating pattern include insulating nitride.

Images