Method and device for rapidly testing system jitter transfer function
By combining a signal generator and a spectrum analyzer, the jitter transfer function testing process for high-speed digital systems is simplified, solving the problems of complexity and high cost of existing testing methods, and realizing efficient and low-cost 3dB bandwidth evaluation.
Patent Information
- Application Number
- CN202511067998.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-07
AI Technical Summary
Existing 3dB bandwidth testing methods rely on high-cost equipment, have complex testing processes, and are susceptible to environmental instability, making it difficult to meet the needs of rapid verification and large-scale production testing.
A modulation reference clock is generated by a signal generator, and jitter of different frequencies is superimposed. The frequency domain amplitude of the input and output signals is collected by a spectrum analyzer, and the jitter transfer function is calculated to determine the 3dB bandwidth of the system, simplifying the testing process and reducing equipment dependence.
It achieves high-precision, low-cost testing, simplifies the testing process, improves testing efficiency and consistency, reduces equipment costs, and is suitable for evaluating jitter transmission characteristics of high-speed digital systems.
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Figure CN120908730A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to a method and device for quickly testing a jitter transfer function of a system. BACKGROUND
[0002] In high-speed digital systems, such as Peripheral Component Interconnect Express (PCIe), Ethernet, high-speed SerDes interface, and Phase Locked Loop (PLL) and Clock Data Recovery (CDR) modules, are widely used in processors, memories, network switching devices, and high-speed communication links. These systems need to filter and track the input reference clock or data jitter during operation, and the transfer characteristics are usually represented by the jitter transfer function. The 3dB bandwidth of the system is an important indicator for evaluating the dynamic performance of the PLL and CDR.
[0003] Existing 3dB bandwidth testing methods mostly rely on high-precision oscilloscopes, Bit Error Rate Testers (BERTs), and special jitter margin analyzers, which are costly, complex, and require special software for data processing. These testing devices are usually large in size, complex in parameter setting, and require complex calibration procedures before testing, which is time-consuming and difficult to meet the needs of rapid verification and large-scale production testing. In addition, the traditional method relies heavily on the stability of the test environment, and is affected by system noise, non-ideal device response, and other factors, which may cause deviations in the test results.
[0004] Therefore, there is an urgent need for a method and system that simplifies the testing process, reduces device dependence, and improves testing efficiency, which can quickly evaluate the jitter transfer characteristics of the PLL or CDR module in the high-speed digital system and determine its 3dB bandwidth under the premise of ensuring testing accuracy, to meet the needs of research and development verification and production application. SUMMARY
[0005] The present application aims to provide a method and device for quickly testing the jitter transfer function of a system, which generates a modulated reference clock through a signal generator, and sequentially superimposes jitter of different frequencies. The frequency domain amplitudes of the input and output signals are collected using a spectrum analyzer, the jitter transfer function is obtained by calculating the amplitude difference, and the 3dB bandwidth of the system is determined. This method simplifies the testing process, reduces the cost of equipment, and ensures the accuracy of the test.
[0006] In a first aspect, the present application provides a method for quickly testing the jitter transfer function of a system, comprising the following steps:
[0007] outputting a reference clock signal of a specific frequency by a signal generator, and superimposing a jitter at a frequency offset by an offset amount with respect to the specific frequency on the reference clock signal;
[0008] testing a first signal amplitude at the frequency offset on the reference clock signal by a spectrum analyzer;
[0009] inputting the reference clock signal to a system under test and providing an output clock signal through the system under test;
[0010] testing a second signal amplitude at a frequency offset by a corresponding offset amount on the output clock signal by the spectrum analyzer;
[0011] calculating a transfer function value of the jitter at the frequency offset according to the first signal amplitude and the second signal amplitude; and
[0012] obtaining a relationship between a jitter transfer function and a frequency according to the transfer function values of the respective jitters superimposed with the jitters at the frequencies offset by different offset amounts.
[0013] In one preferred embodiment, the transfer function value is calculated by the following formula:
[0014]
[0015] wherein Ain(f) represents the first signal amplitude at the frequency offset by f on the reference clock signal, and Aout(f) represents the second signal amplitude at the frequency offset by f on the output clock signal.
[0016] In one preferred embodiment, the step of obtaining the relationship between the jitter transfer function and the frequency according to the transfer function values of the respective jitters superimposed with the jitters at the frequencies offset by different offset amounts further comprises:
[0017] controlling the signal generator and the spectrum analyzer to test the transfer function values of the respective jitters superimposed with the jitters at the frequencies offset by different offset amounts from low frequency to high frequency by integrating an automatic test script in an upper computer, taking the transfer function value at the frequency offset by the minimum offset amount as a reference transfer function value, calculating the difference of the transfer function value at each subsequent frequency offset by a different offset amount with respect to the reference transfer function value, and fitting a curve between the jitter transfer function and the frequency
[0018] In one preferred embodiment, the frequency position where the 3dB bandwidth is located is determined according to the curve between the jitter transfer function and the frequency.
[0019] In one preferred embodiment, the signal generator increases the value of the offset amount in a logarithmic form.
[0020] In a preferred embodiment, the offset ranges from 0.1 MHz to 100 MHz.
[0021] In a preferred embodiment, the system under test is a clock recovery circuit of a PCIe or Ethernet system.
[0022] In a preferred embodiment, when the system under test is PCIe, the specific frequency of the reference clock is 100 MHz, and when the system under test is Ethernet, the specific frequency of the reference clock is 156.25 MHz or 312.5 MHz.
[0023] In another embodiment, the jitter is injected in the form of sinusoidal periodic jitter.
[0024] In a second aspect, the application provides a device for quickly testing the jitter transfer function of a system, comprising:
[0025] a signal generator for outputting a reference clock signal of a specific frequency, superimposing jitter on the reference clock signal at a frequency offset by a certain offset from the specific frequency, and inputting the reference clock signal to a system under test and providing an output clock signal through the system under test;
[0026] a spectrum analyzer for testing a first signal amplitude at the frequency offset on the reference clock signal and testing a second signal amplitude at a frequency offset by a corresponding offset on the output clock signal;
[0027] a host computer for calculating the transfer function value of the jitter at the frequency offset according to the first signal amplitude and the second signal amplitude, and obtaining the relationship between the jitter transfer function and the frequency according to the transfer function values of the corresponding jitter superimposed at frequencies offset by different offsets.
[0028] In a preferred embodiment, the host computer integrates an automatic test script, the signal generator and the spectrum analyzer are controlled by the automatic test script to sequentially test the transfer function values of the corresponding jitter superimposed at frequencies offset by different offsets from low frequency to high frequency, and the difference of the transfer function value at each subsequent frequency offset from the reference transfer function value at the frequency offset by the minimum offset is calculated to fit the relationship curve between the jitter transfer function and the frequency.
[0029] In a preferred embodiment, the frequency position of the 3 dB bandwidth is determined according to the relationship curve between the jitter transfer function and the frequency.
[0030] In a preferred embodiment, the system does not require a dedicated instrument and supporting software for testing the jitter transfer function.
[0031] Compared with the prior art, the present application has at least the following technical effects:
[0032] 1. High-precision measurement: By differential spectrum analysis, the influence of system inherent noise is eliminated, and the frequency response is accurately extracted.
[0033] 2. High-efficiency testing: Dynamic sweep strategy optimizes testing time, and both low-frequency resolution and high-frequency dynamic range are considered.
[0034] 3. Low-cost implementation: Only general test equipment (signal generator + spectrum analyzer) is needed, without expensive special instruments and supporting software.
[0035] 4. Automated process: Python-based automated control reduces manual intervention and improves test repeatability.
[0036] A large number of technical features are described in the specification of the present application, distributed in various technical solutions. If all possible combinations of technical features (i.e. technical solutions) of the present application are listed, the specification will be too long. In order to avoid this problem, each technical feature disclosed in the above invention content, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined to form various new technical solutions (these technical solutions should be considered to have been described in the specification), unless such combination of technical features is technically infeasible. For example, features A+B+C are disclosed in one example, features A+B+D+E are disclosed in another example, features C and D are equivalent technical means that play the same role, and can only be used at a time, and feature E can be combined with feature C technically. Therefore, the scheme of A+B+C+D should not be considered to have been described because it is technically infeasible, and the scheme of A+B+C+E should be considered to have been described. BRIEF DESCRIPTION OF DRAWINGS
[0037] Figure 1 is a flowchart of a method for quickly testing a jitter transfer function of a system according to an embodiment of the present application.
[0038] Figure 2 is an example of a curve showing the relationship between the transfer function and the frequency of a phase-locked loop with a reference clock of 100 MHz.
[0039] Figure 3 is a structural schematic diagram of an apparatus for quickly testing a jitter transfer function of a system according to an embodiment of the present application. DETAILED DESCRIPTION
[0040] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without such specific details and that numerous implementation variations and modifications can be possible.
[0041] Brief description of partial concepts:
[0042] Jitter Transfer Function: Jitter Transfer refers to the ratio between the jitter of the output signal of the device under test (DUT) and the jitter applied to the input reference signal, applicable to clock or data signals, usually represented by Jitter Transfer Function.
[0043] 3dB Bandwidth: In analog circuits and communication systems, 3dB is the frequency point at which the signal power is halved (because 10log 10 (0.5)≈-3dB), and for signal amplitude (voltage / current), i.e. the signal amplitude drops to 0.707x the maximum value, so the amplitude at this frequency point is still relatively usable, but the frequency response can be clearly seen to drop. In high-speed communication systems, the 3dB bandwidth determines the upper limit of inter-symbol interference (ISI) and data rate. The narrower the bandwidth, the more blurred the high-speed signal edge, and the more closed the eye diagram.
[0044] The following is a brief description of some of the innovations of the embodiments of the present application:
[0045] The present application proposes a fast evaluation of jitter transfer function test method based on periodic jitter injection, which superimposes a controllable frequency sinusoidal periodic jitter on the reference clock, calculates the jitter transfer function through the input-output jitter amplitude ratio, and indirectly measures the 3dB bandwidth of the system, avoiding the complexity of directly measuring the loop characteristics. The test process only relies on signal generators and spectrum analyzers, without the need for expensive equipment such as dedicated jitter analyzers, significantly reducing the test cost and simplifying the laboratory and production line construction. In addition, by integrating an automatic test script on the host computer, a logarithmic step frequency sweep from low to high frequency is realized, and the jitter transfer function values at each frequency point are automatically collected and calculated, the continuous transfer function curve is fitted, and the 3dB bandwidth point is automatically located, significantly improving the test efficiency and consistency.
[0046] In order to make the purpose, technical scheme and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.
[0047] One embodiment of the present application relates to a method for quickly testing the jitter transfer function of a system, the flowchart of which is shown in Figure 1 The method comprises the following steps:
[0048] Step 101, output a reference clock signal of a specific frequency through a signal generator. The reference clock is applied to a PCIe (Peripheral Component Interconnect Express) or Ethernet system. The PCIe and Ethernet belong to high-speed serial communication interfaces, and are high-speed serial links. Data is transmitted by a SerDes (serializer-deserializer), and data and clock are mixed in the same serial bit stream, and the clock signal is not transmitted separately. The receiving end recovers the clock from the data through a clock recovery circuit (Clock Data Recovery, CDR). For example, when applied to a PCIe system, the signal generator generates a 100MHz reference clock, and when applied to an Ethernet system, the signal generator generates a reference clock of a frequency of 156.25MHz, 312.5MHz, etc. Moreover, the signal generator superimposes jitter at a frequency offset by a certain offset amount from the specific frequency on the reference clock signal. For example, for a 100MHz reference clock, jitter is superimposed at a frequency position offset by a certain amount f from 100MHz, for example, at a frequency position offset by 1MHz, that is, at a 101MHz position. For example, for a 156.25MHz reference clock, jitter is superimposed at a frequency position offset by a certain amount f from 156.25MHz. It should be noted that the injection method of the jitter can adopt the form of periodic jitter (Periodic Jitter, PJ). In addition, the amplitude of the jitter is as small as possible relative to the main frequency signal, and cannot be too large. As long as the spectrum analyzer can test it, otherwise the poor quality of the reference clock makes the system not work. For example, in the example, the amplitude of the superimposed jitter is about -50dB smaller than the main frequency (reference clock 100MHz).
[0049] In one embodiment, the offset amount ranges from 0.1MHz to 100MHz. It should be understood that the range of the offset amount can be set accordingly according to different systems. For example, it can generally be set within 3 to 5 times the frequency corresponding to the estimated 3dB bandwidth, for example, preferably 5 times.
[0050] Step 102, test the first signal amplitude F1 at the frequency offset by the offset amount f on the reference clock signal through a spectrum analyzer. Specifically, the signal amplitude of the reference clock signal superimposed with the jitter is measured by the spectrum analyzer, and the signal amplitude F1 at the frequency position offset by the offset amount f is recorded. For example, for a reference clock with a specific frequency of 100MHz and an offset amount of 1MHz, the signal amplitude F1 at the 101MHz frequency position is recorded.
[0051] Step 103, input the reference clock signal to the system under test and provide the output clock signal through the system under test. The clock recovery circuit of the PCIe or Ethernet system under test is tested. The reference clock enters the system under test and normally outputs the responsive clock signal. It should be noted that the frequency of the clock signal output by the Fourier transform after the reference clock passes through the system under test changes. For example, the output frequency of the reference clock with a specific frequency of 100MHz and an offset of 1MHz after passing through the PCIe system may change to 16GHz. Then, the relative position of the superimposed jitter does not change fundamentally, so the corresponding jitter is still around the position offset by about 1MHz from the 16GHz peak value.
[0052] Step 104, test the second signal amplitude F2 at the frequency corresponding to the offset on the output clock signal through the spectrum analyzer. Specifically, the signal amplitude of the output clock signal passing through the system under test is measured by the spectrum analyzer, the corresponding signal peak after the specific frequency is changed is determined, the peak of the corresponding jitter signal is determined at the position around the position offset by the set offset, and the signal amplitude F2 at the frequency position of the corresponding jitter is recorded. For example, for the reference clock with a specific frequency of 100MHz and an offset of 1MHz, the corresponding 16GHz signal peak after transformation is found, and the corresponding jitter signal peak is found at a position about 1MHz from 16GHz (for example, at a position about 0.962MHz away), and the signal amplitude F2 at the position is recorded.
[0053] Step 105, calculate the transfer function value H(f) of the jitter at the frequency offset by the offset f according to the first signal amplitude F1 and the second signal amplitude F2.
[0054] Specifically, the transfer function value H(f) is calculated by the following formula:
[0055]
[0056] Wherein, Ain(f) represents the first signal amplitude F1 at the frequency offset by the offset f on the reference clock signal, and Aout(f) represents the second signal amplitude F2 at the frequency offset by the offset f on the output clock signal.
[0057] At step 106, the relationship between the jitter transfer function and the frequency is obtained according to the superimposed jitter transfer function values at the frequencies with different offset amounts. In this embodiment, the relationship curve between the jitter transfer function and the frequency is fitted according to the measured signal amplitudes and the calculated jitter transfer function values corresponding to different offset amounts. In addition, the step 106 further comprises: determining the frequency position of the 3dB bandwidth of the to-be-tested system according to the relationship curve between the jitter transfer function and the frequency.
[0058] Specifically, the automatic test script can be integrated in the host computer, and the signal generator and the spectrum analyzer are controlled according to the automatic test script to sequentially perform the following operations: the signal generator sequentially outputs the reference clock signals with superimposed jitter at the frequencies with different offset amounts from low frequency to high frequency, the spectrum analyzer sequentially measures the signal amplitudes with superimposed jitter at the frequencies with different offset amounts, the signal generator inputs the reference clock signals with superimposed jitter at the frequencies with different offset amounts to the to-be-tested system and obtains the output clock signals, the spectrum analyzer sequentially measures the signal amplitudes with superimposed jitter at the frequencies with different offset amounts, the host computer calculates the corresponding transfer function values according to the measured signal amplitudes, takes the transfer function value at the frequency with the minimum offset as the reference transfer function value, calculates the difference between the transfer function value at each subsequent frequency with different offset amounts and the reference transfer function value, and fits the relationship curve between the jitter transfer function and the frequency, and determines the frequency position of the 3dB bandwidth according to the relationship curve between the jitter transfer function and the frequency. In order to test more quickly, the signal generator can increase the value of the offset amount f in a logarithmic form.
[0059] In addition, the measurement error can be prevented by multiple measurements, multiple samplings and the average value formula when calculating the transfer function value.
[0060] In the PCIe / Ethernet transceiver system, the sending end (such as a signal generator) is responsible for generating a high-speed clock (such as 10 GHz+) to drive the SerDes. In the receiving end, the phase-locked loop (PLL) is the core component of the CDR, which dynamically adjusts the clock frequency and phase through the phase comparator, loop filter and voltage-controlled oscillator (VCO) to achieve accurate phase locking and frequency tracking. As part of the CDR, the PLL tracks the input data phase to recover the correct clock. The PLL can track the highest frequency of jitter, which is determined by its bandwidth. If the frequency of the input jitter is greater than the PLL bandwidth, then H(f) << 1, indicating that the high-frequency jitter is filtered out, and the PLL suppresses the jitter. If the frequency of the input jitter is less than the PLL bandwidth, then H(f) is approximately equal to 1, indicating that the low-frequency jitter is directly transmitted, and the PLL completely tracks the input jitter.
[0061] In order to better understand the technical solutions of the present application, a specific example will be described below, and the details listed in the example are mainly for the purpose of understanding and should not be regarded as a limitation on the scope of protection of the present application.
[0062] By injecting a periodic jitter (PJ) of known frequency and amplitude to the reference clock, measuring the output end's response to the same frequency jitter, and calculating the transfer function, the specific implementation steps are as follows:
[0063] 1. Signal generation: use a signal generator to configure its output reference clock signal (such as 100 MHz).
[0064] 2. Jitter injection: superimpose a sinusoidal periodic jitter (PJ) of test frequency f on the 100 MHz reference clock signal.
[0065] 3. Input signal measurement: use a spectrum analyzer to test the signal peak amplitude F1 at the frequency position offset f superimposed on the reference clock. Figure 2 This represents the 100 MHz reference clock superimposed with a periodic jitter of a certain frequency (such as 1 MHz), and the signal peak amplitude at the 1 MHz offset is tested.
[0066] 4. System connection: connect the reference clock with periodic jitter to the DUT.
[0067] 5. System output: configure the system to normally output data or clock signals.
[0068] 6. Output signal measurement: use a spectrum analyzer to test the signal peak amplitude F2 at the frequency position offset f superimposed on the output signal of the DUT.
[0069] 7. Transfer function value calculation: the signal peak amplitudes F1 and F2 are used to calculate the transfer function value of the periodic jitter at the injection frequency f using the above formula.
[0070] 8. Automated scanning: use an automated test script developed based on Python to integrate SCPI instructions to control the signal generator and test equipment. Set the periodic jitter at different frequency offsets ranging from low frequency to high frequency (usually covering 5 times the frequency range of the system loop bandwidth), and use a logarithmic step scanning method. Perform multiple measurements, real-time data verification, and re-measurement of abnormal points at each frequency point.
[0071] 9. Calibration and curve fitting: use the jitter transfer function value of the first point at low frequency as the reference H0, and use the difference between other points and H0 for calibration to build a continuous jitter transfer function confirmation and determine the frequency point at which the amplitude decreases by 3 dB.
[0072] The transfer function values of the jitter at each offset frequency point are scanned by using Python, and the jitter transfer function and 3dB bandwidth of the system are obtained by calibrating the reference point, Figure 2 The jitter transfer function and frequency relationship curve of the period jitter superimposed on the 100MHz reference clock is shown.
[0073] The embodiments of the present application also relate to a device for quickly testing the jitter transfer function of a system, which has the structure as Figure 3 The device includes a signal generator 201, a spectrum analyzer 202, and a host computer 204. The signal generator 201 is used to output a reference clock signal of a specific frequency, superimpose jitter at a frequency offset by a certain offset amount on the reference clock signal, and input the reference clock signal to the system to be tested 203 and provide an output clock signal through the system to be tested 203. The spectrum analyzer 202 is used to test the first signal amplitude at the offset frequency on the reference clock signal and test the second signal amplitude at the frequency corresponding to the offset amount on the output clock signal. The host computer 204 is used to calculate the transfer function value of the jitter at the offset frequency according to the first signal amplitude and the second signal amplitude, and obtain the relationship between the jitter transfer function and the frequency according to the corresponding jitter transfer function values of the jitter superimposed at the frequencies offset by different offset amounts.
[0074] In one embodiment, an automatic test script is integrated in the host computer 204, and the signal generator and the spectrum analyzer are controlled by the automatic test script to test the corresponding jitter transfer function values of the jitter superimposed at the frequencies offset by different offset amounts from low frequency to high frequency in sequence. The transfer function value at the frequency offset by the minimum offset amount is taken as the reference transfer function value, and the difference between the transfer function value at each subsequent frequency offset by a different offset amount and the reference transfer function value is calculated, and the relationship curve between the jitter transfer function and the frequency is fitted. Further, the host computer 204 determines the frequency position of the 3dB bandwidth according to the relationship curve between the jitter transfer function and the frequency. It should be understood that the signal generator 201 and the spectrum analyzer 202 can communicate through a standard interface, and the host computer can be controlled by PC software.
[0075] The method and device for quickly testing the jitter transfer function of the system of the present application are particularly suitable for clock performance verification of high-speed digital systems (such as 56G PAM4, PCIe, PLL, etc.), and provide an efficient and reliable solution for jitter transfer characteristic testing, which only requires a general signal generator and a spectrum analyzer, without the need for expensive special instruments and supporting software.
[0076] Accordingly, the embodiments of the present application also provide a computer readable storage medium, having stored therein computer-executable instructions that, when executed by a processor, implement the method embodiments of the present application. The computer readable storage medium includes persistent and non-persistent, movable and non-movable media, which can be implemented by any method or technology for storing information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to computing devices. According to the definition herein, the computer readable storage medium does not include transitory computer readable media, such as modulated data signals and carrier waves.
[0077] Further, the embodiments of the present application also provide a device for testing the jitter transfer function of a rapid test system, comprising a memory for storing computer executable instructions, and a processor; the processor is used to implement the steps in the above method embodiments when executing the computer executable instructions in the memory. The processor can be a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP), a microcontroller unit (MCU), a neural processing unit (NPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, etc. The memory can be a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk or a solid state disk, etc. The steps of the methods disclosed in the embodiments of the present application can be directly embodied as hardware processor execution, or be executed by a combination of hardware and software modules in the processor.
[0078] Further, the embodiments of the present application also provide a computer program product comprising computer executable instructions, which are executed by a processor to implement the steps in the above method embodiments.
[0079] It is to be noted that the terms "first", "second", and the like, as used in the specification, are used merely to distinguish one element from another, and are not necessarily used to denote sequential or chronological order. Also, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. Where an indefinite or definite article is used when referring to a singular noun entity, "an" or "one" is intended to cover "at least one" or "one or more" unless otherwise specifically limited. Where the term "about" is used, this is intended to cover variations of + / - 10% from the value being described.
[0080] The term "coupled to" and its derivatives can be used herein. "Coupled" can mean that two or more elements are in direct physical or electrical contact. However, "coupled" can also mean that two or more elements indirectly contact each other, but yet are still in cooperation or interaction with each other. It can also mean that one or more other elements are coupled or connected between the elements which are said to be coupled to each other.
[0081] All documents referred to herein are hereby incorporated by reference in their entirety in the disclosure of the application in order to more fully describe the application and the state of the art to which it pertains. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the scope of the present application. It must be noted that, as used in the specification and the appended claims, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise.
Claims
1. A method of rapidly testing a jitter transfer function of a system, characterized by, The method comprises the following steps: outputting a reference clock signal of a specific frequency by a signal generator, and superimposing jitter at a frequency offset by a certain offset amount relative to the specific frequency on the reference clock signal; testing a first signal amplitude at the offset frequency on the reference clock signal by a spectrum analyzer; inputting the reference clock signal to a system under test and providing an output clock signal through the system under test; testing a second signal amplitude at a frequency offset by a corresponding offset amount on the output clock signal by the spectrum analyzer; calculating a transfer function value of the jitter at the offset frequency according to the first signal amplitude and the second signal amplitude; and obtaining a relationship between a jitter transfer function and a frequency according to respective jitter transfer function values of jitters superimposed at frequencies offset by different offset amounts.
2. The method of claim 1, wherein, The transfer function value is calculated by the following formula: wherein Ain(f) represents the first signal amplitude at a frequency offset by an offset amount of f on the reference clock signal, and Aout(f) represents the second signal amplitude at a frequency offset by an offset amount of f on the output clock signal.
3. The method of claim 1, wherein, The step of obtaining the relationship between the jitter transfer function and the frequency according to respective jitter transfer function values of jitters superimposed at frequencies offset by different offset amounts further comprises: controlling the signal generator and the spectrum analyzer to test the respective jitter transfer function values of jitters superimposed at frequencies offset by different offset amounts in sequence from low frequency to high frequency by integrating an automatic test script in a host computer, taking the transfer function value at the frequency offset by the minimum offset amount as a reference transfer function value, calculating a difference value of the transfer function value at each subsequent frequency offset by a different offset amount relative to the reference transfer function value, and fitting a relationship curve between the transfer function and the frequency.
4. The method of claim 3, wherein, The signal generator increases the value of the offset amount in a logarithmic form.
5. The method of claim 1 or 3, wherein, Further comprising: determining a frequency position of a 3dB bandwidth of the system under test according to the relationship between the jitter transfer function and the frequency.
6. The method of claim 1, wherein, The system under test is a clock recovery circuit of a PCIe or Ethernet system.
7. The method of claim 6, wherein, When the system under test is PCIe, the specific frequency of the reference clock is 100MHz, and when the system under test is Ethernet, the specific frequency of the reference clock is 156.25MHz or 312.5MHz.
8. An apparatus for rapid testing of a jitter transfer function of a system, characterized by Comprising: a signal generator for outputting a reference clock signal of a specific frequency, superimposing jitter at a frequency offset by a certain offset amount relative to the specific frequency on the reference clock signal, and inputting the reference clock signal to a system under test and providing an output clock signal through the system under test; a spectrum analyzer for testing a first signal amplitude at the offset frequency on the reference clock signal, and testing a second signal amplitude at a frequency offset by a corresponding offset amount on the output clock signal; a host computer for calculating a transfer function value of the jitter at the offset frequency according to the first signal amplitude and the second signal amplitude, and obtaining a relationship between a jitter transfer function and a frequency according to respective jitter transfer function values of jitters superimposed at frequencies offset by different offset amounts.
9. The apparatus of claim 8, wherein, The host computer is integrated with an automatic test script, and the signal generator and the spectrum analyzer are controlled according to the automatic test script to sequentially test corresponding dithered transfer function values at frequencies with different offset amounts with superimposed dithering from low frequencies to high frequencies, to take the transfer function value at the frequency with the minimum offset amount as a reference transfer function value, to calculate the difference of the transfer function value at each subsequent frequency with a different offset amount relative to the reference transfer function value, and to fit a relationship curve between the dithered transfer function and the frequency.
10. The apparatus of claim 8, wherein, The system does not need special instruments and supporting software for testing the transfer function.