Multifunctional low-frequency test equipment

Abstract

The invention discloses multifunctional low-frequency test equipment, which relates to the technical field of low-frequency test and comprises a core processing unit, and a multiplexing functional circuit, an AD functional circuit, a 4M 1553B functional circuit, an RS422 functional circuit, a relay functional circuit, a DMM functional circuit, a state quantity functional circuit and a network interface circuit which are connected with the core processing unit, the network interface circuit is used for acquiring a task instruction; the core processing unit is used for generating a control instruction based on the task instruction; the multiplexing function circuit, the AD function circuit, the 4M 1553B function circuit, the RS422 function circuit, the relay function circuit, the DMM function circuit and the state quantity function circuit are used for obtaining corresponding signal data from a system to be tested based on a control instruction. And the core processing unit is also used for processing the signal data to obtain a test result. The system to be tested can be accurately and reliably tested from multiple aspects.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of low-frequency testing, in particular to a multifunctional low-frequency testing device. BACKGROUND

[0002] With the rapid development of aerospace, aviation, industrial automation and other fields, higher requirements are put forward for low-frequency devices in distributed standard testing systems.

[0003] In the distributed standard testing system, the low-frequency testing device has the following technical problems: 1. Insufficient measurement accuracy: the measurement resolution and accuracy of some devices cannot meet the demand of high-precision testing in high-end fields such as aerospace and aviation.

[0004] 2. Reliability needs to be improved: the use of non-domestic components or imperfect design may cause faults in complex electromagnetic environments or harsh working conditions.

[0005] 3. Single function: most devices have single functions and cannot realize the integration of multiple measurement and communication functions, resulting in high system complexity and difficult maintenance.

[0006] 4. Poor communication compatibility: the communication interface and protocol are not flexible enough to interact with different devices and systems and work cooperatively.

[0007] 5. Existence of security risks and high cost. SUMMARY

[0008] The application aims to provide a multifunctional low-frequency testing device that can accurately and reliably test the system to be tested from multiple aspects.

[0009] To achieve the above-mentioned purpose, the application provides the following solutions: The application provides a multifunctional low-frequency testing device, which comprises a core processing unit and a multiplexing function circuit, an AD function circuit, a 4M 1553B function circuit, an RS422 function circuit, a relay function circuit, a DMM function circuit, a state quantity function circuit and a network interface circuit connected with the core processing unit. The network interface circuit is used to obtain a task instruction. The core processing unit is used to generate a control instruction based on the task instruction; the multiplexing function circuit, the AD function circuit, the 4M 1553B function circuit, the RS422 function circuit, the relay function circuit, the DMM function circuit and the state quantity function circuit are all used to obtain corresponding signal data from the system to be tested based on the control instruction; and the core processing unit is further used to process the signal data to obtain a test result.

[0010] In an embodiment, the multifunctional low-frequency test device further comprises a display screen; the display screen is connected with the core processing unit. The display screen is used for displaying the working state of the core processing unit.

[0011] In an embodiment, the core processing unit comprises a main controller, a 4M 1553B control logic circuit, an RS422 processing logic circuit, a DMM processing logic circuit, an AD control logic circuit, a switching quantity test processing logic circuit, a relay control logic circuit and a MUX control logic circuit. The main controller is connected with the 4M 1553B control logic circuit, the RS422 processing logic circuit, the DMM processing logic circuit, the AD control logic circuit, the switching quantity test processing logic circuit, the relay control logic circuit and the MUX control logic circuit through an AXI bus respectively. The 4M 1553B control logic circuit is connected with the 4M 1553B function circuit; the RS422 processing logic circuit is connected with the RS422 function circuit; the DMM processing logic circuit is connected with the DMM function circuit; the AD control logic circuit is connected with the AD function circuit; the switching quantity test processing logic circuit is connected with the state quantity function circuit; the relay control logic circuit is connected with the relay function circuit; and the MUX control logic circuit is connected with the multiplexing function circuit. The main controller is used for generating a control instruction based on the task instruction; the 4M 1553B control logic circuit is used for controlling the 4M 1553B function circuit based on the control instruction; the RS422 processing logic circuit is used for controlling the RS422 function circuit based on the control instruction; the DMM processing logic circuit is used for controlling the DMM function circuit based on the control instruction; the AD control logic circuit is used for controlling the AD function circuit based on the control instruction; the switching quantity test processing logic circuit is used for controlling the state quantity function circuit based on the control instruction; the relay control logic circuit is used for controlling the relay function circuit based on the control instruction; and the MUX control logic circuit is used for controlling the multiplexing function circuit based on the control instruction.

[0012] In an embodiment, the 4M 1553B control logic circuit comprises a control circuit and a data address circuit; both the control circuit and the data address circuit are connected with the 4M 1553B function circuit. The control circuit is used for controlling the 4M 1553B function circuit based on the control instruction. The data address circuit is used for data transmission with the 4M 1553B function circuit.

[0013] In an embodiment, the RS422 processing logic circuit adopts a universal asynchronous receiver-transmitter.

[0014] In an embodiment, the multifunctional low-frequency test device further comprises a power supply and a case; The power supply is connected with the core processing unit; the power supply, the core processing unit, the multiplexing function circuit, the AD function circuit, the 4M 1553B function circuit, the RS422 function circuit, the relay function circuit, the DMM function circuit and the state quantity function circuit are arranged in the case.

[0015] In an embodiment, the AD function circuit comprises an input isolation and limiting circuit, a multipath gating circuit, a program-controlled amplification circuit and an A / D converter; The input isolation and limiting circuit is connected with the multipath gating circuit; the program-controlled amplification circuit is connected with the multipath gating circuit and the A / D converter respectively; the A / D converter is connected with the core processing unit.

[0016] In an embodiment, the DMM function circuit comprises a relay channel switching circuit, an AC / DC voltage conditioning circuit, an AC / DC effective value measurement circuit, a resistance measurement conversion circuit, a multipath selector, a voltage amplification circuit and an AD conversion circuit; The relay channel switching circuit is connected with the AC / DC voltage conditioning circuit, the resistance measurement conversion circuit and the core processing unit respectively; the multipath selector is connected with the AC / DC voltage conditioning circuit, the resistance measurement conversion circuit and the voltage amplification circuit respectively; the voltage amplification circuit is connected with the AD conversion circuit and the AC / DC effective value measurement circuit respectively; the AC / DC effective value measurement circuit is connected with the AD conversion circuit; the AD conversion circuit is connected with the core processing unit.

[0017] In an embodiment, the network interface circuit comprises a network protocol chip and a network connector; the network protocol chip is connected with the core processing unit and the network connector respectively.

[0018] In an embodiment, the relay function circuit comprises a drive chip and a relay; the drive chip is connected with the relay and the core processing unit respectively.

[0019] According to the specific embodiments provided by the present application, the present application has the following technical effects: The application provides a multifunctional low-frequency test device, comprising an integrated instrument resource module, a power supply and a case. By integrating a multiplexing function circuit, an AD function circuit, a 4M 1553B function circuit, an RS422 function circuit, a relay function circuit, a DMM function circuit, a state quantity function circuit and a network interface circuit in the integrated instrument resource module, the multifunctional low-frequency test device has more comprehensive functions, solves the problem of single function and reduces the size of the low-frequency test device. The multifunctional low-frequency test device supports 4M 1533B communication and RS422 communication, can interact with different systems and communicate with different systems, improves communication compatibility and is suitable for various application scenarios. The network interface circuit obtains a task instruction, and the core processing unit processes the instruction, so that the core processing unit can select a circuit corresponding to the task, and then the circuit executes the task instruction. The signal data in the to-be-tested system is obtained by executing the task instruction through the corresponding circuit, the signal data is processed in the core processing unit, and then accurate and reliable testing of the to-be-tested system is realized. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0021] Figure 1 FIG. 1 is a structural schematic diagram of a multifunctional low-frequency test device according to an embodiment of the present application; Figure 2 FIG. 2 is a structural schematic diagram of a core processing unit according to an embodiment of the present application; Figure 3 FIG. 3 is a schematic diagram of a 4M 1553B function circuit according to an embodiment of the present application; Figure 4 FIG. 4 is a schematic diagram of an RS422 function circuit according to an embodiment of the present application; Figure 5 FIG. 5 is a schematic diagram of an RS422 processing logic circuit according to an embodiment of the present application; Figure 6 FIG. 6 is a schematic diagram of a state quantity function circuit according to an embodiment of the present application; Figure 7 FIG. 7 is a schematic diagram of an AD function circuit according to an embodiment of the present application; Figure 8 FIG. 8 is a schematic diagram of a DMM function circuit according to an embodiment of the present application; Figure 9 FIG. 9 is a schematic diagram of a relay function circuit according to an embodiment of the present application; Figure 10A schematic diagram of a network interface circuit provided in an embodiment of this application; Figure 11 This is a schematic diagram of the internal layout of a multifunctional low-frequency testing device provided in another embodiment of this application; Figure 12 A flowchart illustrating the network communication process of a multifunctional low-frequency test device provided in an embodiment of this application; Figure 13 This is a schematic diagram of the task execution process of a multifunctional low-frequency testing device provided in an embodiment of this application; Figure 14 A front panel layout design diagram of a multifunctional low-frequency testing device provided in an embodiment of this application; Figure 15 This is a rear panel layout design diagram of a multifunctional low-frequency testing device provided in an embodiment of this application; Figure 16 This is a left panel layout design diagram of a multifunctional low-frequency testing device provided in an embodiment of this application.

[0022] Attached diagram: 1-Display screen, 2-Switch, 3-Air switch, 4-Rugged LAN module, 5-Power interface. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] In one exemplary embodiment, such as Figure 1 As shown, a multifunctional low-frequency testing device is provided, including: a core processing unit and multiplexing function circuit, AD function circuit, 4M 1553B function circuit, RS422 function circuit, relay function circuit, DMM function circuit, status function circuit, and network interface circuit connected to the core processing unit.

[0026] The network interface circuit is used to obtain task instructions.

[0027] The core processing unit is configured to generate control instructions based on task instructions. The multiplexing functional circuit, the AD functional circuit, the 4M 1553B functional circuit, the RS422 functional circuit, the relay functional circuit, the DMM functional circuit, and the state quantity functional circuit are configured to acquire corresponding signal data from the to-be-tested system based on the control instructions. The core processing unit is further configured to process the signal data to obtain a test result.

[0028] In actual applications, in order to reduce the size of the device and improve the consistency of the device, the core processing unit, the multiplexing functional circuit, the AD functional circuit, the 4M 1553B functional circuit, the RS422 functional circuit, the relay functional circuit, the DMM functional circuit, the state quantity functional circuit, and the network interface circuit can be integrated on a single circuit board as an integrated instrument resource module to realize integrated design.

[0029] The test range of the multifunctional low-frequency test device is specifically the electrical signal test category without high-frequency signal processing (such as radio frequency and microwave), and covers signals of low frequency, slow change, and stable amplitude, such as direct current signals, low-frequency alternating current signals, and low-speed communication signals. The low-frequency test in the present application is clearly distinguished from high-frequency radio frequency (≥30 MHz) and microwave (≥1 GHz) tests.

[0030] As an optional implementation, the multifunctional low-frequency test device further includes a display screen. The display screen is connected with the core processing unit. The display screen is configured to display the working state of the core processing unit. The main features of the display screen are as follows: (1) working power supply: DC 3.3V, power: 0.8W; (2) size: the physical size of the display screen is 4.3 inches; (3) interface mode: serial peripheral interface (SPI); (4) maximum transmission rate supported: not less than 1 Mbps; (5) display color: full color; (6) resolution: the display resolution of the display screen is 800x480, and a picture of 640x360 can be displayed at any position according to actual application requirements; (7) visual range of the display screen: ≥150°; (8) working temperature: -43℃ to +70℃; (9) storage temperature: -50℃ to +70℃; (10) relative humidity: 95% (+40℃); (11) the character library of the display screen includes commonly used character libraries such as Chinese, English, Arabic numerals, and digital tube font (numbers); (12) environmental adaptability should meet the related requirements of GJB150A-2009, specifically including high temperature, low temperature, vibration, and impact; (13) the insulation resistance of the power line of the display screen and the housing, mounting hole, and joint surface is greater than or equal to 500MΩ; and (14) the withstand voltage of the power line of the display screen and the housing, mounting hole, and joint surface is greater than 250V.

[0031] As an optional implementation, the core processing unit comprises a main controller, a 4M 1553B control logic circuit, an RS422 processing logic circuit, a DMM processing logic circuit, an AD control logic circuit, a switching value test processing logic circuit, a relay control logic circuit and a MUX control logic circuit.

[0032] The main controller is connected with the 4M 1553B control logic circuit, the RS422 processing logic circuit, the DMM processing logic circuit, the AD control logic circuit, the switching value test processing logic circuit, the relay control logic circuit and the MUX control logic circuit through an AXI bus.

[0033] The 4M 1553B control logic circuit is connected with a 4M 1553B function circuit. The RS422 processing logic circuit is connected with an RS422 function circuit. The DMM processing logic circuit is connected with a DMM function circuit. The AD control logic circuit is connected with an AD function circuit. The switching value test processing logic circuit is connected with a state value function circuit. The relay control logic circuit is connected with a relay function circuit. The MUX control logic circuit is connected with a multiplexing function circuit.

[0034] The main controller is configured to generate a control instruction based on a task instruction. The 4M 1553B control logic circuit is configured to control the 4M 1553B function circuit based on the control instruction. The RS422 processing logic circuit is configured to control the RS422 function circuit based on the control instruction. The DMM processing logic circuit is configured to control the DMM function circuit based on the control instruction. The AD control logic circuit is configured to control the AD function circuit based on the control instruction. The switching value test processing logic circuit is configured to control the state value function circuit based on the control instruction. The relay control logic circuit is configured to control the relay function circuit based on the control instruction. The MUX control logic circuit is configured to control the multiplexing function circuit based on the control instruction.

[0035] For example, the core processing unit is mainly a data processing system taking a new type of FPGA (Field-Programmable Gate Array) as a core. Based on the reconfigurable FPGA, a reconfigurable system structure is constructed, and a dynamic part of a reconfigurable area is fully utilized for data processing, so as to improve the efficiency of data processing. The logic processing of each function circuit is realized by using a static area of the FPGA. The core processing unit adopts a self-developed core board of a programmable fusion chip, as shown in FIG. 1. Figure 2 As shown in FIG. 1, the core processing unit comprises a main controller, a 4M 1553B control logic circuit, an RS422 processing logic circuit, a DMM processing logic circuit, an AD control logic circuit, a switching value test processing logic circuit, a relay control logic circuit and a MUX control logic circuit.

[0036] Table 1: Internal component description table of core processing unit

[0037] The main controller (CPU) of the core processing unit is a programmable chip FMQL45T900 of the integrated architecture of Fudan micro FPGA+ARM. The FMQL45T900 has a four-core processor and integrates a processing system (PS) and programmable logic (PL) and is based on a TSMC 28nm HPC+ process. The programmable fusion chip integrates the processor system PS based on the high-performance processor and the programmable logic PL.

[0038] The 4M 1553B control logic circuit includes a control circuit and a data address circuit. The control circuit and the data address circuit are connected with the 4M 1553B function circuit. The control circuit is used to control the 4M 1553B function circuit based on a control instruction. The data address circuit is used to perform data transmission with the 4M 1553B function circuit.

[0039] For example, the 4M 1553B function circuit is implemented by using a dedicated chip HT-61843GB-1. The HT-61843GB-1 has a double-channel design, a simple interface and software operation supporting three function modes of a bus controller (BC), a remote terminal (RT) and a monitor terminal (MT). The connection of the 4M 1553B function circuit with the 4M 1553B control logic circuit is shown in FIG. 2. Figure 3

[0040] The 4M 1553B control logic circuit includes a control circuit and a data address circuit. The control circuit includes a selection control logic circuit, a data conversion logic circuit, a read-write control logic circuit, a ready control logic circuit and an interrupt control logic circuit. The data address circuit includes an address mapping logic circuit and a data mapping logic circuit.

[0041] ​The selection control logic circuit is connected with the chip selection control pin ( / SELECT) and the memory / register selection pin ( / MEM / REG) of the HT-61843GB-1 chip; the selection control logic circuit is used for sending a chip selection signal (4M SC) to the HT-61843GB-1 chip, starting the HT-61843GB-1 chip, and making the HT-61843GB-1 chip enter a working state; the selection control logic circuit is also used for sending a memory / register selection signal (4M MR) to the HT-61843GB-1 chip, and controlling data transmission between the FPGA and the memory or the register. The data conversion logic circuit is connected with the data strobe pin ( / STRBD) of the HT-61843GB-1 chip; the data conversion logic circuit is used for sending a data strobe signal (4M STRB) to the HT-61843GB-1 chip, and the data strobe signal and the chip selection signal are used for controlling data transmission from the FPGA to the HT-61843GB-1 chip and data transmission from the HT-61843GB-1 chip to the FPGA. The read / write control logic circuit is connected with the read / write control pin ( / RD / / WR) of the HT-61843GB-1 chip; the read / write control logic circuit is used for sending a read / write signal (4M R_W) to the HT-61843GB-1 chip, and judging whether the FPGA performs a read operation or a write operation on the HT-61843GB-1 chip. The ready control logic circuit is connected with the ready state pin ( / READYD) of the HT-61843GB-1 chip; The ready control logic circuit is used for sending a ready signal (4M RDY) to the HT-61843GB-1 chip, and also used for receiving a ready signal sent by the HT-61843GB-1 chip, and judging whether all related signals are ready. The interrupt control logic circuit is connected with the interrupt request pin ( / INT) of the HT-61843GB-1 chip; the interrupt control logic circuit is used for receiving an interrupt request signal (4M INT) sent by the HT-61843GB-1 chip, and judging whether an interrupt is generated. The control circuit is used for realizing control of the 4M 1553B functional circuit by the FPGA.

[0042] The address mapping logic circuit is connected with the address bus pin (A[12:0]) of the HT-61843GB-1 chip; the address mapping logic circuit is used for address decoding through the address signal (4M A[12:0]) so that the FPGA can correctly locate the 4M 1553B functional circuit and thus perform corresponding operations. The data mapping logic circuit is connected with the bidirectional data bus pin (D[15:0]) of the HT-61843GB-1 chip; the data mapping logic circuit and the HT-61843GB-1 chip are connected through the data signal (4M D[15:0]) for bidirectional data transmission so that the FPGA can send data to the 4M 1553B functional circuit and also receive data from the 4M 1553B functional circuit, thereby realizing the function of bidirectional data exchange.

[0043] In addition to the HT-61843GB-1 chip, the 4M 1553B functional circuit further includes a crystal oscillator circuit and a transformer circuit. The crystal oscillator circuit is a key component for providing basic clock input for the HT-61843GB-1 chip. In the crystal oscillator circuit: the 4th pin is connected to the power supply line VCC3.3 to provide a 3.3V power supply voltage for the crystal oscillator circuit and other related components; the 2nd pin is connected to the digital ground line DGND to provide a ground connection for the circuit; the 3rd pin is connected to the clock input pin ( / CLOCK IN) of the HT-61843GB-1 chip; and the 1st pin is a null pin. The input clock signal has a frequency of 16MHz, which is the output of the crystal oscillator circuit and is used to provide basic clock input for the HT-61843GB-1 chip.

[0044] The transformer circuit has two paths, and each path of the transformer circuit is an isolation transformer. In the isolation transformer: the IN+ pin is connected to the differential signal channel A (positive, that is, the TX / RX_A pin) of the HT-61843GB-1 chip, which is used to transmit the positive signal of the received or sent signal. The IN- pin is connected to the differential signal channel A (negative, that is, the TX / RX_ / A pin) of the HT-61843GB-1 chip, which is used to transmit the differential signal opposite to the TX / RX_A; the TX / RX_A pin and the TX / RX_ / A pin have the same function, and are used for transmitting or receiving signals. The NC pin is a null pin. The OUT+ pin is the positive signal output end of the isolation transformer, corresponding to the IN+ pin; the OUT+ pin is the output interface of the positive differential signal after the isolation and signal transmission processing of the isolation transformer; the signal output by the OUT+ pin can be transmitted to the subsequent device or circuit module that needs to receive the differential signal, which is used to provide the positive differential signal component to realize the complete transmission of the differential signal. The OUT- pin is the reverse signal output end of the isolation transformer, corresponding to the IN- pin; the OUT- pin is the output interface of the reverse differential signal after the processing of the isolation transformer. The reverse differential signal component is output through the OUT- pin, which cooperates with the positive differential signal output by the OUT+ pin to form a complete differential signal pair, which is transmitted to the subsequent circuit to ensure the accuracy and anti-interference of the differential signal transmission. The isolation transformer is connected to the TX / RX_A pin and the TX / RX_ / A pin (or the standby differential signal channel B (positive, that is, the TX / RX_B pin) and the standby differential signal channel B (negative, that is, the TX / RX_ / B pin)) of the HT-61843GB-1 chip, which can isolate the signal and complete the sending and receiving functions. Such a design enables each signal to be isolated and transmitted / received through the transformer circuit, thereby realizing the corresponding signal transmission function. The GND1 pin (or the GND2 pin) is the ground pin inside the isolation transformer, which is used to provide a ground reference for the primary side circuit (or the secondary side circuit) of the isolation transformer, to ensure the electrical stability of the primary side circuit (or the secondary side), to reduce signal interference, to enable the signal output by the primary side (or the secondary side) to have a stable potential reference, and to help the isolation transformer to realize the electrical isolation function between the primary and the secondary, to avoid direct electrical interference between the primary and the secondary circuits.

[0045] The CH1A+ pin is a positive signal receiving or sending end connected to the external circuit for the 4M 1553B function circuit. The CH1A- pin is a negative signal receiving or sending end connected to the external circuit, corresponding to the CH1A+ pin. The CH1A+ pin (or the CH1A- pin) cooperates with the OUT+ pin (or the OUT- pin) of the corresponding isolation transformer (the isolation transformer connected to the TX / RX_A and TX / RX_ / A pins of the HT-61843GB-1 chip) to transmit a positive differential signal (or a negative differential signal) between the external circuit and the isolation transformer, and is a positive signal interface (or a negative signal interface) in a differential signal transmission path between the external circuit and the isolation transformer, so as to realize the interaction of the positive signal (or the negative signal) between the external circuit and the isolation transformer. The CH1A+ pin and the CH1A- pin jointly complete the interaction of a differential signal pair between the external circuit and the isolation transformer.

[0046] The CH1B+ pin is another positive signal receiving or sending end connected to the external circuit for the 4M 1553B function circuit. The CH1B- pin is another negative signal receiving or sending end connected to the external circuit, corresponding to the CH1B+ pin. The CH1B+ pin (or the CH1B- pin) cooperates with the OUT+ pin (or the OUT- pin) of the corresponding isolation transformer (the isolation transformer connected to the TX / RX_B and TX / RX_ / B pins of the HT-61843GB-1 chip) to transmit a positive differential signal (or a negative differential signal) between the external circuit and the isolation transformer, and is a positive signal interface (or a negative signal interface) in a differential signal transmission path between the external circuit and the isolation transformer, so as to realize the interaction of the positive signal (or the negative signal) between the external circuit and the isolation transformer. The CH1B+ pin (or the CH1B- pin) and the CH1A+ pin (or the CH1A- pin) are similar in function, but correspond to different differential signal channels (channel B).

[0047] In addition, the RS422 processing logic circuit adopts a universal asynchronous receiver / transmitter (UART). For example, the universal asynchronous receiver / transmitter is connected with the RS422 function circuit, and the RS422 function circuit includes eight identical RS422 receiving and sending circuits, and the eight RS422 receiving and sending circuits are all connected with the RS422 processing logic circuit. The RS422 receiving and sending circuit includes two isolated RS485 transceivers, such as Figure 4RS485 transceiver is CA-IS3908W, and the highest speed supports 10Mbps. The signal data input RS485 transceiver CA-IS3908W, and the output serial signal is transmitted to RS422 processing logic circuit, which is processed by the main controller in the core processing unit; the core processing unit sends serial signals to the RS485 transceiver CA-IS3908W through the RS422 processing logic circuit.

[0048] The communication protocol of RS422 processing logic circuit is UART, and the control logic is as shown in Figure 5 The 8 channels in the RS422 processing logic circuit connected with the RS422 receiving and sending circuit are independent of each other, and the control logic is similar. The receiving process: the RS422 processing logic circuit receives the serial signal transmitted by the RS422 function circuit, identifies the start bit of the serial signal through the self-developed IP core (the self-developed IP core refers to the IP core designed and developed independently), identifies the serial data according to the set baud rate and word structure, and converts it into parallel data, which is sent to the receiving FIFO, and the AXI bus reads the data through the receiving FIFO. The sending process: the data is written into the sending FIFO in the RS422 processing logic circuit through the AXI bus, the sending logic identifies the non-empty FIFO, automatically reads the data from the sending FIFO, and sends the serial signal to the RS422 function circuit according to the set baud rate and word structure. In addition, the 11.0592MHz clock signal has the following advantages in the RS422 processing logic circuit: 1) baud rate generation: the baud rate / control word setting module provides a reference clock. After the 11.0592MHz clock is processed by a specific frequency division, various commonly used baud rate clock signals can be obtained. By dividing the reference clock by different multiples, the baud rate / control word setting module can generate baud rates that meet different communication requirements, thereby ensuring that the RS422 processing logic circuit can normally communicate with RS422 devices of different baud rates. 2) Synchronization signal processing: as the time reference of the entire RS422 processing logic circuit, it is used to synchronize the operation of each module. The 11.0592MHz clock signal can provide a stable time reference for sampling operations, ensuring that the receiving logic can accurately capture and process serial data. In the sending logic, the serial signal needs to be sent according to the set baud rate based on the clock signal, to ensure the accuracy and stability of data transmission.

[0049] Through this design, the RS422 function circuit can achieve the following functional indicators: ①Number of channels: 8 channels, channel isolation. ②Baud rate: 9.6Kbps~1024Kbps. ③Digital bits: 5, 6, 7, 8. Stop bit: 1, 1.5, 2. Check bit: None, Even, Odd, Space, Mark.

[0050] None is no parity bit, that is, no check information is added in the data transmission process. The sending end directly sends the data bits according to the set format (digital bits, stop bits, etc.), and the receiving end also does not perform check-related processing on the data.

[0051] Even is even parity: when sending data, the sending end calculates the number of "1"s in the data bits. If the number of "1"s is odd, a "1" is added to the check bit, so that the total number of "1"s in the data bits and the check bit is even; if the number of "1"s is even, the check bit is "0". After receiving the data, the receiving end also calculates the number of "1"s in the data bits and the check bit. If the result is odd, it means that the data may have errors in the transmission process.

[0052] Odd is odd parity: contrary to even parity, the sending end calculates the number of "1"s in the data bits. If the number of "1"s is even, a "1" is added to the check bit, so that the total number of "1"s in the data bits and the check bit is odd; if the number of "1"s is odd, the check bit is "0". After receiving the data, the receiving end calculates the number of "1"s. If the result is even, it means that the data transmission may have errors.

[0053] Space is space parity: the sending end does not matter the value of the data bit, the check bit is always fixed as "0". In the receiving end, it will check whether the check bit is always "0". If it is not "0", it is considered that the data transmission has errors.

[0054] Mark is mark parity: the sending end does not matter the value of the data bit, the check bit is always fixed as "1". The receiving end checks whether the check bit is always "1". If it is not, it is determined that there is an error in the data transmission process. Similarly, the error detection capability of this check method is limited, which is only based on the fixed value of the check bit for simple judgment.

[0055] For the state quantity function circuit, it includes a 64-channel optocoupler isolation circuit for a 28V signal. Each channel is isolated, and the input channel is isolated from the device ground, such as Figure 6The optical coupling isolation circuit is shown in the figure. The optical coupling model of the optical coupling isolation circuit is HT281-4. Each channel includes an IN+ pin (positive input pin) and an IN- pin (negative input pin). The IN+ pin is the positive input end of the differential signal, which is used to receive the positive component of the differential signal transmitted by the external circuit through the device interface. In differential signal transmission, the signal is transmitted in two complementary forms (positive and negative). The IN+ pin is responsible for carrying the positive part of the signal, which helps to improve the anti-interference ability of signal transmission, reduce the influence of external noise on the signal, and ensure that the core processing unit can accurately receive the effective signal from the device interface. The IN- pin is the negative input end of the differential signal, which is used to receive the negative component of the differential signal transmitted by the external device interface. The IN- pin and the IN+ pin together form a differential signal pair. By comparing the difference between the signals on the IN+ pin and the IN- pin, the effective data can be extracted. This differential transmission method can effectively suppress common mode interference (such as electromagnetic interference), ensuring the accuracy and stability of signal transmission even in an environment with interference, so that the core processing unit can reliably obtain information from the device interface. Through this design, the state quantity functional circuit can achieve the following functional indicators: ① When the input signal voltage is less than 8V, the signal is "0". ② When the input signal voltage is greater than 16V, the signal is "1".

[0056] As an optional implementation, the multifunctional low-frequency test device further includes a power supply and a case. The power supply is connected to the core processing unit. The power supply, the core processing unit, the multiplexing functional circuit, the AD functional circuit, the 4M 1553B functional circuit, the RS422 functional circuit, the relay functional circuit, the DMM functional circuit, and the state quantity functional circuit are arranged in the case.

[0057] The power supply is an AC / DC power supply, which has the following characteristics: (1) ultra-wide input voltage range: 85-305VAC / 88-430VDC; (2) ultra-wide operating temperature range: -40℃~+85℃; (3) high reliability and low ripple noise; (4) EMI performance meets CISPR32 / EN55032 CLASS B; (5) meets 1.2 / 50us 5KV impulse voltage requirements; (6) complies with UL / EN62368, BSEN 62368 certification standards; (7) size is 105mm×50mm, height is 30mm.

[0058] As an optional implementation, the AD functional circuit includes an input isolation and limiting circuit, a multiplexing circuit, a programmable amplification circuit, and an A / D converter. The input isolation and limiting circuit is connected to the multiplexing circuit. The programmable amplification circuit is connected to the multiplexing circuit and the A / D converter, respectively. The A / D converter is connected to the core processing unit.

[0059] For example, as shown in the figure,Figure 7 As shown in the figure, the AD function circuit includes eight groups of the same input isolation and limiting circuit. The input isolation and limiting circuit selects the high-precision signal conditioning chip TE5550CN, which can realize the effective isolation of all channels of the AD function circuit. The multi-channel gating circuit is an eight-to-one analog switch SB508A, which can realize reliable switching of the input voltage in the range of -10V~10V. The program-controlled amplification circuit realizes four-grade program-controlled amplification by using a relay to switch the feedback resistor of an operational amplifier, and the operational amplifier selects the HHDJ7188F1 type instrument amplifier. The A / D converter selects the successive approximation type conversion chip SAD7606EN, which has six input channels, a resolution of up to 16 bits, and a maximum sampling rate of up to 250kSa / s. In addition, considering that the multi-functional low-frequency test equipment provided in the present application has a large enough DDR3 SDRAM (third generation double data rate synchronous dynamic random access memory) capacity, it can fully meet the requirement of 4MSa / CH. Through the above design, the AD function circuit can realize the following functional indicators: ① Channel number: the 32 channels of the AD function circuit are completely isolated. ② Input range: ±10V (4-grade program-controlled). ③ Sampling frequency: 40kHz per channel. ④ Time base accuracy: ±15ppm. ⑤ DC error: <0.5%. ⑥ Storage depth: 4MSa / CH.

[0060] As an optional embodiment, as shown in Figure 8 As shown in the figure, the DMM function circuit includes a relay channel switching circuit, an AC / DC voltage conditioning circuit (including low-voltage direct connection and high-voltage attenuation), an AC / DC effective value measurement circuit, a resistance measurement conversion circuit (i.e. R / V conversion), a multi-channel selector, a voltage amplification circuit, and an AD conversion circuit.

[0061] The relay channel switching circuit is connected with the AC / DC voltage conditioning circuit, the resistance measurement conversion circuit, and the core processing unit. The multi-channel selector is connected with the AC / DC voltage conditioning circuit, the resistance measurement conversion circuit, and the voltage amplification circuit. The voltage amplification circuit is connected with the AD conversion circuit and the AC / DC effective value measurement circuit. The AC / DC effective value measurement circuit is connected with the AD conversion circuit. The AD conversion circuit is connected with the core processing unit.

[0062] Among them, the multiplexer selects an eight-to-one analog switch SB508A, which can realize reliable switching of input voltage in the range of -10V~10V. The operational amplifier used in the voltage amplification circuit is Sengbon Microelectronics' s dual-channel operational amplifier SGM8249-2. The A / D conversion circuit selects HWD7734MAI chip, which contains 4 input channels with a resolution of up to 24 bits. In addition, in order to reduce interference, magnetic isolation chips JS1400 and JS1401 are used in this design to achieve effective isolation of the signals of the digital and analog parts. The relay channel switching circuit also has overload protection. Through the above design, the resistance voltage measurement function can achieve the following function indicators: ①It can measure the effective value and resistance value of DC voltage and AC voltage. ②Resolution: not less than 5½-digits. ③DC / AC voltage measurement range: 300Vrms or 300Vdc. ④Resistance measurement range: ≤20MΩ.

[0063] As an optional implementation, as shown in Figure 9 The relay function circuit includes a driving chip and a relay. The driving chip is connected with the relay and the core processing unit respectively. Among them, the driving chip selects ULN2402A, which can provide a maximum driving current of 500mA. The relay selects 6A relay HFD41F, which has a maximum switching voltage of 400VAC / 300DC, an action time of less than 8ms, and a release time of less than 4ms. One driving chip and one relay form a relay sub-circuit, and the relay function circuit includes 30 relay sub-circuits. Through the above design, the relay function circuit can achieve the following function indicators: ①Switching voltage: 220VDC / 250VAC. ②Switching current: 3A. ③Switching speed: <10ms. ④Number of ways: 30.

[0064] In addition, 30 high-speed signal relays are used to realize a 30-way two-wire signal multiplexer function circuit for switching the signal path of the measured object. Among them, the high-speed signal relay selects HFD42 type signal relay, which has a maximum switching voltage of 250VAC / 220VDC, supports 110VDC / 0.5A or 125VAC / 0.5A contact load, contact resistance is less than 0.1Ω, insulation resistance is more than 1000MΩ, and its action time and release time are both within 3ms. Through the above design, the multiplexer circuit can achieve the following function indicators: ①Maximum input voltage: 100V rms or 100VDC. ②Maximum input current: 0.5AAC rms or DC. ③Closed impedance: ≤1.0Ω (initial). ④Insulation resistance: >100MΩ. ⑤Switching speed: <3ms (on).

[0065] As an optional implementation, the network interface circuit includes a network protocol chip and a network connector. The network protocol chip is connected with the core processing unit and the network connector respectively.

[0066] The network interface circuit is used to realize the communication between the core processing unit and the host computer, receive the monitoring command from the host computer, and return the monitoring data, state and data processing result. The network interface circuit includes two parts of network connector and network protocol chip, as shown in Figure 10 .

[0067] The network protocol chip selects the YT8511 chip of Yutai Microelectronics. The chip internally integrates MAC and PHY protocol stack, supports TCP / IP, UDP, IPv4, ICMP, ARP, IGMP, PPPoE Ethernet protocol, internally integrates 16K memory, and integrates 4-way SOCKET. The YT8511 chip supports three kinds of control interfaces: SPI interface, direct parallel interface and indirect parallel interface. In the embodiment, the direct parallel interface is used for control. The network connector is the HR911130A chip of Hanren, which has the functions of 10M / 100M / 1000M network equipment connection, network signal coupling, double-color LED signal indication, built-in network transformer / filter circuit optional, POE self-power supply function optional. Through the above design, the expandable function board can realize the gigabit communication with the host computer module.

[0068] As an optional implementation, the integrated instrument resource module and the power supply can be integrated and arranged in the case in combination with the structure in the above embodiment. The display screen is embedded on the case, and the five data interfaces XS401-XS405 and J1 and J2 are arranged on the case. The J1 and J2 are connection interfaces of the integrated instrument resource module, which are used to connect different functional circuits and expansion modules. As shown in Figure 11 . Among them, in the case, the XS401 interface is connected with the network interface circuit; the XS402 interface is connected with the state quantity functional circuit; the XS403 interface is connected with the multiplexing functional circuit, the AD functional circuit and the DMM functional circuit respectively; the XS404 interface is connected with the relay functional circuit; and the XS405 interface is connected with the 4M 1553B functional circuit and the RS422 functional circuit respectively.

[0069] The host computer is connected with XS401 through interface (through data line, Bluetooth, etc.) to communicate with the core processing unit to make the core processing unit obtain task instructions through the network interface circuit, and connect the system under test with any one or more of XS402~XS405. The task instructions include: analog signal measurement instruction, multimeter measurement instruction, digital signal measurement instruction, relay control instruction, multi-channel selection instruction, RS422 communication instruction and 4M 1553B communication instruction. The core processing unit generates control instructions according to the task instructions, and then makes the corresponding circuit obtain the corresponding signal data from the system under test based on the control instructions, and transmits to the core processing unit for processing, and finally obtains the test result. The test result can be transmitted to the host computer through the network interface circuit for viewing or storage.

[0070] For example, if the communication function of the system under test is tested, the network interface circuit obtains the RS422 communication instruction and the 4M 1553B communication instruction issued by the host computer, generates corresponding control instructions (including RS422 instructions and 4M 1553B instructions) in the core processing unit, and the 4M 1553B function circuit and the RS422 function circuit respectively obtain signal data from the system under test through the XS405 interface according to the corresponding control instructions, and finally process in the core processing unit to obtain the test result. Other test tasks are the same.

[0071] In an exemplary embodiment, the process of executing customer tasks on the multifunctional low-frequency test device in the above embodiment (i.e. after the multifunctional low-frequency test device is connected with the system under test, the process of accepting the task instruction of the host computer and completing the task instruction) is described.

[0072] 1. The implementation process of network communication is shown in Figure 12 , including: Step 1: After the program of the processing system (PS) is started, the initialization operation is performed on other peripherals, specifically including: the ARM processor of the core processing unit activates the power supply, display screen, network interface circuit, etc. through the initialization instruction, and ensures that the hardware is ready. Provide a basic environment for the normal operation of each functional module, and ensure that the hardware device is in working condition.

[0073] Step 2: Call API to complete the initialization of TCP / IP protocol stack, specifically including: the ARM processor runs the protocol stack software, controls the YT8511 chip through the direct parallel interface, and configures the network communication parameters. Establish the protocol basis of network communication, and make the device have the network data transmission capability.

[0074] Step 3: Create a network data transmission thread and establish a listener, prepare to connect with the host computer, including: the ARM processor creates a thread to allocate memory resources, the network interface circuit receives the host computer connection request through the HR911130A connector, and the hardware level realizes signal coupling through the network transformer. Start network connection listening and wait for the host computer's connection request to prepare for communication between the device and the host computer.

[0075] Step 4: Continuously monitor whether there is a connection request from the host computer in the network data transmission thread, including: the YT8511 chip detects physical layer signals in real time, transmits the connection request to the ARM processor through the SPI interface, and the thread loops to query the request state. Discover the host computer's connection intention in time to establish a communication link.

[0076] Step 5: After detecting the host computer's connection request and establishing a network connection, always receive the client's (host computer) data, including: the host computer data enters the YT8511 chip through the HR911130A, and after being converted into a digital signal, it is transmitted to the receiving buffer of the ARM processor part through the AXI bus. Ensure that the device can obtain the control commands and data sent by the host computer in real time.

[0077] Step 6: Select and execute the corresponding function by parsing the command code (i.e. task instruction) of the received data, including: the ARM processor parses the command and sends the instruction to the FPGA part through the internal bus, and the FPGA triggers the corresponding function module. According to the instructions of the host computer, drive the device to perform specific operations to realize human-computer interaction.

[0078] Step 7: Continuously monitor the task instructions from the host computer until the host computer actively disconnects, including: the ARM processor thread remains in a loop, the network interface circuit continuously detects the link state, and releases the thread resources when disconnected. Maintain communication status with the host computer to ensure that the device can respond to various instructions from the host computer in a timely manner until the communication ends.

[0079] 2. The core processing unit processes task instructions and drives the corresponding circuit to execute the implementation process of the task as shown in Figure 13 , including: Step 1: After the PS network port receives the data packet, call the callback function, including: the data packet received by the network interface circuit is processed by the YT8511 chip, triggering the interrupt callback function of the ARM processor, starting the data processing flow. Trigger the processing flow of the received data to ensure that the data can be processed in time.

[0080] Step 2, the data packet is parsed in the callback function, the command number is obtained, including: the ARM processor part parses the data packet format through a software algorithm, and extracts the command number. The instruction type sent by the upper computer is determined, which provides a basis for subsequent instruction execution.

[0081] Step 3, according to the command number, corresponding processing is made, the task is divided into seven categories according to the function module, namely analog signal measurement instruction, multimeter measurement instruction, digital signal measurement instruction, relay control instruction, multi-channel selection instruction, RS422 communication instruction and 4M 1553B communication instruction (i.e. determining the type of task instruction). Different types of instructions are classified and processed, so that the device can execute various functions in an orderly manner, and the stability and maintainability of the system are improved.

[0082] Step 4, for each category of task, its corresponding subtask is executed (the specific subtask is set according to the board card requirement), including: (1) analog signal measurement: FPGA trigger input isolation and limiting circuit (TE5550CN chip): pre-process the input analog signal, limit the peak interference. Control SB508A analog switch: gate the target channel, switch the measured signal. Drive program-controlled amplification circuit (HHDJ7188F1 operational amplifier): automatically adjust the gain according to the signal amplitude. Start SAD7606EN AD conversion chip: convert the analog signal to 16-bit digital quantity at a rate of 200kSPS, and return to FPGA processing through SPI bus. (2) Multimeter measurement: FPGA writes configuration instructions to HWD7734MAI chip. The internal constant current source module outputs 1mA test current, which is connected to the measured resistance through the relay. The voltage feedback end signal is collected and converted to resistance value. When measuring voltage / current, the AD conversion result is directly collected and returned to FPGA through SPI. (3) Digital signal measurement: the measured switch quantity signal is isolated by HT281-4 optocoupler and converted to TTL level. FPGA reads the level state in real time. When measuring pulse frequency, start the FPGA internal counter logic to count the high-frequency pulse signal output by the optocoupler and convert it to frequency value. (4) Relay control: FPGA outputs control signals to the relay drive circuit. The drive circuit outputs 5V voltage to trigger the HFD41F relay coil to attract. The relay contact switches to realize the on-off control of the external circuit. The contact state is detected by the optocoupler and returned to the FPGA to confirm the execution result. (5) Multi-channel selection: FPGA outputs channel encoding. The encoding signal is converted to relay control signal by the decoding circuit to drive the HFD42 relay matrix switch. The measured signal of the selected channel is connected to the later stage measurement circuit. (6) RS422 communication: FPGA writes data to be sent to CA-IS3098W transceiver. The transceiver converts TTL level to RS422 differential signal (A+ / B-), which is enhanced by isolation transformer for anti-interference capability. When receiving, the differential signal is restored to TTL level by the transceiver and returned to FPGA for analysis through UART interface. (7) 4M 1553B communication: FPGA enables HT-61843GB-1 chip through 4M SC. Write instruction data to 4M D [15:0] data bus and select communication mode through 4MA [12:0] address bus. The chip converts parallel data to 1553B bus signal and connects to the bus through isolation transformer. When receiving, the bus signal is converted to parallel data by the chip after isolation by the transformer, and FPGA reads the data through 4M INT interrupt pin to realize real-time response. The above processes (1)~(7) can realize the specific functions of multifunctional low-frequency test equipment and meet different measurement, control and communication requirements.

[0083] In an exemplary embodiment, the chassis and the layout of various components on or in the chassis in the above embodiments are described.

[0084] The chassis has the following dimensions: W420xH88.9 (2U)xD400mm (widthxheightxdepth). U represents the height specification of the rack device, and 2U=88.9mm. The front panel layout design of the multifunctional low-frequency test device is shown in Figure 14 The front panel is provided with a display screen 1 and a switch 2, etc. The rear panel layout design of the multifunctional low-frequency test device is shown in Figure 15 The rear panel is provided with an air switch 3, a ruggedized LAN module 4, a power supply interface 5, and XS401-XS405 data interfaces, etc. The left side panel layout design of the multifunctional low-frequency test device is shown in Figure 16 The ruggedized LAN module is a LAN module (or interface) with a reinforced structure and anti-interference and anti-harsh environment capabilities, which can ensure stable network data transmission of the multifunctional low-frequency test device under complex working conditions.

[0085] Through the above embodiments, the multifunctional low-frequency test device provided by the application has the following advantages: 1. High-precision measurement: The AD conversion circuit in the DMM function circuit adopts HWD7734MAI chips and precise analog circuit design, such as an eight-to-one analog switch SB508A for a multiplexer and a dual-channel operational amplifier SGM8249-2 in a voltage amplification circuit, so that the resistance voltage measurement resolution is not less than 5½-digits, the DC / AC voltage measurement range is up to 300Vrms or 300Vdc, and the resistance measurement range is ≤20MΩ; the A / D conversion circuit has a direct current error of <0.5%, a time base accuracy of ±15ppm, and can realize high-precision signal measurement and data acquisition, meet the needs of high-end test scenarios, and ensure the accuracy and stability of measurement.

[0086] 2. High reliability: Long-term verified reliable chips are selected, such as FMQL45T900 chips and HT-61843GB-1 chips. The device has perfect self-checking functions and anti-interference design, such as optocoupler isolation circuit and overload protection, which improves the reliability and stability of the device in complex environments.

[0087] 3. Multifunctional integration: Various functional circuits are integrated on one circuit board to form an integrated instrument resource module, which realizes the integration and collaborative work of multifunctional circuits and the design of “All in One” through the unified control and coordination of the core processing unit, reduces the size and complexity of the device, and improves its consistency and maintainability.

[0088] 4. Flexible communication capability: The independent design of 4M 1553B function circuit and RS422 function circuit and the support of standardized protocol enable the device to be compatible with and interact with different communication protocols and systems. The device supports 4M 1553B communication (compatible with GJB 289A - 97 requirements, optional BC, RT or MT working mode) and 8-way RS-422 communication (Baud rate 9.6Kbps ~ 1024Kbps, multiple parameters configurable), and can interact with and communicate with different devices and systems, and is suitable for various application scenarios.

[0089] 5. Wide working range: The components such as power supply and display screen have a wide working temperature range, for example, the working temperature of the power supply is -40℃ ~ +85℃, and the working temperature of the display screen is -43℃ ~ +70℃, so that the device can work normally in harsh environmental conditions.

[0090] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data need to comply with relevant regulations.

[0091] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0092] The principles and implementation modes of the present application are described by applying specific examples in the present application. The above embodiment descriptions are only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In conclusion, the content of the present application should not be understood as a limitation.

Claims

1. A multi-functional low frequency test apparatus characterized by comprising: The multifunctional low-frequency test device comprises a core processing unit and a multiplexing function circuit, an AD function circuit, a 4M 1553B function circuit, an RS422 function circuit, a relay function circuit, a DMM function circuit, a state quantity function circuit and a network interface circuit connected with the core processing unit. The network interface circuit is used for obtaining a task instruction. The core processing unit is used for generating a control instruction based on the task instruction; the multiplexing function circuit, the AD function circuit, the 4M 1553B function circuit, the RS422 function circuit, the relay function circuit, the DMM function circuit and the state quantity function circuit are all used for obtaining corresponding signal data from a system to be tested based on the control instruction; and the core processing unit is further used for processing the signal data to obtain a test result. The multifunctional low-frequency test device further comprises a display screen connected with the core processing unit.

2. The multi-functional low frequency test equipment of claim 1, wherein, The display screen is used for displaying the working state of the core processing unit. The core processing unit comprises a main controller, a 4M 1553B control logic circuit, an RS422 processing logic circuit, a multimeter processing logic circuit, an AD control logic circuit, a switching quantity test processing logic circuit, a relay control logic circuit and a MUX control logic circuit.

3. The multi-functional low frequency test equipment of claim 1, wherein, The main controller is connected with the 4M 1553B control logic circuit, the RS422 processing logic circuit, the multimeter processing logic circuit, the AD control logic circuit, the switching quantity test processing logic circuit, the relay control logic circuit and the MUX control logic circuit through an AXI bus. The 4M 1553B control logic circuit is connected with the 4M 1553B function circuit; the RS422 processing logic circuit is connected with the RS422 function circuit; the multimeter processing logic circuit is connected with the DMM function circuit; the AD control logic circuit is connected with the AD function circuit; the switching quantity test processing logic circuit is connected with the state quantity function circuit; the relay control logic circuit is connected with the relay function circuit; and the MUX control logic circuit is connected with the multiplexing function circuit. The main controller is used for generating a control instruction based on the task instruction; the 4M 1553B control logic circuit is used for controlling the 4M 1553B function circuit based on the control instruction; the RS422 processing logic circuit is used for controlling the RS422 function circuit based on the control instruction; the multimeter processing logic circuit is used for controlling the DMM function circuit based on the control instruction; the AD control logic circuit is used for controlling the AD function circuit based on the control instruction; the switching quantity test processing logic circuit is used for controlling the state quantity function circuit based on the control instruction; the relay control logic circuit is used for controlling the relay function circuit based on the control instruction; and the MUX control logic circuit is used for controlling the multiplexing function circuit based on the control instruction. ​ 4. The multi-functional low frequency test equipment of claim 3, wherein, The 4M 1553B control logic circuit comprises a control circuit and a data address circuit; the control circuit and the data address circuit are connected with the 4M 1553B function circuit; The control circuit is used for controlling the 4M 1553B function circuit based on the control instruction; The data address circuit is used for data transmission with the 4M 1553B function circuit.

5. The multi-functional low frequency test equipment of claim 3, wherein, The RS422 processing logic circuit adopts a general asynchronous transceiver.

6. The multi-functional low frequency test device of claim 1, wherein, The multifunctional low-frequency test equipment further comprises a power supply and a case; The power supply is connected with the core processing unit; the power supply, the core processing unit, the multiplexing function circuit, the AD function circuit, the 4M 1553B function circuit, the RS422 function circuit, the relay function circuit, the DMM function circuit and the state quantity function circuit are arranged in the case.

7. The multi-functional low frequency test device of claim 1, wherein, The AD function circuit comprises an input isolation and limiting circuit, a multipath gating circuit, a program-controlled amplification circuit and an A / D converter; The input isolation and limiting circuit is connected with the multipath gating circuit; the program-controlled amplification circuit is connected with the multipath gating circuit and the A / D converter respectively; the A / D converter is connected with the core processing unit.

8. The multi-functional low frequency test device of claim 1, wherein, The DMM function circuit comprises a relay channel switching circuit, an AC / DC voltage conditioning circuit, an AC / DC effective value measurement circuit, a resistance measurement conversion circuit, a multipath selector, a voltage amplification circuit and an AD conversion circuit; The relay channel switching circuit is connected with the AC / DC voltage conditioning circuit, the resistance measurement conversion circuit and the core processing unit respectively; the multipath selector is connected with the AC / DC voltage conditioning circuit, the resistance measurement conversion circuit and the voltage amplification circuit respectively; the voltage amplification circuit is connected with the AD conversion circuit and the AC / DC effective value measurement circuit respectively; the AC / DC effective value measurement circuit is connected with the AD conversion circuit; the AD conversion circuit is connected with the core processing unit.

9. The multi-functional low frequency test device of claim 1, wherein, The network interface circuit comprises a network protocol chip and a network connector; the network protocol chip is connected with the core processing unit and the network connector respectively.

10. The multi-functional low frequency test device of claim 1, wherein, The relay function circuit comprises a drive chip and a relay; the drive chip is connected with the relay and the core processing unit respectively.

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