Reset control method and device, electronic equipment, storage medium and computer program product

Abstract

The embodiment of the invention provides a reset control method and device, electronic equipment, a storage medium and a computer program product, the reset control method is applied to a bare chip included in a chip, the chip comprises a master bare chip and at least one slave bare chip, and the method comprises the steps that a target reset request sent by a target reset source in a plurality of reset sources is received; determining a target reset control logic and a target reset domain corresponding to the target reset request; according to the target reset control logic, a reset signal is sent to a reset object included in the target reset domain, so that the reset object executes a reset action, and the reset object comprises at least part of functional modules in the master bare chip and / or at least part of functional modules in the slave bare chip. According to the scheme, multi-type, multi-layer and multi-bare-chip cooperative reset requirements in the multi-bare-chip system can be met, correct reset can be ensured, and normal temperature and function of the multi-bare-chip system can be ensured.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of computer, and in particular, to a reset control method and device, electronic equipment, storage medium and computer program product. BACKGROUND

[0002] Reset is an essential function of a chip, which is used to ensure that the chip starts working from a determined initial state. In a package or system including multiple dies, through specific design and control strategies, multiple dies can cooperatively perform reset operations to ensure that the entire system can work normally after reset, while avoiding system instability or functional abnormalities caused by the propagation and timing problems of the reset signal.

[0003] For a package or system including multiple dies, there are multiple types of resets covering different levels of reset objects, and multiple dies need to cooperatively perform reset operations. If the reset control is improper, it may lead to system instability or functional abnormalities. Therefore, how to determine the reset objects covered by the reset according to the reset type and control the reset objects to perform correct reset operations is a technical problem to be solved urgently. SUMMARY

[0004] In view of this, embodiments of the present disclosure provide a reset control method and device, electronic equipment, storage medium and computer program product to at least solve or alleviate the above problems.

[0005] According to a first aspect of embodiments of the present disclosure, a reset control method is provided, applied to a die included in a chip, the chip including a master die and at least one slave die, the method comprising: receiving a target reset request sent by a target reset source in multiple reset sources; determining a target reset control logic and a target reset domain corresponding to the target reset request; and sending a reset signal to a reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action, the reset object including at least part of functional modules in the master die and / or at least part of functional modules in the slave die.

[0006] According to a second aspect of embodiments of the present disclosure, a reset control device is provided, applied to a die included in a chip, the chip including a master die and at least one slave die, the device comprising: a receiving unit configured to receive a target reset request sent by a target reset source in multiple reset sources; a processing unit configured to determine a target reset control logic and a target reset domain corresponding to the target reset request; and a sending unit configured to send a reset signal to a reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action, the reset object including at least part of functional modules in the master die and / or at least part of functional modules in the slave die.

[0007] According to a third aspect of the embodiments of the present disclosure, an electronic device is provided, comprising a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to perform operations corresponding to the reset control method according to the first aspect.

[0008] According to a fourth aspect of the embodiments of the present disclosure, a computer storage medium is provided, and the computer storage medium stores a computer program, and the program is executed by a processor to implement the reset control method according to the first aspect.

[0009] According to a fifth aspect of the embodiments of the present disclosure, a computer program product is provided, comprising computer instructions, and the computer instructions instruct a computing device to execute the reset control method according to the first aspect.

[0010] According to the reset control scheme provided by the embodiments of the present disclosure, multiple reset sources can send reset requests, after receiving a target reset request sent by a target reset source in the multiple reset sources, a target reset control logic corresponding to the target reset request and a target reset domain are determined, and then a reset request can be sent to a reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action. The reset object can include at least part of the functional modules in the master die and / or the slave die. Since reset requests from multiple reset sources can be received, the corresponding reset control logic and reset domain are determined based on the received reset request, and the reset domain includes part or all of the functional modules in the master die and / or the slave die, so that the reset requirements of multiple types, multiple levels and multiple dies in the multi-die system can be met, and the temperature and function of the multi-die system can be ensured to be normal. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0012] Figure 1 is a schematic diagram of an exemplary system to which an embodiment of the present disclosure is applied;

[0013] Figure 2 is a flowchart of a reset control method according to an embodiment of the present disclosure;

[0014] Figure 3 is a flowchart of a reset signal sending method according to an embodiment of the present disclosure;

[0015] Figure 4 is a timing diagram of an iFLR of one embodiment of the present disclosure;

[0016] Figure 5 is a timing diagram of an iFLR of another embodiment of the present disclosure;

[0017] Figure 6 is a reset timing diagram of one embodiment of the present disclosure;

[0018] Figure 7 is a reset timing diagram of another embodiment of the present disclosure;

[0019] Figure 8 is a schematic diagram of a reset control device of one embodiment of the present disclosure;

[0020] Figure 9 is a schematic diagram of an electronic device of one embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The present disclosure is described below based on embodiments, but the present disclosure is not limited only to these embodiments. In the following detailed description of the present disclosure, some specific details are described in detail. The present disclosure can also be fully understood without the description of these details by those skilled in the art. In order to avoid confusion of the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0022] First, some nouns or terms appearing in the description of the embodiments of the present disclosure are applicable to the following explanations.

[0023] Chip: A chip, also known as an integrated circuit (IC), is a microelectronic device that integrates a large number of electronic components (such as transistors, resistors, capacitors, etc.) on a small semiconductor material. According to the function and purpose, the chip can be divided into various types, such as central processing unit (CPU), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), etc.

[0024] Die: Die refers to a single chip obtained after a wafer is processed, tested and cut in the semiconductor manufacturing process. The die only has pads for packaging and cannot be directly applied to actual circuits. Since the die is extremely susceptible to the effects of temperature, impurities and physical forces from the external environment, it is easily damaged, so it must be enclosed in a sealed space and the corresponding pins must be introduced to be used as a basic component.

[0025] Reset: Chip reset refers to the process of restoring the chip from the current state to the initial state. The initial state of the chip is usually the default configuration state after the chip is powered on. The internal resources such as registers, state machines, etc. are set to the initial value, the program counter points to the initial address, and waits for new instruction input.

[0026] PCIe: Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard used to connect computers and peripheral devices, widely used in desktop computers, servers, embedded systems and other devices. It is one of the important bus technologies in modern computer systems.

[0027] Exemplary system

[0028] Figure 1 An exemplary system suitable for the reset control method of the embodiments of the present disclosure is shown. As shown in Figure 1 The exemplary system includes a master Die 11 and a plurality of slave Dies 12, and the master Die 11 and the plurality of slave Dies 12 are interconnected, such as the master Die 11 can be interconnected with the slave Die 12 through a PCIe bus. The embodiments of the present disclosure do not limit the packaging relationship between the master Die 11 and the slave Die 12, such as the master Die 11 and the slave Die 12 included in the exemplary system can be packaged in the same chip, or the master Die 11 and part of the slave Die 12 are packaged in the same chip, or the slave Die 12 included in the exemplary system is packaged in the same chip, or the master Die 11 and the slave Die 12 are packaged as independent chips. When the master Die 11 and the slave Die 12 are packaged in the same chip, the master Die 11 and the slave Die 12 can communicate through an on-chip bus. When the master Die 11 and the slave Die 12 are packaged in different chips, the master Die 11 and the slave Die 12 can communicate through an inter-chip interconnection bus.

[0029] When the master Die 11 and the slave Die 12 included in the example system are packaged in the same chip, the example system can be a System On Chip (SoC) including a multi-Die chip. In addition to including the multi-Die chip, the SoC can also include a scheduling unit (such as a CPU, an ASIC, an FPGA, etc.). The scheduling unit can schedule the multi-Die chip to perform a computing task, such as scheduling the multi-Die chip to perform a model training task or a model inference task.

[0030] When the master Die 11 and the slave Die 12 included in the example system are packaged into different chips, the example system can be a SoC including multiple chips or an electronic device. If the example system is a SoC including multiple chips, in addition to including the chips corresponding to the master Die 11 and the slave Die 12, the SoC can also include a scheduling unit. If the example system is an electronic device, the electronic device includes a Printed Circuit Board (PCB), the chips corresponding to the master Die 11 and the slave Die 12 are connected on the PCB, and the scheduling unit is also connected on the PCB. The master Die 11 and the slave Die 12 are connected through wires in the PCB, and the scheduling unit and the master Die 11 are connected through wires in the PCB.

[0031] In one example, the master Die 11 and the slave Die 12 constitute a Graphics Processing Unit (GPU) including multiple basic computing units. The master Die 11 and the slave Die 12 respectively serve as basic computing units of the GPU. The basic computing unit can be a CUDA (Compute Unified Device Architecture) core or a Stream Processor (SP). The CPU can schedule the GPU to perform a computing task, such as scheduling the GPU to perform a model training task or a model inference task.

[0032] It should be noted that in addition to being able to communicate with the master Die 11, different slave Dies 12 can also communicate through an on-chip bus or an inter-chip bus.

[0033] The master Die 11 can reset part or all of the modules in the master Die 11 and / or the slave Die 12 according to a reset request from a reset source. The reset source can be of various types, such as a module in the master Die 11 or the slave Die 12, a watchdog, a scheduling unit, etc.

[0034] The present disclosure mainly focuses on the process of controlling the reset of the master Die 11 and the slave Die 12, which will be described in detail in the following.

[0035] Reset control method

[0036] Based on the above exemplary system, the embodiments of the present disclosure provide a reset control method, which can be executed by the master Die 11 or the slave Die 12 in the above exemplary system embodiment. The reset control method is described in detail through multiple embodiments as follows.

[0037] Figure 2 The reset control method is executed by the master Die 11 or the slave Die 12 in the above system embodiment. As shown in the figure, the reset control method includes the following steps: Figure 2

[0038] Step 201, receiving a target reset request sent by a target reset source in multiple reset sources.

[0039] The reset source is software or hardware that sends a reset request. There are multiple reset sources that can send a reset request. The current received reset request is defined as a target reset request, and the reset source that sends the target reset request in multiple reset sources is defined as a target reset source. The reset source can send a reset request to the master Die 11 or the slave Die 12. When the master Die 11 receives the target reset request, the master Die 11 resets the master Die 11, the master Die 11 and at least one slave Die 12, or at least part of the functional modules included in multiple slave Dies 12 based on the target reset request. When the slave Die 12 receives the target reset request, the slave Die 12 resets at least part of the functional modules included in the slave Die 12 based on the target reset request. That is, the master Die 11 can reset multiple Dies included in the chip according to the reset request, and the slave Die 12 can reset itself according to the reset request.

[0040] Step 202, determining a target reset control logic and a target reset domain corresponding to the target reset request.

[0041] After receiving the target reset request, the target reset control logic corresponding to the target reset request is determined from multiple reset control logics, and the target reset domain corresponding to the target reset request is determined. The reset control logic defines the operations required to be executed to achieve the reset and the timing of the operations, such as the type and timing of the signals sent and received to achieve the reset. The reset domain defines the reset objects involved in the reset operation, which includes at least part of the functional modules in the master Die 11 and / or at least part of the functional modules in the slave Die 12, that is, the reset domain defines which functional modules in the master Die 11 and / or the slave Die 12 need to be reset.

[0042] ​Different reset requests correspond to different reset domains, and different reset domains include different functional modules. For example, a global cross-die reset request (por_n) corresponds to a reset domain including all functional modules of the master die 11 and the slave die 12, a reset domain corresponding to a reset request (pf_cov_ctrl, pe_as_por) of a plurality of subsystems across dies is a plurality of subsystems included in the master die 11 and the slave die 12, a reset domain corresponding to a calculation subsystem cross-die reset request (pf_reset) is a calculation subsystem included in the master die 11 and the slave die 12, and a reset request (inter conn reset) of an interconnection subsystem corresponds to a reset domain including an interconnection subsystem included in the master die 11 and / or the slave die 12. The interconnection subsystem is used for inter-chip interconnection.

[0043] In one example, a plurality of reset control logics are stored in a memory of the chip, and the master die 11 and the slave die 12 can access the reset control logics stored in the memory. After receiving a target reset request, the master die 11 or the slave die 12 can read a target reset control logic corresponding to the target reset request from the memory, so that the master die 11 and the slave die 12 can share the reset control logic. For example, the chip memory stores a reset control logic A for resetting the interconnection subsystem, after receiving a reset request for resetting the interconnection subsystem, the master die 11 can read the reset control logic A from the chip memory, and after receiving a reset request for resetting the interconnection subsystem, the slave die 12 can read the reset control logic A from the chip memory.

[0044] In step 203, according to the target reset control logic, a reset signal is sent to a reset object included in the target reset domain, so that the reset object performs a reset action.

[0045] After determining the target reset control logic and the target reset domain, a reset signal is sent to a reset object included in the target reset domain according to the target reset control logic, so as to control the reset object to perform a reset action.

[0046] If the target reset domain only includes functional modules in the master Die 11, the master Die 11 sends a reset signal to the reset objects in the target reset domain according to the target reset control logic. If the target reset domain includes functional modules in the master Die 11 and at least one slave Die 12, the master Die 11 sends a reset signal to the reset objects in the target reset domain in the master Die 11 according to the target reset control logic, and sends a reset signal to the reset objects in the target reset domain in the slave Die 12 through the slave Die 12. If the target reset domain includes functional modules in multiple slave Dies 12, the master Die 11 sends a reset signal to the reset objects in the target reset domain in the slave Die 12 through the slave Die 12 according to the target reset control logic. If the target reset domain only includes functional modules in a slave Die 12, the slave Die 12 sends a reset signal to the functional modules in the target reset domain in the slave Die 12 according to the target reset control logic.

[0047] In the embodiments of the present disclosure, multiple reset sources can send reset requests, after receiving a target reset request sent by a target reset source in the multiple reset sources, the target reset request corresponding target reset control logic and target reset domain are determined, and then a reset request can be sent to the reset objects included in the target reset domain according to the target reset control logic, so that the reset objects perform a reset action. The reset objects can include at least part of the functional modules in the master Die 11 and / or the slave Die 12. Since reset requests from multiple reset sources can be received, the corresponding reset control logic and reset domain are determined based on the received reset requests, and the reset domain includes part or all of the functional modules in the master Die 11 and / or the slave Die 12, so that the reset requirements of multiple types, multiple levels and multiple Die coordination in the multi-Die system can be met, and the correct reset can be ensured, thereby ensuring the temperature and function of the multi-Die system to be normal.

[0048] In a possible implementation, the target reset request can be a soft reset with a protocol built-in handshake mechanism, a custom soft reset, a linked reset caused by a partial functional module reset, a gatekeeper reset under a protection mechanism, a reset under a debugging mechanism, etc.

[0049] The soft reset with a protocol built-in handshake mechanism is a function level reset (FLR), and the FLR mechanism enables software to reset a device with a function granularity. The FLR is mainly for a PCIe device supporting multiple functions (Multi-Fun PCIe Device), and can reset a specific function without affecting other functions. The reset source of the soft reset with a protocol built-in handshake mechanism can be software running on a CPU.

[0050] The custom soft reset can be a reset implemented by software of a microcontroller unit (MCU) or a control subsystem, and thus the reset source of the custom soft reset can be the MCU or the control subsystem.

[0051] The linkage reset caused by the partial function module reset includes a sideband signal reset (perst_n), a link down reset, and a hot reset. The sideband signal reset is a reset based on a sideband signal, and the sideband signal is used to trigger a fundamental reset of a PCIe device, including a cold reset and a warm reset. The sideband signal reset is triggered by power-on or power-off of a main power supply or by assertion of a register in a host, that is, the reset source of the sideband signal reset is the main power supply or the register in the host. The link down reset is a non-fundamental reset mode, and is a reset operation related to link down. The hot reset is an in-band reset, and is not triggered by a sideband signal. The hot reset is triggered by writing 0 and then 1 to a secondary bus reset bit in a configuration space of a specific port of a bridge device, that is, the reset source of the hot reset is the bridge device.

[0052] The watchdog reset under the protection mechanism is a reset triggered by a die watchdog, that is, the reset source of the watchdog reset under the protection mechanism is the die watchdog.

[0053] The reset under the debug mechanism (MCU debug reset) is a reset triggered by an MCU outside a die under a debug mechanism, that is, the reset source of the reset under the debug mechanism is the MCU outside the die.

[0054] In the embodiments of the present disclosure, the target reset request has multiple types, and can be a soft reset with a protocol self-held handshaking mechanism, a custom soft reset, a linkage reset caused by a partial function module reset, a watchdog reset under a protection mechanism, and a reset under a debug mechanism. Thus, the corresponding reset control logic and reset domain can be determined for different types of resets, to ensure that different types of resets can be correctly executed, and the stability of system operation is ensured.

[0055] In a possible implementation, when the target reset control logic corresponding to the target reset request is determined, the target reset control logic corresponding to the target reset request can be determined from multiple candidate reset control logics. At least part of the candidate reset control logics correspond to reset requests from multiple reset sources, and different candidate reset control logics correspond to reset requests from different reset sources.

[0056] A plurality of alternative reset control logics are pre-created, at least part of the alternative reset control logics correspond to reset requests from a plurality of reset sources, that is, some of the alternative reset control logics are applicable to reset requests from different reset sources, that is, some of the alternative reset control logics are multiplexed by a plurality of reset sources. After receiving a target reset request, a target reset control logic corresponding to the target reset request is determined from the plurality of alternative reset control logics.

[0057] In one example, the reset control logics of the sideband signal reset (perst_n), the link down reset, the hot reset, and the soft reset of the protocol handshake mechanism (FLR) are multiplexed by the reset control logic of the calculation subsystem cross Die reset (pf reset), that is, the sideband signal reset, the link down reset, the hot reset, the soft reset of the protocol handshake mechanism, and the calculation subsystem cross Die reset correspond to the same alternative reset control logic. The MCU reset enablings (MCU rst_en) and the watchdogs and the like MCU-related resets are multiplexed by the reset control logic of the MCU reset, that is, the MCU reset enablings and the watchdogs correspond to the same alternative reset control logic. The plurality of interconnection subsystem reset enablings (INTER CONN rst en) are multiplexed by the reset control logic of the interconnection subsystem reset (inter conn reset). The pf_cov_ctrl and the pe_as_por are two reset configurations of the reset domain optional multi-subsystem cross Die reset, the same reset source under different reset configurations will produce different reset effects, the pf_cov_ctrl multiplexes the reset control logic of the calculation subsystem cross Die reset (pf reset), and the pe_as_por multiplexes the reset control logic of the Power-On Reset (PoR) Finite State Machine (FSM) to complete the global reset and the re-power-on reset initialization of the whole chip.

[0058] In one example, the plurality of alternative reset control logics are stored in the memory of the chip, and different types of reset requests or reset requests from different reset sources share and multiplex the alternative reset control logics in the memory.

[0059] In the embodiments of the present disclosure, different types of reset requests or reset requests from different reset sources can multiplex the reset control logics, at least part of the alternative reset control logics are multiplexed by a plurality of different types of reset requests or reset requests from different reset sources, and the reset operations of each type of reset request can be implemented by a smaller number of alternative reset control logics, so that the alternative reset control logics occupy a smaller storage space, ensure the performance of the chip, and can make the chip reset system more simple.

[0060] In a possible implementation, the global reset request refers to a reset request affecting the entire chip, i.e., the global reset request causes all functional modules included in the master Die 11 and the slave Die 12 to reset, and the non-global reset request refers to a reset request affecting part of the chip, i.e., the non-global reset request causes part of the functional modules included in the master Die 11 and / or the slave Die 12 not to reset, and the other functional modules in the master Die 11 and the slave Die 12 except the functional modules not to reset are reset.

[0061] When the target reset request is a non-global reset request, an isolation signal (Resetiso) can be sent to at least part of the reset objects included in the target reset domain before a reset signal is sent to the reset objects included in the target reset domain, and the isolation signal can cause the signals at the boundary positions of the target reset domain in the master Die 11 and the slave Die 12 to return to the initial state.

[0062] In an example, a system control unit (SCU) in the master Die 11 or the slave Die 12 can select and initiate a suitable isolation mechanism according to the reset mode of the target reset request before sending the target reset request, and after completing the isolation task of the corresponding minimum granularity, the reset objects in the target reset domain are reset. The reset source can be some soft reset specified by a protocol or some data sequence (such as FLR, hot reset, etc.) specified by the protocol, can be some configurable registers (such as inter_conn_rst_en, mcu_sw_rst_en, and ctrl_sw_rst_en), can be some externally controlled reset signals (such as perst_n), or can be some abnormal events (such as linkdown and watchdog timeout) currently occurring.

[0063] In the embodiments of the present disclosure, the isolation signal is sent to the reset objects at the boundary positions of the target reset domain before the reset signal is sent, the isolation signal can be the signals at the boundary positions of the target reset domain in the master Die 11 and the slave Die 12 returning to the initial state, ensuring that the cross-Die signals are in a known state when the reset is released, and avoiding the metastable state caused by the timing deviation. The boundary signals of the reset domain are forced to return to the initial value, avoiding the logic confusion (such as deadlock and data conflict) caused by the incomplete reset of part of the modules, cooperating with the reset sequence control, ensuring the stability of the data path, and reducing the logic errors caused by the reset timing difference.

[0064] In a possible implementation, before sending the reset signal to the reset objects included in the target reset domain, a reset assertion guard signal can be sent to at least part of the reset objects included in the target reset domain, and the reset assertion guard signal can prevent the non-reset functional modules from being affected by the reset functional modules when the reset objects included in the target reset domain are asynchronously reset.

[0065] The reset assertion guard signal can activate an isolation and protection mechanism, ensure the protocol integrity of the interface before reset and return to the initial state, and ensure that the subsequent reset behavior will not affect the adjacent control modules.

[0066] After sending the reset signal to the reset objects included in the target reset domain, a reset deassertion guard signal can be sent to at least part of the reset objects included in the target reset domain, and the reset deassertion guard signal can prevent the reset residual data from being input into the de-reset reset objects. By sending the reset deassertion guard signal, when the reset is de-asserted, the residual data backflow time caused by the difference in reset time (to prevent the other party from being reset while the reset is de-asserted) can be prevented, and the protection guard can block the residual data to protect the circuit that is de-asserted first.

[0067] After sending the reset deassertion guard signal, a de-reset signal is sent to the reset objects included in the target reset domain according to the target reset control logic.

[0068] In an example, the SCU needs to reuse the reset control logic as much as possible and reasonably use the Reset iso or guard logic of the reset domain interface position during the control of the reset process, so as to achieve the purpose of minimum impact. For example, when the current reset configuration (pf_cov_ctrl or pe_as_por) changes, the SCU will select to expand or reduce the range of Reset iso / FLR on the current reset control logic, and after the Reset iso is ended, the current reset domain is expanded or reduced. If the reset configuration is a global reset mode, there will be no Reset iso initiated, and the logic of the local cross-die reset request (por_n) is directly reused, and after the reset, the power-on reset flow is restarted.

[0069] All reset sources share and reuse multiple reset isolation mechanisms and logic in the current chip memory, and the SCU is responsible for overall planning and handshaking. The SCU reuses reset control logic to simultaneously initiate corresponding Reset Assertion Guard and ResetDeassertion Guard. Reset Assertion Guard is used to protect functional modules that are not subject to reset, and ResetDeassertion Guard (mainly for the case where the reset of an interface intellectual property core such as PCIe is not controlled by the SCU, and after the PCIe reset, because the downstream computing subsystem needs to be reset in conjunction, and the reset in conjunction of the downstream computing subsystem needs to be completed after the reset isolation) is used to protect the reset of the upstream PCIe from occurring before the reset in conjunction of the downstream computing subsystem, and to block residual data from flowing to the reset upstream PCIe.

[0070] In the embodiments of the present disclosure, before sending the reset signal to the reset objects in the target reset domain, a reset activation protection signal is sent to at least part of the reset objects in the target reset domain, so that when the reset objects in the target reset domain are reset activated, the functional modules that have not been reset are not affected by the functional modules that have been reset. After sending the reset signal, a reset release protection signal is sent to at least part of the reset objects in the target reset domain to prevent residual data from being input to the reset objects that have been reset. By sending the reset activation protection signal and the reset release protection signal, it is ensured that the reset process can be correctly executed, and the stability and normal function of the chip after reset are ensured.

[0071] In a possible implementation, if the reset objects include at least part of the functional modules in the master Die 11 and at least one slave Die 12, when the master Die 11 sends the reset signal to the reset objects included in the target reset domain, the master Die 11 first acquires a master die isolation completion signal and a slave die isolation completion signal. The master die isolation completion signal is used to indicate that the signals located at the boundary position of the target reset domain in the master Die 11 return to the initial state, and the slave die isolation completion signal is used to indicate that the signals located at the boundary position of the target reset domain in the slave Die 12 return to the initial state. After the master Die 11 acquires the master die isolation completion signal and the slave die isolation completion signal, the master Die 11 sends a first reset signal to the reset objects located in the target reset domain in the master Die 11, and sends a second reset signal to the slave Die 12, so that the slave Die 12 controls the reset of the reset objects located in the target reset domain according to the second reset signal.

[0072] It should be noted that when the reset object includes multiple functional modules in the slave Die 12, the master Die 11 sends the first reset signal and the second reset signal after receiving the master die isolation completion signal and the slave die isolation completion signal returned by all slave Dies 12 in which the functional module is located in the target reset domain. After receiving the second reset signal, the slave Die 12 controls the functional module located in the target reset domain in the slave Die 12 to perform the reset action based on the second reset signal. The master Die 11 controls the functional module located in the target reset domain in the master Die 11 to perform the reset action through the first reset signal.

[0073] If the reset object includes at least part of the functional modules in the slave Die 12, the master Die 11 sends the reset signal to the reset object included in the target reset domain, and then the master Die 11 acquires the slave die isolation completion signal returned by all slave Dies 12 in which the functional module is located in the target reset domain. After receiving the slave die isolation completion signal returned by all slave Dies 12 in which the functional module is located in the target reset domain, the master Die 11 sends the second reset signal to each slave Die 12 in which the functional module is located in the target reset domain. After receiving the second reset signal, the slave Die 12 controls the functional module located in the target reset domain in the slave Die 12 to perform the reset action based on the second reset signal.

[0074] The responsibilities of the master Die 11 and the slave Die 12 are different. When the target reset domain includes functional modules in multiple Dies (the master Die 11 + the slave Die 12 or multiple slave Dies 12), the target reset source mainly reacts in the master Die, specifically in the SCU of the master Die, and the slave Die 12 is responsible for the reset control of the included functional modules. The master Die 11 controls the reset flow of multiple Dies (the master Die 11 + the slave Die 12 or multiple slave Dies 12), and the slave Die 12 collects its own information and returns it to the master Die 11. After collecting the isolation completion signals (the master die isolation completion signal and / or the slave die isolation completion signal) of multiple Dies (the master Die 11 + the slave Die 12 or multiple slave Dies 12), the master Die 11 initiates the corresponding reset signal (the first reset signal and / or the second reset signal), resets the master Die 11 at the same time, and transmits the reset signal to the slave Die 12. While the slave Die 12 cooperates with the master Die 11 to complete the current reset process, it ensures that the reset process with the master Die 11 is kept in synchronization.

[0075] In the embodiments of the present disclosure, when the reset object includes at least part of the functional modules in the at least two dies, the target reset source is mainly reflected in the master die, the master die controls the reset flow of the plurality of dies covered by the target reset domain, the slave die 12 sends a slave die isolation completion signal to the master die 11 after isolation is completed, and the master die 11 sends a first reset signal and a second reset signal after the master die 11 obtains the master die isolation completion signal and the slave die isolation completion signal. The master die 11 sends the reset signal to the slave die 12, and the slave die 12 cooperates with the master die 11 to complete the reset, and at the same time, the reset process of the slave die 12 is kept synchronous with the master die. The master die 11 controls the reset flow of the plurality of dies, and the slave die 12 cooperates with the master die 11 to control the reset of the functional modules included in the slave die 12, so that the reset process of the master die 11 and the slave die 12 is kept synchronous, and the reset process can be correctly performed, thereby ensuring that the system is stable and functional.

[0076] In a possible implementation, the first reset signal is a reset signal sent by the master die 11 to the functional module to be reset in the master die 11, and the second reset signal is a reset signal sent by the master die 11 to the functional module to be reset in the slave die 12. The second reset signal includes less information than the first reset signal.

[0077] In the embodiments of the present disclosure, the master die 11 controls the reset flow of the plurality of dies, and more reset information is transmitted between the master die 11 and the slave die 12. In order to reduce the input / output (I / O) resources occupied by the transmission of the reset information between the dies, the slave die 12 only receives the necessary multiplexed reset information, and the reset information of the master die 11 and the slave die 12 is asymmetric, that is, the second reset signal includes less information than the first reset signal. Therefore, the amount of data of the information transmitted between the dies in the reset process can be reduced, the occupation of the I / O resources by the reset information can be reduced, and the performance of the system in the reset process can be ensured.

[0078] In a possible implementation, when the target reset request is a linked reset (such as perst_n, linkdown reset, hot reset, etc.) caused by partial functional module reset, the master die 11 can send the first reset signal and the second reset signal to the master die 11 and the slave die 12, respectively, and the slave die 12 can send the first reset signal and the second reset signal to the master die 11 and the slave die 12, respectively. Figure 3 The reset signal sending method shown in FIG. 8 sends a reset signal to a reset object included in a target reset domain. As shown in FIG. 9, the reset signal sending method includes the following steps: Figure 3 The reset signal sending method shown in FIG. 8 sends a reset signal to a reset object included in a target reset domain. As shown in FIG. 9, the reset signal sending method includes the following steps:

[0079] Step 301: inputting a target reset request into a virtual function level reset state machine included in a master die, so that the virtual function level reset state machine generates an intermediate reset signal.

[0080] The control logic of the SCU mainly includes a virtual function level reset (VFLR) generator (VFLR_GEN) and a function level reset state machine (FLR_FSM). In the PCIe protocol, the VFLR is an independent reset mechanism for a virtual function (VF) in a single root I / O virtualization (SR-IOV) architecture. The SCU in the Die 12 does not contain the VFLR_GEN part.

[0081] The VFLR_GEN is responsible for receiving some interface reset events, such as perst_n, linkdown reset, hot reset, and the like. After the events occur, the VFLR imitates the handshaking mechanism of the VFLR in the PCIe protocol FLR part in a state machine manner. The state IDLE / BME / ACTIVE / RETIRE of the virtual function level reset state machine in the VFLR_GEN is a virtual FLR generator with configurable timing parameters set according to the FLR.

[0082] After receiving the target reset request, the main Die 11 inputs the target reset request into the virtual function level reset state machine, and the virtual function level reset state machine can generate an intermediate reset signal according to the target reset request.

[0083] In step 302, the intermediate reset signal is input into the function level reset state machine included in the main Die, so that the function level reset state machine included in the main Die generates a first reset signal, and the first reset signal is sent to a reset object in the target reset domain in the main Die.

[0084] VFLR_GEN multiplexes FLR_FSM with the FLR mechanism from PCIe, and FLR_FSM is responsible for receiving handshake signals of FLR from VFLR_GEN or PCIe, completing the handshake mechanism of Intelligent Function Level Reset (iFLR) in the Die, and sending the physical function reset signal (pf_rstb) of the Die. The Die 12 only receives the pf_rstb of the master Die 11. In the PCIe protocol, iFLR is an enhanced function level reset mechanism, aiming to optimize the efficiency and controllability of the traditional FLR. The pf_rstb signal acts on a single physical function (PF) module, resets its internal logic (such as configuration registers, state machines, data paths, etc.), but does not affect other PFs or virtual functions (VFs) in the same device. The reset domain of pf_rstb normally contains only a calculation subunit, and when pf_cov_ctrl is configured to enable, the reset domain of pf_rstb will be expanded to the control subsystem (including the inter-Die transmission module).

[0085] FLR_FSM mainly includes states such as DEASSERT / FLR_REQ / FLR_DONE / ASSERT, and is basically the timing control of the iFLR handshake mechanism and the timing control of the assertion / deassertion of pf_rstb.

[0086] After the master Die 11 inputs the intermediate reset signal into the FLR_FSM included in the master Die, the FLR_FSM included in the master Die 11 will generate a first reset signal according to the intermediate reset signal, and then can send the first reset signal to the reset object (function module) in the target reset domain in the master Die.

[0087] Step 303, input the intermediate reset signal into the function level reset state machine included in the slave Die, so that the function level reset state machine included in the slave Die generates a second reset signal, and sends the second reset signal to the reset object in the target reset domain in the slave Die.

[0088] After the virtual function level reset state machine in the master Die 11 generates the intermediate reset signal, the master Die 11 will input the intermediate reset signal into the FLR_FSM included in the master Die, and simultaneously input the intermediate reset signal into the FLR_FSM in the slave Die 12. The FLR_FSM in the slave Die 12 will generate a second reset signal according to the intermediate reset signal, and then can send the second reset signal to the reset object (function module) in the target reset domain in the slave Die 12.

[0089] In the embodiment of the present disclosure, the SCU control logic of the master Die 11 includes VFLR_GEN and FLR_FSM, the SCU control logic of the slave Die 12 includes FLR_FSM, when the target reset request is a virtual function level reset (such as perst_n, linkdownreset, hot reset, etc.), the VFLR_GEN generates an intermediate reset signal according to the target reset request, and inputs the intermediate reset signal into the FLR_FSM included in the master Die 11 and the slave Die 12 respectively, the FLR_FSM in the master Die 11 generates a first reset signal based on the intermediate reset signal, the FLR_FSM in the slave Die 12 generates a second reset signal based on the intermediate reset signal, so as to ensure that the master Die 11 and the slave Die 12 can normally process the virtual function level reset, simplify the reset process, and ensure the efficiency and reliability of the reset process.

[0090] In a possible implementation, when the target reset request is a soft reset (such as FLR) of a protocol self-handling mechanism, the master Die 11 inputs the target reset request into the FLR_FSM included in the master Die 11 and the slave Die 12 respectively, so that the FLR_FSM included in the master Die 11 generates a first reset signal, and the FLR_FSM included in the slave Die 12 generates a second reset signal. The master Die 11 sends the first reset signal to the reset object in the target reset domain in the master Die 11, and the slave Die 12 sends the second reset signal to the reset object in the target reset domain in the slave Die 12.

[0091] In the PCIe protocol, the FLR_FSM is a hardware state machine used for controlling and managing the function level reset (FLR) process.

[0092] In the embodiment of the present disclosure, when the target reset request is a soft reset of a protocol self-handling mechanism, the target reset request is input into the FLR_FSM included in the master Die 11 to generate a first reset signal, and the target reset request is input into the FLR_FSM included in the slave Die 12 to generate a second reset signal, and when the target reset request is a linkage reset caused by a partial function module reset, the intermediate reset signal is input into the FLR_FSM included in the master Die 11 to generate a first reset signal, and the intermediate reset signal is input into the FLR_FSM included in the slave Die 12 to generate a second reset signal, that is, the soft reset of the protocol self-handling mechanism and the linkage reset caused by the partial function module reset can reuse the FLR_FSM, without setting FSMs for the soft reset of the protocol self-handling mechanism and the linkage reset caused by the partial function module reset, so as to simplify the hardware structure of the Die, and reduce the manufacturing cost and power consumption of the Die.

[0093] In one possible implementation, the timing diagram of iFLR corresponding to soft reset with protocol handshake and the linkage reset caused by partial function module reset is different. Figure 4 The timing diagram of iFLR when the target reset request is soft reset with protocol handshake (taking perst_n as an example) is shown. Figure 5 The timing diagram of iFLR when the target reset request is linkage reset caused by partial function module reset (taking FLR as an example) is shown.

[0094] As shown in Figure 4 perst_n triggers the virtual function level reset state machine to send FLR_ACTIVE to the FLR_FSM of the master Die and the slave Die. The FLR_FSM triggers iFLR_req to each target module (function module to be reset) according to FLR_ACTIVE. The FLR_FSM returns iFLR_done after each target module completes the traffic drain task and ensures that the reset domain boundary position returns to the initial state. The FLR_FSM of the slave Die returns FLR_DONE to the FLR_FSM of the master Die after collecting iFLR_done of the slave Die. The FLR_FSM of the master Die initiates pf reset assertion to the master Die and the slave Die. After waiting for some time, the master Die withdraws iFLR_req, and the slave Die receives pf_rstb assertion sent by the master Die, which is used as iFLR_done to the FLR_FSM of the slave Die in addition to direct reset. The slave Die also waits for some time and withdraws iFLR_req. The target modules of the master Die and the slave Die can withdraw iFLR_done, and then after a certain assertion time, the FLR_FSM returns to the initial state, and the master Die withdraws pf_rstb.

[0095] As shown in Figure 5As shown, after the PCIe host configures the Device Control Register through a configuration write request (CFGWr request) to configure the iFLR, the PCIe sends FLR ACTIVE to the FLR FSM of the master Die and the slave Die. The FLR FSM triggers iFLR_req to each target module (with reset function module) according to the FLR ACTIVE. After each target module completes the traffic drain task and ensures that the reset domain boundary position returns to the initial state, iFLR_done is returned. The FLR FSM of the slave Die returns FLR_DONE to the FLR FSM of the master Die after collecting iFLR_done of the slave Die. The FLR FSM of the master Die initiates pf reset assertion to the master Die and the slave Die. After waiting for a period of time, the master Die withdraws iFLR_req, and the slave Die receives the pf_rstb assertion sent by the master Die, which is used as iFLR_done to the FLR FSM of the slave Die in addition to direct reset. After waiting for a period of time, the slave Die withdraws iFLR_req. The target module of the master Die and the slave Die can then withdraw iFLR_done. After a certain assertion time, the FLR FSM returns to the initial state, the master Die withdraws pf_rstb, and the master Die returns FLR_DONE to the PCIe. After a period of time, the master Die returns to normal.

[0096] In a possible implementation manner, Figure 6 and Figure 7 The timing diagram of reset under the watchdog reset / debug mechanism under other soft reset / protection mechanisms is shown. For reset under the watchdog reset / debug mechanism under other soft reset / protection mechanisms, before reset assertion, the SCU initiates reset isolation handshake of the corresponding minimum granularity, and completes reset assertion after the handshake ends. After waiting for a period of assertion time, the current reset is withdrawn, and the reset target module can withdraw the iso_done signal according to the req or rstb signal. Figure 6 The timing diagram shown is for withdrawing the iso_done signal according to the rstb signal, Figure 7 The timing diagram shown is for withdrawing the iso_done signal according to the req signal.

[0097] Reset control device

[0098] Figure 8A schematic diagram of a reset control apparatus 800 is shown, which is applied to a chip including a die, and the chip includes a master die and at least one slave die. As shown in the figure, the reset control apparatus 800 includes: Figure 8

[0099] A receiving unit 801 is configured to receive a target reset request sent by a target reset source in a plurality of reset sources;

[0100] A processing unit 802 is configured to determine target reset control logic and a target reset domain corresponding to the target reset request;

[0101] A sending unit 803 is configured to send a reset signal to a reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action, and the object includes at least part of functional modules in the master die and / or at least part of functional modules in the slave die.

[0102] In the embodiment of the present disclosure, the plurality of reset sources can send reset requests, after the receiving unit 801 receives a target reset request sent by a target reset source in the plurality of reset sources, the processing unit 802 determines target reset control logic and a target reset domain corresponding to the target reset request, and then the sending unit 803 can send a reset request to a reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action, and the reset object can include at least part of functional modules in the master die and / or at least part of functional modules in the slave die. Since reset requests from multiple reset sources can be received, the corresponding reset control logic and reset domain are determined based on the received reset requests, and the reset domain includes part or all of the functional modules in the master die and / or the slave die, so that the reset requirements of multiple types, multiple levels and multiple dies in the multi-die system can be met, and the temperature and function of the multi-die system can be ensured to be normal.

[0103] In a possible implementation, the processing unit 802 is also responsible for processing the interface isolation reset of the current die, and cooperates with the master die to control the isolation and reset. The processing unit 802 is responsible for processing and controlling the reset request, such as reasonably multiplexing the isolation and reset control logic according to the reset request, and controlling the isolation and interface protection.

[0104] It should be noted that the reset control apparatus of the embodiment is used to implement the reset control method in the foregoing method embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described here.

[0105] Electronic device

[0106] Figure 9 ​is a schematic block diagram of an electronic device provided by an embodiment of the present disclosure, and embodiments of the present disclosure do not limit the specific implementation of the electronic device. As shown in Figure 9 The electronic device can include a processor 902, a communications interface 904, a memory 906, and a communications bus 908. Among them:

[0107] The processor 902, the communications interface 904, and the memory 906 complete the communication among each other through the communications bus 908.

[0108] The communications interface 904 is configured to communicate with other electronic devices or servers.

[0109] The processor 902 is configured to execute the program 910, and specifically can execute the related steps in any of the preceding reset control method embodiments.

[0110] Specifically, the program 910 can include program code, and the program code includes computer operation instructions.

[0111] The processor 902 can be a CPU, or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present disclosure. One or more processors included in the smart device can be the same type of processor, such as one or more CPUs; or can be different types of processors, such as one or more CPUs and one or more ASICs.

[0112] RISC-V is an open-source instruction set architecture based on the principle of reduced instruction set (RISC), which can be applied to various aspects such as single-chip microcomputers and FPGA chips. Specifically, it can be applied in the fields of Internet of Things security, industrial control, mobile phones, personal computers, etc. And because it takes into account the realities of small, fast, and low power consumption when designing, it is particularly suitable for modern computing devices such as warehouse-scale computers, high-end mobile phones, and tiny embedded systems. With the rise of artificial intelligence Internet of Things (AIoT), the RISC-V instruction set architecture has also received more and more attention and support, and is expected to become the next generation of widely used CPU architecture.

[0113] The computer operation instruction in the embodiments of the present disclosure can be a computer operation instruction based on the RISC-V instruction set architecture, and correspondingly, the processor 902 can be based on the instruction set design of RISC-V. Specifically, the chip of the processor in the electronic device provided by the embodiments of the present disclosure can be a chip adopting the RISC-V instruction set design, which can execute executable code based on the configured instructions, thereby implementing the reset control method in the above embodiments.

[0114] The memory 906 is configured to store a program 910. The memory 906 can include a high-speed RAM memory, and can also include a non-volatile memory such as at least one disk memory.

[0115] The program 910 can be specifically configured to cause the processor 902 to perform the reset control method in any of the foregoing embodiments.

[0116] The specific implementation of each step in the program 910 can refer to the corresponding description in the corresponding steps and units of any of the foregoing reset control method embodiments, and will not be described here. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the devices and modules described above can refer to the corresponding process description in the foregoing method embodiments, which will not be described here.

[0117] Through the electronic device of the embodiments of the present disclosure, multiple reset sources can send reset requests, after receiving a target reset request sent by a target reset source in the multiple reset sources, a target reset control logic corresponding to the target reset request and a target reset domain are determined, and then a reset request can be sent to a reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action. The reset object can include at least part of the functional modules in the master Die and / or the slave Die. Since reset requests can be received from multiple reset sources, the corresponding reset control logic and reset domain are determined based on the received reset requests, and the reset domain includes part or all of the functional modules in the master Die and / or the slave Die, thereby meeting the reset requirements of multiple types, multiple levels and multiple Die coordination in the multi-Die system, ensuring correct reset, and thus ensuring the temperature and function of the multi-Die system to be normal.

[0118] Computer storage medium

[0119] The present disclosure also provides a computer readable storage medium storing instructions for causing a machine to perform the reset control method as described herein. Specifically, a system or device equipped with a storage medium can be provided, on which a software program code implementing the functions of any of the above embodiments is stored, and the computer (or CPU or MPU) of the system or device reads out and executes the program code stored in the storage medium.

[0120] In this case, the program code read from the storage medium itself can implement the functions of any of the above-described embodiments, and therefore the program code and the storage medium storing the program code constitute a part of the present disclosure.

[0121] Embodiments of the storage medium for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as a CD-ROM, a CD-R, a CD-RW, a DVD-ROM, a DVD-RAM, a DVD-RW, a DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer via a communication network.

[0122] Computer program product

[0123] The embodiments of the present disclosure also provide a computer program product comprising computer instructions instructing a computing device to perform any corresponding operation in the above-described method embodiments.

[0124] It should be noted that the information related to the user (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data for training the model, data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present disclosure are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of the related data need to comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for the user to choose authorization or refusal.

[0125] It should be noted that, according to the needs of implementation, each component / step described in the embodiments of the present disclosure can be split into more components / steps, or two or more components / steps or part of the operation of the components / steps can be combined into a new component / step to achieve the purpose of the embodiments of the present disclosure.

[0126] The method according to the embodiments of the present disclosure described above can be implemented in hardware, firmware, or as software stored in a recording medium such as a CD ROM, a RAM, a floppy disk, a hard disk, or a magneto-optical disk, or computer code downloaded over a network originally stored in a remote recording medium or a non-transitory machine-readable medium and to be stored in a local recording medium, so that the method described herein can be processed by such software using a general-purpose computer, a special-purpose processor, or programmable or special-purpose hardware such as an ASIC or an FPGA. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component (for example, a RAM, a ROM, a flash memory, and the like) that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method shown herein, the execution of the code will convert the general-purpose computer into a special-purpose computer for executing the method shown herein.

[0127] It should be noted that the information related to the user (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to sample data for training the model, data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present disclosure are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation portal for user to choose authorization or refusal.

[0128] Those of ordinary skill in the art can realize that the units and method steps of the examples described in combination with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for a specific application, but such implementation should not be considered beyond the scope of the embodiments of the present disclosure.

[0129] The above embodiments are only used to illustrate the embodiments of the present disclosure, and not to limit the embodiments of the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, therefore all equivalent technical solutions also belong to the scope of the embodiments of the present disclosure, the patent protection scope of the embodiments of the present disclosure should be defined by the claims.

Claims

1. A reset control method applied to a die included in a chip, the chip including a master die and at least one slave die, the method comprising: receiving a target reset request sent by a target reset source in a plurality of reset sources; determining a target reset control logic and a target reset domain corresponding to the target reset request; and sending a reset signal to a reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action, the reset object including at least part of functional modules in the master die and / or at least part of functional modules in the slave die. The target reset request includes a soft reset with a protocol self-handling mechanism, a custom soft reset, a cascaded reset caused by a partial functional module reset, a watchdog reset under a protection mechanism, or a reset under a debugging mechanism. The determination of the target reset control logic corresponding to the target reset request comprises: determining the target reset control logic corresponding to the target reset request from a plurality of alternative reset control logics, at least part of the alternative reset control logics corresponding to reset requests from a plurality of reset sources, and different alternative reset control logics corresponding to reset requests from different reset sources.

2. The method of claim 1, wherein, 4.The method of claim 1, when the target reset request is a non-global reset request, before sending the reset signal to the reset object included in the target reset domain, the method further comprises: sending an isolation signal to at least part of the reset objects included in the target reset domain, the isolation signal being used to return signals at a boundary position of the target reset domain in the master die and the slave die to an initial state.

3. The method of claim 1, wherein, 5.The method of claim 1, wherein, before sending the reset signal to the reset object included in the target reset domain, the method further comprises: sending a reset activation protection signal to at least part of the reset objects included in the target reset domain, the reset activation protection signal being used to prevent an unreset functional module from being affected by a reset functional module when the reset object included in the target reset domain is asynchronously reset activated; and after sending the reset signal to the reset object included in the target reset domain, the method further comprises: sending a reset deprotection signal to at least part of the reset objects included in the target reset domain, the reset deprotection signal being used to prevent reset residual data from being input to the reset object that has been de-reset; and sending a de-reset signal to the reset object included in the target reset domain according to the target reset control logic. When the reset object includes at least part of functional modules in at least two dies, the sending of the reset signal to the reset object included in the target reset domain comprises: the master die acquires a master die isolation completion signal and a slave die isolation completion signal, the master die isolation completion signal being used to indicate that signals at a boundary position of the target reset domain in the master die return to an initial state, and the slave die isolation completion signal being used to indicate that signals at the boundary position of the target reset domain in the slave die return to the initial state; ​ ​ ​ ​ 6. The method of claim 4, wherein, ​ ​ After the master die isolation completion signal and the slave die isolation completion signal are acquired, the master die sends a first reset signal to a reset object in the master die within the target reset domain, and sends a second reset signal to the slave die, so that the slave die controls the reset object within the target reset domain to reset according to the second reset signal.

7. The method of claim 6, wherein, The second reset signal includes less information than the first reset signal.

8. The method of claim 2, wherein, When the target reset request is a linked reset caused by the partial function module reset, the sending of the reset signal to the reset object included in the target reset domain comprises: inputting the target reset request into a virtual function level reset state machine included in the master die, so that the virtual function level reset state machine generates an intermediate reset signal; inputting the intermediate reset signal into a function level reset state machine included in the master die, so that the function level reset state machine included in the master die generates a first reset signal, and sends the first reset signal to the reset object in the master die within the target reset domain; inputting the intermediate reset signal into a function level reset state machine included in the slave die, so that the function level reset state machine included in the slave die generates a second reset signal, and sends the second reset signal to the reset object in the slave die within the target reset domain.

9. The method of claim 8, wherein, When the target reset source is a soft reset of a protocol self-held handshaking mechanism, the sending of the reset signal to the reset object included in the target reset domain comprises: inputting the target reset request into a function level reset state machine included in the master die, so that the function level reset state machine included in the master die generates a first reset signal, and sends the first reset signal to the reset object in the master die within the target reset domain; inputting the target reset request into a function level reset state machine included in the slave die, so that the function level reset state machine included in the slave die generates a second reset signal, and sends the second reset signal to the reset object in the slave die within the target reset domain. 10.A reset control apparatus, applied to a die included in a chip, the chip comprising a master die and at least one slave die, and the apparatus comprising: a receiving unit configured to receive a target reset request sent by a target reset source in a plurality of reset sources; a processing unit configured to determine target reset control logic and a target reset domain corresponding to the target reset request; a sending unit configured to send a reset signal to a reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action, the reset object comprising at least part of function modules in the master die and / or at least part of function modules in the slave die.

11. An electronic device comprising: a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface performing communication with each other through the communication bus; the memory is configured to store at least one executable instruction, and the executable instruction causes the processor to perform operations corresponding to any one of the methods in claims 1-9.

12. A computer storage medium having stored thereon a computer program which, when executed by a processor, implements the method of any one of claims 1-9.

13. A computer program product comprising computer instructions which instruct a computing device to perform the method of any one of claims 1-9.

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