Storage structure, routing method and computer readable storage medium

Abstract

The invention provides a storage structure, a routing method and a computer readable storage medium, a 3D network-shaped storage structure is formed in the storage structure, and in the 3D network-shaped storage structure, each flash memory unit can have a plurality of data transmission directions. Therefore, during data transmission, each flash memory unit in the 3D network-shaped storage structure can select from a plurality of communication lines connected with the flash memory unit to transmit data, so that the path diversity among flash memory chips is increased, the path blockage condition among the flash memory chips is reduced, and the data transmission efficiency is improved. The parallelism of the storage structure during processing of multiple I / O requests is increased, resulting in a reduction in latency in data transmission.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic circuits, and in particular to a storage structure, a routing method and a computer readable storage medium. BACKGROUND

[0002] A solid state disk is a storage device based on flash memory or other non-volatile storage media, and its core function is to efficiently store and read and write data. In order to meet the growing demand of modern data-intensive applications, the performance and capacity of solid state disks are also constantly improving. However, with the improvement of flash memory performance and the increase of bandwidth, since the solid state disk adopts a multi-channel shared bus architecture, that is, multiple memory chips connected on the same channel communicate with the solid state disk controller through a path. Therefore, path conflicts often occur during processing multiple I / O requests, which greatly limits the parallelism of the solid state disk. SUMMARY

[0003] The present application provides a storage structure, a routing method and a computer readable storage medium to increase the parallelism of the storage structure during processing multiple I / O requests.

[0004] According to a first aspect of the present application, a storage structure is provided, comprising: a plurality of layers of interconnected network structures, each layer of the interconnected network structure comprising a plurality of arrayed flash memory units, and communication lines being provided between the flash memory units corresponding in up and down in the plurality of layers of interconnected network structures for connection, and in the same layer of interconnected network structure, any flash memory unit is connected with adjacent flash memory units in the same row and adjacent flash memory units in the same column through communication lines respectively; each of the flash memory units comprises a routing chip and a flash memory chip, the flash memory chip is used for storing fixed data, and the routing chip is used for finding a specified communication line within a specified range based on a received data packet and its own address to determine a specified communication path from a first source address to a first destination address for processing data to be processed based on a data processing instruction; wherein the data packet comprises the first source address, the first destination address and the data processing instruction, the specified range is used to represent all communication lines connected with adjacent routing chips, and the data to be processed is the fixed data to be read, data to be written to the flash memory chip or the fixed data to be erased.

[0005] Optionally, further comprising: a central processing unit, the central processing unit is used for outputting a control instruction, and is used for scheduling the data to be processed after determining the specified communication path; a plurality of flash memory control modules, each of the flash memory control modules being connected to a flash memory cell in a first row or a first column of the interconnection network structure, the flash memory control module being configured to parse the received control instruction to obtain the data packet and output the data packet to the flash memory cell connected to the flash memory control module, the flash memory control module being further configured to output or receive the to-be-processed data through the designated communication path, and the flash memory control module being further configured to output the to-be-processed data received through the designated communication path based on the scheduling of the central processing unit.

[0006] Optionally, the control instruction includes a read command, a write command or a garbage collection command, and the storage structure further includes: a buffer, the buffer being configured to cache the data to be written as temporary data when the control instruction is a write command, and output the temporary data to the flash memory control module based on the scheduling of the central processing unit after the designated communication path is determined, so that the temporary data is used as the to-be-processed data. a system bus serving as a communication line between the central processing unit and the flash memory control module, between the central processing unit and the buffer, and between the flash memory control module and the buffer.

[0007] Optionally, the control instruction is a garbage collection command with a collection source address and a collection destination address, and the data packet includes a first data packet, a second data packet and a third data packet. In the first data packet, the data processing instruction is a read instruction, the first source address is the address of the flash memory control module, and the first destination address is the collection source address. In the second data packet, the data processing instruction is a write instruction, the first source address is the address of the flash memory control module, and the first destination address is the collection destination address. In the third data packet, the data processing instruction is an erase instruction, the first source address is the address of the flash memory control module, and the first destination address is the collection source address. The flash memory control module is further configured to transmit valid pages in the solid data at the collection source address to the collection destination address according to the garbage collection command, and after the valid pages in the solid data at the collection source address are transmitted to the collection destination address, erase the solid data at the collection source address.

[0008] Optionally, the flash memory control module is further configured to perform error correction on the to-be-processed data received by the flash memory control module.

[0009] According to a second aspect of the present application, a path finding method is provided, which is applied to the above-mentioned storage structure and includes: The current routing chip finds a specified communication line within a specified range according to a received data packet and its own address, the data packet including the first source address, the first destination address and the data processing instruction, the specified range representing all communication lines connected with routing chips adjacent to itself, the data to be processed being data to be read, data to be written into the flash chip or data to be erased; If the first destination address is different from the address of the current routing chip, the current routing chip transmits the data packet to a next routing chip through a specified communication line found by itself, or the current routing chip returns the data packet to a previous routing chip through a specified communication line found by the previous routing chip, the distance between the next routing chip and the first destination address being less than the distance between the current routing chip and the first destination address, and the distance between the previous routing chip and the first destination address being greater than the distance between the current routing chip and the first destination address; According to a plurality of routing chips in a plurality of layers of interconnected network structures and specified communication lines between the plurality of routing chips, a specified communication path from the first source address to the first destination address for processing the data to be processed based on the data processing instruction is determined.

[0010] Optionally, if the first destination address is different from the address of the current routing chip, the current routing chip further updates a port state of a flash unit corresponding to the next routing chip to an occupied state in a routing table of the next routing chip after transmitting the data packet to the next routing chip through a specified communication line found by itself. Or, the current routing chip further updates a port state of a flash unit corresponding to the current routing chip to an idle state in a routing table of the current routing chip after returning the data packet to the previous routing chip through a specified communication line found by the previous routing chip.

[0011] Optionally, the first source address is an address of the flash control module, and the first routing chip is one of routing chips connected with the flash control module, and before the first routing chip finds a specified communication line within a specified range according to a received data packet and its own address, the path finding method further comprises: The central processing unit sends a control instruction to the corresponding flash control module through a system bus; The flash control module sends the data packet to the first routing chip according to the control instruction, and updates a port state of the first routing chip to an occupied state in a routing table of the first routing chip.

[0012] Optionally, the method for finding the specified communication line in the specified range according to the received data packet and the address of the current routing chip comprises the following steps: If the address of the current routing chip is the same as the first destination address, the current routing chip sends a success signal to the flash control module. If the address of the current routing chip is not the same as the first destination address, it is determined whether the port of the next routing chip on the shortest path stored in the routing table of the current routing chip is idle, the shortest path representing the shortest one of the several communication paths from the current routing chip to the first destination address. If the port of the next routing chip on the shortest path is idle, it is determined that the communication line between the current routing chip and the next routing chip on the shortest path is the specified communication line. If the port of the next routing chip on the shortest path is not idle, it is determined whether the ports of the next routing chips on the several non-shortest paths are idle in a first order, the non-shortest paths representing the several communication paths other than the shortest path from the routing chip to the first destination address. If the ports of the next routing chips on the several non-shortest paths are all not idle, the specified communication line is the specified communication line found by the previous routing chip. If it is determined that the port of the next routing chip on one of the non-shortest paths is idle, it is determined that the communication line between the routing chip and the next routing chip on the non-shortest path is the specified communication line.

[0013] Optionally, if the data packet is returned to the flash control module, the flash control module sends a failure signal to the central processing unit.

[0014] According to a third aspect of the present application, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the above-mentioned path finding method.

[0015] Compared with the prior art, the technical scheme of the present application has the following beneficial effects: In the storage structure provided in the technical scheme, a plurality of layers of interconnected network structures are stacked, and communication lines are arranged between the flash memory units corresponding to each other in the plurality of layers of interconnected network structures to connect the flash memory units. In the same layer of interconnected network structures, any flash memory unit is connected with the adjacent flash memory units in the same row and the adjacent flash memory units in the same column, respectively. Therefore, a 3D network-shaped storage structure is formed in the storage structure, and each flash memory unit can have a plurality of directions of transmitting data. On this basis, each flash memory unit includes a routing chip and a flash memory chip, and the routing chip is used to find a specified communication line in a specified range based on a received data packet and an address of the routing chip to determine a specified communication path of transmitting data to be processed from a source address to a destination address. The data packet includes the source address, the destination address and a data processing instruction, and the flash memory chip is used to store fixed data. Therefore, each flash memory unit in the 3D network-shaped storage structure can select a plurality of communication lines connected thereto to transmit data during data transmission, so that the path diversity between the flash memory chips is increased, the path congestion between the flash memory chips is reduced, and the parallelism of the storage structure during processing of a plurality of I / O requests is increased, thereby reducing the waiting time during data transmission.

[0016] Further, the flash memory control module is used to obtain a first data packet, a second data packet and a third data packet according to the garbage collection instruction. The first data packet includes a read instruction, the second data packet includes a write instruction, and the third data packet includes an erase instruction. Therefore, the flash memory control module is used to execute the garbage collection instruction, so that the system bus is not occupied when the garbage collection instruction is executed, the pressure of the central processing unit and the system bus is reduced, the garbage collection instruction and the I / O request do not interfere with each other, and the efficiency of the storage structure in implementing garbage collection and processing I / O requests is further improved.

[0017] Further, the flash memory control module is further used to correct the data to be processed received by the flash memory control module, so that the pressure of the central processing unit and the system bus is further reduced.

[0018] In the path finding method provided in the technical scheme, the path diversity in the 3D network-shaped storage structure is fully utilized, so that the communication conflict is further relieved in a high-density read-write scenario, and the read-write performance is significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a schematic diagram of an internal structure of a solid state disk; Figure 2 is a schematic diagram of an internal structure of a storage structure provided in an embodiment of the application; Figure 3is a structural schematic diagram of an interconnection network provided by an embodiment of the present application; Figure 4 is a structural schematic diagram of a flash memory unit provided by an embodiment of the present application; Figure 5 is a flowchart of a path finding method provided by an embodiment of the present application; Figure 6 is a flowchart of a current routing chip determining a designated communication path provided by an embodiment of the present application.

[0020] Reference signs: 10 - system bus; D - flash memory unit; C - routing chip; FL - flash memory chip. DETAILED DESCRIPTION

[0021] As described in the background, the parallelism during the solid state disk processing multiple I / O requests is limited. The following is explained in combination with Figure 1 .

[0022] Figure 1 is a schematic diagram of the internal structure of a solid state disk.

[0023] Referring to Figure 1 , the solid state disk adopts a multi-channel shared bus architecture, including a central processor, an error correction unit, a buffer, a plurality of flash memory control modules and a plurality of flash memory chips F. Among them, the central processor and the flash memory control module, the central processor and the buffer and the flash memory control module and the buffer can communicate through the system bus 1, and each flash memory control module can communicate with a plurality of flash memory chips F through a flash memory bus 2.

[0024] Since multiple flash memory chips communicate with a corresponding flash memory control module through a flash memory bus 2, communication conflicts often occur on the flash memory bus 2, that is, path conflicts often occur when the solid state disk processes multiple I / O requests, so that the parallelism during the solid state disk processing multiple I / O requests is limited.

[0025] In view of this, the technical scheme of the present application creatively provides a kind of, including: A plurality of layers of stacked interconnection network structure, each layer of the interconnection network structure includes a plurality of arrayed flash memory units, and communication lines are arranged between the flash memory units corresponding to each other in the plurality of layers of interconnection network structure to connect, in the same layer interconnection network structure, any flash memory unit and the adjacent flash memory units in the same row and the adjacent flash memory units in the same column where it is located are connected with communication lines respectively; Each of the flash memory units comprises a routing chip and a flash memory chip, the flash memory chip is used for storing fixed data, and the routing chip is used for finding a specified communication line in a specified range based on a received data packet and a self address to determine a specified communication path from a first source address to a first destination address for processing to-be-processed data based on a data processing instruction. The data packet comprises the first source address, the first destination address and the data processing instruction, the specified range is used for representing all communication lines connected with a routing chip adjacent to the self, and the to-be-processed data is to-be-read fixed data, to-be-written data into the flash memory chip or to-be-erased fixed data.

[0026] The 3D network-like storage structure is formed in the storage structure, each flash memory unit can have multiple directions of transmitting data. On this basis, since each flash memory unit comprises a routing chip and a flash memory chip, and the routing chip is used for finding a specified communication line in a specified range based on a received data packet and a self address to determine a specified communication path from a first source address to a first destination address for processing to-be-processed data based on a data processing instruction, the data packet comprises the first source address, the first destination address and the data processing instruction, and the flash memory chip is used for storing fixed data. Therefore, during data transmission, each flash memory unit in the 3D network-like storage structure can select multiple communication lines connected thereto to transmit data, so that the path diversity between the flash memory chips is increased, thereby reducing the path congestion between the flash memory chips, and further, the parallelism of the storage structure during processing of multiple I / O requests is increased, resulting in reduced waiting time during data transmission.

[0027] The embodiments in the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present application. The terms "first", "second", "third" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to the clearly listed steps or units, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0028] Figure 2 is a schematic diagram of an internal structure of a storage structure provided by an embodiment of the present application; Figure 3 is a schematic diagram of a structure of an interconnection network provided by an embodiment of the present application; Figure 4 is a schematic diagram of a structure of a flash memory unit provided by an embodiment of the present application.

[0029] Please refer to Figure 2 , the present application provides a storage structure, comprising a plurality of layers of stacked interconnection network structures.

[0030] Specifically, please refer to Figure 3 and Figure 4 , each interconnection network structure comprises a plurality of arrayed flash memory units D, and communication lines are arranged between the flash memory units D corresponding to each other in the plurality of layers of interconnection network structures for connection, in the same interconnection network structure, any flash memory unit D is connected with the adjacent flash memory units D in the same row and the adjacent flash memory units D in the same column by communication lines. Each flash memory unit D comprises a routing chip C and a flash memory chip FL, the flash memory chip FL is used for storing fixed data, and the routing chip C is used for finding a specified communication line in a specified range based on a received data packet and its own address, to determine a specified communication path from a first source address to a first destination address for processing the to-be-processed data based on a data processing instruction.

[0031] Among them, the data packet comprises the first source address, the first destination address and the data processing instruction, the specified range is used to represent all the communication lines connected with the adjacent routing chip C, and the to-be-processed data is to-be-read fixed data, to-be-written data to the flash memory chip FL or to-be-erased fixed data.

[0032] In this embodiment, please continue to refer to Figure 2 , the storage structure further comprises a central processing unit and a plurality of flash memory control modules.

[0033] The central processing unit is used for outputting a control instruction, and is used for scheduling the to-be-processed data after determining the specified communication path.

[0034] Each flash memory control module is connected with a flash memory unit D in the first row or the first column of an interconnection network structure, and the flash memory control module is used for parsing a received control instruction to obtain a data packet, and outputting the data packet to the flash memory unit D connected with itself, the flash memory control module is also used for outputting or receiving the to-be-processed data through the specified communication path, and the flash memory control module is also used for outputting the to-be-processed data received through the specified communication path based on the scheduling of the central processing unit.

[0035] In this embodiment, the storage structure further comprises a buffer and a system bus 10.

[0036] The buffer is configured to buffer the data to be written as temporary data when the control instruction is a write command, and configured to output the temporary data as to-be-processed data to the flash control module based on the scheduling of the central processor after the communication path is determined.

[0037] The system bus 10 is used as a communication line between the central processor and the flash control module, between the central processor and the buffer, and between the flash control module and the buffer.

[0038] In this embodiment, the control instruction includes a read command, a write command, or a garbage collection command.

[0039] In this embodiment, the flash control module is capable of receiving the to-be-processed data through the specified communication path according to the received read command, and then outputting the to-be-processed data to the specified location in the read command through the system bus 10.

[0040] In this embodiment, the flash control module is also capable of writing the to-be-processed data received through the system bus 10 to the first destination address through the specified communication path according to the received write command.

[0041] In this embodiment, the flash control module is also configured to transfer the valid pages in the solid data at the recycling source address to the recycling destination address according to the garbage collection command, and after the valid pages in the solid data at the recycling source address are transferred to the recycling destination address, erase the solid data at the recycling source address. Specifically, when the central processor detects that the number of free flash blocks in a flash chip FL is less than a first preset threshold, the control instruction includes a garbage collection command.

[0042] In this embodiment, the control instruction is a garbage collection command with a recycling source address and a recycling destination address, and the data packet includes a first data packet, a second data packet, and a third data packet.

[0043] In the first data packet, the data processing instruction is a read instruction, the first source address is the address of the flash control module, and the first destination address is the recycling source address. The read instruction is used to read the valid pages in the solid data at the recycling source address into the flash control module, and the to-be-processed data at this time is the valid pages.

[0044] In the second data packet, the data processing instruction is a write instruction, the first source address is the address of the flash control module, and the first destination address is the recycling destination address. The write instruction is used to write the valid pages in the flash control module to the recycling destination address, so as to achieve the transfer of the valid pages in the solid data at the recycling source address to the recycling destination address, and the to-be-processed data at this time is the valid pages.

[0045] In the third data packet, the data processing instruction is an erasing instruction, the first source address is the address of the flash control module, and the first destination address is the recycling source address. The erasing instruction is used to erase the solid data at the recycling source address to clean up the idle storage space. At this time, the data to be processed is the solid data at the recycling source address.

[0046] In the embodiment, the flash control module is further used to correct errors of the data to be processed received by the flash control module, so as to further reduce the pressure of the central processing unit and the system bus 10 on the basis of reducing the error rate.

[0047] Specifically, for the read instruction, after the flash control module sends the data packet to the first destination address through the specified communication path, the flash control module can receive the data sent by the first destination address. After the flash control module receives the data sent by the first destination address, the flash control module can perform ECC decoding on the data to be processed and correct possible errors in the data, and finally perform de-randomization on the read data to restore the original data. For the write instruction, the flash control module can perform data randomization on the received data to be processed (i.e., data to be written) to avoid high error rate caused by worst data mode, then perform ECC encoding to improve reliability and performance, and then transmit the randomized ECC encoded data to be processed to the first destination address.

[0048] In summary, in the storage structure provided in the embodiment of the application, a plurality of layers of interconnected network structures are stacked, and communication lines are arranged between the flash memory units D corresponding to each other in the plurality of layers of interconnected network structures to connect the flash memory units D. In the same layer of interconnected network structure, any flash memory unit D is connected with the adjacent flash memory units D in the same row and the adjacent flash memory units D in the same column through communication lines. Therefore, a 3D network-like storage structure is formed in the storage structure, and each flash memory unit D in the 3D network-like storage structure can have multiple directions of transmitting data. On this basis, since each flash memory unit D includes a routing chip C and a flash chip FL, and the routing chip C is used to find a specified communication line within a specified range based on a received data packet and its own address to determine a specified communication path of the data to be processed from the source address to the destination address, the data packet includes the source address, the destination address and the data processing instruction, and the flash chip FL is used to store solid data. Therefore, during data transmission, each flash memory unit D in the 3D network-like storage structure can select a plurality of communication lines connected thereto to transmit data, so that the path diversity between the flash chips FL is increased, thereby reducing the path congestion between the flash chips FL, and further increasing the parallelism of the storage structure during processing of multiple I / O requests, which reduces the waiting time during data transmission.

[0049] Further, since the flash control module is configured to obtain the first data packet, the second data packet and the third data packet according to the garbage collection instruction, the first data packet comprises the read instruction, the second data packet comprises the write instruction, and the third data packet comprises the erase instruction. Therefore, the flash control module is configured to execute the garbage collection instruction, i.e. the garbage collection instruction does not need to occupy the system bus 10 when the garbage collection instruction is executed, so as to alleviate the pressure of the central processing unit and the system bus 10, and meanwhile, the garbage collection instruction and the I / O request do not disturb each other, and the efficiency of the storage structure in implementing garbage collection and processing I / O request is further improved.

[0050] Further, the flash control module is further configured to correct the to-be-processed data received by the flash control module, so as to further alleviate the pressure of the central processing unit and the system bus 10.

[0051] Correspondingly, the embodiment of the present application further provides a path searching method based on the above storage structure, which will be described in detail below. Figure 5 and Figure 6 Correspondingly, the embodiment of the present application further provides a path searching method based on the above storage structure, which will be described in detail below. Figure 5 is a flowchart of the path searching method provided by the embodiment of the present application, Figure 6 is a flowchart of the current routing chip C determining the specified communication path.

[0052] Please refer to Figure 5 The path searching method comprises the following steps. In step S100, the flash control module sends a data packet to the first routing chip C according to a control instruction, and updates the port state of the first routing chip C to an occupied state in the routing table of the first routing chip C. In step S200, the flash control module sends a failure signal to the central processing unit through the system bus 10 to inform the central processing unit that the path searching fails, if the data packet is returned to the flash control module; and in step S300, the specified communication path from the first source address to the first destination address for processing the to-be-processed data based on the data processing instruction is determined according to the plurality of routing chips C in the plurality of layers of stacked interconnection network structures and the specified communication lines between the plurality of routing chips C, if the data packet is not returned to the flash control module.

[0053] In step S100, the control instruction is sent by the central processing unit to the flash control module through the system bus 10, and the first routing chip C is one of the routing chips C connected to the flash control module.

[0054] It can be understood that, as an example, the specified communication path includes: the specified communication line between the flash control module and the first routing chip C, the N ordered routing chips C of the first routing chip C, and the N-1 specified communication lines between the N routing chips C. Therefore, the first N-1 routing chips C each correspond to a specified communication line connecting the next routing chip C. The next routing chip C is closer to the first destination address than the current routing chip C, and N is a positive integer greater than or equal to 1.

[0055] Correspondingly, for step S300, according to the plurality of routing chips C in the interconnection network structure of the plurality of layers of stacks and the specified communication lines between the plurality of routing chips C, determining the specified communication path from the first source address to the first destination address for processing the to-be-processed data based on the data processing instruction can further include: step S310, the current routing chip C finds the specified communication line in the specified range according to the received data packet and the self address.

[0056] The data packet includes the first source address, the first destination address, and the data processing instruction, the specified range is used to represent all the communication lines connected to the routing chip C adjacent to the self, and the to-be-processed data is the to-be-read solid data, the data to be written to the flash chip FL, or the to-be-erased solid data.

[0057] The current routing chip C is used to represent one of the N ordered routing chips C, and the specified communication line found by the current routing chip C is a specified communication line connecting the next routing chip C. Please refer to Figure 6 For step S310, the current routing chip C finds the specified communication line in the specified range according to the received data packet and the self address, which specifically includes: determining whether the self address of the current routing chip C is the same as the first destination address: if the same, executing step S311, the current routing chip C sends a success signal to the flash control module; if not the same, executing step S312, determining whether the port of the next routing chip C on the shortest path stored in the routing table of the current routing chip C is idle.

[0058] The shortest path is used to represent the shortest one of the plurality of communication paths from the current routing chip C to the first destination address.

[0059] Then, according to the determination result of step S312, continue to the next step, which includes: If idle, execute: step S313, determining that the communication line between the current routing chip C and the next routing chip C on the shortest path is the designated communication line; step S314, the current routing chip C transmits the data packet to the next routing chip C through the designated communication line found by itself; and step S315, updating the port state of the flash unit D corresponding to the next routing chip C in the routing table of the next routing chip C to the occupied state; If not idle, execute step S316, judging whether the ports of the next routing chip C on the several non-shortest paths are idle in the first order, and continue to the next step based on the judgment result of step S315.

[0060] Specifically, according to the judgment result of step S316, continue to the next step, which specifically includes: If all are not idle, execute: step S317, the designated communication line is the designated communication line found by the previous routing chip C; step S318, the current routing chip C returns the data packet to the previous routing chip C through the designated communication line found by the previous routing chip C, wherein the distance between the previous routing chip C and the first destination address is greater than the distance between the current routing chip C and the first destination address; and step S319, updating the port state of the flash unit D corresponding to the current routing chip C in the routing table of the current routing chip C to the idle state; If idle, execute step S320, step S314 and step S315 in sequence. Specifically, step S320 is: determining that the communication line between the routing chip C and the next routing chip C on the non-shortest path is the designated communication line.

[0061] Among them, for step S316, the non-shortest path is used to represent other communication paths in the several communication paths from the routing chip C to the first destination address except the shortest path.

[0062] In this embodiment, the path finding method further includes the following steps after executing S300: Step S400, the routing chip C at the first destination address transmits the received data packet to the corresponding flash chip FL; Step S500, the flash chip FL completes the corresponding operation according to the control instruction in the data packet, and sends a success signal to the central processing unit through the designated communication path, the flash control module and the system bus 10 to notify the central processing unit that the path finding is completed.

[0063] After the path finding is completed, the port state of the routing chip C in the specified communication path is updated to the occupied state, and during the execution of the data processing instruction in the data packet, the port state of the routing chip C in the specified communication path is updated to the idle state. For example, if the data processing instruction is a read instruction, after the flash memory chip FL receives the data packet, the flash memory chip FL transmits the to-be-processed data (i.e., the to-be-read stored data) in the flash memory chip FL to the flash memory control module through the specified communication path, and during the transmission of the to-be-processed data (i.e., the to-be-read stored data) in the flash memory chip FL to the flash memory control module through the specified communication path, the port state of the routing chip C is updated to the idle state, i.e., after a flash memory unit D receives the to-be-processed data, the port state of the flash memory unit D that transmits the to-be-processed data is updated to the idle state.

[0064] In conclusion, in the path finding method provided by the embodiment of the present application, the path diversity in the 3D network storage structure is fully utilized, so that the communication conflict is further relieved in the high-density read-write scenario, and the read-write performance is significantly improved.

[0065] The embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the path finding method.

[0066] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A storage structure, characterized by, The application relates to a memory structure and a memory system. The memory structure comprises a plurality of layers of interconnected network structures, each layer of the interconnected network structures comprising a plurality of arrayed flash memory units, and communication lines being arranged between corresponding flash memory units in the plurality of layers of interconnected network structures to connect the corresponding flash memory units, and any flash memory unit in the same layer of interconnected network structures being connected to adjacent flash memory units in the same row and the same column of the same layer of interconnected network structures via communication lines. Each flash memory unit comprises a routing chip and a flash memory chip, the flash memory chip being configured to store fixed data, and the routing chip being configured to search for a specified communication line in a specified range based on a received data packet and an address of the routing chip to determine a specified communication path from a first source address to a first destination address for processing of to-be-processed data based on a data processing instruction. The data packet comprises the first source address, the first destination address and the data processing instruction, the specified range is used to represent all communication lines connected to adjacent routing chips, and the to-be-processed data is to-be-read fixed data, to-be-written data or to-be-erased fixed data.

2. The memory structure of claim 1, wherein, The memory system further comprises a central processing unit configured to output a control instruction and schedule the to-be-processed data after the specified communication path is determined. A plurality of flash memory control modules are connected to a first row or a first column of flash memory units in the interconnected network structures, and each flash memory control module is configured to parse the received control instruction to obtain the data packet and output the data packet to a flash memory unit connected to the flash memory control module, output or receive the to-be-processed data via the specified communication path, and output the to-be-processed data received via the specified communication path based on the scheduling of the central processing unit. The control instruction comprises a read command, a write command or a garbage collection command, and the memory structure further comprises a buffer configured to buffer data to be written as temporary data when the control instruction is a write command, and output the temporary data as the to-be-processed data to the flash memory control module based on the scheduling of the central processing unit after the specified communication path is determined.

3. The memory structure of claim 2, wherein, A system bus is used as a communication line between the central processing unit and the flash memory control module, between the central processing unit and the buffer, and between the flash memory control module and the buffer. The control instruction is a garbage collection command with a collection source address and a collection destination address, and the data packet comprises a first data packet, a second data packet and a third data packet. In the first data packet, the data processing instruction is a read instruction, the first source address is an address of the flash memory control module, and the first destination address is the collection source address.

4. The memory structure of claim 2, wherein, In the second data packet, the data processing instruction is a write instruction, the first source address is an address of the flash memory control module, and the first destination address is the collection destination address. ​ ​ The third data packet, the data processing instruction is an erase instruction, the first source address is the address of the flash memory control module, and the first destination address is the recycling source address. The flash memory control module is further configured to transmit valid pages in the solid data at the recycling source address to the recycling destination address according to the garbage recycling command, and after the valid pages in the solid data at the recycling source address are transmitted to the recycling destination address, the solid data at the recycling source address is erased.

5. The memory structure of claim 2, wherein, The flash memory control module is further configured to perform error correction on the to-be-processed data received by the flash memory control module.

6. A routing method characterized by, The method is applied to the storage structure of any one of claims 1-5, and the method comprises: A current routing chip searches for a specified communication line in a specified range according to a received data packet and a self address, the data packet comprising the first source address, the first destination address and the data processing instruction, the specified range representing all communication lines connected to routing chips adjacent to the self address, and the to-be-processed data being solid data to be read, data to be written into the flash memory chip or solid data to be erased. If the self address of the current routing chip is different from the first destination address, the current routing chip transmits the data packet to a next routing chip through the specified communication line found by the self address, or the current routing chip returns the data packet to a previous routing chip through the specified communication line found by the previous routing chip, the distance between the next routing chip and the first destination address being less than the distance between the current routing chip and the first destination address, and the distance between the previous routing chip and the first destination address being greater than the distance between the current routing chip and the first destination address. A specified communication path from the first source address to the first destination address for processing the to-be-processed data based on the data processing instruction is determined according to a plurality of routing chips in a plurality of layers of interconnected network structures and specified communication lines between the plurality of routing chips.

7. The pathfinding method of claim 6, wherein, If the self address of the current routing chip is different from the first destination address, the current routing chip further updates the port state of the flash memory unit corresponding to the next routing chip to an occupied state in a routing table of the next routing chip after transmitting the data packet to the next routing chip through the specified communication line found by the self address. Or, the current routing chip further updates the port state of the flash memory unit corresponding to the current routing chip to an idle state in a routing table of the current routing chip after returning the data packet to the previous routing chip through the specified communication line found by the previous routing chip.

8. The pathfinding method of claim 7, wherein, The first source address is the address of the flash memory control module, and the first routing chip is one of the routing chips connected to the flash memory control module, and before the first routing chip searches for a specified communication line in a specified range according to a received data packet and a self address, the path searching method further comprises: The central processor sends a control instruction to a corresponding flash memory control module through a system bus; The flash memory control module sends the data packet to a first routing chip according to the control instruction, and updates a port state of the first routing chip to an occupied state in a routing table of the first routing chip.

9. The pathfinding method of claim 8, wherein, The method for finding a specified communication line by a current routing chip in a specified range according to a received data packet and an address of the current routing chip includes: If the address of the current routing chip is the same as the first destination address, the current routing chip sends a success signal to the flash memory control module; If the address of the current routing chip is not the same as the first destination address, it is judged whether a port of a next routing chip on a shortest path stored in a routing table of the current routing chip is idle, the shortest path being used to represent a shortest one of a plurality of communication paths from the current routing chip to the first destination address; If the port of the next routing chip on the shortest path is idle, it is determined that a communication line between the current routing chip and the next routing chip on the shortest path is the specified communication line; If the port of the next routing chip on the shortest path is not idle, it is judged in a first order whether ports of next routing chips on a plurality of non-shortest paths are idle, the non-shortest paths being used to represent other communication paths than the shortest path among the plurality of communication paths from the routing chip to the first destination address; If the ports of the next routing chips on the plurality of non-shortest paths are all not idle, the specified communication line is the specified communication line found by the previous routing chip; If it is determined that the port of the next routing chip on one of the non-shortest paths is idle, it is determined that a communication line between the routing chip and the next routing chip on the non-shortest path is the specified communication line.

10. The pathfinding method of claim 9, wherein, If the data packet is returned to the flash memory control module, the flash memory control module sends a failure signal to the central processor.

11. A computer readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the path finding method according to any one of claims 6 to 10. The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the path finding method according to any one of claims 6 to 10.

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