Initial configuration method, memory storage device and memory control circuit unit

Abstract

The invention provides an initial configuration method, a memory storage device and a memory control circuit unit. The initial configuration method comprises the following steps: after the storage device of the memory is powered on, judging whether an energy-saving instruction is continuously received after a reset instruction is received for the first time; and executing an initial configuration operation in at least one of the preparation mode and the first energy-saving mode in response to the fact that the energy-saving instruction is continuously received after the reset instruction is received for the first time.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory management technique, and more particularly, to an initial configuration method, a memory storage device, and a memory control circuit unit. BACKGROUND

[0002] The growth of portable electronic devices such as mobile phones and notebook computers has been very rapid in recent years, which has resulted in a rapid increase in the demand for storage media. Rewritable non-volatile memory modules (e.g., flash memories) are very suitable for being built into various portable electronic devices because they have the characteristics of data non-volatility, power saving, small size, and no mechanical structure.

[0003] The existing memory storage device needs to perform an initialization operation after power-on in the case of being allowed to be accessed. That is, the memory storage device can only perform initialization after completing a reset or exiting an ultra-low power consumption mode.

[0004] However, in the case of being allowed to be accessed, the memory storage device can need to perform other operations at the same time, and the initialization operation performed based on the existing method can cause configuration errors, thereby resulting in compatibility problems. SUMMARY

[0005] The present application provides an initial configuration method, a memory storage device, and a memory control circuit unit, which can avoid compatibility problems, reduce initialization time, and provide two-stage power saving modes to meet the power consumption requirements in various power states.

[0006] An example embodiment of the present application provides an initial configuration method for a memory storage device, the initial configuration method comprising: after the memory storage device is powered on, determining whether a power saving instruction is received subsequently after a reset instruction is received for the first time; and in response to the power saving instruction being received subsequently after the reset instruction is received for the first time, performing an initial configuration operation in at least one of a preparation mode and a first power saving mode.

[0007] In an example embodiment of the present application, the initial configuration method further comprises: in response to the power saving instruction not being received subsequently after the reset instruction is received for the first time, performing the initial configuration operation in the preparation mode.

[0008] In an example embodiment of the present application, the initial configuration method further comprises: in response to the reset instruction being received for the first time, the memory storage device entering the preparation mode or a reset mode.

[0009] In an example embodiment of the present invention, the initial configuration method further comprises: in the reset mode, not performing the initial configuration operation.

[0010] In an example embodiment of the present invention, the initial configuration method further comprises: in response to receiving the power saving instruction again, the memory storage device enters the second power saving mode.

[0011] In an example embodiment of the present invention, the initial configuration method further comprises: in response to receiving the power saving instruction after receiving the reset instruction for the first time, the memory storage device enters the first power saving mode or the second power saving mode.

[0012] In an example embodiment of the present invention, the initial configuration method further comprises: in the second power saving mode, not performing the initial configuration operation.

[0013] In an example embodiment of the present invention, the initial configuration method further comprises: in response to receiving the power saving instruction again, the memory storage device enters the second power saving mode.

[0014] An example embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. After the memory storage device is powered on, the memory control circuit unit is configured to determine whether a power saving instruction is received after a reset instruction is received for the first time. In response to receiving the power saving instruction after the reset instruction is received for the first time, the memory control circuit unit is configured to perform an initial configuration operation in a preparation mode and / or a first power saving mode.

[0015] In an example embodiment of the present invention, in response to not receiving the power saving instruction after the reset instruction is received for the first time, the memory control circuit unit is further configured to perform the initial configuration operation in the preparation mode.

[0016] In an example embodiment of the present invention, in response to receiving the reset instruction for the first time, the memory storage device enters the preparation mode or the reset mode.

[0017] In an example embodiment of the present invention, in the reset mode, the memory control circuit unit is not configured to perform the initial configuration operation.

[0018] In an example embodiment of the present invention, in response to receiving the reset instruction again, the memory storage device enters the reset mode.

[0019] In an example embodiment of the present invention, in response to receiving the power saving instruction after the reset instruction is received for the first time, the memory storage device enters the first power saving mode or the second power saving mode.

[0020] In an example embodiment of the present disclosure, in the second power saving mode, the memory control circuit unit is not used to perform the initial configuration operation.

[0021] In an example embodiment of the present disclosure, in response to receiving the power saving instruction again, the memory storage device enters the second power saving mode.

[0022] An example embodiment of the present disclosure further provides a memory control circuit unit disposed in a memory storage device. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is coupled to the interface unit. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. After the memory storage device is powered on, the memory management circuit is used to determine whether the power saving instruction is received subsequently after the reset instruction is received for the first time. In response to the power saving instruction being received subsequently after the reset instruction is received for the first time, the memory management circuit is further used to perform the initial configuration operation in the preparation mode or the first power saving mode.

[0023] In an example embodiment of the present disclosure, in response to the power saving instruction not being received subsequently after the reset instruction is received for the first time, the memory management circuit is further used to perform the initial configuration operation in the preparation mode.

[0024] In an example embodiment of the present disclosure, in the reset mode, the memory management circuit is not used to perform the initial configuration operation.

[0025] In an example embodiment of the present disclosure, in the second power saving mode, the memory management circuit is not used to perform the initial configuration operation.

[0026] Based on the above, the initial configuration method, the memory storage device, and the memory control circuit unit of the present disclosure can perform the initial configuration operation in the preparation mode and / or the low power consumption mode after being powered on, so as to avoid the compatibility problem caused by the prior art method and reduce the initialization time. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an example embodiment of the present disclosure;

[0028] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an example embodiment of the present disclosure;

[0029] Figure 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the present disclosure;

[0030] Figure 4is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0031] Figure 5 is a schematic diagram of a memory control circuit unit shown in accordance with an example embodiment of the present invention;

[0032] Figure 6 shows a schematic diagram of an existing method of managing access rights and modes of a memory storage device;

[0033] Figure 7 is a flowchart of an initial configuration method shown in accordance with an example embodiment of the present invention;

[0034] Figure 8 is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0035] Figure 9 is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0036] Figure 10 is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0037] Figure 11 is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0038] Figure 12 is a flowchart of an initial configuration method shown in accordance with an example embodiment of the present invention. DETAILED DESCRIPTION

[0039] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0040] Generally speaking, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0041] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present invention. Figure 2is a schematic diagram of a host system, a memory storage device, and an I / O device according to an example embodiment of the present application.

[0042] Referring to Figure 1 and Figure 2 The host system 11 can include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be connected to a system bus 110.

[0043] In an example embodiment, the host system 11 can be connected to the memory storage device 10 through the data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 can be connected to the I / O device 12 through the system bus 110. For example, the host system 11 can transmit an output signal to or receive an input signal from the I / O device 12 via the system bus 110.

[0044] In an example embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be disposed on a host board 20 of the host system 11. The number of the data transfer interface 114 can be one or more. Through the data transfer interface 114, the host board 20 can be connected to the memory storage device 10 via a wired or wireless manner.

[0045] In an example embodiment, the memory storage device 10 can be, for example, a USB 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy (BLE) memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the host board 20 can also be connected to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like, through the system bus 110. For example, in an example embodiment, the host board 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

[0046] In an example embodiment, the host system 11 is a computer system. In an example embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 can respectively comprise Figure 3 a memory storage device 30 and a host system 31.

[0047] Figure 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the present application. Please refer to Figure 3 The memory storage device 30 can be used in cooperation with the host system 31 to store data. For example, the host system 31 can be a digital camera, a camcorder, a communication device, an audio player, a video player, or a tablet computer, etc. For example, the memory storage device 30 can be a secure digital (SD) card 32, a compact flash (CF) card 33, or an embedded storage device 34, etc. The embedded storage device 34 includes an embedded multi media card (eMMC) 341 and / or an embedded multi chip package (eMCP) storage device 342, etc. The embedded storage device is a type of embedded storage device that directly connects a memory module on a substrate of the host system.

[0048] Figure 4 is a schematic diagram of a memory storage device according to an example embodiment of the present application. Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0049] The connection interface unit 41 is configured to connect to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an example embodiment, the connection interface unit 41 is compliant with the Universal Flash Storage (UFS) interface standard. In an example embodiment, the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Peripheral Component Interconnect Express (PCI Express) standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip that includes the memory control circuit unit 42.

[0050] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is configured to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 43 according to instructions from the host system 11.

[0051] The rewritable nonvolatile memory module 43 stores data written by the host system 11. The rewritable nonvolatile memory module 43 can include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one bit can be stored in one memory cell), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which two bits can be stored in one memory cell), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module in which three bits can be stored in one memory cell), a quad level cell (QLC) NAND type flash memory module (i.e., a flash memory module in which four bits can be stored in one memory cell), another flash memory module, or another memory module having the same characteristics.

[0052] Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between a control gate and a channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons of the charge trapping layer is changed, and thus the threshold voltage of the memory cell is changed. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage is changed, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, and thus it is possible to acquire one or more bits stored in the memory cell.

[0053] In an example embodiment, the memory cells of the rewritable nonvolatile memory module 43 can constitute a plurality of physical program units, and the physical program units can constitute a plurality of physical erase units. Specifically, the memory cells on the same word line can form one or more physical program units. If each memory cell can store more than two bits, the physical program units on the same word line can be classified into at least lower physical program units and upper physical program units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical program unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical program unit. Generally, in an MLC NAND type flash memory, the write speed of a lower physical program unit is greater than that of an upper physical program unit, and / or the reliability of a lower physical program unit is higher than that of an upper physical program unit.

[0054] In an example embodiment, a physical program unit is the smallest unit of programming. That is, a physical program unit is the smallest unit of writing data. For example, a physical program unit can be a physical page or a physical sector. If a physical program unit is a physical page, the physical program units can include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is for storing system data (e.g., management data such as error correction codes). In an example embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit area can contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can be greater or smaller. On the other hand, a physical erase unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased together. For example, a physical erase unit is a physical block.

[0055] Figure 5 FIG. 1 is a schematic diagram of a memory control circuit unit according to an example embodiment of the present application. Referring to FIG. 1, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. Figure 5

[0056] ​The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and these control instructions are executed to perform data write, read and erase operations, etc. when the memory storage device 10 is in operation. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0057] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform data write, read and erase operations, etc.

[0058] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code form in a specific area (e.g., a system area in the memory module for storing system data) of the rewritable non-volatile memory module 43. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform data write, read and erase operations, etc.

[0059] In an example embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or the groups of memory cells of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations, etc. In an example embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct to perform corresponding operations.

[0060] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify the instructions and data of the host system 11. For example, the instructions and data of the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In the present example embodiment, the host interface 52 is compatible with the UFS standard. However, it must be understood that the present application is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the PCI Express standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0061] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written into the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 transmits corresponding instruction sequences. For example, these instruction sequences can include a write instruction sequence indicating write data, a read instruction sequence indicating read data, an erase instruction sequence indicating erase data, and corresponding instruction sequences to indicate various memory operations (e.g., change the read voltage level or perform a garbage collection (GC) operation, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on a bus. These signals or data can include instruction codes or program codes. For example, in a read instruction sequence, the identification code of the read, the memory address, etc. information are included.

[0062] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0063] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 obtains a write instruction from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 writes the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the corresponding error correcting code and / or error detecting code corresponding to this data is also read, and the error checking and correction circuit 54 performs error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0064] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0065] In an example embodiment, Figure 4 The rewritable non-volatile memory module 43 can comprise a flash memory module. In an example embodiment, Figure 4 The memory control circuit unit 42 can comprise a flash memory controller. In an example embodiment, Figure 5 The memory management circuit 51 can comprise a flash memory management circuit.

[0066] Figure 6 An existing schematic diagram of managing access permission and mode of a memory storage device is shown. Please refer to Figure 6 Generally, after the memory storage device 10 is powered on, based on a received reset instruction CMDR, at this time, Figure 6 The reset instruction CMDR shown is a logic value "0", the memory storage device 10 can enter a reset mode MR2. In addition, based on a received power saving instruction CMDL, at this time, Figure 6 The power saving instruction CMDL shown is a logic value "0", the memory storage device 10 can enter an ultra-low power consumption mode MS2.

[0067] When the memory storage device 10 is in the reset mode MR2 or the ultra-low power consumption mode MS2, most of the functions and / or internal circuits of the memory storage device 10 are turned off, at this time, the memory storage device 10 is not allowed to be accessed. The memory storage device 10 (the memory management circuit 51) can only perform an initialization operation (also referred to as an initial configuration operation) which needs to be performed after the memory storage device 10 is powered on, under the condition that the memory storage device 10 is not in the reset mode MR2 (or the ultra-low power consumption mode MS2). In other words, the memory storage device 10 (the memory management circuit 51) needs to continue to perform the initial configuration operation after the memory storage device 10 completes a reset or the memory storage device 10 exits the ultra-low power consumption mode MS2. That is, the memory management circuit 51 needs to perform the initial configuration operation under the condition that the memory storage device 10 is allowed to be accessed.

[0068] However, under the condition that the memory storage device 10 is allowed to be accessed, the memory management circuit 51 can need to perform other operations at the same time, and the initial configuration operation performed based on the existing method can cause configuration errors, thereby causing compatibility problems.

[0069] Accordingly, the present application provides an initial configuration method which can avoid the above-mentioned compatibility problems and reduce initialization time. Figure 7 is a flowchart of an initial configuration method according to an example embodiment of the present application. Please refer to Figure 7 In step S701, the memory storage device 10 is powered on.

[0070] In step S702, the memory management circuit 51 can determine whether the power saving command CMDL is received subsequently to the first received reset command CMDR. If the memory storage device 10 (the memory management circuit 51) receives the power saving command CMDL subsequently to the first received reset command CMDR, step S703 is entered. Conversely, if the memory storage device 10 (the memory management circuit 51) does not receive the power saving command CMDL subsequently to the first received reset command CMDR, step S704 is entered.

[0071] In step S703, the memory management circuit 51 can perform the initial configuration operation in the preparation mode MR1 and / or the low power consumption mode MS1 (also referred to as the first power saving mode). Specifically, after the memory storage device 10 is powered on, if the memory storage device 10 (the memory management circuit 51) receives the power saving command CMDL subsequently to the first received reset command CMDR (i.e., the first received reset command CMDR is adjacent to the power saving command CMDL), the memory management circuit 51 can perform the initial configuration operation in the preparation mode MR1 and / or the low power consumption mode MS1, as shown in FIG. 7B. Figures 8 to 10

[0072] Figures 8 to 10 FIG. 7A is a schematic diagram showing the management of access rights and modes of a memory storage device according to an example embodiment of the present application. Please refer to FIG. 7A. Figures 8 to 10 When the reset command CMDR (or the power saving command CMDL) is a logic value of "0", it means that the memory storage device 10 (the memory management circuit 51) receives the reset command CMDR (or the power saving command CMDL).

[0073] In an example embodiment, after the first received reset command CMDR, the memory storage device 10 can enter, for example, the preparation mode MR1 or the reset mode MR2, and after the first received reset command CMDR and the subsequently received power saving command CMDL, the memory storage device 10 can enter, for example, the low power consumption mode MS1 or the ultra low power consumption mode MS2 (also referred to as the second power saving mode).

[0074] ​To further explain, when the memory storage device 10 is in reset mode MR2 or ultra-low power mode MS2, most of the functions and / or internal circuits of the memory storage device 10 are turned off, and the memory storage device 10 is not allowed to be accessed at this time. Therefore, when the memory storage device 10 is in reset mode MR2 or ultra-low power mode MS2, the memory management circuit 51 cannot perform the initial configuration operation. Conversely, when the memory storage device 10 is in ready mode MR1 or low power mode MS1, some of the functions and / or internal circuits of the memory storage device 10 are turned on, and the memory storage device 10 is allowed to be accessed, enabling the memory management circuit 51 to perform the initial configuration operation.

[0075] It should be noted that when the memory storage device 10 is in the ready mode MR1 or the low-power mode MS1, the memory storage device 10 only activates some functions and / or internal circuits used to perform the initial configuration operation. Therefore, in the ready mode MR1 or the low-power mode MS1, the memory management circuit 51 can only perform the initial configuration operation and does not perform other operations.

[0076] In one exemplary embodiment, when the memory storage device 10 (memory management circuit 51) receives the reset command CMDR again, the memory storage device 10 may, for example, enter the reset mode MR2, and when the memory storage device 10 (memory management circuit 51) receives the power saving command CMDL again, the memory storage device 10 may, for example, enter the ultra-low power mode MS2.

[0077] To further explain, since the memory management circuit 51 has completed the initial configuration operation when the memory storage device 10 is in the ready mode MR1 and / or the low power mode MS1, when the memory storage device 10 (memory management circuit 51) receives the reset instruction CMDR (or power saving instruction CMDL) again, the memory storage device 10 may no longer enter the ready mode MR1 (or the low power mode MS1).

[0078] like Figure 8 As shown, after receiving the reset command CMDR for the first time, the memory storage device 10 can enter the ready mode MR1, and after receiving the power saving command CMDL, the memory storage device 10 can enter the low power mode MS1. When the memory storage device 10 is in the ready mode MR1 and the low power mode MS1, the memory management circuit 51 can perform the initial configuration operation, but does not perform other operations.

[0079] like Figure 9As shown, after receiving the reset command CMDR for the first time, the memory storage device 10 can enter the ready mode MR1, and after receiving the power saving command CMDL subsequently, the memory storage device 10 can enter the ultra-low power mode MS2. When the memory storage device 10 is in the ready mode MR1, the memory management circuit 51 can perform the initial configuration operation, and no other operation.

[0080] As shown, after receiving the reset command CMDR for the first time, the memory storage device 10 can enter the ready mode MR1, and after receiving the power saving command CMDL subsequently, the memory storage device 10 can enter the ultra-low power mode MS2. When the memory storage device 10 is in the ready mode MR1, the memory management circuit 51 can perform the initial configuration operation, and no other operation. Figure 10 Based on the above, after the memory storage device 10 is powered on, if the reset command CMDR received for the first time is adjacent to the power saving command CMDL, the memory management circuit 51 can perform the initial configuration operation when the memory storage device 10 is in the ready mode MR1 and / or the low power mode MS1, and no other operation. In this way, the memory management circuit 51 can complete the initial configuration operation before performing other operations, thereby avoiding compatibility problems and reducing initialization time.

[0081] On the other hand, in step S704, the memory management circuit 51 can perform the initial configuration operation in the ready mode MR1. Specifically, after the memory storage device 10 is powered on, if the memory storage device 10 (the memory management circuit 51) does not receive the power saving command CMDL subsequently after receiving the reset command CMDR for the first time (i.e., the reset command CMDR received for the first time is not adjacent to the power saving command CMDL), as shown in

[0082] Figure 11

[0083] Figure 11 is a schematic diagram of managing access rights and modes of a memory storage device according to an example embodiment of the present application. Please refer to Figure 11 When the reset command CMDR (or the power saving command CMDL) is a logic value of "0", it means that the memory storage device 10 (the memory management circuit 51) receives the reset command CMDR (or the power saving command CMDL).

[0084] As shown, after receiving the reset command CMDR for the first time, the memory storage device 10 can enter the ready mode MR1, and after receiving the power saving command CMDL subsequently, the memory storage device 10 can enter the ultra-low power mode MS2. When the memory storage device 10 is in the ready mode MR1, the memory management circuit 51 can perform the initial configuration operation, and no other operation. Figure 11 ​​As shown, after first receiving the reset command CMDR, the memory storage device 10 may, for example, enter the ready mode MR1. In the case that the memory storage device 10 is in the ready mode MR1, the memory management circuit 51 can perform the initial configuration operation and does not perform other operations.

[0085] Based on the above, after the memory storage device 10 is powered on, if the first received reset command CMDR is not adjacent to the power saving command CMDL, the memory management circuit 51 can perform the initial configuration operation in the case that the memory storage device 10 is in the ready mode MR1 and does not perform other operations. In this way, the memory management circuit 51 can complete the initial configuration operation before performing other operations, thereby avoiding compatibility problems and reducing initialization time.

[0086] It should be noted that the initial configuration method provided by the present application is based on the existing reset mode MR2 and the ultra-low power consumption mode MS2, and additionally proposes the ready mode MR1 and the low power consumption mode MS1, so that the memory management circuit 51 can complete the initial configuration operation before performing other operations, thereby avoiding compatibility problems caused by the existing method and reducing initialization time, and providing a two-stage power saving mode (i.e., the low power consumption mode MS1 and the ultra-low power consumption mode MS2) to meet different power consumption requirements.

[0087] It is worth mentioning that the power saving effect of the ultra-low power consumption mode MS2 may, for example, be better than the power saving effect of the low power consumption mode MS1. The power saving effect of the low power consumption mode MS1 may, for example, be equal to the power saving effect of the ready mode MR1. The power saving effect of the ultra-low power consumption mode MS2 may, for example, be equal to the reset mode MR2. Compared with the existing memory architecture, the memory storage device 10 provided by the present application is more difficult to enter the ultra-low power consumption mode MS2. Further, in the existing memory architecture, the reset command CMDR is used to instruct the memory storage device 10 to enter the reset mode MR2, and the power saving command CMDL is used to instruct the memory storage device 10 to enter the ultra-low power consumption mode MS2. However, the memory storage device 10 provided by the present application can enter the ready mode MR1 or the reset mode MR2 based on the first received reset command CMDR, and can enter the low power consumption mode MS1 or the ultra-low power consumption mode MS2 based on the power saving command CMDL received after the first received reset command CMDR. From the perspective of power saving effect, the initial configuration method of the present application is a method that is more difficult to enter the sleep mode (i.e., the ultra-low power consumption mode MS2).

[0088] Figure 12 is a flowchart of the initial configuration method according to an example embodiment of the present application. Please refer to Figure 12In step S1201, after the memory storage device 10 is powered on, it is determined whether the power saving instruction CMDL is received subsequently after the reset instruction CMDR is received for the first time. In step S1202, in response to the power saving instruction CMDL being received subsequently after the reset instruction CMDR is received for the first time, the initial configuration operation is performed in at least one of the preparation mode MR1 and the first power saving mode MS1.

[0089] However, Figure 12 The steps in the above embodiments have been described in detail, and thus will not be repeated here. It is worth noting that, Figure 12 The steps in the above embodiments can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. In addition, Figure 12 The method of the above embodiments can be used in combination with the above example embodiments, or can be used alone, and the present application is not limited thereto.

[0090] In summary, the initial configuration method, the memory storage device and the memory control circuit unit provided by the example embodiments of the present application can perform the initial configuration operation after power-on in the provided preparation mode and / or low power consumption mode, so that the memory storage device can complete the initial configuration operation before performing other operations, thereby avoiding the compatibility problem caused by the prior art method, reducing the initialization time, and providing a two-stage power saving mode to meet the power consumption demand in various power states.

[0091] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An initial configuration method, characterized by, An initial configuration method for a memory storage device, the initial configuration method comprising: after power-up of the memory storage device, determining whether a power saving instruction is subsequently received after a reset instruction is first received; and in response to the power saving instruction being subsequently received after the reset instruction is first received, performing an initial configuration operation in at least one of a preparation mode and a first power saving mode.

2. The initial configuration method of claim 1, further comprising: in response to the power saving instruction not being subsequently received after the reset instruction is first received, performing the initial configuration operation in the preparation mode.

3. The initial configuration method of claim 1, further comprising: in response to the reset instruction being first received, the memory storage device enters the preparation mode or a reset mode.

4. The initial configuration method of claim 3, further comprising: in the reset mode, the initial configuration operation is not performed.

5. The initial configuration method of claim 3, further comprising: in response to the reset instruction being received again, the memory storage device enters the reset mode.

6. The initial configuration method of claim 1, further comprising: in response to the power saving instruction being subsequently received after the reset instruction is first received, the memory storage device enters the first power saving mode or a second power saving mode.

7. The initial configuration method of claim 6, further comprising: in the second power saving mode, the initial configuration operation is not performed.

8. The initial configuration method of claim 6, further comprising: in response to the power saving instruction being received again, the memory storage device enters the second power saving mode.

9. A memory storage device, characterized by, comprising: a connection interface unit connected to a host system; a rewritable non-volatile memory module; and a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, wherein after power-up of the memory storage device, the memory control circuit unit is configured to: determine whether a power saving instruction is subsequently received after a reset instruction is first received, in response to the power saving instruction being subsequently received after the reset instruction is first received, perform an initial configuration operation in at least one of a preparation mode and a first power saving mode.

10. The memory storage device of claim 9, wherein, the memory control circuit unit is further configured to: in response to the power saving instruction not being subsequently received after the reset instruction is first received, perform the initial configuration operation in the preparation mode.

11. The memory storage device of claim 9, wherein, in response to the reset instruction being first received, the memory storage device enters the preparation mode or a reset mode.

12. The memory storage device of claim 11, wherein, the memory control circuit unit is further configured to: in the reset mode, the initial configuration operation is not performed.

13. The memory storage device of claim 11, wherein, in response to the reset instruction being received again, the memory storage device enters the reset mode.

14. The memory storage device of claim 9, wherein, in response to the power saving instruction being subsequently received after the reset instruction is first received, the memory storage device enters the first power saving mode or a second power saving mode.

15. The memory storage device of claim 14, wherein, the memory control circuit unit is further configured to: in the second power saving mode, the initial configuration operation is not performed.

16. The memory storage device of claim 14, wherein, In response to receiving the power saving instruction again, the memory storage device enters the second power saving mode.

17. A memory control circuit unit, characterized by The memory control circuit unit is disposed in a memory storage device, and includes: a host interface connected to the connection interface unit; a memory interface connected to the rewritable non-volatile memory module; and a memory management circuit connected to the host interface and the memory interface, wherein, after the memory storage device is powered on, the memory management circuit is configured to: determine whether a power saving instruction is received subsequently after a reset instruction is received for the first time, in response to the power saving instruction being received subsequently after the reset instruction is received for the first time, perform an initial configuration operation in at least one of a preparation mode and a first power saving mode.

18. The memory control circuit unit of claim 17, wherein, The memory management circuit is further configured to: in response to the power saving instruction not being received subsequently after the reset instruction is received for the first time, perform the initial configuration operation in the preparation mode.

19. The memory control circuit unit of claim 17, wherein, In response to receiving the reset instruction for the first time, the memory storage device enters the preparation mode or a reset mode.

20. The memory control circuit unit of claim 19, wherein, The memory management circuit is further configured to: in the reset mode, the initial configuration operation is not performed.

21. The memory control circuit unit of claim 19, wherein, In response to receiving the reset instruction again, the memory storage device enters the reset mode.

22. The memory control circuit unit of claim 17, wherein, In response to the power saving instruction being received subsequently after the reset instruction is received for the first time, the memory storage device enters the first power saving mode or a second power saving mode.

23. The memory control circuit unit of claim 22, wherein, The memory management circuit is further configured to: in the second power saving mode, the initial configuration operation is not performed.

24. The memory control circuit unit of claim 22, wherein, In response to receiving the power saving instruction again, the memory storage device enters the second power saving mode.

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