FPGA online updating implementation method based on PCIe interface

Abstract

The invention relates to an FPGA online updating implementation method based on a PCIe interface, and belongs to the technical field of embedding. On the basis of an original FPGA function module, a series of modules including the PCIe controller, the online updating module and the like are additionally added to achieve the online updating function. The mainboard sends a mirror image needing to be updated online to the FPGA through the PCIe interface, the FPGA writes the mirror image into the Flash chip through an online updating module achieved through internal logic, and online updating is achieved. Meanwhile, in the FPGA configuration mode, a multi-mirror-image scheme is adopted, that is, two or more mirror images exist in the Flash chip, only one mirror image is updated in online updating, and even if updating fails, the FPGA can be successfully configured through the other mirror image in the Flash chip. The method can be widely applied to computer products or similar scenes which are long in debugging period, difficult in structure disassembly and difficult in leading out special interfaces.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of embedded technology, and particularly relates to a PCIe interface-based FPGA online updating implementation method. BACKGROUND

[0002] In recent years, due to rich logical resources, flexible external interfaces, superior performance and the advantage of being able to be repeatedly changed, FPGAs gradually replace traditional MCU devices such as single-chip microcomputers and DSPs, and are widely applied to embedded computers and various engineering systems thereof. Whether in the early development or the later maintenance of products, FPGA images need to be updated.

[0003] The traditional FPGA updating method is to use the development software provided by the corresponding chip manufacturer to burn the FPGA image to be updated into a flash chip through a JTAG interface. However, this updating method has poor flexibility, and needs to be updated by another computer and specially installed development software. Meanwhile, the product or even the entire system needs to be disassembled to connect the special JTAG interface on the internal board card or module each time for updating, which is often difficult to achieve after the system is assembled, debugged and delivered for use. If a special interface is reserved on the external panel or other positions of the product during design, and the JTAG interfaces of the internal board card or module are all led to the interface through a cable, on the one hand, the cost and complexity of design are increased, and on the other hand, the electromagnetic compatibility and corrosion resistance of the product are affected. SUMMARY

[0004] (I) Technical problem to be solved

[0005] The technical problem to be solved by the application is how to provide a PCIe interface-based FPGA online updating implementation method to solve the problems of poor flexibility of the traditional FPGA updating method and increased design cost.

[0006] (II) Technical scheme

[0007] In order to solve the above technical problem, the application provides a PCIe interface-based FPGA online updating implementation method, which comprises the following steps:

[0008] The initial FPGA image is burned into the flash chip through JTAG only at the first time of debugging, and the FPGA image to be updated is transmitted into the product through any communication interface of the product and an updating program is run on the mainboard of the product in subsequent updating, the mainboard transmits the image data to the FPGA through the PCIe interface, and the FPGA writes the image data into the flash chip through the internal online updating module, so that the online updating of the FPGA image is realized.

[0009] The configuration of the FPGA adopts a MultiBoot multi-mirror image, that is, two or more mirror images exist in the Flash chip, and only one mirror image is updated online, so that the FPGA can be successfully configured through another mirror image in the Flash chip even if the update fails.

[0010] (III) Beneficial Effects

[0011] The application provides an FPGA online update implementation method based on a PCIe interface, which realizes an online update function by additionally adding a series of modules including a PCIe controller and an online update module to original FPGA function modules. In the method, a mainboard (or a main processor) sends a mirror image that needs to be updated online to the FPGA through a PCIe interface, and the FPGA writes the mirror image into a Flash chip through an online update module realized by internal logic, so that the online update is realized. Meanwhile, in terms of FPGA configuration, a multi-mirror image scheme is adopted, that is, two or more mirror images exist in the Flash chip, and only one mirror image is updated online, so that the FPGA can be successfully configured through another mirror image in the Flash chip even if the update fails. The method can be widely applied to computer products or similar scenes with long debugging periods, difficult structure disassembly and difficulty in leading special interfaces. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 An architecture comparison diagram of the two update methods of the application and prior art;

[0013] Figure 2 A MultiBoot multi-mirror image loading flowchart;

[0014] Figure 3 An FPGA logic architecture diagram;

[0015] Figure 4 A data encoding and decoding and protocol conversion module architecture diagram;

[0016] Figure 5 An online update module architecture diagram;

[0017] Figure 6 An initialization sub-module state transition diagram;

[0018] Figure 7 A data scheduling sub-module state transition diagram;

[0019] Figure 8 A command control sub-module state transition diagram. DETAILED DESCRIPTION

[0020] In order to make the purpose, content and advantages of the application clearer, the specific embodiments of the application are further described in detail below with reference to the drawings and examples.

[0021] The FPGA online updating implementation method based on a PCIe interface provided in the present application is a new FPGA program online updating method proposed in view of the shortcomings of the traditional method, and the architecture of the method is shown in Figure 1 The method comprises the following steps.

[0022] Unlike the traditional method, the initial FPGA image is burned into the Flash chip through JTAG only at the first time of debugging, and in subsequent updating, neither a special development machine installed with a development environment nor the connection of the JTAG interface between the development machine and the internal function board card of the product is needed, but only the FPGA image to be updated is transmitted into the product through any communication interface of the product, and the updating program is run on the mainboard (or main processor) of the product, so that the mainboard (or main processor) can download the image data to the FPGA through the PCIe interface, and the FPGA can write the image data into the Flash chip through the internal online updating module, thereby realizing the online updating of the FPGA image and greatly reducing the cumbersome degree of updating the FPGA image and the dependence on the external environment. In addition, in the design, the configuration of the FPGA adopts "MultiBoot multi-image", that is, two or more images exist in the Flash chip, and only one of the images is updated in the online updating, so that even if the updating fails, the FPGA can be configured successfully through another image in the Flash chip, and therefore even if the power is cut off or other unexpected situations occur during the updating, the subsequent updating can still be continued in this way, and the situation that the FPGA cannot be loaded with a complete image and cannot be updated again will not occur.

[0023] 1. Principle of MultiBoot multi-image

[0024] The so-called MultiBoot multi-image is that two or more images are stored in the configuration chip of the FPGA. Taking two images as an example, one of the images is stored from the base address of the configuration chip, and this image will never be changed or updated, which is called a Golden image; the other image is stored at the rear address of the configuration chip, which is called a Multi image, and the image is updated when online reconfiguration is performed.

[0025] When the device or board card is powered on, the FPGA loads the image from the base address of the configuration chip, that is, the Golden image, but in the constraint of the FPGA program of the Golden image, the IPROG command and the address of the Multi image are added, so that when the FPGA reads the command, the Golden image is directly skipped and the Multi image is directly loaded. However, when an error occurs during the loading of the Multi image, the FPGA triggers a rollback mechanism to load the Golden image again, and the specific loading process is as followsFigure 2 as shown.

[0026] In this way, it can be ensured that there is always a normal loadable image in the configuration chip. When power failure or other abnormal operation occurs during online reconfiguration, resulting in incomplete or erroneous Multi image that cannot be normally loaded, the Golden image can still be loaded to re-perform online update.

[0027] 2. FPGA logic design

[0028] In the implementation method described in the present application, in addition to realizing the original function of the FPGA logic, an independent switching module is additionally realized to realize the online update function. The switching module exchanges data with the driving software in the CPU through the internally instantiated PCIe controller, and writes the Multi image into the configuration chip through the online update module realized by logic. The design architecture of the FPGA logic is shown in Figure 3 , mainly including: PCIe controller, data encoding and decoding and protocol conversion module, and online update module, etc.

[0029] (1) PCIe controller

[0030] The PCIe controller module mainly realizes the interconnection communication between the CPU and the FPGA, so that the CPU can write the image to be updated into the FPGA. In the present method, the 7Series Integrated Block for PCI Express hard core integrated in the FPGA is used as the PCIe controller. The controller can generate or process the transaction layer data packet (TLP packet) of the PCIe bus between the CPU and the FPGA, and convert it into an AXI-Stream bus for interconnection with other modules inside the FPGA. The IP core supports a maximum of x8 channel quantity and 5GT / s communication speed, meeting the needs of the present method.

[0031] (2) Data encoding and decoding and protocol conversion module

[0032] The data encoding and decoding and protocol conversion module mainly realizes the conversion fan-out function of data among the internal buses of the FPGA. That is, the AXI-Stream bus at one end of the PCIe controller module is converted into an AXI-Lite bus, and is expanded according to the address, and finally forms a 16-way AXI-Lite bus for mounting up to 16 independent functional modules. The architecture of the data encoding and decoding and protocol conversion module is shown in Figure 4

[0033] ​At the receiving end, the data receiving submodule decodes the TLP packet of AXI-Stream protocol, extracts the request type, length, data address and other information and passes them to the fan-out module, the master end of 16-way AXI-Lite bus is generated in the fan-out module, according to the address in the decoding information, the corresponding slave end device is selected to initiate AXI-Lite write operation, and the data transmission is completed.

[0034] At the sending end, the fan-out module selects the corresponding slave end device to initiate AXI-Lite read operation according to the address decoded and passed by the data receiving submodule, and passes the read data to the data sending submodule. The data sending submodule synthesizes the data and address to complete the preparation of TLP packet, and sends it to the PCIe controller module according to the AXI-Stream bus protocol.

[0035] (3) Online updating module

[0036] The online updating module is a module for writing Multi image into configuration chip to complete updating, the uplink end of which is AXI-Lite bus interface, which is interconnected with the data coding and decoding and protocol conversion module for data exchange, and the downlink end of which is SPI bus interface, which is interconnected with the configuration chip to realize the reading and writing of image. In the method, the module is realized by self-written logic code and packaged into IP core, and the specific architecture is as shown in Figure 5

[0037] The module includes two parts, namely the register submodule and the updating implementation submodule.

[0038] The register submodule is a window for communication between the online updating module and the upper module, and its main function is to generate a corresponding control word according to the content written in the register, or to store a status word in the register for query. At the same time, the buffer area for storing data is also placed in the module, and the buffer area size is 512 bytes. Before the driving software writes data into the buffer area each time, the status register is queried first. When the space in the buffer area is greater than 256 bytes (1 page), 256 bytes of data are written into the buffer area at a time, and after these data are written into the flash chip, the operation is repeated until all data are written. The specific registers set in the module are shown in Table 1.

[0039] Table 1 Register list

[0040]

[0041]

[0042] ​The main function of the update implementation sub-module is to complete the online update of the image according to the configuration instructions of the register sub-module, or to feed back the state information to the register sub-module. The main structure thereof includes four third-level sub-modules, namely, an initialization sub-module, a data scheduling sub-module, a command control sub-module and an interface control sub-module.

[0043] The initialization sub-module is mainly responsible for generating control commands in the chip initialization stage, and executes the commands through the interface control sub-module, including reset, setting communication mode and the like. The main state machine of the module is shown in Figure 6 .

[0044] (a) After power-on, the timer contained in the module automatically starts running, and generates a trigger signal after reaching the timing value. The state machine starts from IDLE, and executes steps 11, 2 in turn, and completes the reset enable and reset operation of the configuration chip in the RSEN and RSMM states;

[0045] (b) After executing step 13 and waiting for the completion of the reset of the configuration chip, step 14 is executed to jump to the EQPI state to complete the enable of the QSPI mode of the configuration chip.

[0046] (c) After executing step 15 and waiting, step 16 is executed to jump to the RFLAG state to read the state of the configuration chip to judge whether the setting is completed, and after completion, steps 17, 18 are executed to return to the IDLE state.

[0047] The data scheduling sub-module and the command control sub-module are jointly responsible for generating control commands in the online update stage of the image. The data scheduling sub-module is responsible for generating task instructions in different stages, such as block erasing and page writing, according to the control word of the register module and the buffer state; and the command control sub-module is responsible for decomposing each task instruction into specific flash control commands, such as write enable, write-in and read state commands.

[0048] The main state machine of the data scheduling sub-module is shown in Figure 7 .

[0049] (aa) Initially located in the IDLE state, when receiving the control word for starting the online update, step 21 is executed to generate a block erasing task instruction in the ERASE state, and then step 22 is executed to jump to the E_ERASE state to wait for the completion of erasing;

[0050] (bb) When the erasing is completed, step 23 is executed to jump to the CHECK state to check whether there is one page (256 bytes) of data in the buffer that can be written into the flash, or although there is no one page of data, the tail flag has been detected. If yes, step 24 is executed to jump to the PROG state, otherwise, waiting;

[0051] (cc) generating a page write task instruction in the PROG state, and then executing step 25 to jump to the E_PROG state to wait for completion of the page write;

[0052] (dd) when the page write is completed, first, the address is accumulated, and then, a judgment is made, if the frame end flag is detected and the cache is empty, step 26 is executed to jump to the END state, and then the on-line update is completed, and step 29 is executed to return to the IDLE state; if the frame end flag is not detected, the number of written pages is judged by counting, if the number of written pages reaches 256, step 27 is executed to jump to the ERASE state to perform block erasing on the next block, otherwise, step 28 is executed to jump to the CHECK state to perform the next page write.

[0053] The main state machine of the command control sub-module is shown in Fig. 2. Figure 8

[0054] (aaa) initially located in the IDLE state, when receiving a task instruction of the data scheduling sub-module, and the initialization sub-module has completed the initialization of the flash, the type of the task is judged, if the task is a page erase, block erase, page write or other write type operation, step 31 is executed to jump to the WREN state; otherwise, step 37 is executed to directly jump to the RUN state.

[0055] (bbb) when located in the WREN state, a write enable command is generated, and step 32 is executed to jump to the WAIT1 state to wait for 0.5 ms, and after the waiting is completed, step 33 is executed to jump to the R_STATUS state.

[0056] (ccc) when located in the R_STATUS state, a read status command is generated, and after the completion, a judgment is made, if the bits 1-0 of the obtained status are 11, the write enable command is not executed completely, step 34 is executed to jump back to the WAIT1 state to continue waiting for 0.5 ms; if the bits 1-0 of the obtained status are 0X, the write enable command is executed unsuccessfully, step 35 is executed to jump back to the WREN state to re-execute the write enable command; if the bits 1-0 of the obtained status are 10, the write enable command is executed successfully, step 36 is executed to jump to the RUN state.

[0057] (ddd) when located in the RUN state, according to the type of the task instruction, a corresponding flash control command (block erase, page write, fast read, etc.) is generated, and step 38 is executed to jump to the WAIT2 state to wait for 0.5 ms, and after the waiting is completed, step 39 is executed to jump to the R_FLAG state.

[0058] ​(eee) When in the R_FLAG state, a read state command is generated, and after completion, it is determined whether the bit0 of the obtained state is 0, and if so, steps 311 and 312 are executed, and the task instruction is completed, and the IDLE state is returned; if the bit0 of the obtained state is 1, step 310 is executed, and the WAIT2 state is returned to continue waiting for 0.5 ms.

[0059] The interface control sub-module is mainly responsible for the actual implementation of writing the image into the flash. According to the control commands, data and other contents generated by the previous modules, the module organizes the information into data in the spi protocol format, and performs operations such as resetting, erasing, writing data and reading states on the flash chip.

[0060] Embodiment 1:

[0061] The application will be described in detail below by a system that has been applied in engineering practice. The example is only used to further illustrate the application, and does not limit the application.

[0062] Specifically, the product includes a mainboard (the mainboard also includes an FPGA), two functional board cards, and is inserted into the bottom plate in the case. The CPU on the mainboard is connected with the mainboard and the FPGA on the other functional board cards through the PCIe bus. Due to objective factors, the case cannot be disassembled and the JTAG debugging cable cannot be introduced after overall assembly, but the debugging Ethernet interface can be introduced through the aviation plug.

[0063] Before the product is completed and assembled, the two images need to be burned into the flash chip through the JTAG interface using a special development machine. After it is determined that the burning is successful, the product can be delivered for assembly.

[0064] When the image needs to be updated during subsequent debugging, the image to be updated is transmitted into the device through the debugging Ethernet interface, the driving software is loaded on the mainboard, the application software for online updating is run, the board card whose FPGA image needs to be updated and the path where the image is saved are selected, and the updating operation is performed. After the updating is completed, the mainboard receives an interrupt and prints that the updating is successful.

[0065] After the updating is completed, the device is powered off and powered on again. After the driving program is loaded, it can be confirmed that the FPGA online updating is successful by printing the board card version number information.

[0066] The application relates to a PCIe interface-based FPGA online updating implementation method. The method realizes the online updating function by additionally adding a series of modules including a PCIe controller and an online updating module and the like on the basis of original FPGA function modules. In the method, a mainboard (or a main processor) sends an image needing online updating to the FPGA through a PCIe interface, the FPGA writes the image into a Flash chip through an online updating module realized by internal logic, and online updating is realized. Meanwhile, in the FPGA configuration mode, a multi-image scheme is adopted, that is, two or more images exist in the Flash chip, and only one image is updated in the online updating, so that the FPGA can be configured successfully through another image in the Flash chip even if the updating fails. The method can be widely applied to computer products or similar scenes with long debugging periods, difficult structure disassembly and difficulty in leading special interfaces.

[0067] The above only describes the preferred embodiments of the application, and it should be noted that those skilled in the art can make several improvements and modifications without departing from the technical principles of the application, and these improvements and modifications should also be considered as the protection scope of the application.

Claims

1. A PCIe interface-based FPGA online updating implementation method, characterized in that, The method comprises: Only the initial FPGA image is burned into the Flash chip through JTAG at the first time of debugging, and subsequent updates require the updated FPGA image to be transmitted into the product through any communication interface of the product, and an update program is run on the mainboard of the product, the mainboard transmits the image data to the FPGA through the PCIe interface, and the FPGA writes the image data into the Flash chip through the internal online update module to realize online update of the FPGA image; The configuration of the FPGA adopts "MultiBoot multi-image", that is, two or more images exist in the Flash chip, and only one of the images is updated online, so that the FPGA can be successfully configured through another image in the Flash chip even if the update fails.

2. The PCIe interface-based FPGA online updating implementation method according to claim 1, wherein, The MultiBoot multi-image is two or more images stored in the configuration chip of the FPGA; if there are two images, one of the images is stored from the base address of the configuration chip, and the image is never changed or updated and is called a Golden image; the other image is stored at a position close to the rear address of the configuration chip and is called a Multi image, which is updated when online reconstruction is performed; When the device or board card is powered on, the FPGA loads the image from the base address of the configuration chip, that is, the Golden image, but in the constraint of the FPGA program of the Golden image, the IPROG command and the address of the Multi image are added, so that when the FPGA reads the command, the Golden image is directly skipped and the Multi image is directly loaded; when an error occurs during loading of the Multi image and the loading cannot continue, the FPGA triggers a fallback mechanism to load the Golden image again.

3. The PCIe interface-based FPGA online updating implementation method according to claim 1 or 2, wherein, The FPGA logic realizes the online update function through a set of independent adapter modules, the adapter modules exchange data with the driving software in the CPU through the internally instantiated PCIe controller, and the Multi image is written into the configuration chip through the online update module realized by logic.

4. The PCIe interface-based FPGA online updating implementation method according to claim 3, wherein, The adapter module of the FPGA comprises a PCIe controller, a data encoding and decoding and protocol conversion module, and an online update module. The PCIe controller is used for realizing interconnection communication between the CPU and the FPGA, so that the CPU writes the image to be updated into the FPGA. The data encoding and decoding and protocol conversion module is used for realizing the conversion fan-out function of data among internal buses of the FPGA, that is, converting the AXI-Stream bus at one end of the PCIe controller module into an AXI-Lite bus. The online update module is used for writing the Multi image into the configuration chip to complete the update, the uplink end of the online update module is an AXI-Lite bus interface, the online update module is interconnected with the data encoding and decoding and protocol conversion module to exchange data, and the downlink end of the online update module is an SPI bus interface, and the online update module is interconnected with the configuration chip to realize reading and writing of the image.

5. The PCIe interface-based FPGA online updating implementation method according to claim 4, wherein, In the PCIe controller, a 7Series Integrated Block for PCI Express hard core integrated in the FPGA is used as the PCIe controller, the controller generates or processes transaction layer data packet (TLP) of the PCIe bus between the CPU and the FPGA, and is converted into an AXI-Stream bus to interconnect with other modules in the FPGA.

6. The PCIe interface based FPGA online updating implementation method according to claim 5, characterized in that, In the data coding and protocol conversion module, in the receiving end, a data receiving submodule decodes the TLP packet of the AXI-Stream protocol, extracts the request type, length and data address information and transmits them to a fan-out module, a master end of a 16-way AXI-Lite bus is generated in the fan-out module, an AXI-Lite write operation is initiated to the corresponding slave end device according to the address in the decoding information, and data transmission is completed; In the sending end, the fan-out module initiates an AXI-Lite read operation to the corresponding slave end device according to the address decoded and transmitted by the data receiving submodule, and transmits the read data to a data sending submodule; The data sending submodule synthesizes data and address to complete the preparation of the TLP packet, and transmits it to the PCIe controller module in compliance with the AXI-Stream bus protocol.

7. The PCIe interface based FPGA online updating implementation method according to claim 6, wherein, The online updating module comprises a register submodule and an updating implementation submodule. The register submodule is a window for the online updating module to communicate with the upper module, generates a corresponding control word according to the content written in the register, or stores a state word in the register for query; meanwhile, a buffer area for storing data is also placed in the module, the buffer area has a size of 512 bytes, before the driving software writes data into the buffer area each time, the state register is queried first, when the space in the buffer area is greater than 256 bytes, 256 bytes of data are written into the buffer area at one time, and after the data are written into the flash chip, the operation is repeated until all data are written in; The updating implementation submodule completes the online updating of the image according to the configuration instructions of the register submodule, or feeds back the state information to the register submodule, comprising four third-level submodules, namely, an initialization submodule, a data scheduling submodule, a command control submodule and an interface control submodule; The initialization submodule is responsible for generating control commands in the chip initialization stage, and executes the control commands through the interface control submodule, including reset and setting communication mode; The data scheduling submodule and the command control submodule jointly generate control commands in the image online updating stage; the data scheduling submodule is responsible for generating task instructions in different stages according to the control word of the register module and the buffer state; the command control submodule is responsible for decomposing each task instruction into specific flash control commands; The interface control submodule is responsible for the actual implementation of writing the image into the flash, the module organizes information into data in compliance with the spi protocol format according to the control commands and data content generated by the previous modules, and performs reset, erasing, writing data and reading state operations on the flash chip.

8. The PCIe interface based FPGA online updating implementation method according to claim 7, characterized in that, The running logic of the initialization sub-module is: (a) After power-on, the timer contained in the module automatically starts running, and generates a trigger signal after reaching the timing value, the state machine starts from IDLE, and executes steps 11, 2 in turn, and completes the reset enable and reset operation of the configuration chip in the RSEN and RSMM states; (b) After executing step 13 and waiting for the completion of the configuration chip reset, execute step 14 to jump to the EQPI state to complete the enable of the configuration chip QSPI mode; (c) After executing step 15 and waiting, execute step 16 to jump to the RFLAG state to read the configuration chip state to determine whether the setting is completed, and after completion, execute steps 17, 18 to return to the IDLE state.

9. The PCIe interface-based FPGA online updating implementation method according to claim 7, wherein, The running logic of the data scheduling sub-module is: (aa) Initially in the IDLE state, when receiving the control word for starting online updating, execute step 21 to generate a block erase task instruction in the ERASE state, and then execute step 22 to jump to the E_ERASE state to wait for completion of erasing; (bb) When the erasing is completed, execute step 23 to the CHECK state to check whether there is a page of data 256Byte written into the flash in the cache, or although there is no page of data, but the tail flag has been detected, if it is satisfied, execute step 24 to jump to the PROG state, otherwise wait; (cc) Generate a page write task instruction in the PROG state, and then execute step 25 to jump to the E_PROG state to wait for completion of page writing; (dd) When the page writing is completed, first, the address is accumulated, and then it is judged, if the frame tail flag is detected and the cache is empty, execute step 26 to jump to the END state, and then complete the online updating to execute step 29 to return to the IDLE state; if the frame tail flag is not detected, it is judged by counting whether the number of written pages reaches 256, if it reaches, execute step 27 to jump to the ERASE state to perform block erasing on the next block, otherwise, execute step 28 to jump to the CHECK state to execute the next page writing.

10. The PCIe interface based FPGA online update implementation method of claim 7, wherein, The running logic of the command control sub-module is: (aaa) Initially in the IDLE state, when receiving a task instruction of the data scheduling sub-module, and the initialization sub-module has completed the initialization of the flash, the task type is judged, if the task is a write type operation, execute step 31 to jump to the WREN state; otherwise, execute step 37 to directly jump to the RUN state; (bbb) When in the WREN state, generate a write enable command, and execute step 32 to the WAIT1 state to wait for 0.5ms, and after the waiting is completed, execute step 33 to jump to the R_STATUS state; (ccc) When in the R_STATUS state, a read status command is generated, and after completion, a determination is made. If the bits 1-0 of the obtained status are 11, the write enable command is not executed completely, step 34 is executed to jump back to the WAIT1 state to continue waiting for 0.5 ms. If the bits 1-0 of the obtained status are 0X, the write enable command is executed unsuccessfully, step 35 is executed to jump back to the WREN state to re-execute the write enable command. If the bits 1-0 of the obtained status are 10, the write enable command is executed successfully, step 36 is executed to jump to the RUN state; (ddd) When in the RUN state, a corresponding flash control command is generated according to the task instruction type, step 38 is executed to jump to the WAIT2 state to wait for 0.5 ms, and after the waiting is completed, step 39 is executed to jump to the R_FLAG state; (eee) When in the R_FLAG state, a read status command is generated, and after completion, a determination is made. If the bit 0 of the obtained status is 0, steps 311 and 312 are executed to jump back to the IDLE state to complete the task instruction. If the bit 0 of the obtained status is 1, step 310 is executed to jump back to the WAIT2 state to continue waiting for 0.5 ms.

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