Instruction scheduling circuits, chips, data processing methods, and electronic devices

Abstract

This application provides an instruction scheduling circuit, a chip, a data processing method, and an electronic device. The instruction scheduling circuit includes a collector, a first timestamp counter, and a data buffer. The collector receives instruction status signals from the engine, including start and end status signals of the instructions received by the engine. The first timestamp counter receives a first timestamp signal generated based on a sampling clock counter. The data buffer receives a data packet composed of the instruction status signal, the first timestamp signal, and a second timestamp signal, and writes the data packet into memory. The second timestamp signal is generated based on a system clock counter. This application enables precise counting of the start and end timestamps of each instruction in a multi-threaded scheduler to obtain the runtime of each instruction.

Description

Technical Field

[0001] This application relates to the field of AI chip design, and more particularly to an instruction scheduling circuit, a chip, a data processing method, and an electronic device. Background Technology

[0002] In AI chips, the instruction scheduler has a profiling function, which is an important tool for performance optimization and resource management. Profiling can track instruction runtime, idle cycle ratio, and high-energy-consuming operations (such as frequently repeated calls). Accurate data collection and analysis can reveal hardware execution details, which is crucial for resource and performance tuning. However, it is difficult to accurately obtain the runtime of each instruction in related technologies. Summary of the Invention

[0003] This application provides an instruction scheduling circuit, chip, data processing method, and electronic device, which can accurately count the start and end timestamps of each instruction in a multi-threaded scheduler to obtain the runtime of each instruction.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] This application provides an instruction scheduling circuit, including: a collector, a first timestamp counter, and a data buffer;

[0006] The collector is used to receive command status signals from the engine, wherein the command status signals include start status signals and end status signals of the commands received by the engine.

[0007] The first timestamp counter is used to receive a first timestamp signal generated based on a sampling clock counter;

[0008] The data buffer is used to receive a data packet consisting of the instruction status signal, the first timestamp signal, and the second timestamp signal, and to write the data packet into memory;

[0009] The second timestamp signal is generated based on the system clock counter.

[0010] This application provides a data processing method, including:

[0011] The collector receives command status signals from the engine, wherein the command status signals include start status signals and end status signals of the commands received by the engine.

[0012] The first timestamp counter receives the first timestamp signal generated based on the sampling clock counter;

[0013] The data buffer receives a data packet consisting of the instruction status signal, the first timestamp signal, and the second timestamp signal, and writes the data packet into memory;

[0014] The second timestamp signal is generated based on the system clock counter.

[0015] This application provides a data processing apparatus, including:

[0016] The acquisition module is used for the acquisition unit to receive command status signals from the engine, wherein the command status signals include start status signals and end status signals of the commands received by the engine.

[0017] The counting module is used to receive the first timestamp signal generated based on the sampling clock counter from the first timestamp counter;

[0018] The caching module is used for the data cache to receive a data packet consisting of the instruction status signal, the first timestamp signal, and the second timestamp signal, and to write the data packet into memory; wherein the second timestamp signal is generated based on the system clock counter.

[0019] This application provides a chip having the instruction scheduling circuit described above deployed on it.

[0020] This application provides an electronic device, including a processor, wherein a chip within the processor is equipped with the instruction scheduling circuit described above.

[0021] This application provides an electronic device, including:

[0022] Memory is used to store executable instructions or computer programs.

[0023] The processor, when executing computer-executable instructions or computer programs stored in the memory, implements the data processing method provided in the embodiments of this application.

[0024] This application provides a computer-readable storage medium storing a computer program or computer-executable instructions, which, when executed by a processor, implements the data processing method provided in this application.

[0025] This application provides a computer program product, including a computer program or computer executable instructions. When the computer program or computer executable instructions are executed by a processor, they implement the data processing method provided in this application.

[0026] The embodiments of this application have the following beneficial effects:

[0027] The scheduling circuit provided in this application receives instruction status signals from the engine through a data acquisition unit, ensuring real-time feedback on instruction execution status. The data acquisition unit integrates the start and end status signals of the instruction, acquiring the complete lifecycle of the instruction for easier subsequent management and optimization. Secondly, by sampling the timestamp signals generated by the clock counter and the system clock counter using a timestamp counter, high-precision timing can be provided to accurately determine the execution time of different instruction states. Thirdly, by receiving instruction status signals through a data buffer and combining the timestamp signals with the instruction status signals to form a data packet, a temporary storage space is provided for the data packet. This ensures data integrity before the data packet is written to memory, and by caching data, the risk of data loss and the number of direct memory accesses are reduced, improving the overall operating efficiency of the system. Attached Figure Description

[0028] Figure 1 Schematic diagram of the instruction scheduling circuit provided in the embodiments of this application Figure 1 ;

[0029] Figure 2 Schematic diagram of the instruction scheduling circuit provided in the embodiments of this application Figure 2 ;

[0030] Figure 3 Schematic diagram of the instruction scheduling circuit provided in the embodiments of this application Figure 3 ;

[0031] Figure 4 Schematic diagram of the instruction scheduling circuit provided in the embodiments of this application Figure 4 ;

[0032] Figure 5 Schematic diagram of the instruction scheduling circuit provided in the embodiments of this application Figure 5 ;

[0033] Figure 6 This is a flowchart illustrating the data processing method provided in an embodiment of this application;

[0034] Figure 7 This is a schematic diagram of the instruction scheduling circuit provided in an embodiment of this application;

[0035] Figure 8 This is a schematic diagram of the performance analysis provided in the embodiments of this application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0038] It is understood that in the embodiments of this application, data such as user information are involved. When the embodiments of this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of related data must comply with relevant laws, regulations and standards.

[0039] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0040] In the following description, the terms “first, second, ...” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first, second, ...” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0042] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0043] 1) Responding to: used to indicate the conditions or states on which the operation is performed depends. When the conditions or states on which it depends are met, one or more operations can be performed in real time or with a set delay. Unless otherwise specified, there is no restriction on the order in which the multiple operations are performed.

[0044] 2) Instruction Scheduler: The instruction scheduler is a component of the processor responsible for optimizing the execution order of instructions to improve processor performance. The purpose of the instruction scheduler is to reduce execution latency by rearranging the execution order of instructions, allowing for more efficient use of processor resources. When the processor executes instructions, it encounters various types of instructions, including arithmetic operations, data loading, data storage, and branch instructions. These instructions may have data dependencies (e.g., the output of one instruction is the input of another), or they may be completely independent. The instruction scheduler analyzes these dependencies and, where possible, rearranges the execution order of instructions to execute as many instructions in parallel as possible without violating data dependencies.

[0045] 3) Profile Unit: In the instruction scheduler, the Profile unit analyzes the program's behavior by collecting statistical information during the program's execution. The statistical information can include the number of times each instruction is executed, the execution time, the accuracy of branch prediction, the cache hit rate, etc. Through the Profile unit, the instruction scheduler can more accurately understand the program's behavior and optimize it based on this information to improve the program's execution efficiency and overall performance.

[0046] 4) Timestamp Counter (TC): The timestamp counter is used to record the number of clock cycles that have elapsed since the processor started. It can provide a precise time measurement function for the program. The value of the timestamp counter increments with each processor clock cycle. It can be used to measure time intervals, calculate the execution time of the program, or serve as a mechanism for synchronizing multiple processors or threads.

[0047] 5) Burst Statistical Counter: A Burst Statistical Counter is a high-performance counter used in processors or network devices to record the number of occurrences or duration of specific events. It can be used to handle a large number of events that occur in a short period of time, such as burst transmission of data packets or burst operation of the processor.

[0048] 6) Central Processing Unit (CPU): The CPU is the core computing and control component of a computer system. It is responsible for executing program instructions, processing data, and coordinating the work of various hardware components. Its performance directly affects the overall operating efficiency of the computer.

[0049] 7) Register: A register is a high-speed storage component used to temporarily store instructions, data and addresses. It consists of flip-flops or latches, and each flip-flop stores 1 bit of binary code.

[0050] 8) Sampling Clock: The sampling clock is the reference clock signal used in a digital signal processing system to synchronize the sampling of analog signals. Its frequency and stability directly determine the accuracy of the analog-to-digital converter (ADC) and the quality of signal reproduction.

[0051] 9) Thread: A thread is the smallest unit of execution that the operating system can schedule. It is the actual execution unit within a process. A process can contain multiple threads. Each thread represents an independent flow of control, shares process resources (such as memory and file handles), but has its own independent call stack and register state.

[0052] 10) Engine: In the field of computer science, an engine is a modular component that provides core functional support for a system or application. Engines provide standardized interfaces for developers by encapsulating complex underlying logic.

[0053] 11) AXI Bus (Advanced eXtensible Interface): The AXI bus is a high-performance, on-chip interconnect protocol primarily used for high-speed data communication between various modules within a chip (such as CPU, DMA, accelerators, memory controllers, etc.). It supports parallel transmission of address, data, and control signals, thereby improving throughput. A single address transmission can follow multiple data cycles, reducing address channel overhead. It includes five independent channels: read address, read data, write address, write data, and write response. It supports full-duplex communication and can achieve out-of-order transaction completion through ID tags to improve bus utilization. It has configurable data bit widths, commonly 32, 64, 128, 256, and 512 bits, to adapt to different bandwidth requirements. The AXI bus is widely used in SoC (System-on-a-Chip) design, serving as a high-performance bridge connecting the processor with peripherals, memory, and accelerators.

[0054] In AI chips, the instruction scheduler has a profiling function, which is an important tool for performance optimization and resource management. Profiling can track instruction runtime, idle cycle ratio, and high-energy-consuming operations (such as frequently repeated calls). Accurate data collection and analysis can reveal hardware execution details, which is crucial for resource and performance tuning. However, it is difficult to accurately obtain the runtime of each instruction in related technologies.

[0055] Based on this, embodiments of this application provide an instruction scheduling circuit, chip, data processing method, and electronic device, which can accurately count the start and end timestamps of each instruction in a multi-threaded scheduler to obtain the runtime of each instruction.

[0056] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0057] In some embodiments, Figure 1 Schematic diagram of the instruction scheduling circuit provided in the embodiments of this application Figure 1 .like Figure 1 As shown, the instruction scheduling circuit 10 may include a collector 101, a first timestamp counter 102, and a data buffer 103, wherein:

[0058] Collector 101 is used to receive command status signals from the engine.

[0059] Here, the command status signals include the start status signal and the end status signal of the command received by the engine.

[0060] In some embodiments, the data acquisition device can be a communication interface, such as RS-485; it can also be a sensor module, that is, synchronously acquiring the status signals transmitted by the engine; it can also be a signal conditioning circuit, etc., without specific limitations.

[0061] It should be noted that different encoding methods can be used to represent command status signals. For example, in one-hot encoding, each bit represents the start or end state of the command on different engines; another example is to use the first three bits to represent different engines and the fourth bit to represent the start or end state of the command.

[0062] As an example, taking one-hot encoding, suppose there are four engines 0 to 3. At a certain moment, the command status signal includes the start status signal of the command of engine 0 and the end status signal of the command of engine 3. Then the command status signal can be encoded as 1000, 0001, with the first four bits recording the start status signal and the last four bits recording the end status signal.

[0063] It should be noted that the high four bits correspond to "engine 0 starts, engine 1 starts, engine 2 starts, engine 3 starts" in sequence, and the low four bits correspond to "engine 0 ends, engine 1 ends, engine 2 ends, engine 3 ends" in sequence. When any engine starts or ends at any time, the corresponding bit is set to 1, and the other bits remain 0. When engine 0 sends out a start pulse, the first bit of the high four bits is set to 1. When engine 3 sends out an end pulse, the fourth bit of the low four bits is set to 1, ultimately forming an 8-bit vector 1000_0001.

[0064] In some embodiments, the instruction status signal may also include the thread to which the instruction belongs.

[0065] As an example, taking one-hot encoding, suppose there are two threads 0 and 1, and four engines 0 to 3. At a certain moment, the instruction status signal includes the start status signal of the instruction of engine 1 of thread 0 and the end status signal of the instruction of engine 2 of thread 1. Then the instruction status signal can be encoded as 0100, 0000, 0000, 0010, with the first eight bits recording the start status signal and the last eight bits recording the end status signal.

[0066] It should be noted that the high eight bits are arranged in the following order: "Thread 0 Engine 0 Start → Thread 0 Engine 1 Start → Thread 0 Engine 2 Start → Thread 0 Engine 3 Start → Thread 1 Engine 0 Start → Thread 1 Engine 1 Start → Thread 1 Engine 2 Start → Thread 1 Engine 3 Start". The low eight bits correspond to the end status events in the same order. When Thread 0 emits a start pulse at Engine 1, the second bit of the high eight bits is set to 1. At the same time, when Thread 1 emits an end pulse at Engine 2, the sixth bit of the low eight bits is set to 1. The remaining 14 bits remain 0, ultimately forming a 16-bit vector 0100_0000_0000_0010.

[0067] The first timestamp counter 102 is used to receive the first timestamp signal generated based on the sampling clock counter.

[0068] It should be noted that the sampling clock counter is a key component in digital signal processing and data acquisition systems, used to precisely control the sampling timing of analog signals and count the number of clock pulses.

[0069] The data buffer 103 is used to receive a data packet consisting of an instruction status signal, a first timestamp signal, and a second timestamp signal, and write the data packet into memory.

[0070] Here, the second timestamp signal is generated based on the system clock counter. The system clock counter is a core hardware module in a computer or embedded system used to accurately measure time intervals. It is usually integrated inside the CPU or microcontroller and can provide precise time units through the system clock pulse.

[0071] It should be noted that the data packet consisting of the instruction status signal, the first timestamp signal, and the second timestamp signal can be implemented in hardware, using a parallel bus to transmit data, and using a custom protocol (such as UART or SPI) to package the instruction status and timestamp into a fixed format frame (e.g., [instruction][T1][T2]).

[0072] In some embodiments, a data buffer is a technical component for temporarily storing data, which improves system efficiency by coordinating the differences in data transmission rates between different hardware or software modules.

[0073] In this embodiment, the collector 101 is used to receive instruction status signals from the engine. The instruction status signals include start status signals and end status signals of the instructions received by the engine. For example, the start status signal includes the start status signal of engine 1 and the end status signal of engine 2. The first timestamp counter 102 can receive the first timestamp signal generated based on the sampling clock counter, which can provide high-precision timing. The data buffer 103 can receive data packets composed of instruction status signals, first timestamp signals and second timestamp signals, and write the data packets into memory. By associating time information with instruction status signals, the start and end times of different instructions can be accurately recorded, so as to facilitate subsequent analysis of different instruction data.

[0074] As an example, the data acquisition device receives command status signals from the engine. The first timestamp signal received by the first timestamp counter is the first timestamp signal generated by the sampling clock counter. The second timestamp signal generated based on the system clock counter is , will command status signal First timestamp signal and the second timestamp signal Composition of data packets for[ , , The data buffer receives data packets. and data packets Write to memory.

[0075] It should be noted that the collector receives a status signal from the engine. Simultaneously, a 700MHz sampling clock counter and a 25MHz system clock counter are triggered respectively, and the count values ​​at this moment are captured as... and The three are assembled into a complete packet S in a fixed order. Then the buffer pushes the entire packet into the FIFO. Once the cumulative bit width reaches the width of the AXI bus, it is written into memory at once, completing a lossless event recording with double timestamps.

[0076] In some embodiments, Figure 2 Schematic diagram of the instruction scheduling circuit provided in the embodiments of this application Figure 2 .like Figure 2 As shown, the instruction scheduling circuit 10 may also include a statistical counter 104.

[0077] Data buffer 103 is used to buffer received data packets, and when the amount of data in the data buffer reaches the bus width, or when the last instruction status signal data packet is received, all buffered data packets in the data buffer are written to memory.

[0078] It should be noted that bus width refers to the number of bits of binary data that a bus in a computer system can transmit simultaneously. It is usually expressed in bits. Bus width determines the amount of data that can be transmitted in each clock cycle. The larger the bus width, the larger the amount of data transmitted in a single transmission and the higher the data transmission efficiency.

[0079] The statistics counter 104 is used to count the first number of data packets written to memory by the statistics buffer. When the first number of data packets written to memory reaches a first threshold, the first number of data packets is synchronized to the central processing unit.

[0080] It should be noted that the first threshold is preset and is used to measure whether the amount of data written to memory needs to be synchronized to the central processing unit.

[0081] In this embodiment, the data buffer 103 is used to buffer the received data packets. When the amount of data in the data buffer reaches the bus width, or when the last instruction status signal is received, all the buffered data packets are written to memory. By buffering data packets, the number of frequent memory accesses can be reduced. Batch writing when the amount of data reaches the bus width or when a termination signal is received can significantly reduce bus load and improve memory write efficiency. The statistical counter can count the first number of data packets written to memory by the data buffer. When the first number of data packets written to memory reaches a first threshold, the first number of data packets are synchronized to the central processing unit. This can reduce the overhead of frequent CPU polling, reduce system latency, and by counting the write frequency, the CPU can dynamically adjust the memory allocation strategy to avoid performance fluctuations caused by conflicting writes.

[0082] As an example, assuming each data packet is 5 bits in size, the bus width is 10 bits, and the first threshold is 4, when the amount of data in the data buffer reaches 10 bits, all the buffered data is written to memory. Simultaneously, a counter records the first number of data packets written to memory as 2. When the first number of packets written to memory reaches 4, the first 4 packets written to memory are synchronized to the central processing unit (CPU). Here, the buffer is incremented bit by bit, appending to the end of each received 5-bit packet, and the width counter is incremented by 5. Once the counter reaches 10, an AXI write transaction is triggered, pushing the entire 10-bit data segment into memory and clearing the buffer and counter. At the same time, the counter accumulates the "number of writes," incrementing by 2 after each write operation. The current value is 2. If subsequent writes continue, when the accumulated result reaches the preset first threshold of 4, the control logic immediately packages the 4 data packets into a status register and synchronously reports it to the CPU via interrupt or bus write, informing it that "4 memory write operations have been completed," so that the CPU can make timely scheduling decisions.

[0083] In some embodiments, Figure 3 Schematic diagram of the instruction scheduling circuit provided in the embodiments of this application Figure 3 .like Figure 3 As shown, the instruction scheduling circuit 10 may also include a register 105.

[0084] Register 105 is used to receive configuration instructions from the central processing unit and forward the configuration instructions to data cache 103 and statistics counter 104 to configure the memory space size, the starting write address, and the first threshold of statistics counter 104.

[0085] It should be noted that the CPU's configuration instructions are used to configure the memory space size, the starting write address, and the first threshold of the statistical counter. For example, after receiving a configuration instruction from the CPU, the register forwards the instruction to the data buffer. The data buffer allocates the appropriate memory space based on the configuration information in the instruction and sets the starting write address. Similarly, after receiving a configuration instruction from the CPU, the register forwards the instruction to the statistical counter and sets the first threshold of the statistical counter based on the configuration information in the instruction. Registers are high-speed storage components used to temporarily store instructions, data, and addresses. They are composed of flip-flops or latches, with each flip-flop storing one bit of binary code.

[0086] In this embodiment, register 105 can receive configuration instructions from the central processing unit and forward the configuration instructions to the data cache 103 and the statistics counter 104. By using register 105 as a bridge between the central processing unit (CPU) and the data cache 103 and the statistics counter 104, and uniformly receiving the CPU's configuration instructions, resource contention caused by multiple components directly accessing the CPU can be avoided.

[0087] As an example, when the register receives a configuration instruction from the central processing unit, it forwards the configuration instruction to the data cache and the statistics counter. The data cache allocates a storage space of a specified size in memory according to the configuration information of the configuration instruction, and sets the initial write address of the write pointer according to the configuration information of the configuration instruction. The statistics counter sets the first threshold of the statistics counter according to the configuration information of the configuration instruction.

[0088] Here, after receiving the configuration instruction, the register obtains the configuration information of the three fields: "space size", "starting address", and "first threshold". Then, it broadcasts the complete parameter package to the data buffer and the statistics counter simultaneously through the internal control bus. After parsing the parameter package, the data buffer first allocates a contiguous storage area of ​​the specified space size in the memory mapping, initializes the write pointer to the starting address given in the configuration, and stores the starting address in the register to provide a basis for subsequent rollback judgment. The statistics counter then parses and extracts the first threshold from the same parameter package and configures the counting threshold of the statistics counter (i.e., the first threshold) according to the first threshold.

[0089] In some embodiments, Figure 4 Schematic diagram of the instruction scheduling circuit provided in the embodiments of this application Figure 4 .like Figure 4 As shown, the instruction scheduling circuit 10 may also include a transmit logic unit 106.

[0090] The transmit logic unit 106 is used to receive instructions sent by the thread instruction queue, add a thread identifier to the instruction, and send the instruction with the added thread identifier to the engine corresponding to the instruction.

[0091] It should be noted that thread identifiers added to instructions can use labels, such as marking the instruction location with an identifier ending with a colon, or adding an identifier and colon at the beginning of the code line; they can also use variable or function names as identifiers, such as indirectly identifying instruction blocks by naming variables or functions, or using local or global variables to associate operation flow; they can also use pseudo-instructions or macro definitions, such as defining data labels with pseudo-instructions, or using #define to create parameterized macros to identify operation logic; they can also use comments to assist in identification, such as adding comments before instructions; and they can also use structured programming elements, such as implicitly identifying code blocks through if, while, etc. The specific methods can be determined according to the actual situation, and no specific limitations are made here.

[0092] In this embodiment, the transmission logic unit 106 can receive instructions sent by the thread queue, add a thread identifier to the instructions, and send the instructions with added thread identifiers to the engine corresponding to the instructions. By attaching a thread identifier to the instructions, the thread ownership of the instructions can be clearly defined, avoiding identifier conflicts in a multi-threaded environment.

[0093] As an example, suppose thread 1 issues an instruction in the thread instruction queue. The sending logic unit receives the instruction. After that, it will be an instruction. Add the identifier information for thread 1, and receive the instruction to add the thread identifier. And then send the instruction with the added thread identifier to the engine corresponding to the instruction (e.g., engine 1). Here, thread 1 first sends the instruction... The instruction is pushed into the thread instruction queue. Once the sending logic unit detects that the queue is not empty, it immediately reads the instruction and appends a unique ID field for thread 1 to the instruction header, forming a new instruction carrying the thread identifier. Subsequently, according to The engine selection field forwards the entire packet to the input buffer of engine 1, completing the binding of thread identity and operation instructions, and ensuring that the engine can accurately identify the status when it returns it later.

[0094] In some embodiments, Figure 5 Schematic diagram of the instruction scheduling circuit provided in the embodiments of this application Figure 5 .like Figure 5 As shown, the instruction scheduling circuit 10 may also include a visualization unit 107.

[0095] The visualization unit 107 is used to perform performance analysis based on the data packets written to memory, obtain performance analysis data, and generate performance analysis graphs based on the performance analysis data.

[0096] It should be noted that performance analysis charts can be timeline swimlane charts, histograms, waterfall charts, pie charts, etc., and no specific restrictions are made here.

[0097] In this embodiment of the application, the visualization unit can perform performance analysis based on the data packets written to memory, obtain performance analysis data, and generate a performance analysis graph based on the performance analysis data. By analyzing the data written to memory and generating a performance analysis graph based on the analysis data, the execution time of each instruction and the calling status of each engine can be clearly identified, thereby facilitating subsequent performance and power optimization.

[0098] In some embodiments, see Figure 6 , Figure 6 This is a flowchart illustrating the data processing method provided in the embodiments of this application, which will be combined with... Figure 6 The steps shown are explained.

[0099] In step 201, the collector receives the command status signal from the engine.

[0100] Here, the command status signals include the start status signal and the end status signal of the command received by the engine.

[0101] As an example, suppose there are four engines 0 to 3. At a certain moment, the command status signals include the start status signal of the command of engine 0 and the end status signal of the command of engine 3.

[0102] In some embodiments, the instruction status signal may also include the thread to which the instruction belongs.

[0103] As an example, suppose there are two threads 0 and 1, and four engines 0 to 3. At a certain moment, the instruction status signals include the start status signal of the instruction of engine 1 in thread 0 and the end status signal of the instruction of engine 2 in thread 1.

[0104] In some embodiments, the data acquisition device can be a communication interface, such as RS-485; it can also be a sensor module, that is, synchronously acquiring the status signals transmitted by the engine; it can also be a signal conditioning circuit, etc., without specific limitations.

[0105] In some embodiments, before performing step 201, the following processing may also be performed: in response to an instruction sent by the receiving thread instruction queue, a thread identifier is added to the instruction; the instruction with the added thread identifier is sent to the engine indicated by the instruction, so that the engine generates the instruction status signal. Thus, by attaching a thread identifier to the instruction, the thread affixing of the instruction can be clearly defined, avoiding identifier conflicts in a multi-threaded environment.

[0106] As an example, suppose thread 2 issues an instruction in the thread instruction queue. The sending logic unit receives the instruction. After that, it will be an instruction. Add the identifier information for thread 2, and receive the instruction to add the thread identifier. And then send the instruction with the added thread identifier to the engine corresponding to the instruction (e.g., engine 3). Here, thread 2 first sends the instruction... The instruction is pushed into the thread instruction queue. Once the sending logic unit detects that the queue is not empty, it immediately reads the instruction and appends a unique ID field for thread 2 to the instruction header, forming a new instruction carrying the thread identifier. Subsequently, according to The engine selection field forwards the entire packet to the input buffer of engine 3, completing the binding of thread identity and operation instructions, ensuring that the engine can accurately identify the status when it returns it later.

[0107] In step 202, the first timestamp counter receives the first timestamp signal generated based on the sampling clock counter.

[0108] It should be noted that when a sampling event (such as receiving an instruction status signal) occurs, the hardware interrupt controller captures the current timestamp counter's count value and generates a signal with a timestamp. The sampling clock counter is a key component in digital signal processing and data acquisition systems, used to precisely control the sampling timing of analog signals and count the number of clock pulses.

[0109] In step 203, the data buffer receives a data packet consisting of the instruction status signal, the first timestamp signal, and the second timestamp signal, and writes the data packet into memory.

[0110] Here, the second timestamp signal is generated based on the system clock counter. The system clock counter is a core hardware module in a computer or embedded system used to accurately measure time intervals. It is usually integrated inside the CPU or microcontroller and can provide precise time units through the system clock pulse.

[0111] As an example, the data acquisition device receives command status signals from the engine. The first timestamp signal received by the first timestamp counter is the first timestamp signal generated by the sampling clock counter. The second timestamp signal generated based on the system clock counter is , will command status signal First timestamp signal and the second timestamp signal Composition of data packets for[ , , The data buffer receives data packets. and data packets Write to memory.

[0112] It should be noted that the collector receives a status signal from the engine. Simultaneously, a 700MHz sampling clock counter and a 25MHz system clock counter are triggered respectively, and the count values ​​at this moment are captured as... and The three are assembled into a complete packet S in a fixed order. Then the buffer pushes the entire packet into the FIFO. Once the cumulative bit width reaches the width of the AXI bus, it is written into memory at once, completing a lossless event recording with double timestamps.

[0113] In some embodiments, before performing step 203, the following processing may also be performed: encoding the instruction status signal to obtain a first code. Thus, by using field encoding to compress the instruction status signal into binary code, storage space is significantly reduced compared to direct representation.

[0114] It should be noted that different encoding methods can be used to represent command status signals. For example, in one-hot encoding, each bit can represent the start or end state of a command on different engines; another example is using the first three bits to represent different engines and the fourth bit to represent the start or end state of a command. No specific limitations are made here.

[0115] As an example, taking one-hot encoding as an example, suppose there are four engines 0 to 3. At a certain moment, the instruction status signal includes the start status signal of the instruction of engine 1 and the end status signal of the instruction of engine 2. Then the instruction status signal can be encoded as 0100, 0010, with the first four bits recording the start status signal and the last four bits recording the end status signal.

[0116] It should be noted that the high four bits correspond to "engine 0 starts, engine 1 starts, engine 2 starts, engine 3 starts" in sequence, and the low four bits correspond to "engine 0 ends, engine 1 ends, engine 2 ends, engine 3 ends" in sequence. When any engine starts or ends at any time, the corresponding bit is set to 1, and the other bits remain 0. When engine 1 sends out a start pulse, the second bit of the high four bits is set to 1. When engine 2 sends out an end pulse, the third bit of the low four bits is set to 1, ultimately forming an 8-bit vector 0100_0010.

[0117] In some embodiments, the instruction status signal may also include the thread to which the instruction belongs.

[0118] As an example, taking one-hot encoding, suppose there are two threads 0 and 1, and four engines 0 to 3. At a certain moment, the instruction status signal includes the start status signal of the instruction of engine 1 of thread 0 and the end status signal of the instruction of engine 2 of thread 1. Then the instruction status signal can be encoded as 0100, 0000, 0000, 0010, with the first eight bits recording the start status signal and the last eight bits recording the end status signal.

[0119] It should be noted that the high eight bits are arranged in the following order: "Thread 0 Engine 0 Start → Thread 0 Engine 1 Start → Thread 0 Engine 2 Start → Thread 0 Engine 3 Start → Thread 1 Engine 0 Start → Thread 1 Engine 1 Start → Thread 1 Engine 2 Start → Thread 1 Engine 3 Start". The low eight bits correspond to the end status events in the same order. When Thread 0 emits a start pulse at Engine 1, the second bit of the high eight bits is set to 1. At the same time, when Thread 1 emits an end pulse at Engine 2, the sixth bit of the low eight bits is set to 1. The remaining 14 bits remain 0, ultimately forming a 16-bit vector 0100_0000_0000_0010.

[0120] In some embodiments, the data buffer receiving the data packet composed of the instruction status signal, the first timestamp signal, and the second timestamp signal in step 203 above can be implemented in the following way: the data buffer receives the data packet composed of the first encoding, the first timestamp signal, and the second timestamp signal. Thus, by associating time information with the instruction status signal, the start and end times of different instructions can be accurately recorded, facilitating subsequent analysis of different instruction data.

[0121] It should be noted that the data packet consisting of the first code, the first timestamp signal, and the second timestamp signal can be implemented in hardware, using a parallel bus to transmit data, and using a custom protocol (such as UART or SPI) to package the instruction status and timestamp into a fixed format frame (e.g., [first code][T1][T2]).

[0122] As an example, the data acquisition device receives command status signals from the engine. Regarding the command status signal Encode to obtain the first code. The first timestamp signal received by the first timestamp counter is the first timestamp signal generated by the sampling clock counter. The second timestamp signal generated based on the system clock counter is , the first code First timestamp signal and the second timestamp signal Composition of data packets for[ , , Here, the collector receives a status signal from the engine. It is then fed into the one-hot encoding module to generate a first code of fixed width. Simultaneously, a 700 MHz sampling clock counter and a 25 MHz system clock counter are triggered respectively, and the count values ​​at this moment are captured as... and The three are assembled into a complete packet S in a fixed order. Then the buffer pushes the entire packet into the FIFO. Once the cumulative bit width reaches the width of the AXI bus, it is written into memory at once, completing a lossless event recording with double timestamps.

[0123] In some embodiments, writing the data packet to memory in step 203 above can be achieved by: buffering the received data packets; and writing all buffered data packets to memory when the amount of buffered data reaches the bus width or when the last instruction status signal is received. In this way, by buffering data packets, the number of frequent memory accesses can be reduced, and batch writing when the amount of data reaches the bus width or a termination signal is received can significantly reduce bus load and improve memory write efficiency.

[0124] It should be noted that bus width refers to the number of bits of binary data that a bus in a computer system can transmit simultaneously. It is usually expressed in bits. Bus width determines the amount of data that can be transmitted in each clock cycle. The larger the bus width, the larger the amount of data transmitted in a single transmission and the higher the data transmission efficiency.

[0125] As an example, assuming each data packet is 5 bits in size and the bus width is 10 bits, when the amount of data in the data buffer reaches 10 bits, all the data buffered in the data buffer is written to memory; or, when the data packet of the last instruction status signal is received, the current amount of data in the data buffer is only 5 bits. Although it has not reached 10 bits, the last instruction status signal has been received, so all the data buffered in the data buffer is written to memory.

[0126] It should be noted that the data buffer is incremented bit by bit. Each incoming 5-bit packet is appended to the end, and the bit width counter is incremented by 5 simultaneously. Once the counter reaches 10, an AXI write transaction is immediately triggered, pushing the entire 10-bit data into memory and clearing the buffer and counter to prepare for the next round. If the process reaches the end, the scheduler issues a last instruction status signal. At this time, there is only one 5-bit packet left in the data buffer, and the counter only shows 5, far from reaching 10. To prevent the packet from being stuck, the control logic also initiates a write operation, writing the only 5 bits of data into memory and marking it as a valid byte to ensure that the memory side knows the actual valid bit width.

[0127] In some embodiments, after performing step 203, the following process may also be performed: when the memory is full, the write address of the memory is rolled back to the starting address for continued storage. Thus, when the memory is full, it automatically rolls back to the starting address, forming a circular buffer structure, which can avoid frequent memory allocation or release operations, thereby reducing dynamic memory management overhead.

[0128] As an example, assume the memory size is 10MB and the starting address is During the process of writing data into memory, when memory is full, a rollback operation is triggered, resuming from the starting address in memory. Continue writing data. Here, the write pointer starts from... Starting from this point, each piece of data is written with an incrementing byte offset, and the pointer is checked in real time to see if it has crossed the threshold. A +10MB boundary is defined; when the control logic detects that the next write operation will exceed the end address, it immediately sets the rollback flag and resets the write pointer to the specified address. At the same time, the remaining data is split into two parts: the last part fills the top space, and the first part starts from... Continue writing to achieve seamless circular caching.

[0129] In some embodiments, after performing step 203, the following processes may also be performed: performance analysis based on the data packets written to memory to obtain performance analysis data; and a performance analysis graph generated based on the performance analysis data. This allows for a clear understanding of the execution time of each instruction and the calling status of each engine, facilitating subsequent performance and power tuning.

[0130] The following describes an exemplary application of the embodiments of this application in a practical application scenario. This exemplary application describes the specific implementation process of the instruction scheduling circuit.

[0131] In AI chips, the instruction scheduler has a profiling function, which is an important tool for performance optimization and resource management. Profiling can track instruction runtime, idle cycle ratio, and high-energy-consuming operations (such as frequently repeated calls). Accurate data collection and analysis can reveal hardware execution details, which is crucial for resource and performance tuning. However, it is difficult to accurately obtain the runtime of each instruction in related technologies.

[0132] Based on this, this application realizes the accurate counting of the start and end timestamps of each instruction in each thread in the multi-threaded scheduler, and the runtime of each instruction can be obtained in turn. Furthermore, this application supports writing the statistical information directly into memory through the AXI bus, and the performance analysis graph can be drawn by reading the contents of memory, and the software and hardware optimization can be performed in turn.

[0133] In some embodiments, when the scheduler sends an instruction to the accelerator engine, it passes the thread identifier of the sending thread to the engine. This identifier serves as the unique identity of the thread and is sent along with the instruction. When the instruction begins execution, the engine sends the start status signal and the thread to which the instruction belongs to the scheduler together. After the scheduler obtains the instruction status signal and the thread to which the instruction belongs, it generates a set of profile flag data in a one-hot manner and merges the current system timestamp and the sampling timestamp data to form a set of profile data and writes it into the FIFO. When the effective data bit width in the FIFO reaches the AXI bus bit width, it is written into memory to ensure that the data is transferred to memory in a timely manner.

[0134] It should be noted that the engine also generates corresponding termination status signals and the thread signal to which the instruction belongs when the instruction finishes execution, and the processing method is similar to that described above.

[0135] In some embodiments, the Profile flag data is encoded using a one-hot encoding method, where each bit corresponds to the start or end state of a thread on a certain engine. One sampling period can support the collection of multiple state signals. For example, if there are a total of 2 threads 0 and 1, and four engines 0-3, and at a certain moment the start of the engine 1 instruction of thread 0 and the end of the engine 2 instruction of thread 1 occur simultaneously, then the Profile flag data is 0100, 0000, 0000, 0010; that is, 2 bits are set to 1 and the other bits are set to 0.

[0136] It should be noted that the one-hot encoding method expands the data first by thread number, then by engine number, and finally by "start / end" in two levels, forming a long bit vector. Each bit uniquely identifies "a certain thread-a certain engine-a certain state". Therefore, whenever the corresponding event occurs, this bit will be set to 1, while the rest remain zero. When multiple events occur at the same sampling point, the corresponding bits can be set to 1 simultaneously, achieving lossless recording of "multiple events in a single cycle". As mentioned above, thread 0's start state in engine 1 and thread 1's end state in engine 2 are completely concurrent, so only these two bits in the vector are 1, and the rest are 0.

[0137] In some embodiments, the software analyzes the Profile data written to memory and draws a performance analysis graph. From the performance analysis graph, the start and end times of each instruction can be determined, thereby identifying the frequently called engines and instructions with excessively long execution times, and then performing performance and power optimization accordingly.

[0138] In some embodiments, see Figure 7 , Figure 7 This is a schematic diagram of the instruction scheduling circuit provided in an embodiment of this application, as shown below. Figure 7 As shown, firstly, when different threads send instructions to the engine, they mark an n-bit thread ID (n = $clog2(thread count)) in a special field of the instruction. This ID serves as a unique identifier for the thread and is sent along with the instruction. Next, the engine receives the instruction and generates start and end status signals to the scheduler when the instruction starts running and when it finishes running. When the engine sends the instruction status signal, it synchronously sends the n-bit thread ID to the scheduler to ensure that the scheduler knows the thread corresponding to the current status. Subsequently, the scheduler's Profile unit receives the status signal and thread ID signal from the engine and generates a Profile flag signal. The timestamp signal of the sampling clock is generated based on a 700M sampling clock counter, and the timestamp signal of the system clock is generated based on a 25M system clock counter. Both are used to record the precise timing of events. After that, when the amount of data in the FIFO reaches the bus width, or after the scheduler completes the collection of the last instruction status, an AXI write operation to memory is triggered to ensure that the data is transferred to memory in a timely manner. Finally, when the amount of data written to memory reaches a specified number or the allocated memory space is full, an interrupt is generated for the CPU. It also supports rolling back to the starting address to continue writing after the memory is full.

[0139] It should be noted that the aforementioned interrupt is implemented through a burst counter. Each time data is written to memory, it constitutes a burst. Assuming the memory can store 10 bursts, and the burst counter's threshold is set to 2, an interrupt is generated every two bursts, sending transmission information to the CPU for synchronization. After the CPU records that 10 bursts have been written to memory, it controls memory rollback to the starting address via registers to continue writing. Here, the register belongs to a module in the instruction scheduler, used to control the initialization settings of the burst counter and the FIFO logic. For example, it sets the technical threshold of the burst counter, sends the configured memory space size and the start address for writing data to the memory space to the FIFO logic, and stores the starting address of the memory in the register for use during memory rollback.

[0140] In some embodiments, see Figure 8 , Figure 8 This is a schematic diagram of the performance analysis provided in the embodiments of this application, such as... Figure 8 As shown, the software draws a performance analysis graph based on the profile data written to memory. The performance analysis graph can reveal the frequently called engines and instructions with excessively long execution times, and performance and power consumption can be optimized accordingly.

[0141] This application provides a chip that may include the instruction scheduling circuit 10 described in any of the foregoing embodiments.

[0142] This application provides an electronic device, which includes a processor, wherein the processor includes an instruction scheduling circuit 10 as described in any of the foregoing embodiments.

[0143] This application provides a computer program product, which includes a computer program or computer-executable instructions stored in a computer-readable storage medium. The processor of an electronic device reads the computer-executable instructions from the computer-readable storage medium and executes the computer-executable instructions, causing the electronic device to perform the data processing method described in this application.

[0144] This application provides a computer-readable storage medium storing computer-executable instructions or computer programs. When the computer-executable instructions or computer programs are executed by a processor, the processor will execute the data processing method provided in this application.

[0145] In some embodiments, the computer-readable storage medium may be a memory such as ferroelectric random access memory (FRAM), ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); or it may be a device that includes one or any combination of the above-mentioned memories.

[0146] In some embodiments, computer-executable instructions may take the form of programs, software, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.

[0147] As an example, computer-executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple co-located files (e.g., files that store one or more modules, subroutines, or code sections).

[0148] As an example, computer-executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located at one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0149] In summary, the scheduling circuit provided in this application receives instruction status signals from the engine via a data collector, ensuring real-time feedback on instruction execution status. Furthermore, the data collector integrates the start and end status signals of the instruction, allowing for the acquisition of the instruction's complete lifecycle, facilitating subsequent management and optimization. Secondly, by sampling the timestamp signals generated by the clock counter and the system clock counter using a timestamp counter, high-precision timing can be provided to accurately determine the execution time of different instruction states. Thirdly, by receiving instruction status signals through a data buffer and combining the timestamp signals with the instruction status signals to form a data packet, a temporary storage space is provided for the data packet. This ensures data integrity before the data packet is written to memory, and by caching data, the risk of data loss and the number of direct memory accesses are reduced, thereby improving the overall operating efficiency of the system.

[0150] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0151] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device and circuit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0152] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, encoding instruction status signals using one-hot encoding is only one possible implementation method, and other encoding methods may be used in actual implementation, such as no encoding. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0153] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0154] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0155] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0156] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0157] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0158] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0159] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0160] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. An instruction scheduling circuit, characterized by, The instruction scheduling circuit comprises a collector, a first timestamp counter, a data buffer, a statistical counter and a register. The collector is configured to receive an instruction state signal from an engine, wherein the instruction state signal comprises a start state signal and an end state signal of an instruction received by the engine. The first timestamp counter is configured to receive a first timestamp signal generated based on a sampling clock counter. The first timestamp signal and a second timestamp signal are acquired simultaneously when the collector receives the instruction state signal, and the second timestamp signal is generated based on a system clock counter. The data buffer is configured to receive a data packet composed of the instruction state signal, the first timestamp signal and the second timestamp signal in a fixed order, and buffer the received data packet. The data buffer is further configured to write all the buffered data packets in the data buffer to a memory when the amount of data in the data buffer reaches a bus bit width or a data packet of a last instruction state signal is received. The statistical counter is configured to count a first number of data packets written to the memory by the data buffer, and synchronize the first number of data packets to a central processing unit when the first number reaches a first threshold. The register is configured to receive a configuration instruction of the central processing unit, and forward the configuration instruction to the data buffer and the statistical counter to configure a space size and a start write address of the memory and the first threshold of the statistical counter.

2. The circuit of claim 1, wherein, The instruction scheduling circuit further comprises a transmission logic unit. The transmission logic unit is configured to receive an instruction sent by a thread instruction queue, add a thread identifier to the instruction, and send the instruction with the added thread identifier to an engine corresponding to the instruction.

3. The circuit of claim 1, wherein, The instruction scheduling circuit further comprises a visualization unit. The visualization unit is configured to perform performance analysis based on the data packet written to the memory, obtain performance analysis data, and generate a performance analysis diagram based on the performance analysis data.

4. A chip, characterized by The chip is deployed with the instruction scheduling circuit of any one of claims 1 to 3.

5. An electronic device, comprising: A processor is included, wherein a chip in the processor is deployed with the instruction scheduling circuit of any one of claims 1 to 3.

6. A data processing method, characterized by, The method comprises: The collector receives an instruction state signal from an engine, wherein the instruction state signal comprises a start state signal and an end state signal of an instruction received by the engine. The first timestamp counter receives a first timestamp signal generated based on a sampling clock counter. The first timestamp signal and a second timestamp signal are acquired simultaneously when the collector receives the instruction state signal, and the second timestamp signal is generated based on a system clock counter. The data buffer receives a data packet composed of the instruction state signal, the first timestamp signal and the second timestamp signal in a fixed order, and buffers the received data packet. The data buffer is further configured to write all the buffered data packets in the data buffer to a memory when the amount of data in the data buffer reaches a bus bit width or a data packet of a last instruction state signal is received. When the amount of data in the data buffer reaches the bus bit width or the data buffer receives a last instruction state signal data packet, the data buffer writes all buffered data packets in the data buffer to the memory; A statistical counter counts a first number of data packets written to the memory by the data buffer, and when the first number reaches a first threshold, synchronizes the first number of data packets to the central processor; A register receives a configuration instruction of the central processor and forwards the configuration instruction to the data buffer and the statistical counter to configure a space size and a starting write address of the memory and the first threshold of the statistical counter.

7. The method of claim 6, wherein, The method further comprises: encoding processing the instruction state signal to obtain a first encoding; The data buffer receives a data packet composed of the instruction state signal, the first timestamp signal and the second timestamp signal in a fixed order, comprising: The data buffer receives a data packet composed of the first encoding, the first timestamp signal and the second timestamp signal in a fixed order.

8. The method of claim 6, wherein, Before the collector receives the instruction state signal from the engine, the method further comprises: In response to receiving an instruction sent by a thread instruction queue, adding a thread identifier to the instruction; Send the instruction with the thread identifier to the engine indicated by the instruction to make the engine generate the instruction state signal.

9. The method of claim 6, wherein, The method further comprises: When the memory is full, roll back the write address of the memory to the starting address for continuous storage.

10. The method of claim 6, wherein, After the data buffer writes all buffered data packets to the memory, the method further comprises: Based on the data packets written to the memory, performance analysis is performed to obtain performance analysis data; Based on the performance analysis data, a performance analysis graph is generated.

11. An electronic device, comprising: Comprise: Memory for storing computer executable instructions or computer programs; The processor is used to execute the computer executable instructions or computer programs stored in the memory, and realizes the data processing method in any one of claims 6 to 10.

Images