A method and system for locating an error module in an FPGA image system

Abstract

This disclosure relates to the field of FPGA image system technology, and discloses a method and system for locating faulty modules in an FPGA image system. The method includes: constructing a diagnostic data path independent of the original image transmission path; if an image anomaly is detected, switching to the diagnostic data path via a path switching module; receiving the test data sequence flowing through the module to be tested at each moment via a distributed error detection module, and comparing the predicted data with the actual transmitted data; if the target module to be tested satisfies the condition that the comparison result of the input interface is correct but the comparison result of the output interface is incorrect, the target module to be tested is determined to be a faulty module. This disclosure, by constructing an independent diagnostic data path and switching to this path when an image anomaly is detected, and using a distributed error detection module to compare the input and output data of each module to be tested, can directly pinpoint the faulty module, significantly reducing the time and manpower required for error location and improving the efficiency of onboard debugging.

Description

Technical Field

[0001] This disclosure relates to the field of field-programmable gate array (FPGA) image system technology, and specifically to a method and system for locating faulty modules in an FPGA image system. Background Technology

[0002] In the design of FPGA-based image transmission systems, image data is typically acquired through a camera. After processing by multiple sub-modules such as data acquisition, clock domain conversion, Ethernet transmission, buffering, and display control, the image is finally displayed on the monitor.

[0003] In actual onboard debugging, due to various reasons, the displayed image may not match the expected result. However, it is difficult to deduce the cause of the error solely from the displayed image; each module must be checked one by one. Furthermore, such problems are difficult to locate through functional simulation, thus often requiring a significant investment of time and manpower. Therefore, how to easily and quickly locate the faulty module in the FPGA image system, reducing time and manpower costs, has become an urgent problem to be solved. Summary of the Invention

[0004] In view of this, this disclosure provides a method and system for locating faulty modules in an FPGA image system, in order to solve the problem of how to simply and quickly locate faulty modules in an FPGA image system and reduce time and manpower costs.

[0005] This disclosure provides a method for locating faulty modules in an FPGA image system. The method includes: constructing a diagnostic data path independent of the original image transmission path in the FPGA image system; wherein the diagnostic data path includes: a data generation module, a path switching module, and a distributed error detection module; the distributed error detection module is deployed at the input interface and output interface of the module under test; if an image anomaly is detected, the FPGA image system is switched from the original image transmission path to the diagnostic data path through the path switching module; the distributed error detection module receives the test data sequence flowing through the module under test at each moment and compares the predicted data with the actual transmitted data; if the target module under test satisfies the condition that the comparison result of the input interface is correct and the comparison result of the output interface is incorrect, the target module under test is determined to be a faulty module; wherein the predicted data is generated by the distributed error detection module based on a preset rule.

[0006] This disclosure also provides an FPGA image system, comprising: a raw image transmission path for acquiring, processing, and displaying image data; and a diagnostic data path, independent of the raw image transmission path, including: a data generation module for generating a test data sequence with a preset pattern; a path switching module connected to the starting end of the raw image transmission path and the starting end of the diagnostic data path, for switching the system from the raw image transmission path to the diagnostic data path when an image anomaly is detected, allowing the test data sequence to flow into downstream processing modules; a distributed error detection module deployed at the input and output interfaces of each functional processing module, for receiving the test data sequence flowing through the corresponding module, generating predicted data based on a preset pattern, comparing it with the actual transmitted data, and outputting the comparison result; and an error location unit, for determining that the target functional processing module is an error module when the comparison result of the input interface of the target functional processing module is correct and the comparison result of the output interface is incorrect, based on the comparison result of the distributed error detection module.

[0007] This disclosure also provides a computer device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the above-described method for locating an error module in an FPGA image system.

[0008] This disclosure also provides a computer-readable storage medium storing computer instructions for causing a computer to implement the above-described method for locating fault modules in an FPGA image system.

[0009] This disclosure also provides a computer program product, including computer instructions for causing a computer to execute the above-described method for locating an error module in an FPGA image system.

[0010] The method and system for locating faulty modules in the FPGA image system disclosed above can directly lock the faulty module by constructing an independent diagnostic data path and switching to this path when an image abnormality is detected, and by using a distributed error detection module to compare the input and output data of each module to be detected. This significantly reduces the time and manpower costs required for error location and improves the efficiency of onboard debugging. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the architecture of an FPGA-based image processing system in related technologies;

[0013] Figure 2 This is a flowchart illustrating a method for locating an error module in an FPGA image system according to an embodiment of this disclosure;

[0014] Figure 3 This is a schematic diagram of the error detection process of an error detection module in an FPGA image system provided in this embodiment of the disclosure;

[0015] Figure 4 This is a schematic diagram of the structure of an FPGA image system provided in an embodiment of this disclosure;

[0016] Figure 5 This is a schematic diagram of another FPGA image system provided in an embodiment of this disclosure;

[0017] Figure 6 This is a schematic diagram of the structure of another FPGA image system provided in the embodiments of this disclosure. Detailed Implementation

[0018] In such Figure 1 In the design of the FPGA image processing system shown in the related technology, after the camera acquires data, it goes through modules such as data acquisition, clock domain conversion, Ethernet, buffering, and display control before finally being displayed on the monitor. However, during the actual on-board debugging stage, the system often exhibits abnormal phenomena such as screen tearing, line misalignment, frame errors, and image stuttering. There are many reasons for this phenomenon, which may be caused by clock domain crossing, insufficient bandwidth, insufficient memory in the buffer module, or even by the FPGA chip itself. It is difficult to deduce the cause of the error from the displayed image alone. Each module needs to be checked one by one, and these problems are difficult to locate through functional simulation. Therefore, it often requires a lot of time and manpower.

[0019] To address the aforementioned issues, various embodiments of this disclosure provide a method for locating faulty modules in an FPGA image system. The method includes: constructing a diagnostic data path independent of the original image transmission path within the FPGA image system; wherein the diagnostic data path includes: a data generation module, a path switching module, and a distributed error detection module; the distributed error detection module is deployed at the input and output interfaces of the module under test; if an image anomaly is detected, the path switching module switches the FPGA image system from the original image transmission path to the diagnostic data path; the distributed error detection module receives a sequence of test data flowing through the module under test at each moment, and compares the predicted data with the actual transmitted data; if the target module under test satisfies the condition that the comparison result of the input interface is correct but the comparison result of the output interface is incorrect, the target module under test is determined to be a faulty module; wherein the predicted data is generated by the distributed error detection module based on a preset rule.

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating a method for locating an error module in an FPGA image system according to an embodiment of this disclosure. The method may include the following steps:

[0022] Step S201: Construct a diagnostic data path in the FPGA image system that is independent of the original image transmission path.

[0023] In this embodiment, as Figure 1 The design phase of the FPGA imaging system shown constructs a diagnostic data path independent of the original image transmission path.

[0024] Here, a diagnostic data path is built in advance. During debugging, by switching to this path, the predictable data generated by the data generation module can be used in conjunction with the error detection module to quickly locate the faulty module, which greatly reduces the manpower and time cost of locating the problem and makes the onboard debugging twice as effective.

[0025] The original image transmission path can be as follows: Figure 1 The FPGA image system shown consists of a camera, a data acquisition module, a clock domain conversion module, an Ethernet module, a buffer module, and a display control module, forming an image data transmission path. This path enables image data to be acquired from the camera and then displayed on the monitor via the sub-modules.

[0026] The diagnostic data pathway can be an independent pathway built for the localization system error module. It consists of a data generation module, a pathway switching module, and a distributed error detection module, and is used to transmit predictable diagnostic data and perform error detection.

[0027] The data generation module can continuously generate predictable test data sequences. The test data sequence can calculate the next data using the current data and a specific formula, which facilitates error detection by the error detection module.

[0028] The pathway switching module can be used to flexibly switch between the original image transmission pathway and the diagnostic data pathway, ensuring that changes in the diagnostic pathway do not affect the original pathway.

[0029] The error detection module can be deployed at the input and output interfaces of the module to be detected. It can predict and generate predicted data based on the data type generated by the data generation module according to preset rules, and compare it with the next received actual transmitted data. If they are inconsistent, an error will be prompted.

[0030] Here, the error detection module can be added or removed at any location in the FPGA image system without modifying the design of the original image transmission path. This allows for flexible adjustment of the detection points according to debugging needs, further narrowing down the scope of the problem.

[0031] In addition, the error detection module added during the system design phase can be directly deleted after the original image transmission path is working normally, thereby saving FPGA resources and making the design more flexible.

[0032] In step S202, if an image abnormality is detected, the FPGA image system is switched from the original image transmission path to the diagnostic data path via the path switching module.

[0033] In this embodiment, if it is determined that the image displayed on the screen is inconsistent with the image from the camera, that is, if it is determined that the image displayed on the screen has problems such as screen tearing, misalignment, frame errors, or screen stuttering, and the image is determined to be abnormal, the FPGA image system is switched from the original image transmission path to the diagnostic data path through the path switching module.

[0034] The path switching module can refer to a channel 2-to-1 selector. When the path switching module switches to the original image transmission path, the system transmits image data captured by the camera. When the path switching module switches to the diagnostic data path, the system transmits predictable data generated by the data generation module.

[0035] Here, the channel 2-to-1 selector can essentially be a multiplexer (MUX) implemented based on the internal logic resources of the FPGA. It is a digital logic circuit module used to select one of the two input channels as the output.

[0036] For example, when a channel 2-to-1 selector receives a control signal, if the control signal is 0, the selector selects the original image transmission path and outputs the original image data, and the system operates in normal image transmission mode; if the control signal is 1, the selector selects the diagnostic data path and outputs diagnostic data, and the system switches to error location mode.

[0037] Here, the above switching method ensures that enabling the diagnostic data path will not affect the original image transmission path. It can switch to the diagnostic path when it is necessary to locate the problem, and can also maintain the stable operation of the original path during normal operation. At the same time, it is convenient to delete the positioning module in the later stage of the design to save resources.

[0038] Step S203: The distributed error detection module receives the test data sequence flowing through the module to be detected at each moment and compares the predicted data with the actual transmitted data. If the target module to be detected satisfies the condition that the comparison result of the input interface is correct and the comparison result of the output interface is incorrect, the target module to be detected is determined to be an error module.

[0039] In this embodiment, the prediction data is generated by the distributed error detection module based on preset rules.

[0040] For the target module to be detected, the judgment is made by comparing the error detection module at its inlet and the error detection module at its outlet: if the error detection module at the inlet interface is correct (i.e., the actual transmitted data at the inlet is consistent with the predicted data), and the error detection module at the outlet interface is incorrect (i.e., the actual transmitted data at the outlet is inconsistent with the predicted data), then the target module to be detected is determined to be an erroneous module.

[0041] The method and system for locating faulty modules in the FPGA image system disclosed above, through the construction of an independent diagnostic data path, switches to this path when an image anomaly is detected. A distributed error detection module compares the input and output data of each module under test, directly pinpointing the faulty module. This significantly reduces the time and manpower required for error location and improves onboard debugging efficiency. The error detection module can be flexibly deployed at the interface of any module. This distributed design supports progressively narrowing down the problem scope, achieving precise location from the module level to the sub-module level, meeting the needs of different debugging depths.

[0042] In one possible implementation of step S202 above, if an image anomaly is detected, the FPGA image system is switched from the original image transmission path to the diagnostic data path via the path switching module, including:

[0043] Upon receiving an externally triggered switching command, the switch is executed through the path switching module: disconnecting the data input of the original image transmission path and connecting the data generation module as the data source to the downstream processing module of the FPGA image system;

[0044] Maintain clock continuity for downstream processing modules during the switching process.

[0045] In this embodiment, the switching command can be generated by external triggers, such as by debugging personnel through external pins of the FPGA, host computer commands, or internal system logic.

[0046] The switching command serves as the control signal for the path switching module, used to initiate the path switching operation.

[0047] The path switching module performs a switching action, stopping the reception of image data output from the data acquisition module in the original image path and cutting off the data flow from the camera to the downstream processing module via the data acquisition module. At the same time, the path switching module connects the data generation module with the downstream processing module of the FPGA image system, so that the predictable test data sequence generated by the data generation module is used as a new data source and input to the downstream processing module, replacing the original image data in the system.

[0048] During path switching, the operating clocks of each downstream processing module remain unchanged to ensure continuous and stable clock signals. This avoids additional errors in downstream modules due to clock jitter or interruptions, ensuring that the transmission and processing environment of test data in downstream modules is consistent with the original image data, and ensuring the accuracy of the comparison results of subsequent error detection modules.

[0049] The error module localization method and system in the FPGA image system disclosed above utilizes a path switching module that switches between the original image transmission path data input and the diagnostic data path by disconnecting the original image transmission path data input and connecting the diagnostic data path. This process does not affect the hardware and logic design of the original image transmission path. This ensures that the original path's function remains uninterrupted when using the diagnostic data path to locate errors, and the system continues to operate normally after switching back to the original path, guaranteeing the stability of the system's basic functions. This switching mechanism, combined with the diagnostic data path integrated into the system design phase, allows for a rapid transition to diagnostic mode when image anomalies occur, without requiring large-scale modifications to the original path. Furthermore, after the system recovers, switching back to the original path allows for the removal of diagnostic-related modules to conserve resources. This design enables the system to meet both debugging needs and the resource requirements of normal operation, improving the overall design's adaptability.

[0050] In one possible implementation of step S102 above, the test data sequence includes: an arithmetic increasing sequence, a pseudo-random binary sequence, or a custom computable sequence.

[0051] In this embodiment, the data in the arithmetic increment sequence is generated according to a fixed arithmetic increment rule. The error detection module can calculate the predicted data by adding the currently received data to the fixed increment value, and then compare it with the next actual transmitted data.

[0052] For example, in an arithmetic increasing sequence where each number is 1 greater than the previous number, the error detection module can predict the next number as 5 based on the current number 4 and the preset pattern of "value plus 1".

[0053] A pseudo-random binary sequence is a pseudo-random binary data sequence generated based on a specific polynomial, and it is predictable. The error detection module can calculate the next expected data based on the polynomial corresponding to the pseudo-random binary sequence and the currently received data, and compare it with the next data that is actually transmitted.

[0054] Custom computable sequences can refer to test data sequences other than arithmetic increasing sequences and pseudo-random binary sequences. Their generation rules can be defined by the user, as long as they meet the condition that the next data can be calculated from the current data and the preset formula.

[0055] The error detection method and system in the FPGA image system described in the above embodiments of this disclosure provide test data sequences including arithmetic increment sequences, pseudo-random binary sequences, and custom computable sequences, covering various data generation patterns. This meets the debugging needs of different FPGA image systems and enhances the adaptability of the error detection method to different scenarios. The error detection module does not rely on external storage or complex protocol parsing; it only needs to implement simple calculation logic based on the generation pattern of the corresponding sequence to complete prediction and comparison. This design reduces the hardware resource consumption of the error detection module, making it easy to deploy in an FPGA and allowing for flexible addition or removal without affecting the original system design.

[0056] In one possible implementation of step S203 above, if the target module to be detected satisfies the condition that the comparison result of the input interface is correct but the comparison result of the output interface is incorrect, the target module to be detected is determined to be an erroneous module, including:

[0057] If the target module to be detected satisfies the condition that the comparison result of the input interface is correct but the comparison result of the output interface is incorrect, an error flag information is generated by the distributed error detection module, and the error flag information is output in at least one of the following ways to determine that the target module to be detected is an error module:

[0058] Drive the FPGA physical pins to make external indicating devices respond to error flag information;

[0059] Error flag information is transmitted to the on-chip debugging tool of the FPGA imaging system, and the error status is observed in real time through the debugging interface.

[0060] In this embodiment, after the error detection module detects that the output data is inconsistent with the predicted data, it automatically generates error flag information, which is used to identify that the target module to be detected has a data transmission error.

[0061] The error detection module transmits error flag information to external indicating devices (such as LED indicators, buzzers, etc.) through the FPGA's physical pins. For example, when the error flag information is valid, the FPGA physical pin outputs a high level, driving the LED indicator to light up or flash, visually indicating that the module has an error.

[0062] Alternatively, the error detection module can send error flag information to the on-chip debugging tools built into the FPGA imaging system (such as Xilinx's Integrated Logic Analyzer (ILA) or Virtual Input / Output (VIO)). Debuggers can connect to these tools via the debugging interface to observe the status of the error flag information in real time, obtaining details such as the specific time and module location of the error, thus aiding in further analysis of the cause of the error.

[0063] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the error detection process of an error detection module in an FPGA image system provided in this embodiment of the disclosure, wherein: assuming the test data sequence is an arithmetic increasing sequence that increments by 1 each time, the error detection module predicts the predicted data for the next time step and receives the output data for the current time step, such as... Figure 3 As shown, when the received data is 11, the corresponding predicted data is 9, indicating that there is 1 error. At this time, the target module to be detected is judged to be an error module, and error flag information is output to the outside.

[0064] The error module localization method and system in the FPGA image system described in the above embodiments of this disclosure rely solely on the distributed error detection module and the FPGA's own physical pins or debugging interface for the generation and output of error flag information, without requiring modification of the core logic of the original image transmission path. This ensures that the error identification process does not introduce new interference factors, enabling the output error information to accurately reflect the state of the target module under inspection and guaranteeing the accuracy of error judgment. For less experienced debugging personnel, the intuitive prompts from external indicating devices can reduce reliance on complex tools; for professionals, the refined data from on-chip debugging tools can support in-depth analysis. Both approaches lower the technical threshold for error localization.

[0065] In one embodiment, Figure 4This is a schematic diagram of the structure of an FPGA image system provided in an embodiment of this disclosure. This embodiment of the disclosure provides an FPGA image system 400, which corresponds one-to-one with the error module localization method in the FPGA image system described above. For example... Figure 4 As shown, the system includes a raw image transmission path 41, a diagnostic data path 42, and an error localization unit 43; wherein:

[0066] The original image transmission path 41 is used to acquire, process, and display image data;

[0067] Diagnostic data pathway 42, independent of the original image transmission pathway, includes:

[0068] The data generation module 421 is used to generate a test data sequence with a preset pattern;

[0069] The path switching module 422 is connected to the starting end of the original image transmission path and the starting end of the diagnostic data path. It is used to switch the system from the original image transmission path to the diagnostic data path when an image abnormality is detected, so that the test data sequence flows into the downstream processing module.

[0070] The distributed error detection module 423 is deployed at the input and output interfaces of each functional processing module. It is used to receive the test data sequence flowing through the corresponding module, generate prediction data based on preset rules and compare it with the actual transmitted data, and output the comparison results.

[0071] Error location unit 43 is used to determine that the target function processing module is an error module when the comparison result of the input interface of the target function processing module is correct and the comparison result of the output interface is incorrect, based on the comparison result of the distributed error detection module.

[0072] In one embodiment, the path switching module 422 is used to receive an externally triggered switching command and execute the following through the path switching module: disconnect the data input of the original image transmission path and connect the data generation module as the data source to the downstream processing module of the FPGA image system;

[0073] Maintain clock continuity for downstream processing modules during the switching process.

[0074] In one embodiment, the test data sequence includes: an arithmetic increasing sequence, a pseudo-random binary sequence, or a custom computable sequence.

[0075] In one embodiment, the error location unit 43 is used to determine that the target module to be detected is an erroneous module if the comparison result of the input interface is correct but the comparison result of the output interface is incorrect, by generating error flag information through the distributed error detection module 423, and outputting the error flag information in at least one of the following ways:

[0076] Drive the FPGA physical pins to make external indicating devices respond to error flag information;

[0077] Error flag information is transmitted to the on-chip debugging tool of the FPGA imaging system, and the error status is observed in real time through the debugging interface.

[0078] In one specific embodiment, Figure 5 This is a schematic diagram of another FPGA image system provided in this embodiment. Another FPGA image system 500 is provided, which corresponds one-to-one with the error module localization method in the FPGA image system of the above embodiments. For example... Figure 5 As shown, the FPGA image system 500 includes a raw image transmission path and a diagnostic data path. The raw image transmission path includes a data acquisition module, a clock domain conversion module, Ethernet, a buffer module, and a display control module. The diagnostic data path includes a data generation module, a channel 2-to-1 selection module, and several error detection modules.

[0079] The data acquisition module is connected to an external camera to acquire image data; the Ethernet modules are connected via an optical module interface to enable high-speed, long-distance image data transmission between the Ethernet modules; and the display control module is connected to a monitor to display image data on the monitor.

[0080] The data generation module and the data acquisition module receive switching instructions through a channel 2-to-1 module to switch paths. The error detection module is distributed at any position in the FPGA image system 500 and is used to output error information when an error occurs.

[0081] It should be noted that the FPGA image system provided in the above embodiments, when implementing the error module localization method in the corresponding FPGA image system, is only illustrated by the division of the above program modules. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the above system can be divided into different program modules to complete all or part of the processing described above. In addition, the system provided in the above embodiments and the corresponding Figure 1 The embodiments of the methods shown belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0082] This disclosure also provides a computer device having the above-described features. Figure 4-5 The FPGA image system shown in any one of them.

[0083] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of another FPGA image system provided in this disclosure embodiment, such as... Figure 6As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 6 Take a processor 10 as an example.

[0084] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0085] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0086] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0087] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0088] The computer device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 6 Taking the example of a connection between China and Israel via a bus.

[0089] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as a touchscreen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touchscreen.

[0090] The computer device also includes a communication interface for communicating with other devices or communication networks.

[0091] This disclosure also provides a computer-readable storage medium in which the methods described in this disclosure can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded over a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium may be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0092] A portion of this disclosure can be applied to computer program products, such as computer program instructions, which, when executed by a computer, can invoke or provide methods and / or technical solutions according to this disclosure through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, and installation package files. Accordingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions; the computer compiling the instructions and then executing the corresponding compiled program; the computer reading and executing the instructions; or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0093] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for locating faulty modules in an FPGA image system, characterized in that, The method includes: A diagnostic data path independent of the original image transmission path is constructed in the FPGA image system; wherein, the diagnostic data path includes: a data generation module, a path switching module, and a distributed error detection module; the path switching module is a channel 2-to-1 selector implemented based on the internal logic resources of the FPGA; the distributed error detection module is deployed at the input interface and output interface of the module to be tested; If an image anomaly is detected, the FPGA image system is switched from the original image transmission path to the diagnostic data path via the path switching module. This includes: receiving an externally triggered switching command and executing the following through the path switching module: disconnecting the data input of the original image transmission path and connecting the data generation module as a data source to the downstream processing module of the FPGA image system; maintaining the clock continuity of the downstream processing module during the switching process. The distributed error detection module receives a sequence of test data flowing through the module to be detected at each moment. The test data sequence includes: an arithmetic increasing sequence, a pseudo-random binary sequence, or a custom computable sequence. The predicted data is compared with the actual transmitted data. If the target module to be detected satisfies the condition that the comparison result of the input interface is correct but the comparison result of the output interface is incorrect, the target module to be detected is determined to be an error module. The predicted data is generated by the distributed error detection module based on a preset rule. If the target module to be detected satisfies the condition that the comparison result of the input interface is correct but the comparison result of the output interface is incorrect, the target module to be detected is determined to be an erroneous module, including: If the target module to be detected satisfies the condition that the comparison result of the input interface is correct but the comparison result of the output interface is incorrect, the distributed error detection module generates error flag information and outputs the error flag information in at least one of the following ways to determine that the target module to be detected is an error module: Drive the FPGA physical pins to make the external indicating device respond to the error flag information; The error flag information is transmitted to the on-chip debugging tool of the FPGA imaging system, and the error status is observed in real time through the debugging interface.

2. An FPGA imaging system, characterized in that, The system, applied to the method of claim 1 above, comprises: The raw image transmission path is used to acquire, process, and display image data; The diagnostic data pathway, independent of the original image transmission pathway, includes: The data generation module is used to generate a test data sequence with a preset pattern; the test data sequence includes: an arithmetic increasing sequence, a pseudo-random binary sequence, or a custom computable sequence; A path switching module is connected to the starting end of the original image transmission path and the starting end of the diagnostic data path. When an image abnormality is detected, the system switches from the original image transmission path to the diagnostic data path, so that the test data sequence flows into the downstream processing module. The path switching module is a 2-to-1 channel selector implemented based on the internal logic resources of the FPGA. The distributed error detection module is deployed at the input and output interfaces of each functional processing module. It is used to receive the test data sequence flowing through the corresponding module, generate prediction data based on preset rules and compare it with the actual transmitted data, and output the comparison results. The error location unit is used to determine that the target function processing module is an error module when the comparison result of the input interface of the target function processing module is correct and the comparison result of the output interface is incorrect, based on the comparison result of the distributed error detection module. Specifically, the path switching module is used to receive an externally triggered switching command, disconnect the data input of the original image transmission path, and connect the data generation module as a data source to the downstream processing module of the FPGA image system. Maintain clock continuity for downstream processing modules during switching; The error location unit is specifically used to determine that the target module to be detected is an erroneous module if the comparison result of the input interface is correct but the comparison result of the output interface is incorrect. This is achieved by generating error flag information through the distributed error detection module and outputting the error flag information in at least one of the following ways: Drive the FPGA physical pins to make external indicating devices respond to error flag information; Error flag information is transmitted to the on-chip debugging tool of the FPGA imaging system, and the error status is observed in real time through the debugging interface.

3. A computer device, characterized in that, include: The system includes a memory and a processor, which are interconnected. The memory stores computer instructions, and the processor executes these computer instructions to perform the error module localization method in the FPGA image system of claim 1.

4. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the method for locating an error module in the FPGA image system of claim 1.

5. A computer program product, characterized in that, It includes computer instructions for causing a computer to execute the method for locating an error module in the FPGA image system of claim 1.

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