Single board, debugging method, storage medium and electronic device

Abstract

The application provides a single board, a debugging method, a storage medium and an electronic device, the single board comprising: a CPU and a control module; an interface A on the CPU is connected with an interface B on the control module, and the CPU is further connected with a host computer; after receiving a debugging identifier instruction output by the host computer, the CPU outputs a debugging channel switching instruction to the control module through the interface A; under the condition of receiving the debugging channel switching instruction, the control module redirects the interface B as a debugging interface; the CPU further transmits a debugging instruction output by the host computer to the control module and debugging data output by the control module to the host computer; and the control module further performs debugging based on the debugging instruction and outputs the debugging data to the host computer through the debugging interface. By multiplexing the protocol interface between the CPU and the control module as the debugging interface and transmitting the data of the host computer and the control module through the CPU, the control module can be debugged without additional welding of the interface.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of single board debugging, and in particular to a single board, a debugging method, a storage medium and an electronic device. BACKGROUND

[0002] A control module is arranged on a single board (an independently printed circuit board), and a debugging interface is reserved in a test board, so that the control module can be debugged through the debugging interface. However, in a formal mass production product, a debugging interface is not reserved for the control module. The debugging interface usually provides a very high permission, even a root permission. If the physical interface is exposed, anyone who can physically touch the device (such as malicious internal personnel and data center maintenance personnel) can easily connect and obtain full control of the system. Through the debugging interface, sensitive information such as memory information, kernel logs and business data can be read, resulting in data leakage. In many fields, security certification standards (such as Common Criteria) explicitly require that the debugging interface be disabled or strictly protected to eliminate the physical attack surface.

[0003] In addition, the material cost of the debugging interface in mass production is not negligible. The debugging interface will increase the production cost and occupy the space of the single board component, and increase the complexity of wiring.

[0004] Therefore, if the control module in the formal mass production product needs to be debugged, the prior art needs to manually weld a debugging interface. However, the manual welding of the debugging interface scheme is difficult, time-consuming, and some products do not have the conditions to weld the debugging interface. SUMMARY

[0005] The present application provides a single board, which comprises:

[0006] a CPU and a control module; an interface A on the CPU is connected with an interface B on the control module, and the CPU is further connected with a host computer;

[0007] the CPU is configured to output a debugging channel switching instruction to the control module through the interface A after receiving a debugging identification instruction output by the host computer;

[0008] the control module is configured to redirect the interface B to a debugging interface in the case of receiving the debugging channel switching instruction;

[0009] the CPU is further configured to transmit a debugging instruction output by the host computer to the control module and a debugging data output by the control module to the host computer;

[0010] the control module is further configured to debug based on the debugging instruction and output the debugging data to the host computer through the debugging interface.

[0011] Optionally, the control module further comprises a port C;

[0012] The port C is initialized as a debug port;

[0013] The control module is further configured to, in response to receiving the debug channel switching instruction, close the debug channel of the port C, and redirect the interface B as a debug interface.

[0014] Optionally, the control module comprises a controller and a multiplexer;

[0015] The controller has the interface B and the port C;

[0016] A first input end of the multiplexer is connected with the interface B, a second input end of the multiplexer is connected with the port C, and an output end of the multiplexer is connected with the interface A; a selection end of the multiplexer is connected with an IO end of the controller;

[0017] The controller is configured to, in response to receiving the debug channel switching instruction, output a first selection instruction to the selection end;

[0018] The multiplexer is further configured to, in response to receiving the first selection instruction, turn on a path between the port C and the interface A.

[0019] Optionally, the controller is further configured to, in response to not receiving the debug channel switching instruction and not receiving a debug instruction, output a second selection instruction to the selection end;

[0020] The multiplexer is further configured to, in response to receiving the second selection instruction, turn on a path between the interface B and the interface A.

[0021] Optionally, the controller is further configured to, after receiving the debug channel switching instruction or the debug instruction, start timing, and configured to, in response to the timing ending and not receiving the debug instruction, output the second selection instruction to the multiplexer.

[0022] Optionally, the control module further comprises a monitoring module;

[0023] An input end of the monitoring module is connected with the port C, and an output end of the monitoring module is connected with the interface A; a controlled end of the monitoring module is connected with the controller;

[0024] The controller is further configured to, in response to the port C being a debug interface and receiving a monitoring trigger signal, output a monitoring signal to the monitoring module;

[0025] The monitoring module is configured to output the debugging data output by the port C to the CPU when the monitoring signal is received.

[0026] Optionally, the CPU is connected to the host computer through a network cable.

[0027] The application further provides a debugging method applied to the control module in the single board.

[0028] The debugging method comprises the following steps of:

[0029] The port C is initialized as a debugging port, and the interface B is initialized as a protocol interface.

[0030] When the debugging channel switching instruction is received, the interface B is configured as a data flow mode, and the port C is closed.

[0031] The debugging data flow is output through the interface B.

[0032] The application further provides a storage medium storing a single board debugging program, wherein the single board debugging program realizes the corresponding steps of the debugging method when processed by a processor.

[0033] The application further provides an electronic device comprising the single board.

[0034] The application provides a single board, a debugging method, a storage medium and an electronic device, the single board comprising a CPU and a control module; an interface A on the CPU is connected to an interface B on the control module, and the CPU is further connected to a host computer; the CPU is configured to output a debugging channel switching instruction to the control module through the interface A after receiving a debugging identification instruction output by the host computer; the control module is configured to redirect the interface B as a debugging interface when the debugging channel switching instruction is received; the CPU is further configured to transmit a debugging instruction output by the host computer to the control module and debugging data output by the control module to the host computer; and the control module is further configured to perform debugging based on the debugging instruction and output the debugging data to the host computer through the debugging interface. The application multiplexes the protocol interface between the CPU and the control module as a debugging interface, transmits the data of the host computer and the control module through the CPU, and realizes the debugging of the control module without the need of welding an additional interface for the control module. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only show some of the embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the structures shown in these drawings without any creative effort.

[0036] Figure 1 The structure schematic diagram of the first embodiment of the single board of the present application;

[0037] Figure 2 The first structure schematic diagram of the second embodiment of the single board of the present application;

[0038] Figure 3 The second structure schematic diagram of the second embodiment of the single board of the present application.

[0039] Explanation of reference signs:

[0040]

[0041] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the scope of protection of the present application.

[0043] It should be noted that all the directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directionality indications will also change accordingly.

[0044] In the present application, unless otherwise explicitly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense, for example, "fixation" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through intermediate medium; can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0045] In addition, the description such as "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor in the protection scope required by the present application.

[0046] The present application provides a solution to the debugging problem of the control module 10 in the formal mass production single board, which aims to complete the debugging of the control module 10 in the single board without manual welding debugging interface.

[0047] The present application provides a single board, in the first embodiment, as shown in Figure 1 The single board comprises:

[0048] CPU and control module 10; the interface A on the CPU is connected with the interface B on the control module 10, and the CPU is also connected with the host computer;

[0049] The CPU is used for outputting the debugging channel switching instruction to the control module 10 through the interface A after receiving the debugging identification instruction output by the host computer;

[0050] The control module 10 is used for redirecting the interface B as a debugging interface under the condition of receiving the debugging channel switching instruction;

[0051] The CPU is also used for transmitting the debugging instruction output by the host computer to the control module 10 and the debugging data output by the control module 10 to the host computer;

[0052] The control module 10 is also used for debugging based on the debugging instruction and outputting the debugging data to the host computer through the debugging interface.

[0053] As shown in Figure 1As shown, the single board includes a CPU and a control module 10; the CPU is also connected with the host computer and interacts with the host computer. The CPU is connected with the interface B provided on the control module 10 through the interface A provided on the port of the CPU, so as to realize the connection of the control module 10. There is no interface for debugging in the mass-produced product; in the present application, the control module 10 further includes a port C, which is used for debugging the control module 10 and is initialized as a debugging port. An interface can be welded at the port C as a debugging interface for testing the product debugging. It should be noted that the functions of the ports of the control module 10 are related to the internal hardware circuit and program design, and the port C is used for connecting with external equipment, transmitting debugging data and debugging. Therefore, the debugging data is output by the port C. For example, after the debugging data is acquired and stored, the debugging data is written into the register of the port C to realize the output.

[0054] However, in the present application, since the application scenario is the mass-produced product, the port C is not allowed to be welded with an interface as a debugging interface.

[0055] In the embodiment, the CPU connected with the control module 10 is used to debug the control module 10. Specifically, the operator can first operate the host computer to output a debugging identification instruction to the CPU, which represents that the control module 10 needs to be debugged.

[0056] It is easy to understand that the CPU and the control module 10 transmit data through the interface A and the interface B, and the interface A and the interface B are protocol interfaces. The CPU and the control module 10 transmit data through corresponding protocol rules. The function of the protocol interface is to provide a set of conversation rules between "machines and machines", so as to realize the standardization, automation and remote of system management. For example, the protocol interface (such as IPMI) defines a set of standard command set and data structure, so that the hardware and management software of different manufacturers can be compatible and cooperative. However, in the protocol interface state, the data is mainly transmitted by the protocol data packet, the data packet is highly structured, and includes a packet header, a target address, a command word, a data payload, a checksum and the like. The data sending and receiving need to be packed and unpacked.

[0057] The function of the debugging identification instruction is to identify the start of the debugging function, which can be any signal form determined by the R&D personnel; for example, a character that can be recognized by the CPU and mapped to the start of the debugging identification; or the debugging identification instruction is used to modify the flag bit of a specific register, which is used to judge whether the debugging is started. Similarly, the function of the debugging channel switching instruction is to inform the control module 10 to start the debugging function through the CPU. The debugging channel switching instruction can also be a signal form determined by the R&D personnel.

[0058] In an example, the debug channel switching instruction can be initiated by an open source program ipmitool on the CPU.

[0059] In addition, under the initial module (when the CPU does not receive a debug identification instruction), the CPU transmits data with the control module 10 through a protocol data packet. When the control module 10 receives a debug channel switching instruction, the control module 10 redirects the interface B as a debug interface. The specific explanation is as follows: it is mentioned in the foregoing that, in the present application, the port C is assumed to be a debug port, but the port C is applied to a debug version product for debugging; in a mass production product, the interface of the port C is not set, and debugging cannot be performed. In the present embodiment, the control module 10 redirects the interface B as a debug interface, that is, debug data is output through the interface B. It needs to be explained that the debug data is a byte stream, which is a continuous and original byte sequence without a predefined format. The characteristic of the debug interface is that the debug data is directly written into a sending register of a hardware serial port (interface) without any encapsulation.

[0060] In the present embodiment, the protocol interface between the CPU and the control module 10 is multiplexed as a debug interface, so that the control module 10 outputs debug data, which is output to the host computer through the CPU, and waits for an operator to perform debugging or related operations.

[0061] In an example, the interface B redirected as a debug interface can perform the following operations:

[0062] 1. Configure the interface B as a data stream mode; in a protocol mode, the hardware and the underlying driver of the interface B expect to receive correctly formatted IPMI data packets. If debug instructions are directly filled in at this time, these data will be parsed by the IPMI protocol stack of the receiving end (the control module 10). This will cause a large number of checksum errors, invalid command errors, and finally make the protocol stack of the receiving end chaotic or directly discard all data, resulting in the failure of both normal management communication and debug communication.

[0063] The essence of the debug information is a clear text byte stream for people to see. Only by switching to the data stream mode, the bytes are sent out one by one without being changed, and the host computer software at the remote end can correctly receive and display them as readable text. If the debug information is sent in the protocol mode, the debug information will be disassembled and distorted into an unrecognizable data packet, and the terminal will see random codes. In addition, in the protocol mode, the hardware (UART) of the interface B is usually controlled exclusively by the IPMI kernel driver. The driver is responsible for packet assembly, sending, receiving and unpacking. To directly operate the hardware to send raw data, the control right of the hardware by the IPMI driver must be released (or made into a "bypass" state). The process of switching to the "data stream mode" is essentially the process of releasing the binding of the protocol stack and releasing the control right of the UART hardware.

[0064] The specific steps of configuring interface B to data stream mode can be as follows,

[0065] Shutting down the protocol service: stopping the IPMI daemon or protocol stack that is using the interface, preventing it from continuing to access the hardware.

[0066] Unloading or resetting the driver: unbinding the kernel driver from the UART hardware, or switching the driver mode from "protocol mode" to "raw mode".

[0067] Reconfiguring the hardware: ensuring that the UART controller 110 is set to common serial port parameters (115200 baud, 8N1), and that its FIFO, interrupts, etc. are set up for transmitting continuous data streams rather than discrete data packets.

[0068] 2. Adding interface B to the output path of the debug data, or modifying the output path of the debug data to interface B.

[0069] It should be noted that if interface B is added to the output path of the debug data, the control module 10 outputs through port C and interface B when outputting the debug data. If the output path of the debug data is modified to interface B, the control module 10 closes the debug channel of port C and only outputs the debug data through interface B.

[0070] The control module 10 performs debugging based on the debugging instruction to obtain debug data, and outputs the debug data to the host computer through the debugging interface. It should be understood that the debugging instruction is determined and sent by the operator based on the debugging purpose; accordingly, the debugging performed by the control module 10 when receiving the debugging instruction is completed by the R&D personnel in advance. The present application does not limit the specific content of the above debugging instruction and debugging process.

[0071] The CPU transmits the debugging instruction output by the host computer to the control module 10 and the debug data output by the control module 10 to the host computer after outputting the debug channel instruction. Since the debugging instruction and the debug data are not encapsulated, the CPU can transmit the content output by the host computer and the control module 10. However, it should be noted that if the CPU and the host computer need to communicate through a related transmission protocol, the CPU needs to encapsulate the debug data according to the requirements of the transmission protocol before transmission. Alternatively, the CPU extracts the original debugging instruction from the data frame transmitted by the host computer according to the transmission protocol, and then outputs it to the control module 10.

[0072] The application provides a single board, which comprises a CPU and a control module 10; an interface A on the CPU is connected with an interface B on the control module 10, and the CPU is also connected with a host computer; the CPU is used for outputting a debugging channel switching instruction to the control module 10 through the interface A after receiving a debugging identification instruction output by the host computer; the control module 10 is used for redirecting the interface B as a debugging interface under the condition of receiving the debugging channel switching instruction; the CPU is also used for transmitting a debugging instruction output by the host computer to the control module 10 and transmitting debugging data output by the control module 10 to the host computer; and the control module 10 is also used for outputting the debugging data to the host computer through the debugging interface based on the debugging instruction. By multiplexing the protocol interface between the CPU and the control module 10 as a debugging interface and by transmitting the data of the host computer and the control module 10 through the CPU, the control module 10 can be debugged without welding an additional interface for the control module 10.

[0073] In an example, the control module 10 further comprises a port C;

[0074] The port C is initialized as a debugging port;

[0075] The control module 10 is also used for closing the debugging channel of the port C and redirecting the interface B as a debugging interface under the condition of receiving the debugging channel switching instruction.

[0076] It is easily understood that the application redirects the interface B as a debugging interface, and normally, the debugging data is output through the port C because the port C is initialized as a debugging port. However, the debugging data can be output through the port C and the interface B because the application multiplexes the interface B. However, the debugging data output through the interface B can be incomplete because the debugging data can be output through two places. In order to ensure the uniqueness of the debugging data channel and the integrity of the debugging data, the control module 10 closes the debugging channel of the port C and redirects the interface B as a debugging interface under the condition of receiving the debugging channel switching instruction.

[0077] In the second embodiment of the application, as shown in Figure 2 The control module 10 comprises a controller 110 and a multiplexer 120;

[0078] The controller 110 has the interface B and the port C;

[0079] A first input end of the multiplexer 120 is connected with the interface B, a second input end is connected with the port C, and an output end is connected with the interface A; and a selection end of the multiplexer 120 is connected with an IO end of the controller 110.

[0080] a controller 110, configured to output a first selection instruction to the selection end in a case where the debug channel switching instruction is received;

[0081] The multiplexer 120 is further configured to turn on a path between the port C and the interface A in a case where the first selection instruction is received.

[0082] It should be noted that the letters after the interface A, the interface B or the port C are only used for distinguishing.

[0083] The embodiment provides a hardware level implementation of transmitting debug data without redirecting the interface B to a debug interface. Specifically, a first input end of a multiplexer 120 is connected with the interface B, a second input end of the multiplexer 120 is connected with the port C, and an output end of the multiplexer 120 is connected with the interface A. The multiplexer 120 selectively turns on an input end connected with the interface A, can turn on a path between the port C (the second input end of the multiplexer 120) and the interface A (the output end of the multiplexer 120) in a case where a first selection instruction is received, and can turn on a path between the interface B (the first input end of the multiplexer 120) and the interface A (the output end of the multiplexer 120) in a case where a second selection instruction is received.

[0084] It can be easily understood that, in a case where the CPU does not output a debug channel switching instruction, the multiplexer 120 turns on a path between the interface B and the interface A, thereby realizing communication between the CPU and the controller 110 through a related protocol data packet. The controller 110 outputs a first selection instruction to the selection end in a case where the debug channel switching instruction is received, controls the multiplexer 120, turns off a path between the interface B and the interface A, and turns on a path between the port C and the interface A.

[0085] In the embodiment, the controller 110 does not need to redirect an interface to a debug interface in a case where a debug channel switching instruction is received, but switches the port C or the interface A connected with the CPU by using the multiplexer 120. The controller 110 can output debug data to the CPU from the port C, and then output to a host computer. In a case where debugging is not needed, the multiplexer 120 can be switched to turn on the interface B and the interface A.

[0086] The controller 110 can include an MCU, an FPGA or an SOC.

[0087] In an example, the controller 110 is further configured to output a second selection instruction to the selection end in a case where the debug channel switching instruction is not received and a debug instruction is not received.

[0088] The multiplexer 120 is also configured to, when the second selection instruction is received, turn on the path between the interface B and the interface A.

[0089] It should be noted that the control module 10 needs to upload the debugging data to the CPU only when the host computer sends a debugging identification instruction or a debugging instruction; if the controller 110 does not receive the debugging channel instruction and does not receive the debugging instruction, it means that the control module 10 does not need to be debugged and needs to communicate normally with the CPU. At this time, in order to ensure the communication channel between the controller 110 and the CPU, the controller 110 outputs a second selection instruction to the selection end to maintain the path between the interface B and the interface A.

[0090] The interface B is connected to the first input end of the multiplexer, the port C is connected to the second input end of the multiplexer, and the interface A is connected to the output end of the multiplexer. Turning on the path between the interface B and the interface A is equivalent to turning on the path between the first input end and the output end of the multiplexer. Turning on the path between the port C and the interface A is equivalent to turning on the path between the second input end and the output end of the multiplexer.

[0091] In another example, the controller 110 is also configured to, after receiving the debugging channel switching instruction or the debugging instruction, start timing, and output a second selection instruction to the multiplexer 120 when the pre-designed time length ends and no debugging instruction is received.

[0092] It is easy to understand that there is a case that the operator forgets to exit the debugging mode after the control module 10 is debugged through the host computer. For example, the host computer can send a debugging end instruction, and the CPU outputs a recovery instruction to the control module 10 after receiving the debugging end instruction. The control module 10 restores the interface B to a protocol interface (or outputs a second selection instruction) after receiving the recovery instruction.

[0093] The controller 110 can include a timer, which starts timing when the debugging channel switching instruction or the debugging instruction is received. It should be explained that this example is to solve the problem that the control module 10 cannot recover normal communication with the CPU for a long time. The timer starts timing again every time the debugging channel switching instruction or the debugging instruction is received. If no debugging instruction is received from the start of timing to the end of the pre-designed time length, it means that the host computer has not responded for a long time. At this time, the controller 110 can output a second selection instruction to the multiplexer 120. The timer can generate an interrupt signal to the core of the controller 110 after the pre-designed time length ends.

[0094] In another example, as shown in Figure 3 The control module 10 also includes a monitoring module 130.

[0095] The input end of the monitoring module 130 is connected with the port C, and the output end is connected with the interface A; the controlled end of the monitoring module 130 is connected with the controller 110;

[0096] The controller 110 is further configured to output a monitoring signal to the monitoring module 130 when the port C is a debugging interface and a monitoring trigger signal is received.

[0097] The monitoring module 130 is configured to output the debugging data output by the port C to the CPU when the monitoring signal is received.

[0098] The present example can solve the problem of viewing and recording debugging data when the operator debugs the control module 10 through the debugging interface of the port C.

[0099] Specifically, the input end of the monitoring module 130 is connected with the port C, and the output end is connected with the interface A; the controlled end of the monitoring module 130 is connected with the controller 110. The monitoring module 130 can output the debugging data output by the port C to the CPU when the port C outputs the debugging data. Specifically, the monitoring module 130 copies the data output by the port C to the interface A.

[0100] The monitoring trigger signal can be output to the controller 110 by the electronic device connected with the port C, or an interrupt signal can be generated after the debugging instruction is received by the port C; the controller 110 receives the interrupt signal as the monitoring trigger signal.

[0101] It is easy to understand that the monitoring module 130 does not work when the control module 10 outputs the debugging data to the host computer through the CPU.

[0102] The monitoring module 130 can include a dual-channel UART switch / reproduction IC, such as a chip with a model number of MAX14866.

[0103] The present application does not limit the connection form of the CPU and the host computer. The CPU can be connected with the host computer through a network cable, or can be connected through a wireless transmission mode.

[0104] The present application further provides an electronic device including the single board. For example, the electronic device can be a server.

[0105] The specific structure of the single board is referred to the above-mentioned embodiments. Since the present electronic device adopts all the technical solutions of the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0106] The application further provides a debugging method applied to the control module 10 in the single board.

[0107] The debugging method comprises:

[0108] initializing the port C as a debugging port and initializing the interface B as a protocol interface;

[0109] configuring the interface B as a data stream mode and closing the port C when receiving a debugging channel switching instruction;

[0110] outputting a debugging data stream through the interface B.

[0111] It is easy to understand that the debugging method is applied to the control module in the single board; the control module comprises the port C and the interface B, and initially (before receiving the debugging channel switching instruction) the port C is a debugging port and the interface B is connected with a CPU and is a protocol interface. Therefore, the port C is initialized as a debugging port and the interface B is initialized as a protocol interface. The control module can initialize the port C and the interface B after a power-on self-test.

[0112] When receiving the debugging channel switching instruction, the control module firstly configures the interface B as a data stream mode to make it out of the protocol interface state, and then closes the port C to make the debugging data output completely from the interface B.

[0113] The debugging method multiplexes the interface B as a debugging interface and realizes the debugging data output through the interface B.

[0114] The application further provides a storage medium storing a single board debugging program, which realizes the corresponding steps of the debugging method when processed by a processor.

[0115] The storage medium can comprise a RAM, a ROM or an EEPROM, etc.

[0116] The above description is only optional embodiments of the application, and does not limit the patent scope of the application, and any equivalent structural transformation, direct / indirect application in other related technical fields under the inventive concept of the application and the contents of the specification and drawings are included in the patent protection scope of the application.

Claims

1. A single board, characterized by, The single board comprises: a CPU and a control module; an interface A on the CPU is connected with an interface B on the control module, and the CPU is further connected with a host computer; the CPU is configured to output a debugging channel switching instruction to the control module through the interface A after receiving a debugging identification instruction output by the host computer; the control module is configured to redirect the interface B as a debugging interface in the case of receiving the debugging channel switching instruction; the CPU is further configured to transmit a debugging instruction output by the host computer to the control module and debugging data output by the control module to the host computer; the control module is further configured to perform debugging based on the debugging instruction and output the debugging data to the host computer through the debugging interface; the control module further comprises a port C; the port C is initialized as a debugging port; the control module is further configured to close the debugging channel of the port C and redirect the interface B as the debugging interface in the case of receiving the debugging channel switching instruction; the control module comprises a controller and a multiplexer; the controller has the interface B and the port C; a first input end of the multiplexer is connected with the interface B, a second input end of the multiplexer is connected with the port C, and an output end of the multiplexer is connected with the interface A; a selection end of the multiplexer is connected with an IO end of the controller; the controller is configured to output a first selection instruction to the selection end in the case of receiving the debugging channel switching instruction; the multiplexer is further configured to turn on a path between the port C and the interface A in the case of receiving the first selection instruction; the controller is further configured to output a second selection instruction to the selection end in the case of not receiving the debugging channel switching instruction and not receiving a debugging instruction; the multiplexer is further configured to turn on a path between the interface B and the interface A in the case of receiving the second selection instruction.

2. The veneer of claim 1, wherein The controller is further configured to start timing after receiving the debugging channel switching instruction or the debugging instruction, and output the second selection instruction to the multiplexer in the case of not receiving the debugging instruction when a pre-designed timing duration ends.

3. The veneer of claim 1, wherein, The control module further comprises a monitoring module; an input end of the monitoring module is connected with the port C, and an output end of the monitoring module is connected with the interface A; a controlled end of the monitoring module is connected with the controller; the controller is further configured to output a monitoring signal to the monitoring module in the case of the port C being a debugging interface and receiving a monitoring trigger signal; the monitoring module is configured to output debugging data output by the port C to the CPU in the case of receiving the monitoring signal.

4. The veneer of claim 1, wherein, The CPU is connected with the host computer through a network cable.

5. A debugging method characterized by, The debugging method is applied to the control module in the single board according to any one of claims 2 to 4; the debugging method comprises: initializing the port C as a debugging port and initializing the interface B as a protocol interface; configuring the interface B as a data flow mode and closing the port C when receiving a debugging channel switching instruction; outputting a debugging data flow through the interface B.

6. A storage medium, characterized by The storage medium stores a single-board debugging program, which, when processed by the processor, implements steps corresponding to the debugging method of claim 5.

7. An electronic device, comprising: The electronic device comprises the single board according to any one of claims 1 to 4.

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