Hardware-accelerated emulation offline debugging method, electronic device, and medium

Abstract

The present application relates to the technical field of chip verification, and particularly relates to a hardware acceleration simulation offline debugging method, an electronic device and a medium, which comprises the following steps: setting a unique corresponding synthesizable monitor for each synthesizable design under test in a hardware acceleration simulation system; a target design under test performs hardware acceleration simulation, a target monitor acquires each simulation data of the target design under test and a time stamp corresponding to each simulation data, and stores the simulation data in a target memory database in chronological order; generating a target file database corresponding to the target design under test based on the target memory database; isolating the target design under test corresponding to the target design under test in the chip verification simulation system and a target test platform, inputting the simulation data in the target file database into the target test platform in chronological order of the corresponding time stamps, and performing hardware acceleration simulation offline debugging based on the output result of the target test platform. The present application improves the debugging efficiency of hardware acceleration simulation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip verification, and in particular to a hardware acceleration simulation offline debugging method, an electronic device and a medium. BACKGROUND

[0002] In the chip verification process, there is a hardware acceleration simulation stage. When the hardware acceleration simulation halts, it may be that a problem has occurred at the current time, resulting in the halt. However, because the chip is large in scale, for example, a graphics processing unit (GPU) chip, the constituent units may be related to each other, and therefore the real reason for the halt of the hardware acceleration simulation may not be the problem that has occurred at the current time, and it may be necessary to trace back to the source of the problem. If online debugging is directly performed, a large amount of resources needs to be consumed, and the speed is very slow, and it is very difficult to implement, and the debugging efficiency is low. Therefore, how to improve the debugging efficiency of the hardware acceleration simulation becomes a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a hardware acceleration simulation offline debugging method, an electronic device and a medium, and improve the debugging efficiency of the hardware acceleration simulation.

[0004] According to a first aspect of the present application, a hardware acceleration simulation offline debugging method is provided, comprising:

[0005] A unique corresponding synthesizable monitor is set for each synthesizable design under test in a hardware acceleration simulation system, and the hardware acceleration simulation system comprises at least one synthesizable design under test;

[0006] The target design under test performs hardware acceleration simulation, the target monitor acquires each simulation data generated by the target design under test performing hardware acceleration simulation and a time stamp corresponding to each simulation data, and stores the simulation data and the time stamp in a target memory database corresponding to the target design under test in chronological order. Each synthesizable design under test in the hardware acceleration simulation system has a unique corresponding memory database. The target design under test is any one of the at least one synthesizable design under test. The target monitor is a synthesizable monitor corresponding to the target design under test. The target memory database is a memory database corresponding to the target design under test. The simulation data corresponding to different synthesizable designs under test is the same in quantity or different in quantity.

[0007] A target file database corresponding to the target design under test is generated based on the target memory database;

[0008] Isolating the target test platform corresponding to the target design under test and the design under test in the chip verification simulation system corresponding to the target design under test in the chip verification simulation system, inputting the simulation data in the target file database into the target test platform according to the chronological order of the corresponding time stamps, and performing hardware accelerated simulation offline debugging based on the output result of the target test platform.

[0009] Further, the target design under test performs hardware accelerated simulation, the target monitor obtains each simulation data generated by the target design under test performing hardware accelerated simulation and the time stamp corresponding to each simulation data, and stores them in the target memory database corresponding to the target design under test in chronological order, including:

[0010] Setting a target DPI interface for the target memory database;

[0011] The target monitor obtains each simulation data generated by the target design under test performing hardware accelerated simulation and the time stamp corresponding to each simulation data, and stores them in the target memory database in chronological order after converting them into the form of a high-level language through the corresponding target DPI interface, and the target memory database is generated based on the high-level language.

[0012] Further, the high-level language is C++, and the target design under test and the target monitor are generated based on the SystemVerilog language.

[0013] Further, the target file database corresponding to the target design under test is generated based on the target memory database, including:

[0014] Setting a target API interface for the target memory database;

[0015] Connecting the target file database and the target memory database, obtaining the simulation data and the corresponding time stamp from the target memory database through the corresponding target API interface, converting them into the file format corresponding to the target file database, and storing the converted simulation data and the corresponding time stamp into the target file database.

[0016] Further, the target test platform corresponding to the target design under test and the design under test in the chip verification simulation system corresponding to the target design under test in the chip verification simulation system are isolated, the simulation data in the target file database is input into the target test platform according to the chronological order of the corresponding time stamps, and hardware accelerated simulation offline debugging is performed based on the output result of the target test platform, including:

[0017] Isolate the target design under test corresponding to the target design under test in the chip verification simulation system and the target test platform corresponding to the target design under test corresponding to the target design under test in the chip verification simulation system, so that the target test platform no longer receives the data generated by the target design under test corresponding to the target design under test in the chip verification simulation system.

[0018] The simulation data in the target file database is input into the score board of the target test platform in the order of the corresponding time stamps, and the score board of the target test platform compares the simulation data with the corresponding reference data, and if they are inconsistent, corresponding prompt information is generated.

[0019] Further, the simulation data in the target file database is input into the score board of the target test platform in the order of the corresponding time stamps, and the score board of the target test platform compares the simulation data with the corresponding reference data, and if they are inconsistent, corresponding prompt information is generated.

[0020] A preset time interval is set.

[0021] The simulation data in the target file database is input into the score board of the target test platform in the order of the corresponding time stamps, and every preset time interval.

[0022] Further, the preset time interval is 1 nanosecond, 1 millisecond or 1 microsecond.

[0023] According to the second aspect of the present application, an electronic device is provided, comprising: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method of the first aspect of the present application.

[0024] According to the third aspect of the present application, a computer readable storage medium is provided, which stores computer executable instructions, and the computer instructions are used to execute the method of the first aspect of the present application.

[0025] Compared with the prior art, the present application has obvious advantages and beneficial effects. By the above technical scheme, the hardware acceleration simulation offline debugging method, electronic device and medium provided by the present application can achieve considerable technical progress and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:

[0026] The application first stores simulation data generated by hardware acceleration simulation of a target design under test in a target memory database and corresponding timestamps, then converts the target memory database into a target file database, and then reuses a target test platform in a chip verification simulation system, inputs data in the target file database into corresponding target test platforms in sequence, and performs offline debugging of the hardware acceleration simulation based on results output by the corresponding target test platforms, thereby improving the debugging efficiency of the hardware acceleration simulation. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0028] Figure 1 The present application provides a hardware acceleration simulation offline debugging method flow chart. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort are within the scope of protection of the present application.

[0030] The present application provides a hardware acceleration simulation offline debugging method, as shown in Figure 1 The method comprises the following steps.

[0031] Step S1, setting a unique corresponding synthesizable monitor for each synthesizable design under test in a hardware acceleration simulation system, wherein the hardware acceleration simulation system comprises at least one synthesizable design under test.

[0032] The hardware acceleration simulation system accelerates the simulation process of integrated circuit (IC) design by means of a special hardware device. Traditional software simulation is slow in processing large-scale design, while the hardware acceleration simulation system can complete the simulation task in a shorter time through the parallel computing capability of hardware, thereby shortening the design cycle of the chip. The specific structure of the hardware acceleration simulation system is not described here. The hardware acceleration simulation system comprises multiple synthesizable designs under test, but there is no corresponding synthesizable monitor, therefore, the corresponding synthesizable monitor is set for the synthesizable design under test in the embodiments of the present application, and the synthesizable monitor is used to collect simulation data corresponding to the synthesizable design under test in the hardware acceleration simulation system.

[0033] In step S2, the target design under test performs hardware acceleration simulation, the target monitor obtains each simulation data generated by the target design under test performing hardware acceleration simulation and a time stamp corresponding to each simulation data, and stores the simulation data and the time stamp in a target memory database corresponding to the target design under test in chronological order. Each synthesizable design under test in the hardware acceleration simulation system has a unique corresponding memory database. The target design under test is any one of at least one synthesizable design under test. The target monitor is a synthesizable monitor corresponding to the target design under test. The target memory database is a memory database corresponding to the target design under test. The simulation data corresponding to different synthesizable designs under test can be the same or different in number.

[0034] It should be noted that the size of the target memory database is set according to specific application requirements. The target memory database stores data in memory rather than in a traditional disk storage device. Based on the high-speed read and write characteristics of memory and the target memory database, the data processing speed can be improved and the data processing response time can be reduced.

[0035] In step S3, a target file database corresponding to the target design under test is generated based on the target memory database.

[0036] The format of the target file database can be selected, for example, comma-separated values (CSV), JavaScript Object Notation (JSON), Extensible Markup Language (XML), etc. CSV is suitable for simple table data and facilitates processing and import into other systems. JSON is suitable for structured and semi-structured data and supports nested structures. XML has good readability and extensibility and is commonly used for data exchange. The corresponding target file database format can be selected according to specific application requirements. After selecting the target file database format, a corresponding data connection library or tool can be used to establish a connection with the target memory database. Then, the required data can be extracted from the target memory database by executing a query statement or using a specific Application Programming Interface (API). The read data is then converted and processed according to the selected target file database format, such as converting the data to a suitable format and processing special characters in the data. Then, the processed data is written to a disk file using a file operation API. Finally, the written target file database is read to verify whether the data is completely and accurately migrated, and the corresponding target file database is obtained.

[0037] Step S4, isolating the target design under test in the chip verification simulation system and the target test platform corresponding to the target design under test in the chip verification simulation system, inputting the simulation data in the target file database into the target test platform according to the chronological order of the corresponding time stamps, and performing hardware accelerated simulation offline debugging based on the output result of the target test platform.

[0038] It should be noted that the chip verification simulation system is provided with a corresponding test platform for each design under test. The usual working process of the test platform is that the excitation generator (Generator) generates an input signal applied to the design under test (DUT) to simulate various input conditions that the chip may encounter in actual application. The monitor (Monitor) monitors the output signal of the DUT in real time, collects and transmits it to the scoreboard for analysis. The scoreboard (Scoreboard) compares the actual output of the DUT collected by the monitor with the expected output to determine whether the function of the DUT is correct. The embodiment of the present application directly reuses the target test platform corresponding to the target design under test which has been set in the chip verification simulation system, and uses the simulation data in the target file database as input to perform hardware accelerated simulation offline debugging. When reusing, the target design under test in the chip verification simulation system and the corresponding target test platform need to be isolated to avoid the data generated by the target design under test in the chip verification simulation system affecting the hardware accelerated simulation offline debugging process.

[0039] As an embodiment, the step S2 comprises:

[0040] Step S21, setting a corresponding DPI (Direct Programming interface) interface for the target memory database.

[0041] It should be noted that DPI is an interface mechanism between hardware description language (such as Verilog, SystemVerilog) and high-level programming language (such as C, C++). DPI allows calling functions and subprograms written in high-level programming language in the hardware simulation environment to achieve efficient implementation of complex algorithms in hardware design and verification. Since the target memory database is implemented based on high-level language, and the comprehensive monitor is implemented based on hardware description language, the data obtained by the monitor cannot be directly stored in the target memory database, and the corresponding DPI needs to be converted.

[0042] Step S22, the target monitor obtains each simulation data generated by the target design under test performing hardware accelerated simulation and the time stamp corresponding to each simulation data, and stores them in the target memory database in chronological order after converting them into the form of high-level language through the corresponding target DPI interface, wherein the target memory database is generated based on the high-level language.

[0043] As an embodiment, the high-level language is C++, and the target design under test and the target monitor are generated based on a SystemVerilog language.

[0044] As an embodiment, the step S3 comprises:

[0045] The step S31 sets a corresponding target API interface for the target in-memory database.

[0046] The step S32 establishes a connection between the target file database and the target in-memory database, obtains simulation data and corresponding time stamps from the target in-memory database through the corresponding target API interface, converts the simulation data and the corresponding time stamps into a file format corresponding to the target file database, and stores the converted simulation data and the corresponding time stamps into the target file database.

[0047] As an embodiment, the step S4 comprises:

[0048] The step S41 isolates the target design under test corresponding to the target design under test in the chip verification simulation system and the target test platform corresponding to the target design under test in the chip verification simulation system, and the target test platform no longer receives data generated by the target design under test in the chip verification simulation system.

[0049] It can be understood that, by isolating the target design under test corresponding to the target design under test in the chip verification simulation system and the target test platform corresponding to the target design under test in the chip verification simulation system, the hardware acceleration simulation offline debugging process can directly reuse the target test platform in the chip verification simulation system and is not affected by data generated by the target design under test in the chip verification simulation system.

[0050] The step S42 inputs simulation data in the target file database into a score board of the target test platform in a sequence of corresponding time stamps, and the score board of the target test platform compares the simulation data with corresponding reference data, and generates corresponding prompt information if the simulation data is inconsistent with the reference data.

[0051] The simulation data in the target file database are input into the score board of the target test platform in a sequence of corresponding time stamps until all data in the target file database are read out.

[0052] The step S42 can find out data that may cause problems in the hardware acceleration simulation process through the target test platform, and quickly and accurately complete the hardware acceleration simulation offline debugging process.

[0053] As an embodiment, the step S42 comprises:

[0054] Step S421, set a preset time interval.

[0055] The preset time interval can be set to 1 nanosecond, 1 millisecond or 1 microsecond, and can be set according to the specific hardware acceleration simulation offline debugging requirement. It should be noted that a coordinator can also be set, and no fixed preset time interval is set. The coordinator coordinates the simulation data input into the scoreboards of the target test platform according to the chronological order of the time stamps.

[0056] Step S422, input the simulation data in the target file database into the scoreboards of the target test platform according to the chronological order of the corresponding time stamps, at a preset time interval.

[0057] The embodiment of the application does not need to debug the hardware acceleration simulation system in an online manner, but first stores the simulation data and the corresponding time stamps in the hardware acceleration simulation system in the target memory database, then converts the target memory database into a target file database, and then reuses the target test platform in the chip verification simulation system, inputs the data in the target file database into the corresponding target test platform in sequence, performs offline debugging on the hardware acceleration simulation based on the results output by the corresponding target test platform, and improves the debugging efficiency of the hardware acceleration simulation.

[0058] It should be noted that some example embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps in a particular order, many of the steps can be performed concurrently, in parallel, or simultaneously. In addition, the order of the steps can be re-arranged. The processes can terminate when their operations are completed, but can also have additional steps not included in the figure. The processes can correspond to methods, functions, procedures, subroutines, subprograms, etc.

[0059] The embodiment of the application also provides an electronic device, comprising: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are arranged to execute the method of the embodiment of the application.

[0060] The embodiment of the application also provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used to execute the method of the embodiment of the application.

[0061] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, as long as it does not deviate from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A method of hardware-accelerated emulation offline debugging, the method comprising: The method comprises the following steps: setting a unique corresponding synthesizable monitor for each synthesizable design under test in a hardware acceleration simulation system, wherein the hardware acceleration simulation system comprises at least one synthesizable design under test; a target design under test performs hardware acceleration simulation, a target monitor acquires each simulation data generated by the target design under test performing hardware acceleration simulation and a time stamp corresponding to each simulation data, and stores the simulation data and the time stamp in a target memory database corresponding to the target design under test in chronological order, each synthesizable design under test in the hardware acceleration simulation system has a unique corresponding memory database, the target design under test is any one of the at least one synthesizable design under test, the target monitor is a corresponding synthesizable monitor of the target design under test, the target memory database is a memory database corresponding to the target design under test, and the simulation data corresponding to different synthesizable design under tests are the same or different in number; generating a target file database corresponding to the target design under test based on the target memory database; isolating a design under test corresponding to the target design under test in a chip verification simulation system and a target test platform corresponding to the design under test corresponding to the target design under test in the chip verification simulation system, inputting simulation data in the target file database into the target test platform in chronological order according to corresponding time stamps, and performing offline debugging of hardware acceleration simulation based on an output result of the target test platform.

2. The method of claim 1, wherein the target design under test performs hardware acceleration simulation, a target monitor acquires each simulation data generated by the target design under test performing hardware acceleration simulation and a time stamp corresponding to each simulation data, and stores the simulation data and the time stamp in a target memory database corresponding to the target design under test in chronological order, comprising: setting a corresponding target DPI interface for the target memory database; the target monitor acquires each simulation data generated by the target design under test performing hardware acceleration simulation and a time stamp corresponding to each simulation data, and stores the simulation data and the time stamp in the target memory database in chronological order after converting the simulation data and the time stamp into a form of a high-level language through the corresponding target DPI interface, wherein the target memory database is generated based on the high-level language.

3. The method of claim 2, wherein the high-level language is C++, and the target design under test and the target monitor are generated based on a SystemVerilog language.

4. The method of claim 1, wherein the target file database corresponding to the target design under test is generated based on the target memory database, comprising: setting a corresponding target API interface for the target memory database; establishing a connection between the target file database and the target memory database, acquiring simulation data and a corresponding time stamp from the target memory database through the corresponding target API interface, converting the simulation data and the time stamp into a file format corresponding to the target file database, and storing the converted simulation data and the time stamp in the target file database.

5. The method of claim 1, wherein The target test platform corresponding to the design under test corresponding to the target design under test in the chip verification simulation system is isolated, and simulation data in the target file database is input into the target test platform in the order of corresponding time stamps. The target test platform corresponding to the design under test corresponding to the target design under test in the chip verification simulation system is isolated, and simulation data in the target file database is input into the target test platform in the order of corresponding time stamps. The target test platform corresponding to the design under test corresponding to the target design under test in the chip verification simulation system is isolated, and simulation data in the target file database is input into the target test platform in the order of corresponding time stamps.

6. The method of claim 1, wherein the simulation data in the target file database is input into the score board of the target test platform in the order of corresponding time stamps, comprising: setting a preset time interval; inputting the simulation data in the target file database into the score board of the target test platform every preset time interval in the order of corresponding time stamps.

7. The method of claim 6, wherein the preset time interval is 1 nanosecond, 1 millisecond or 1 microsecond. comprising: at least one processor; 8. An electronic device, comprising: and a memory connected in communication with the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to perform the method of any one of the preceding claims 1-7. computer executable instructions for performing the method of any one of the preceding claims 1-7. ​ 9. A computer-readable storage medium, characterized in that, ​

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