Gate drive circuit, drive circuit, display panel, and display device

Abstract

The application discloses a gate driving circuit, a driving circuit, a display panel and a display device. The first control module comprises a first input unit and a second input unit. The first input unit is used for controlling the transmission of a first power signal to a first node. The second input unit is used for controlling the transmission of a second power signal to the first node. The first node can have stable first and second levels, so that the potential stability of the first node is improved. The second control module is used for controlling the potential of a second node. The output module can control the time-sharing electrical connection between the first and second power supply ends and a signal output end according to the signals of the first and second nodes, so that the output stability of the gate driving circuit is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driving circuit, a driving circuit, a display panel, and a display device. Background Technology

[0002] The gate control signal output by the gate drive circuit is affected by the stability of the potential of critical nodes in the gate drive circuit. Therefore, to improve the stability of the gate control signal output by the gate drive circuit, it is necessary to reduce unexpected fluctuations in the potential of critical nodes. Summary of the Invention

[0003] This application provides a gate driving circuit, a driving circuit, a display panel, and a display device to improve the potential stability of the first node in the gate driving circuit, thereby improving the output stability of the gate driving circuit.

[0004] To achieve the above objectives, this application provides a gate driving circuit, including a first control module, a second control module, and an output module. The first control module includes a first input unit and a second input unit. The first input unit is electrically connected to a first node and a first power supply terminal. The first input unit is configured to transmit a first power signal supplied by the first power supply terminal to the first node according to a received start signal, so that the signal of the first node has a first level. The second input unit is electrically connected to the first node and the second power supply terminal. The second input unit is configured to transmit a second power signal supplied by the second power supply terminal to the first node according to a first control signal, so that the signal of the first node has a second level. The second control module is electrically connected to the second node and is configured to control the potential of the second node. The output module is electrically connected to the first node and the second node and is configured to control the formation of a current path between the first power supply terminal and the second power supply terminal and the signal output terminal of the gate driving circuit in a time-division manner according to the signals of the first node and the second node. Wherein, the first power signal and the second power signal are DC signals, the first level is one of a high level and a low level, and the second level is the other of a high level and a low level.

[0005] This application also provides a driving circuit, including multiple gate driving circuits as described above and Z clock lines. The multiple gate driving circuits are cascaded, and the Z clock lines are electrically connected to the multi-stage gate driving circuits. The Z clock lines are configured to transmit Z sub-clock signals with sequential phase differences. The start signal corresponding to the ZK+Xth stage gate driving circuit is either a start signal or a gate control signal output by the ZK+XZ / 2th stage gate driving circuit. The ZK+Xth stage gate driving circuit is configured to use the Xth sub-clock signal as the corresponding clock signal to transmit the corresponding start signal to the second node of its own stage gate driving circuit based on the Xth sub-clock signal; ZK+XZ / 2≥1, K≥0, Z≥2, 1≤X≤Z.

[0006] This application embodiment also provides a display panel, including any of the above-described gate driving circuits or driving circuits.

[0007] This application embodiment also provides a display device, including any of the above-described display panels and a timing controller, the timing controller being electrically connected to a driving circuit, and the timing controller being configured to provide a start signal and Z sub-clock signals to the driving circuit.

[0008] The above technical solution includes a first input unit and a second input unit in the first control module of the gate drive circuit. The first input unit controls the transmission of a first power signal to the first node, and the second input unit controls the transmission of a second power signal to the first node. This allows the first node to have a stable first and second voltage levels, thereby improving the potential stability of the first node. Subsequently, the output module can control the first and second power terminals to be electrically connected to the signal output terminal in a time-division manner based on the signals from the first and second nodes, improving the output stability of the gate drive circuit. Furthermore, the first input unit of this application controls the first node's signal to have a first voltage level only through a start signal and a first power signal, and the second input unit controls the first node's signal to have a second voltage level only through a first control signal and a second power signal. Both the first and second power signals are DC signals. This reduces the number of control signals required to control the voltage state of the first node's signal and also reduces the number of units using clock signals in the gate drive circuit. This helps reduce the power consumption of the gate drive circuit and the impact of clock signal voltage changes on the first node's potential, thus improving the potential stability of the first node. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0010] Figures 1A-1B A schematic block diagram of the gate driving circuit provided in the embodiments of this application;

[0011] Figures 2A-2B A schematic diagram of the circuit structure of the gate driving circuit provided in an embodiment of this application;

[0012] Figure 3 A timing diagram of the gate drive circuit provided in an embodiment of this application;

[0013] Figures 4A-4B This is a schematic diagram of the drive circuit provided in an embodiment of this application;

[0014] Figures 5A-5B A timing diagram of the sub-clock signal corresponding to the driving circuit provided in the embodiments of this application;

[0015] Figure 6 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0016] Figure 7 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0017] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] Furthermore, descriptions involving "first," "second," etc., in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0020] Furthermore, the descriptions provided in the Background section should not be presumed to be prior art simply because they are mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter, and the description in this section does not limit the invention.

[0021] Specifically, such as Figures 1A-1B This is a schematic block diagram of a gate driving circuit provided in an embodiment of this application. This application provides a gate driving circuit GA, which includes a first control module 100, a second control module 200, and an output module 300.

[0022] The first control module 100 is electrically connected to the first node No1, the first power supply terminal VA, and the second power supply terminal VB. The first control module 100 is configured to transmit the first power signal supplied by the first power supply terminal VA and the second power signal supplied by the second power supply terminal VB to the first node No1 in a time-division manner according to the start signal STV and the first control signal, so that the first node No1 has a first level and a second level in a time-division manner.

[0023] Wherein, the first power supply terminal VA and the second power supply terminal VB can be voltage terminals. The voltage value corresponding to the first power signal supplied by the first power supply terminal VA can be different from the voltage value corresponding to the second power signal supplied by the second power supply terminal VB. Optionally, the first power supply terminal VA and the second power supply terminal VB can be constant voltage terminals. That is, the first power signal and the second power signal are DC signals, so that when the first power signal and the second power signal are applied to the first node No1 in a time-division manner, the first node No1 can have a stable first level and second level, thereby improving the potential stability of the first node No1 and improving the output stability of the gate drive circuit.

[0024] Optionally, the first power supply terminal VA is one of the high-voltage terminal and the low-voltage terminal, and the second power supply terminal VB is the other of the high-voltage terminal and the low-voltage terminal. The voltage value of the power signal supplied by the high-voltage terminal is greater than the voltage value of the power signal supplied by the low-voltage terminal.

[0025] For ease of understanding this application, Figures 1A-1B This example uses the first power supply terminal VA as the high-voltage terminal VGH and the second power supply terminal VB as the low-voltage terminal VGL. However, it should be understood that in some embodiments, the first power supply terminal VA can be the low-voltage terminal and the second power supply terminal VB can be the high-voltage terminal.

[0026] Optionally, the first voltage level is either a high voltage level or a low voltage level, and the second voltage level is either a high voltage level or a low voltage level. The voltage value corresponding to the first voltage level may be different from the voltage value corresponding to the second voltage level.

[0027] For ease of understanding this application, the corresponding Figures 1A-1B This example uses a first level as high and a second level as low. However, it should be understood that in some embodiments, the first level can be low and the second level can be high.

[0028] It should be noted that the electrical connection referred to in this application can include both direct and indirect connections. Indirect connections can include connections between connected modules, devices, and nodes achieved through electrical components, wired or wireless media, etc. An electrical connection can refer to a physically existing connection or a connection established through signals.

[0029] Please continue reading. Figures 1A-1B The first control module 100 may include a first input unit 101 and a second input unit 102.

[0030] The first input unit 101 is electrically connected to the first node No1 and the first power supply terminal VA. The first input unit 101 is configured to transmit the first power signal supplied by the first power supply terminal VA to the first node No1 according to the received start signal STV, so that the signal of the first node No1 has a first level.

[0031] The second input unit 102 is electrically connected to the first node No1 and the second power supply terminal VB. The second input unit 102 is configured to transmit the second power supply signal supplied by the second power supply terminal VB to the first node No1 according to the first control signal, so that the signal of the first node No1 has a second level.

[0032] By including a first input unit 101 and a second input unit 102 in the first control module 100, the on / off state of the current path between the first node No1 and the first power supply terminal VA and the second power supply terminal VB can be made independent of each other, thereby reducing the risk that the first power supply signal and the second power supply signal are simultaneously applied to the first node No1.

[0033] In some embodiments, the switching of the current path between the first power supply terminal VA and the first node No1 is achieved through the coordination of the clock signal XCK and the start signal STV. On the one hand, this increases the number of signals controlling the potential of the first node No1, thus increasing the difficulty of controlling the potential of the first node No1; on the other hand, it also increases the power consumption of the gate drive circuit GA. However, in this application... Figures 1A-1B In the gate drive circuit GA shown, the signal received by the first input unit 101 does not include the clock signal XCK. The first input unit 101 of this application can control the on / off state of the current path between the first power supply terminal VA and the first node No1 solely based on the start signal STV, without requiring the coordination of the clock signal XCK and the start signal STV. This reduces the number of control signals required to control the on / off state of the current path between the first power supply terminal VA and the first node No1, thus reducing the difficulty of controlling the potential of the first node No1. It also reduces the number of units in the gate drive circuit GA that use the clock signal XCK, thereby reducing the power consumption of the gate drive circuit GA. Furthermore, since the on / off state of the current path between the first power supply terminal VA and the first node No1 is no longer achieved through the coordination of the clock signal XCK and the start signal STV, and the first power supply signal in this application is a DC signal, the influence of the clock signal XCK level change on the potential of the first node No1 is reduced, which helps improve the potential stability of the first node No1.

[0034] In some embodiments, to ensure that the on / off control of the current path between the first power supply terminal VA and the first node No1 is no longer achieved through the coordination of the clock signal XCK and the start signal STV, the signal received by the first input unit 101 of this application does not include the signal of the second node No2. In some embodiments, to ensure that the on / off control of the current path between the first power supply terminal VA and the first node No1 is no longer achieved through the coordination of the clock signal XCK and the start signal STV, the signal received by the first input unit 101 of this application does not include the signal of the fourth node No4, so that the potential of the first node No1 is less affected by the level change of the clock signal XCK, which is beneficial to improving the potential stability of the first node No1.

[0035] In some embodiments, the second input unit 102 is configured to transmit a clock signal XCK to the first node No1 according to a first control signal, so that the signal of the first node No1 has a second level. Since the clock signal XCK is a periodic signal, the clock signal XCK provided to the first node No1 via the second input unit 102 has level transitions, causing the potential of the first node No1 to fluctuate. In this application... Figures 1A-1BIn the gate drive circuit GA shown, by controlling the electrical connection between the second power supply terminal VB and the signal output terminal Gout through the second input unit 102, and since the second power supply signal is a DC signal, the potential fluctuation of the first node No1 can be reduced, and the potential stability of the first node No1 can be improved. Furthermore, the signal received by the second input unit 102 in this application does not include the clock signal XCK. The second input unit 102 obtains the signal of the first node No1 as the second level only through the first control signal and the second power supply signal, reducing the number of units in the gate drive circuit GA that apply the clock signal XCK, which helps to reduce the power consumption of the gate drive circuit GA.

[0036] Please continue reading. Figures 1A-1B The second control module 200 is electrically connected to the second node No2, and the second control module 200 is configured to control the potential of the second node No2.

[0037] The output module 300 is electrically connected to the first node No1 and the second node No2. The output module 300 is configured to control the first power supply terminal VA and the second power supply terminal VB to form a current path with the signal output terminal Gout of the gate drive circuit GA in a time-division manner according to the signal of the first node No1 and the signal of the second node No2, so that the gate control signal Scan output by the gate drive circuit GA from the signal output terminal Gout has a change between an effective level and an ineffective level.

[0038] Optionally, to achieve independent control of the electrical connection between the signal output terminal Gout and the first power supply terminal VA and the second power supply terminal VB, the output module 300 may include a first output unit 301 and a second output unit 302. The first output unit 301 is electrically connected to the first node No1 and the first power supply terminal VA, and is configured to control the duration for which the signal output terminal Gout receives the first power signal according to the signal from the first node No1. The second output unit 302 is electrically connected to the second node No2 and the second power supply terminal VB, and is configured to control the duration for which the signal output terminal Gout receives the second power signal according to the signal from the second node No2.

[0039] Optionally, the first output unit 301 is configured to disconnect the electrical connection between the signal output terminal Gout and the first power supply terminal VA according to a first level of the signal of the first node No1, thereby disconnecting the current path between the first power supply terminal VA and the signal output terminal Gout. The first output unit 301 is also configured to connect the electrical connection between the signal output terminal Gout and the first power supply terminal VA according to a second level of the signal of the first node No1, thereby connecting the current path between the first power supply terminal VA and the signal output terminal Gout.

[0040] Optionally, the second output unit 302 is configured to connect or disconnect the electrical connection between the signal output terminal Gout and the second power supply terminal VB according to the signal of the second node No2, so as to control the duration for which the signal output terminal Gout receives the second power supply signal.

[0041] The effective level of a signal can refer to the level that enables or turns on the device controlled by the signal, while the ineffective level of a signal can refer to the level that turns off or turns off the device controlled by the signal. Optionally, the effective level of a signal can be either a high level or a low level, and the ineffective level of a signal can be either a high level or a low level.

[0042] The gate drive circuit GA of this application includes a first input unit 101 and a second input unit 102 in the first control module 100. The first input unit 101 controls the transmission of a first power signal to the first node No1, and the second input unit 102 controls the transmission of a second power signal to the first node No1. This allows the first node No1 to have a stable first and second level, thereby improving the potential stability of the first node No1. This also allows the output module 300 to control the first power terminal VA and the second power terminal VB to be electrically connected to the signal output terminal Gout in a time-division manner according to the signals from the first node No1 and the second node No2, thereby improving the output stability of the gate drive circuit.

[0043] Alternatively, to reduce the number of control signals used by the gate drive circuit GA, the first control signal can be multiplexed from the signals of the internal nodes of the gate drive circuit GA. Please refer to [further details omitted]. Figures 1A-1B The gate drive circuit GA may also include a third control module 400.

[0044] The third control module 400 is electrically connected to the third node No3. The third control module 400 is configured to control the potential of the third node No3 according to the start signal STV and the clock signal XCK. The third control module 400 is electrically connected to the first control module 100 through the third node No3. The first control signal is the signal of the third node No3, which is used to control the second input unit 102 to control the on / off current path between the first node No1 and the second power supply terminal VB.

[0045] It should be understood that the first control signal may also be set independently without reusing the signal of the internal node of the gate drive circuit GA.

[0046] Optionally, the third control module 400 includes a third input unit 401 and a coupling unit 402, such as... Figures 1A-1B As shown.

[0047] The third input unit 401 is electrically connected to the third node No3 and the first power supply terminal VA. The third input unit 401 is configured to transmit the first power supply signal to the third node No3 according to the effective level of the start signal STV, so that the signal of the third node No3 has a third level.

[0048] The coupling unit 402 is electrically connected to the third node No3. The coupling unit 402 is configured to couple the potential of the third node No3 according to the level change of the clock signal XCK during the period when the start signal STV is invalid, so that the signal of the third node No3 has a fourth level.

[0049] The third level is either a high level or a low level, and the fourth level is either a high level or a low level.

[0050] By including a third input unit 401 and a coupling unit 402 in the third control module 400, level control of the signal of the third node No3 can be achieved.

[0051] Optionally, to further reduce the risk of the first power signal and the second power signal being simultaneously applied to the first node No1, the first input unit 101 is configured to connect the current path between the first power terminal VA and the first node No1 according to the effective level of the start signal STV; the second input unit 102 is configured to connect the current path between the second power terminal VB and the first node No1 according to the fourth level of the signal of the third node No3, so that during the period when the first input unit 101 connects the first power terminal VA and the first node No1 according to the start signal STV, the third input unit 401 can connect the current path between the first power terminal VA and the third node No3 according to the start signal STV, thereby making the signal of the third node No3 have a third level, so that the second input unit 102 disconnects the current path between the second power terminal VB and the first node No1.

[0052] Please continue reading. Figures 1A-1B To further reduce the number of control signals used by the gate drive circuit GA and the power consumption of the gate drive circuit GA, the second control module 200 is configured to transmit the start signal STV to the first node No1 according to the clock signal XCK, so as to control the potential of the first node No1.

[0053] Optionally, during the period when the signal of the first node No1 is at a first level, the second control module 200 is configured to transmit a start signal STV with an effective level to the second node No2 according to the clock signal XCK, so that the output module 300 connects the electrical connection between the corresponding power supply terminal and the signal output terminal Gout according to the signal of the second node No2, thereby allowing the corresponding power signal to be transmitted to the signal output terminal Gout. During the period when the signal of the third node No3 is at a fourth level, the second control module 200 is configured to transmit a start signal STV with an invalid level to the second node No2 according to the clock signal XCK, so that the output module 300 disconnects the electrical connection between the corresponding power supply terminal and the signal output terminal Gout according to the signal of the second node No2, thereby stopping the transmission of the corresponding power signal to the signal output terminal Gout.

[0054] Because the periodic fluctuations of the clock signal XCK are coupled to the second node No2 via parasitic capacitance, causing potential fluctuations at the second node No2, this affects the output stability of the gate drive circuit GA. Therefore, to further improve the potential stability of the second node No2 and thus the output stability of the gate drive circuit GA, the gate drive circuit GA may also include a shielding module 500, such as... Figures 1A-1B As shown.

[0055] The shielding module 500 is electrically connected between the second node No2 and the fourth node No4, and is electrically connected to the second control module 200 through the fourth node No4. The shielding module 500 is configured to shield the coupling effect of the clock signal XCK received by at least one of the second control module 200 and the third control module 400 on the potential of the second node No2.

[0056] Optionally, to enable the first power signal and the second power signal to be transmitted to the first node No1 in a time-division manner, the signals of the first node No1 and the second node No2 need to be out of phase for at least a portion of the time to reduce the risk that the signal output terminal Gout simultaneously receives the first power signal and the second power signal. Therefore, when the first node No1 controls the output module 300 to electrically connect the first power terminal VA and the signal output terminal Gout, the potential of the second node No2 needs to be switched in a timely manner to the state that disconnects the second power terminal VB from the signal output terminal Gout. Therefore, to accelerate the potential switching speed of the second node No2 and further improve the output stability of the gate drive circuit GA, the gate drive circuit GA also includes a voltage regulator module 600, such as... Figure 1B As shown.

[0057] The voltage regulator module 600 is electrically connected to the second node No2, the third node No3 and the first power supply terminal VA. The voltage regulator module 600 is configured to transmit the first power supply signal to the second node No2 according to the signal of the third node No3 during the period when the signal of the first node No1 is at the second level.

[0058] Optionally, the voltage regulator module 600 is electrically connected to the second node No2 via the fourth node No4.

[0059] Optionally, the voltage regulator module 600 is configured to connect the electrical connection between the first power supply terminal VA and the second node No2 according to the fourth level of the signal of the third node No3, thereby connecting the current flow path between the first power supply terminal VA and the second node No2, and thus transmitting the first power signal to the second node No2. The voltage regulator module 600 is also configured to disconnect the electrical connection between the first power supply terminal VA and the second node No2 according to the third level of the signal of the third node No3, thereby disconnecting the current flow path between the first power supply terminal VA and the second node No2.

[0060] Furthermore, since the first power signal is a DC signal, when the signal of the first node No1 is at the second level, the first power signal is transmitted to the second node No2 according to the signal of the third node No3, which can stabilize the signal of the second node No2 at the voltage value corresponding to the first power signal, thereby using the first power signal to stabilize the potential of the second node No2.

[0061] It should be understood that by multiplexing the signal of the third node No3 to simultaneously control the second input unit 102 and the voltage regulator module 600, the second power signal can be transmitted to the first node No1 at the same time as the first power signal is transmitted to the second node No2. This reduces the risk that the first power signal and the second power signal are transmitted to the signal output terminal Gout at the same time, which is beneficial to further improve the output stability of the gate drive circuit GA and reduce the number of control signals used by the gate drive circuit GA. This reduces the control complexity of the gate drive circuit GA and the power consumption of the gate drive circuit GA.

[0062] Figures 2A-2B This is a schematic diagram of the gate drive circuit provided in an embodiment of this application. To facilitate understanding of the design of the gate drive circuit in this application, [the following is a simplified diagram]. Figures 2A-2B The gate drive circuit GA shown is illustrated as an example. In this example, the gate drive circuit GA is... Figures 2A-2B The following explanation uses the first power supply terminal VA as the high-voltage terminal VGH and the second power supply terminal VB as the low-voltage terminal VGL as an example.

[0063] The first input unit 101 of the first control module 100 may include a first transistor T1. The control terminal of the first transistor T1 is configured to receive a start signal STV. The first source-drain terminal of the first transistor T1 is electrically connected to the first power supply terminal VA, and the second source-drain terminal of the first transistor T1 is electrically connected to the first node No1. The start signal STV controls the conduction and cutoff of the first transistor T1, thereby realizing the on / off control of the current path between the first power supply terminal VA and the first node No1.

[0064] The second input unit 102 of the first control module 100 may include a second transistor T2. The control terminal of the second transistor T2 is configured to receive a first control signal. The first source-drain terminal of the second transistor T2 is electrically connected to the second power supply terminal VB, and the second source-drain terminal of the second transistor T2 is electrically connected to the first node No1. By controlling the conduction and cutoff of the second transistor T2 through the first control signal, the on / off control of the current path between the second power supply terminal VB and the first node No1 is achieved.

[0065] Optionally, the gate drive circuit GA further includes a third control module 400. The third input unit 401 of the third control module 400 may include a third transistor T3. The control terminal of the third transistor T3 is configured to receive a start signal STV. The first source-drain terminal of the third transistor T3 is electrically connected to the first power supply terminal VA, and the second source-drain terminal of the third transistor T3 is electrically connected to the third node No3. By controlling the conduction and cutoff of the third transistor T3 through the start signal STV, the current path between the first power supply terminal VA and the third node No3 can be controlled.

[0066] The coupling unit 402 of the third control module 400 includes a first capacitor C1, which is electrically connected between the third node No3 and the clock line of the clock signal XCK, so as to couple the level change of the clock signal XCK to the third node No3 through the first capacitor C1, so that the level of the third node No3 is the fourth level.

[0067] In some implementations, the control terminal of the second transistor T2 is electrically connected to the third node No3 so that the second transistor T2 is turned on and off by the signal of the third node No3, thereby realizing the on and off control of the current path between the second power supply terminal VB and the first node No1. This helps to reduce the number of control signals used by the gate drive circuit GA, and also reduces the risk that the first power supply signal and the second power supply signal are simultaneously applied to the first node No1.

[0068] Please continue reading. Figures 2A-2BThe second control module 200 may include a fourth transistor T4. The control terminal of the fourth transistor T4 is configured to receive a clock signal XCK. The first source-drain terminal of the fourth transistor T4 is configured to receive a start signal STV. The second source-drain terminal of the fourth transistor T4 is electrically connected to the second node No2 so as to control the conduction and cutoff of the fourth transistor T4 through the clock signal XCK, thereby controlling the application of the start signal STV to the second node No2 through the fourth transistor T4.

[0069] Optionally, the gate drive circuit GA may further include a shielding module 500. The shielding module 500 may include a shielding transistor Tsd. The control terminal of the shielding transistor Tsd is electrically connected to the third power supply terminal VC. The first source-drain terminal of the shielding transistor Tsd is electrically connected to the second node No2. The second source-drain terminal of the shielding transistor Tsd is electrically connected to the fourth node No4. This allows the shielding transistor Tsd to be turned on and off by the third power supply signal supplied by the third power supply terminal VC. In turn, the shielding transistor Tsd can shield the effect of the level fluctuation of the clock signal XCK on the potential of the second node No2.

[0070] In some embodiments, the shielding transistor Tsd can remain in the on state to continuously shield the effect of the level change of the clock signal XCK on the potential of the second node No2.

[0071] It should be understood that when the third power supply terminal VC is a high-voltage terminal, the shielding transistor Tsd is an N-type transistor. When the third power supply terminal VC is a low-voltage terminal, the shielding transistor Tsd is a P-type transistor.

[0072] In some embodiments, to reduce the number of signals connected to the gate drive circuit GA, the first power supply terminal VA or the second power supply terminal VB can be multiplexed into the third power supply terminal VC.

[0073] Optionally, the second source-drain terminal of the fourth transistor T4 is electrically connected to the second node No2 through the fourth node No4.

[0074] In some embodiments, the control terminal of the fourth transistor T4 includes a first control terminal and a second control terminal, which are configured to receive a clock signal XCK to reduce the leakage current of the fourth node No4 during the period when the first node No1 is at the second level, thereby maintaining the stability of the potential of the fourth node No4.

[0075] Optionally, the gate drive circuit GA may further include a voltage regulator module 600. The voltage regulator module 600 includes a switching transistor Ts. The control terminal of the switching transistor Ts is electrically connected to the third node No3, the first source-drain terminal of the switching transistor Ts is electrically connected to the first power supply terminal VA, and the second source-drain terminal of the switching transistor Ts is electrically connected to the second node No2. The switching transistor Ts is turned on and off by the signal from the third node No3, thereby connecting or disconnecting the current flow path between the second node No2 and the first power supply terminal VA through the switching transistor Ts.

[0076] Optionally, the second source-drain terminal of the switching transistor Ts is electrically connected to the second node No2 through the fourth node No4, so as to reduce the influence of the clock signal XCK received by the third control module 400 on the potential of the second node No2 through the shielding module 500.

[0077] Please continue reading. Figures 2A-2B The first output unit 301 of the output module 300 includes a first output transistor To1. The control terminal of the first output transistor To1 is electrically connected to the first node No1, the first source-drain terminal of the first output transistor To1 is electrically connected to the first power supply terminal VA, and the second source-drain terminal of the first output transistor To1 is electrically connected to the signal output terminal Gout. This allows the operating state of the first output transistor To1 to be controlled by the signal from the first node No1, thereby controlling the electrical connection between the first power supply terminal VA and the signal output terminal Gout.

[0078] Optionally, during the period when the first input unit 101 transmits the first power signal to the first node No1, the first output transistor To1 is turned off to disconnect the electrical connection between the first power supply terminal VA and the signal output terminal Gout. During the period when the second input unit 102 transmits the second power signal to the first node No1, the first output transistor To1 is turned on to connect the electrical connection between the first power supply terminal VA and the signal output terminal Gout, so that the first power signal is transmitted to the signal output terminal Gout.

[0079] In some embodiments, because the second input unit 102 controls the electrical connection between the second power supply terminal VB and the first node No1 based on the signal of the third node No3, the level fluctuation of the clock signal XCK corresponding to the third control module 400 is coupled to the first node No1 through parasitic capacitance, causing the potential of the first node No1 to fluctuate due to the influence of the clock signal XCK. Therefore, to further improve the potential stability of the first node No1, the first output unit 301 can include a second capacitor C2. The second capacitor C2 is electrically connected between the first power supply terminal VA and the first node No1, so as to maintain the potential of the first node No1 and improve the potential stability of the second node No2.

[0080] Please continue reading. Figures 2A-2B The second output unit 302 of the output module 300 may include a second output transistor To2. The control terminal of the second output transistor To2 is electrically connected to the second node No2. The first source-drain terminal of the second output transistor To2 is electrically connected to the second power supply terminal VB. The second source-drain terminal of the second output transistor To2 is electrically connected to the signal output terminal Gout, so as to control the working state of the second output transistor To2 using the signal of the second node No2, thereby controlling the electrical connection between the second power supply terminal VB and the signal output terminal Gout.

[0081] Optionally, the second output unit 302 may include a third capacitor C3, which is electrically connected between the second node No2 and the signal output terminal Gout, so as to improve the stability of the potential of the second node No2.

[0082] It should be noted that the aforementioned control terminal can be the gate of a transistor, the first source-drain terminal can be one of the source and drain terminals of the transistor, and the second source-drain terminal can be the other of the source and drain terminals of the transistor. Each transistor in the gate drive circuit GA can employ a single-gate or dual-gate design.

[0083] It should be noted that at least one of the following components included in the gate drive circuit GA: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the switching transistor Ts, the shielding transistor Tsd, the first output transistor To1, and the second output transistor To2 can be an N-type transistor or a P-type transistor. The active layer of each transistor in the gate drive circuit GA can include silicon semiconductor material or oxide semiconductor material. The silicon semiconductor material includes monocrystalline silicon, polycrystalline silicon, or amorphous silicon, etc. The oxide semiconductor material includes indium gallium zinc oxide or indium zinc oxide, etc.

[0084] according to Figures 2A-2B As shown in the diagram, the gate driving circuit GA of this application may include 7 or 8 transistors. The smaller number of transistors in the gate driving circuit GA helps to reduce the layout space occupied by it. When the gate driving circuit GA is used in a display panel, it facilitates the implementation of a narrow bezel design.

[0085] It should be understood that, Figures 2A-2B This is merely an illustrative diagram and is not limited to the gate drive circuit GA used in this application. Figures 2A-2BBased on the disclosure of this application, those skilled in the art can still modify the design of each module of the gate drive circuit GA. The modules and units in the gate drive circuit GA can also be implemented in simpler or more complex forms using a greater number of components. These components include, but are not limited to, transistors, capacitors, and other devices.

[0086] Figure 3 The timing diagram corresponds to the gate drive circuit (GA) provided in the embodiments of this application. Figure 3 In this context, Nos1 represents the signal of the first node No1, abbreviated as the first node signal; Nos2 represents the signal of the second node No2, abbreviated as the second node signal; Nos3 represents the signal of the third node No3, abbreviated as the third node signal; and Nos4 represents the signal of the fourth node No4, abbreviated as the fourth node signal. (Combined...) Figures 2A-2B The gate drive circuit GA design shown is illustrated, with the first power supply terminal VA being the high-voltage terminal VGH, the second power supply terminal VB and the third power supply terminal VC being the low-voltage terminals VGL, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the switching transistor Ts, the shielding transistor Tsd, the first output transistor To1 and the second output transistor To2 being P-type transistors. The working principle of the gate drive circuit GA is explained using this example.

[0087] In the first time period t1, the start signal STV and the clock signal XCK are at a low level. Figures 2A-2B In the gate drive circuit GA shown, the first transistor T1, the third transistor T3, the fourth transistor T4, the shielding transistor Tsd, and the second output transistor To2 are turned on. A first power supply signal is transmitted to the first node No1 and the third node No3, causing the signal at the first node No1 to have a high level, and the signal at the third node No3 to have a high level. That is, the first node signal Nos1 is at the first level, and the third node signal Nos3 is at the third level. The second transistor T2 and the first output transistor To1 are turned off. Figure 2B In the gate drive circuit GA shown, the switching transistor Ts is turned off. Figures 2A-2B The gate control signal Scan output from the gate drive circuit GA at the signal output terminal Gout is low.

[0088] During the second time period t2, the start signal STV and the clock signal XCK are at a high level. Figures 2A-2B In the gate drive circuit GA shown, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the first output transistor To1 are cut off, while the shielding transistor Tsd and the second output transistor To2 are turned on. The first node signal Nos1 and the third node signal Nos3 maintain the state of the first time period. Figure 2BIn the gate drive circuit GA shown, the switching transistor Ts is turned off. Figures 2A-2B The gate control signal Scan output by the gate drive circuit GA shown is at a low level.

[0089] In the third time period t3: the start signal STV is high and the clock signal XCK is low. Figures 2A-2B In the gate drive circuit GA shown, the first transistor T1, the third transistor T3, and the second output transistor To2 are off, while the shielding transistor Tsd, the second transistor T2, the fourth transistor T4, and the first output transistor To1 are on. The signal at the first node No1 is low, and the signal at the third node No3 is low. That is, the first node signal Nos1 is at the second level, and the third node signal No3 is at the fourth level. Figure 2B In the gate drive circuit GA shown, the switching transistor Ts is turned on. Figures 2A-2B The gate control signal Scan output by the gate drive circuit GA shown is at a high level.

[0090] In the fourth time period t4: the start signal STV is low and the clock signal XCK is high. Figures 2A-2B In the gate drive circuit GA shown, the first transistor T1, the third transistor T3, and the shielding transistor Tsd are turned on, while the second transistor T2, the fourth transistor T4, the first output transistor To1, and the second output transistor To2 are turned off. The signal at the first node No1 is high, and the signal at the third node No3 is high. That is, the signal at the first node No1 is the first level, and the signal at the third node No3 is the third level. Figure 2B In the gate drive circuit GA shown, the switching transistor Ts is turned off. Figures 2A-2B The gate control signal Scan output by the gate drive circuit GA shown is at a high level.

[0091] In the fifth time period t5: the start signal STV and the clock signal XCK are at a low level. Figures 2A-2B In the gate drive circuit GA shown, the first transistor T1, the third transistor T3, the fourth transistor T4, the shielding transistor Tsd, and the second output transistor To2 are turned on, while the second transistor T2 and the first output transistor To1 are turned off. Figure 2B In the gate drive circuit GA shown, the switching transistor Ts is turned off. Figures 2A-2B The gate control signal Scan output from the gate drive circuit GA at the signal output terminal Gout is low.

[0092] Based on the working principle of the gate drive circuit GA, the gate drive circuit GA of this application can control the first power signal and the second power signal to be transmitted to the first node No1 in a time-division manner through the first control module 100, so that the signal of the first node No1 has a first level and a second level respectively, which is beneficial to improving the potential stability of the first node No1. Furthermore, in the process of controlling the first node No1 to the first level, the first power signal is transmitted to the first node No1 only through the first transistor T1, simplifying the control logic for the first level of the signal of the first node No1. Moreover, the moment when the signal of the first node No1 switches from the second level to the first level can be earlier than the moment when the signal of the second node No2 switches, so that the first output transistor To1 and the second output transistor To2 can have a period of simultaneous cutoff. Consequently, when the first output transistor To1 switches from the on state to the off state, the second output transistor To2 no longer switches from the off state to the on state synchronously, which is beneficial to improving the output stability of the gate drive circuit GA.

[0093] Furthermore, in this application, the switching transistor Ts and the second transistor T2 are simultaneously controlled by the signal of the third node No3, which can reduce the number of control signals applied by the gate drive circuit GA and lower the power consumption of the gate drive circuit GA. When the fourth transistor T4 has a first control terminal and a second control terminal, the leakage current of the second node No2 can be reduced, and the potential stability of the second node No2 can be improved.

[0094] It should be understood that those skilled in the art can adjust the types of transistors included in the gate drive circuit GA, and the settings of the first power supply terminal VA, the second power supply terminal VB, and the third power supply terminal VC according to actual needs, so that the output of the gate drive circuit GA is consistent with... Figure 3 The gate control signal Scan shown is an inverted signal that is permitted and included in this application. The type of transistor includes, but is not limited to, N-type or P-type transistors, silicon or oxide transistors, single-gate or dual-gate transistors, and other types.

[0095] Figures 4A-4B This is a schematic diagram of the driving circuit provided in an embodiment of this application. This application also provides a driving circuit GDC, which includes multiple gate driving circuits GA as described above. The multiple gate driving circuits GA are cascaded.

[0096] It should be noted that the gate control signal Scan output by the gate drive circuit GA can be referred to as the scan signal or the transmit control signal, etc.

[0097] Optionally, the multiple gate control signals Scan output by the multiple gate drive circuits GA have valid pulses in sequence.

[0098] Optionally, in order to ensure that the multiple gate control signals Scan output by the multiple gate drive circuits GA have valid pulses in sequence, and in order to reduce the power consumption of the drive circuit GDC, the multi-level gate drive circuits GA can share the sub-clock signals transmitted by multiple clock lines as the corresponding clock signal XCK.

[0099] Accordingly, the driving circuit GDC may include Z clock lines CL, which are electrically connected to the multi-stage gate driving circuit GA. The Z clock lines CL are configured to transmit Z sub-clock signals with sequential phase differences. The start signal STV corresponding to the ZK+Xth stage gate driving circuit GA (ZK+X) is either the start signal stv or the ZK+XZ / 2th stage gate control signal Scan (ZK+XZ / 2) output by the ZK+XZ / 2th stage gate driving circuit GA (ZK+XZ / 2). The ZK+Xth stage gate driving circuit GA (ZK+X) is configured to use the Xth sub-clock signal as the corresponding clock signal to transmit the corresponding start signal STV to the second node No2 of the current stage gate driving circuit GA according to the Xth sub-clock signal; ZK+XZ / 2≥1, K≥0, Z≥2, 1≤X≤Z.

[0100] In some embodiments, the start signal STV corresponding to the first Z / 2 stage gate drive circuit in the multi-stage gate drive circuit GA is the start signal stv, and the start signal STV corresponding to the gate drive circuit cascaded after the Z / 2 stage gate drive circuit is the gate control signal Scan output by the corresponding previous stage gate drive circuit, so as to use the start signal stv to control the multi-stage gate drive circuit GA in the drive circuit GDC to start sequentially and output the corresponding gate control signal Scan.

[0101] Figures 5A-5B The timing diagram shows the sub-clock signal corresponding to the driving circuit provided in the embodiments of this application. Please continue reading. Figure 4A and Figure 5A Taking Z=2 as an example, the cascading configuration of the multi-stage gate drive circuit GA and the pairing relationship of the clock signal XCK are explained. The start signal STV corresponding to the 2K+X stage gate drive circuit GA(2K+X) is either the start signal stv or the 2K+X-1 stage gate control signal Scan(2K+X-1) output by the 2K+X-1 stage gate drive circuit GA(2K+X-1). The 2K+X stage gate drive circuit GA(2K+X) is configured to receive the Xth sub-clock signal, that is, the clock signal XCK corresponding to the 2K+X stage gate drive circuit GA(2K+X) is the Xth sub-clock signal.

[0102] When Z=2, the Z clock traces CL include the first clock trace CL1 and the second clock trace CL2. The first clock trace CL1 transmits the first sub-clock signal CK1, and the second clock trace CL2 transmits the second sub-clock signal CK2. The phase of the first sub-clock signal CK1 leads the phase of the second sub-clock signal CK2. When K=0 and X=1, the start signal STV corresponding to the first-stage gate drive circuit GA(1) is the start signal stv, and the clock signal XCK corresponding to the first-stage gate drive circuit GA(1) is the first sub-clock signal CK1. When K=0 and X=2, the start signal STV corresponding to the second-stage gate drive circuit GA(2) is the first-stage gate control signal Scan(1) output by the first-stage gate drive circuit GA(1), and the clock signal XCK corresponding to the second-stage gate drive circuit GA(2) is the second sub-clock signal CK2. When K=1 and X=1, the start signal STV corresponding to the third-stage gate drive circuit GA(3) is the second-stage gate control signal Scan(2) output by the second-stage gate drive circuit GA(2), and the clock signal XCK corresponding to the third-stage gate drive circuit GA(3) is the first sub-clock signal CK1. When K=1 and X=2, the start signal STV corresponding to the fourth-stage gate drive circuit GA(4) is the third-stage gate control signal Scan(3) output by the third-stage gate drive circuit GA(3), and the clock signal XCK corresponding to the third-stage gate drive circuit GA(3) is the second sub-clock signal CK2. Similarly, the start signals STV and clock signals XCK corresponding to the other gate drive circuits GA can be obtained.

[0103] For similar examples, please continue reading. Figure 4B and Figure 5B Taking Z=4 as an example, the cascading configuration of multi-stage gate drive circuits GA and the relationship between the clock signal XCK are explained. The start signal STV corresponding to the 4K+X stage gate drive circuit GA(4K+X) is either the start signal stv or the 4K+X-2 stage gate control signal Scan(4K+X-2) output by the 4K+X-2 stage gate drive circuit GA(4K+X-2). The 4K+X stage gate drive circuit GA(4K+X) is configured to receive the Xth sub-clock signal, that is, the clock signal XCK corresponding to the 4K+X stage gate drive circuit GA(4K+X) is the Xth sub-clock signal.

[0104] When Z=4, the Z clock traces CL include the first clock trace CL1, the second clock trace CL2, the third clock trace CL3, and the fourth clock trace CL4. The first clock trace CL1 transmits the first sub-clock signal CK1, the second clock trace CL2 transmits the second sub-clock signal CK2, the third clock trace CL3 transmits the third sub-clock signal CK3, and the fourth clock trace CL4 transmits the fourth sub-clock signal CK4. The phase of the first sub-clock signal CK1 leads the phase of the second sub-clock signal CK2, the phase of the second sub-clock signal CK2 leads the phase of the third sub-clock signal CK3, and the phase of the third sub-clock signal CK3 leads the phase of the fourth sub-clock signal CK4. When K=0 and X=1, the start signal STV corresponding to the first-stage gate drive circuit GA(1) is the start signal stv, and the clock signal XCK corresponding to the first-stage gate drive circuit GA(1) is the first sub-clock signal CK1. When K=0 and X=2, the start signal STV corresponding to the second-stage gate drive circuit GA(2) is the start signal, and the clock signal XCK corresponding to the second-stage gate drive circuit GA(2) is the second sub-clock signal CK2. When K=0 and X=3, the start signal STV corresponding to the third-stage gate drive circuit GA(3) is the first-stage gate control signal Scan(1) output by the first-stage gate drive circuit GA(1), and the clock signal XCK corresponding to the third-stage gate drive circuit GA(3) is the third sub-clock signal CK3. When K=0 and X=4, the start signal STV corresponding to the fourth-stage gate drive circuit GA(4) is the second-stage gate control signal Scan(2) output by the second-stage gate drive circuit GA(2), and the clock signal XCK corresponding to the fourth-stage gate drive circuit GA(4) is the fourth sub-clock signal CK4. When K=1 and X=1, the start signal STV corresponding to the 5th stage gate drive circuit GA(5) is the 3rd stage gate control signal Scan(3) output by the 3rd stage gate drive circuit GA(3), and the clock signal XCK corresponding to the 5th stage gate drive circuit GA(5) is the first sub-clock signal CK1. When K=1 and X=2, the start signal STV corresponding to the 6th stage gate drive circuit GA(6) is the 4th stage gate control signal Scan(4) output by the 4th stage gate drive circuit GA(4), and the clock signal XCK corresponding to the 6th stage gate drive circuit GA(6) is the second sub-clock signal CK2. When K=1 and X=3, the start signal STV corresponding to the 7th stage gate drive circuit GA(7) is the 5th stage gate control signal Scan(5) output by the 5th stage gate drive circuit GA(5), and the clock signal XCK corresponding to the 7th stage gate drive circuit GA(7) is the third sub-clock signal CK3.When K=1 and X=4, the start signal STV corresponding to the 8th stage gate drive circuit GA(8) is the 6th stage gate control signal Scan(6) output by the 6th stage gate drive circuit GA(6), and the clock signal XCK corresponding to the 8th stage gate drive circuit GA(8) is the 4th sub-clock signal CK4. Similarly, the start signals STV and clock signals XCK corresponding to the other gate drive circuits GA can also be obtained.

[0105] Understandably, referring to Figures 4A-4B and Figures 5A-5B The design shown can also be used to design the combination of multi-stage gate drive circuit GA, corresponding clock signal XCK, and start signal STV when Z equals 6, 8, 10, or 12, which will not be elaborated here.

[0106] It should be understood that, Figures 4A-4B and Figures 5A-5B The design shown is merely an example illustrating the design of the drive circuit GDC and is not intended to limit the drive circuit GDC of this application to only adopt the following methods: Figures 4A-4B and Figures 5A-5B The design shown is illustrated. Those skilled in the art can modify the number and phase of the multiple sub-clock signals, the cascading relationship of the multiple gate drive circuits (GA), etc., according to actual needs.

[0107] It should be noted that as the number of sub-clock signals shared by multiple gate drive circuits (GA) increases, the start signal STV corresponding to the nth-stage gate drive circuit GA(n) is not limited to the nZ / 2-stage gate control signal Scan(nZ / 2) output by the nZ / 2-stage gate drive circuit GA(nZ / 2). That is, the start signal STV corresponding to the nth-stage gate drive circuit GA(n) can be the nh-stage gate control signal Scan(nh) output by the nh-stage gate drive circuit GA(nh). Where n > 1, h ≥ 1.

[0108] Optionally, when the gate drive circuit GA includes a third control module 400, in order to reduce the power consumption of the gate drive circuit GA and improve the coordination between the signals of each node in the gate drive circuit GA, the second control module 200 and the third control module 400 may share the same clock signal XCK.

[0109] In the ZK+X stage gate drive circuit GA(ZK+X), the second input unit 102 is electrically connected to the third node No3 of the current stage gate drive circuit, and the first control signal corresponds to the signal of the third node No3. The ZK+X stage gate drive circuit GA(ZK+X) is configured to couple the potential of the third node No3 of the current stage gate drive circuit according to the Xth sub-clock signal, thereby controlling the current path between the second input unit 102 and the first power supply terminal VA and the first node No1.

[0110] When Z=2, the 2K+X stage gate drive circuit GA(2K+X) is configured to couple the potential of the third node No3 of this stage gate drive circuit GA according to the Xth sub-clock signal. That is, the first stage gate drive circuit GA(1) is configured to couple the potential of the third node No3 of the first stage gate drive circuit GA(1) according to the first sub-clock signal CK1, the second stage gate drive circuit GA(2) is configured to couple the potential of the third node No3 of the second stage gate drive circuit GA(2) according to the second sub-clock signal CK2, the third stage gate drive circuit GA(3) is configured to couple the potential of the third node No3 of the third stage gate drive circuit GA(3) according to the first sub-clock signal CK1, and so on, to obtain the clock signals XCK of the remaining gate drive circuits GA corresponding to the potential of the third node No3.

[0111] For example, when Z=4, the 4K+X stage gate drive circuit GA(4K+X) is configured to couple the potential of the third node No3 of the current stage gate drive circuit GA according to the Xth sub-clock signal. That is, the first-stage gate drive circuit GA(1) is configured to couple the potential of the third node No3 of the first-stage gate drive circuit GA(1) according to the first sub-clock signal CK1, the second-stage gate drive circuit GA(2) is configured to couple the potential of the third node No3 of the second-stage gate drive circuit GA(2) according to the second sub-clock signal CK2, the third-stage gate drive circuit GA(3) is configured to couple the potential of the third node No3 of the third-stage gate drive circuit GA(3) according to the third sub-clock signal CK3, the fourth-stage gate drive circuit GA(4) is configured to couple the potential of the third node No3 of the fourth-stage gate drive circuit GA(4) according to the fourth sub-clock signal CK4, the fifth-stage gate drive circuit GA(5) is configured to couple the potential of the third node No3 of the fifth-stage gate drive circuit GA(5) according to the first sub-clock signal CK1, and so on, to obtain the sub-clock signals of the remaining gate drive circuits GA corresponding to the potential of the third node No3.

[0112] Understandable, refer to Figures 2A-2B and Figure 3The relevant descriptions can be used to derive the working principle of multiple cascaded gate drive circuits GA, and then the timing of the multiple gate control signals Scan output by the drive circuit GDC having valid pulses in sequence, which will not be elaborated here.

[0113] It should be noted that although the start signal STV corresponding to some gate drive circuits GA is the gate control signal Scan of the preceding gate drive circuit GA, the effective level of the start signal STV may not be the same as the effective level of the gate control signal Scan. That is, the effective level of the start signal STV can be determined as high or low based on the transistor controlled by the start signal STV, just as the effective level of the gate control signal Scan can be determined as high or low based on the transistor controlled by the gate control signal Scan. Therefore, even if the start signal STV and the gate control signal Scan can correspond to the same signal, the effective level of the start signal STV may differ from the effective level of the gate control signal Scan.

[0114] Figure 6 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. This application also provides a display panel including any of the aforementioned gate driving circuits GA or driving circuits GDC.

[0115] The display panel also includes multiple sub-pixel SPXs and multiple signal transmission lines.

[0116] The driving circuit GDC is configured to output multiple gate control signals Scan, and multiple sub-pixels SPX are configured to implement the display function of the display panel. Multiple signal transmission lines are electrically connected between the multiple sub-pixels SPX and the driving circuit GDC, and the multiple signal transmission lines are configured to transmit the gate control signals Scan output by the signal output terminals Gout of the multiple gate driving circuits GA to the multiple sub-pixels SPX.

[0117] Optionally, the aforementioned start signal stv can be a frame start signal. The duration for which the signal output terminal Gout of at least one gate drive circuit GA is electrically connected to the first power supply terminal VA via the first output unit 301 can be greater than or equal to 2H. Wherein, H corresponds to the row period corresponding to scanning one row of sub-pixels.

[0118] Understandably, the display panel may also include multiple data lines and other components not shown. The aforementioned display panel may be a liquid crystal display panel, a self-emissive display panel using light-emitting devices as sub-pixels, a quantum dot display panel, etc.

[0119] It should be noted that the gate drive circuit (GDC) can be integrated on the display panel in an array substrate-on-a-gate drive manner, or it can be set independently of the display panel.

[0120] It should be understood that the display panel provided in this application includes any of the aforementioned driving circuits GDC or GA, and therefore, this application also has all the beneficial effects of the aforementioned driving circuits GDC or GA, which will not be elaborated here.

[0121] Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. This application also provides a display device, which includes any of the aforementioned driving circuits GDC, GA, or display panels.

[0122] Optionally, the display device may also include a timing controller Tcon, which is electrically connected to the drive circuit GDC. The timing controller is configured to provide a start signal and Z sub-clock signals XCK to the drive circuit GDC so that the drive circuit GDC can start and output a gate control signal Scan according to the start signal STV and the Z sub-clock signals.

[0123] Optionally, the display device may also include a source driver chip (SIC) electrically connected to the display panel, which provides the required data signals to the display panel.

[0124] It should be noted that display devices can be mobile phones, computers, virtual reality displays, augmented reality displays, and other similar devices. Display devices can be used in fields such as education, entertainment, transportation, healthcare, and defense to achieve display functions.

[0125] It is understood that the display device provided in this application includes any of the above-mentioned driving circuits GDC, gate driving circuits GA, or display panels. Therefore, this application also has all the beneficial effects of the above-mentioned driving circuits GDC, gate driving circuits GA, or display panels, which will not be repeated here.

[0126] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, include: A first control module includes a first input unit and a second input unit. The first input unit is electrically connected to a first node and a first power supply terminal. The first input unit is configured to transmit a first power signal supplied by the first power supply terminal to the first node according to a received start signal, so that the signal of the first node has a first level. The second input unit is electrically connected to the first node and the second power supply terminal. The second input unit is configured to transmit a second power signal supplied by the second power supply terminal to the first node according to a first control signal, so that the signal of the first node has a second level. The second control module is electrically connected to the second node and is configured to control the potential of the second node; The third control module, electrically connected to the first control module via a third node, is configured to control the potential of the third node according to the start signal and the clock signal; The output module, electrically connected to the first node and the second node, is configured to control the formation of a current path between the first power supply terminal and the second power supply terminal and the signal output terminal of the gate drive circuit in a time-division manner according to the signal of the first node and the signal of the second node. Wherein, the first power signal and the second power signal are DC signals, the first level is one of a high level and a low level, and the second level is the other of a high level and a low level; the first control signal is the signal of the third node.

2. The gate driving circuit according to claim 1, characterized in that, The signal received by the first input unit does not include the clock signal, and the signal received by the second input unit does not include the clock signal.

3. The gate driving circuit according to claim 1, characterized in that, Also includes: A voltage regulator module, electrically connected to the second node, the third node, and the first power supply terminal, is configured to transmit the first power signal to the second node according to the signal of the third node during the period when the signal of the first node is at the second level.

4. The gate driving circuit according to claim 3, characterized in that, The voltage regulator module includes a switching transistor, the control terminal of which is electrically connected to the third node, the first source-drain terminal of which is electrically connected to the first power supply terminal, and the second source-drain terminal of which is electrically connected to the second node.

5. The gate driving circuit according to claim 1, characterized in that, The third control module includes: The third input unit, electrically connected to the third node and the first power supply terminal, is configured to transmit the first power signal to the third node according to the effective level of the start signal, so that the signal of the third node has a third level; A coupling unit, electrically connected to the third node, is configured to couple the potential of the third node according to the level change of the clock signal during the period when the start signal is at an invalid level, so that the signal of the third node has a fourth level; The third level is one of a high level and a low level, and the fourth level is the other of a high level and a low level; The first input unit is configured to connect the current path between the first power supply terminal and the first node according to the effective level of the start signal; the second input unit is configured to connect the current path between the second power supply terminal and the first node according to the fourth level of the signal of the third node.

6. The gate driving circuit according to claim 5, characterized in that, The first input unit includes a first transistor, the control terminal of the first transistor is configured to receive the start signal, the first source-drain terminal of the first transistor is electrically connected to the first power supply terminal, and the second source-drain terminal of the first transistor is electrically connected to the first node. The second input unit includes a second transistor, the control terminal of the second transistor is electrically connected to the third node, the first source-drain terminal of the second transistor is electrically connected to the second power supply terminal, and the second source-drain terminal of the second transistor is electrically connected to the first node.

7. The gate driving circuit according to claim 5, characterized in that, During the period when the signal at the first node is at the first level, the second control module is configured to transmit the start signal with an active level to the second node according to the clock signal; During the period when the signal at the third node is at the fourth level, the second control module is configured to transmit the start signal, which is at an invalid level, to the second node according to the clock signal.

8. The gate driving circuit according to claim 7, characterized in that, The second control module includes: The fourth transistor has a control terminal configured to receive the clock signal, a first source-drain terminal configured to receive the start signal, and a second source-drain terminal electrically connected to the second node.

9. The gate driving circuit according to claim 8, characterized in that, The control terminals of the fourth transistor include a first control terminal and a second control terminal, which are configured to receive the clock signal.

10. The gate driving circuit according to claim 5, characterized in that, The third input unit includes a third transistor, the control terminal of the third transistor is configured to receive the start signal, the first source-drain terminal of the third transistor is electrically connected to the first power supply terminal, and the second source-drain terminal of the third transistor is electrically connected to the third node. The coupling unit includes a first capacitor, which is electrically connected between the third node and the clock line that transmits the clock signal.

11. The gate driving circuit according to claim 3, characterized in that, Also includes: A shielding module, electrically connected between the second node and the fourth node, and electrically connected to the second control module and the voltage regulator module through the fourth node, is configured to shield the coupling effect of the clock signal received by at least one of the second control module and the third control module on the potential of the second node.

12. The gate driving circuit according to any one of claims 1 to 11, characterized in that, The output module includes: A first output unit, electrically connected to the first node and the first power supply terminal, is configured to control the duration for which the signal output terminal receives the first power supply signal based on the signal from the first node; and The second output unit, electrically connected to the second node and the second power supply terminal, is configured to control the duration for which the signal output terminal receives the second power supply signal based on the signal from the second node.

13. The gate driving circuit according to claim 12, characterized in that, The first output unit includes a first output transistor and a second capacitor. The control terminal of the first output transistor is electrically connected to the first node, the first source-drain terminal of the first output transistor is electrically connected to the first power supply terminal, and the second source-drain terminal of the first output transistor is electrically connected to the signal output terminal. The second capacitor is electrically connected between the first power supply terminal and the first node. The second output unit includes a second output transistor and a third capacitor. The control terminal of the second output transistor is electrically connected to the second node, the first source-drain terminal of the second output transistor is electrically connected to the second power supply terminal, and the second source-drain terminal of the second output transistor is electrically connected to the signal output terminal. The third capacitor is electrically connected between the second node and the signal output terminal.

14. A driving circuit, characterized in that, include: Multiple gate driving circuits as described in any one of claims 1 to 13, wherein the multiple gate driving circuits are cascaded; as well as Z clock lines, electrically connected to the multi-stage gate drive circuit, are configured to transmit Z sub-clock signals with sequential phase differences. Wherein, the start signal corresponding to the ZK+Xth stage gate drive circuit is a start signal or a gate control signal output by the ZK+XZ / 2th stage gate drive circuit. The ZK+Xth stage gate drive circuit is configured to use the Xth sub-clock signal as the corresponding clock signal, so as to transmit the corresponding start signal to the second node of the current stage gate drive circuit according to the Xth sub-clock signal; ZK+X-Z / 2≥1, K≥0, Z≥2, 1≤X≤Z.

15. The driving circuit according to claim 14, characterized in that, In the ZK+X level gate drive circuit, the second input unit is electrically connected to the third node of the gate drive circuit of this level, and the first control signal corresponds to the signal of the third node; The ZK+Xth stage gate drive circuit is configured to couple the potential of the third node of the current stage gate drive circuit according to the Xth sub-clock signal, so as to control the current path between the second input unit and the first power supply terminal and the first node.

16. The driving circuit according to claim 14, characterized in that, Z=2, the start signal corresponding to the 2K+X stage gate drive circuit is the start signal or the gate control signal output by the 2K+X-1 stage gate drive circuit, and the 2K+X stage gate drive circuit is configured to receive the Xth sub-clock signal.

17. The driving circuit according to claim 14, characterized in that, Z=4, the start signal corresponding to the 4K+X level gate drive circuit is either the start signal or the gate control signal output by the 4K+X-2 level gate drive circuit, and the 4K+X level gate drive circuit is configured to receive the Xth sub-clock signal.

18. A display panel, characterized in that, It includes the gate drive circuit as described in any one of claims 1 to 13 or the drive circuit as described in any one of claims 14 to 17.

19. A display device, characterized in that, include: The display panel includes the driving circuit as described in any one of claims 14 to 17; as well as A timing controller, electrically connected to the drive circuit, is configured to provide the drive circuit with the start signal and Z sub-clock signals.

Images