Storage and calculation integrated calculation error low-power-consumption test circuit

Abstract

The invention discloses a storage and calculation integrated low-power-consumption test circuit for calculating errors. The storage and calculation integrated low-power-consumption test circuit comprises a storage and calculation array, an assembly line adder tree and a digital shift adding module. Storage units in the storage array store weights by analog signals such as charge quantities or resistance values. An external circuit performs programming on the storage and calculation unit with the coordinate position being (i, j), writes in a weight value Wi, j, and stores the weight value Wi, j into a plurality of low bits of a shift register in the jth digital shift adding circuit Sj in a digital signal form; a vector is input into a column line of the storage and calculation array, each element of the vector and a weight value of a corresponding position are subjected to multiplication and addition operation, the storage and calculation array completes the multiplication and addition operation through an analog signal, the digital shift addition circuit completes the multiplication and addition operation through a digital signal, and an accurate calculation result is obtained. A multiplication and addition operation result of the storage array is converted into a digital signal through a digital-to-analog conversion unit, the digital signal is compared with an operation result of the digital shift addition circuit, and the calculation error of the storage array in the storage and calculation integration is tested.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory-compute integrated circuits, and particularly relates to a low-power test circuit for memory-compute computing error. BACKGROUND

[0002] Most of the neural network layers of an AI (artificial intelligence) algorithm contain a large number of dot product operations of data vectors and weight vectors, and the multiply-add operation accounts for more than 90% of the arithmetic operations in the AI algorithm. A large number of multipliers and adders are used in the traditional digital circuit or AI chip to complete the multiply-add operation in the algorithm in parallel, resulting in a large circuit area and power consumption.

[0003] The memory-compute integrated chip uses analog signals to complete a large number of multiply-add arithmetic operations in the AI algorithm, and the weight factor in the multiplication is burned into the memory-compute unit through programming; during the multiply-add operation, only the image data is read from the external memory (such as DDR memory), and the weight stamp does not need to be read, thereby solving the problem of a part of the "memory wall", that is, data transfer. Since the multiply-add operation is completed by using analog signals, an analog memory-compute device must be used, and the analog memory-compute device has a small area and low power consumption, and can be deployed on a large scale; the power consumption of the memory-compute unit implemented by the analog memory-compute device is 1-2 orders of magnitude smaller than that of the multiply-add unit in the digital circuit, so the power consumption ratio of the memory-compute chip is very high.

[0004] Although the memory-compute integration has the above advantages, there is a problem of insufficient computing accuracy, that is, the multiply-add operation result obtained by using the analog memory-compute device is not accurate, while the result obtained by using the digital circuit is accurate, so the memory-compute integrated chip should have an error measurement circuit to compensate for the computing result of the analog memory-compute device.

[0005] At present, the memory-compute unit in the memory-compute integration is mainly implemented by using SRAM, RRAM, MRAM, Flash and CAS unit. SUMMARY

[0006] The present application aims to provide a low-power test circuit for memory-compute computing error to solve the problems in the background art.

[0007] To solve the above technical problems, the present application provides a low-power test circuit for memory-compute computing error, which comprises a memory-compute array, a pipeline addition tree and a digital shift-add module.

[0008] The memory-compute array is composed of M rows and N columns of memory-compute units, each memory-compute unit is an F i,j, (i, j) represents the row i and the column j of the memory-computing unit, i = 0, 1, 2, 3, …, M-1, j = 0, 1, 2, 3, …, N-1; the row line of each row of the memory-computing unit is connected with a digital-to-analog converter AD respectively;

[0009] The memory-computing array completes the multiplication and accumulation of the vector and the weight in the form of analog signal quantity;

[0010] The pipeline addition tree and the digital shift-add module constitute a partial product shift compression summation module, and the multiplication and accumulation of the vector and the weight are completed in the form of digital signal quantity.

[0011] The current of each row of the memory-computing array is converted into a digital signal by an analog-to-digital converter AD, and the digital signal is subtracted from the calculation result of the pipeline addition tree to obtain the calculation error of the memory-computing array.

[0012] In an embodiment, the digital shift-add module comprises a data register DR and a weight register WR;

[0013] The data register DR is used to shift the input vector data and provide data ds for each column of the memory-computing array;

[0014] The weight register WR is used to shift the weight and generate a partial product PP of each bit of the data and each bit of the weight.

[0015] In an embodiment, the pipeline addition tree is composed of four stages of pipelines, namely L0, L1, L2 and L3, the first three stages of pipelines sum all the input partial products, and the L3 stage of pipeline accumulates all the bit partial products.

[0016] In an embodiment, one memory-computing unit F i,j The weight W i,j is programmed and written by an external circuit; i,j The weight W i,j is stored in the memory-computing unit F i,j in the form of analog quantity;

[0017] At the moment of programming the weight of the memory-computing unit F i,j , the weight is written into the weight register WR in the form of digital signal quantity, and the weight W N-1 is represented in the form of 8-bit digital quantity.

[0018] In an embodiment, the column line of the memory-computing array inputs an N-dimensional vector V = {E0, E1, E2, …, EN-1}, and each element E k(k = 0, 1, 2, …, N-1) are represented by 8-bit digital quantity; the corresponding elements of the vector V are input to the N digital shift adder module, and the jth element is written to the digital shift adder module S j ; the start signal is given, and the calculation array and all the digital shift adder modules start calculating the partial product PP of the vector V and the N weights j .

[0019] In an embodiment, the data register DR is an 8-bit shift register, which is moved by 1 bit to the low bit each time; and the weight register WR is a 15-bit shift register, which is moved by 1 bit to the high bit each time;

[0020] If the lowest bit of the data register DR is 1, all the bits of the weight register WR are output as the partial product PP j ,

[0021] If the lowest bit of the data register DR is 0, 0 is output as the partial product PP j .

[0022] In an embodiment, in the pipeline addition tree, in the first stage pipeline L0, the partial product PP of each digital shift adder module is output j , and N / 2 adders are used to add two by two; in the second stage pipeline L1, the compressed N / 2 results output by the first stage pipeline L0 are added two by two using N / 4 adders; in the third stage pipeline L2, the compressed N / 4 results output by the second stage pipeline L1 are added two by two using N / 8 adders; and in the last stage pipeline L3, one adder is used to obtain the multiplication and addition operation result of the vector V and the N weight values; wherein if N / 2, N / 4, N / 8, … cannot obtain an integer, the largest integer less than or equal to the result is taken.

[0023] The application provides a low-power test circuit for calculating errors of a memory-compute integrated chip, which completes the test of errors generated by the multiplication and addition operation of a memory-compute integrated chip by a memory-compute array through a digital circuit shift adder, a pipeline addition tree and a memory-compute array. For the multiplication and addition operation of a vector with N dimensions and N weights, the memory-compute integrated error test circuit saves N multipliers and N-1 full adders, greatly reducing the circuit area and power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 The application provides a structure schematic diagram of a low-power test circuit for calculating errors of a memory-compute integrated chip;

[0025] Figure 2 The application provides a structure schematic diagram of a digital shift adder module;

[0026] Figure 3 A pipeline addition tree structure diagram provided by the present application;

[0027] Figure 4 A key signal timing diagram of the low-power test circuit for the storage-computation integrated calculation error provided by the present application;

[0028] Figure 5 A working flow diagram of the low-power test circuit for the storage-computation integrated calculation error provided by the present application. DETAILED DESCRIPTION

[0029] The low-power test circuit for the storage-computation integrated calculation error provided by the present application is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and all use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0030] Figure 1 The low-power test circuit for the storage-computation integrated calculation error provided by the present application is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and all use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application. Figure 1 Each small circle in the array represents a storage-computation unit CM. The PPSCS (Partial Production Shifting-Compress Summation, referred to as PPSCS for short) module completes the multiplication and accumulation of the vector and the weight in the form of digital signal quantity, and the obtained result is accurate; the storage-computation array CIM_ARRAY completes the multiplication and accumulation of the vector and the weight in the form of analog signal quantity. The PPSCS module is composed of two sub-circuits, which are a digital shift-add module and a pipeline addition tree.

[0031] Figure 2 The structure diagram of the digital shift-add module is shown, which mainly consists of two parts, which are a data register DR with a bit width of 8 bits and a weight register WR with a bit width of 15 bits. The data register DR is used to shift the input vector data, and at the same time provides data ds for each column of the storage-computation array; the function of the weight register WR is to shift the weight, and to generate the partial product PP of each bit of the data and each bit of the weight.

[0032] Figure 3 The structure diagram of the pipeline addition tree is shown. The function of this addition tree is to complete the addition of the partial products PP of each column of the storage-computation array. Figure 2The partial products PP of each bit are accumulated to obtain the multiplication and accumulation result of the input vector and the weight. The pipeline addition tree is composed of four pipeline stages, L0, L1, L2 and L3. The first three pipeline stages sum all the input partial products, and the L3 pipeline stage accumulates the partial products of all bits.

[0033] Figure 4 Fig. 4 shows a signal timing diagram of a possible input data of the low-power test circuit for the error of the memory-computing integrated computing.

[0034] The following steps are described in one possible implementation, and the flow is as follows Figure 5 As shown, the steps include the following steps:

[0035] (1) Step 101, write the weight value W i,j into the memory-computing unit at position (i, j), where i represents the i-th row and j represents the j-th column. Figure 1 A 5-row 12-column memory-computing array CIM_ARRAY is given, and the row line of each row is connected to an analog-digital conversion circuit ADi (i = 0, 1, 2, 3, 4); when writing the weight, the row line of the i-th row is pulled high to high level, and the column line of the j-th column is pulled high to high level. By maintaining the above high level for different times, different charge amounts or different conductance values are stored in the memory-computing unit CM.

[0036] At the same time, the 8-bit wide weight value W i,j is written into the low 8 bits of the weight register WR in the digital shift-add module through the interface {w0, w1, w2, w3, w4, w5, w6, w7}, that is, the weight value W = {W7, W6, W5, W4, W3, W2, W1, W0}, and the high 7 bits of the weight register WR are written as 0, that is, {W8, W9, W10, W11, W12, W13, W14} = 0000000, as shown in Figure 2 .

[0037] (2) Step 102, input a 12-dimensional vector into the memory-computing array CIM_ARRAY, the first element E0 = {d7, d6, d5, d4, d3, d2, d1, d 10} = 10110011 = 179, as shown in the data signal in Figure 4 , and the remaining elements E1 ~ E 11 are all 0; E0 is stored in the data register DR of the digital shift-add module, as shown in Figure 2 ; the lowest bit driving signal ds of the data register DR is connected to the column line of the 0th column of the memory-computing array CIM_ARRAY; and so on, Figure 3The ds output signal of the j-th digital shift-add module Sj is connected to the j-th column line of the in-memory array CIM_ARRAY. Simultaneously, the in-memory start signal start is given, and the start signal is high for one clock cycle. (See...) Figure 4 .

[0038] (3) Step 103: In each calculation, the data register DR in the digital shift and add module S0 shifts one bit towards the low-order bit, and the weight register WR shifts one bit towards the high-order bit. Simultaneously, the counter cnt counts once per storage operation. See [link to relevant documentation]. Figure 4 At times 1, 2, 3, 4, 5, 6, 7, and 8, Figure 2 The values ​​of ds are 1, 1, 0, 0, 1, 1, 0, 1, driving the memory array CIM_ARRAY to accumulate the analog current, and then generating the multiplication-accumulation result through the analog-to-digital converter circuit AD0. (See...) Figure 1 The resad0 signal in the counter; at times cnt = 1, 2, 3, 4, 5, 6, 7, 8, Figure 2 The values ​​of the middle part product PP are {W,0}, {W,00}, {0}, {0}, {W,0000}, {W,00000}, {0}, {W,0000000}, that is... Figure 4 The PP signals in the data are: W, W*, 0, 0, W*16, W*32, 0, W*128.

[0039] (4) Step 104: The pipelined addition tree performs a partial product PP of all number shifts and addition modules for each iteration. j To accumulate, see Figure 3 For the 12 partial products, a 4-stage pipelined adder tree can be used to accumulate all partial products. The ADDER(2,2) and the accumulator register ACCR in the L3 pipeline stage constitute the accumulator, and the adders in other pipeline stages complete the addition of every two partial products. The accumulator counter cnt is initialized to 0.

[0040] Because a 4-stage pipelined addition tree is used, at times cnt 4, 5, 6, 7, 8, 1, 2, 3, the sum of the partial products of the digital shift-add module at times 1, 2, 3, 4, 5, 6, 7, 8 reaches the adder input before the accumulator register ACCR in the L3 pipeline. At times cnt 5, 6, 7, 8, 1, 2, 3, 4, the multiply-accumulated result is obtained at the output Q of the accumulator register ACCR. That is, the values ​​of the partial multiply-accumulated results res_mac at each time point are W, W*3, W*3, W*3, W*19, W*51, W*51, W*179, respectively. (See...) Figure 4 and Figure 3 The res_mac signal in the system.

[0041] (5) Step 105, the multiplication-accumulation result res mac obtained by step 104 finally at the time when the counter cnt is 4 is subtracted from the result res ad0 calculated by the storage-computation array CIM_ARRAY in step 103 through a subtracter SUB0, to obtain the error value comp0 of the multiplication-accumulation result calculated by the storage-computation array CIM_ARRAY and the accurate result, see Figure 1 .

[0042] For the sake of simplicity, all possible combinations of different storage-computation unit weights and all possible combinations of different data inputs in the above embodiments are not described, however, as long as there is no contradiction, all of them should be considered as the scope of the present disclosure.

[0043] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application, any modification or change made by a person of ordinary skill in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A low-power test circuit for in-memory computing error, characterized in that, The application relates to a calculation array, a pipeline addition tree and a digital shift addition module. Wherein, the storage-computing array is composed of M rows and N columns of storage-computing units, each of which is F i,j , (i, j) represents the row i and the column j where the storage-computing unit is located, i = 0, 1, 2, 3, …, M-1, j = 0, 1, 2, 3, …, N-1; the row line of each row in the storage-computing unit is connected with a digital-to-analog converter AD; The calculation array completes the multiplication and accumulation of a vector and weights in the form of an analog signal quantity. The pipeline addition tree and the digital shift addition module constitute a partial product shift compression summation module, and the multiplication and accumulation of the vector and the weights are completed in the form of a digital signal quantity. The current of each row in the calculation array is converted into a digital signal by an analog-digital converter AD, and the digital signal is subtracted from the calculation result of the pipeline addition tree to obtain the calculation error of the calculation array.

2. The low-power test circuit for computing error in memory computing integration according to claim 1, wherein, The digital shift addition module comprises a data register DR and a weight register WR. The data register DR is used for shifting the input vector data and simultaneously providing data ds for each column of the calculation array. The weight register WR is used for shifting weights and generating partial products PP of each bit of the data and each bit of the weights.

3. The low-power test circuit of claim 2, wherein, The pipeline addition tree is composed of four stages of pipelines, namely L0, L1, L2 and L3.

4. The low-power test circuit for computing error in memory and computation integration according to claim 3, wherein, One compute-in-memory cell F in the compute-in-memory array i,j Programming write weights W through external circuitry i,j , the weights W i,j are stored in the form of analog quantities in the compute-in-memory cell F i,j ; wherein at the moment of weight programming of the compute-in-memory unit F i,j the weight is written in the form of a digital signal quantity into the weight register WR, and the weight W i,j is represented as a digital quantity of 8 bits wide.

5. The low-power test circuit for computing error in memory and computation integration according to claim 4, wherein, The column line of the storage-computing array inputs an N-dimensional vector V = {E0, E1, E2, …, E N-1}, each element E k (k = 0, 1, 2, …, N-1) of the vector is represented by 8-bit digital quantity; the corresponding element of the vector V is input to the N digital shift-add modules, the jth element is written into the digital shift-add module S j ; a start signal is given, the storage-computing array and all the digital shift-add modules start to calculate the partial product PP j of the vector V and the N weights.

6. The low-power test circuit for computing error in memory and computation integration according to claim 5, wherein, The data register DR is an 8-bit shift register which is shifted by 1 bit to the low bit each time, and the weight register WR is a 15-bit shift register which is shifted by 1 bit to the high bit each time. If the lowest bit of the data register DR is 1, all bits of the weight register WR are output as partial products PP j . If the lowest bit of the data register DR is 0, output 0 as the partial product PP j .

7. The low-power test circuit for computing error in memory and computation integration according to claim 6, wherein, In the pipeline addition tree, in the first stage pipeline L0, the partial product output PP of each digital shift add module is added j N / 2 adders are used to add two by two; In the second stage of the pipeline L1, the compressed N / 2 results output by the first stage of the pipeline L0 are added by N / 4 adders two by two. In the last stage of the pipeline L3, one adder is used to obtain the multiplication and addition operation result of the vector V and N weight values. If N / 2, N / 4, N / 8... cannot obtain an integer, the maximum integer less than or equal to the result is taken.

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