Parity check code updating method, computer readable storage medium and solid state disk

Abstract

The invention discloses a parity check code updating method, a computer readable storage medium and a solid state disk. The parity check code updating method comprises the following steps: acquiring a new write instruction; writing the write-in data corresponding to the new write-in instruction into the data block of the corresponding strip, and changing the flag bit of the strip into a first state so as to mark the parity check bit of the corresponding strip to be in a failure state; after the data is written, detecting whether the current state of the strip meets a preset condition for updating the parity check bit or not; if yes, reading data in the strip, calculating a corresponding parity check code, updating the parity check code obtained through calculation to the parity check bit of the strip, and changing the flag bit of the strip into the second state so as to mark the parity check bit of the corresponding strip to be in an effective state. In the data writing process, calculation of parity check codes is not carried out, so that the burden of real-time writing is greatly reduced, and the problem of write amplification and energy consumption are effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of solid state disks, in particular to a parity code updating method, a computer readable storage medium and a solid state disk. BACKGROUND

[0002] In the current field of solid state disks (SSD), many enterprise-level SSD controllers implement RAID and parity protection to ensure the reliability and error tolerance of data. These controllers usually calculate and update parity in real time during data writing to ensure data consistency and integrity.

[0003] However, these technologies often result in significant performance degradation in high-frequency small block write (Random Write) operations and cause a series of problems. For example, some existing commercial technologies calculate parity synchronously during data writing, which means that the controller needs to perform a series of calculations immediately after each data write to ensure data integrity. This greatly increases the computational burden of the controller, especially under random write-intensive workloads, which can have a significant impact on overall performance. With each write operation requiring calculation and updating of parity, not only does it increase the computational burden, but it also causes write latency. In particular, in high-frequency random write scenarios (e.g., processing millions of small unit writes per second), real-time calculation and updating of parity significantly prolongs the processing time of each write, which has a significant impact on overall system performance. The calculation and updating process of parity involves a large number of write operations. Each time the parity is updated, additional data writing is triggered, exacerbating the write amplification problem in SSDs, leading to a shorter lifespan of NAND Flash and increased energy consumption. SUMMARY

[0004] The purpose of the present application is to provide a parity code updating method, a computer readable storage medium and a solid state disk, which reduces the burden of real-time writing, effectively reduces the problem of write amplification and reduces energy consumption.

[0005] The present application discloses a parity code updating method for a RAID system in a solid state disk, the RAID system comprising a plurality of stripes, the parity code updating method comprising the following steps:

[0006] S1: obtaining a new write instruction;

[0007] S2: writing the write data corresponding to the new write instruction into the data block of the corresponding stripe, and changing the flag bit of the stripe to a first state to indicate that the parity bit of the corresponding stripe is in an invalid state;

[0008] S3: detecting whether the current state of the stripe meets the preset condition for updating the parity bit after writing the data; and

[0009] S4: if yes, reading the data in the stripe, calculating the corresponding parity code, updating the calculated parity code to the parity bit of the stripe, and changing the flag bit of the stripe to the second state to indicate that the parity bit of the corresponding stripe is in the valid state.

[0010] The first state and the second state are two opposite states.

[0011] Optionally, the step S3 comprises:

[0012] S31: detecting the update duration of the state of the flag bit in the plurality of stripes after writing the data, and determining whether the update duration reaches the preset duration; if yes, the preset condition for updating the parity bit is met, and the step S4 is performed; if no, the step S1 is performed.

[0013] Optionally, the step S3 comprises:

[0014] S31': detecting whether the system has a task to be processed after writing the data; if no, determining that the current system is in the idle state, the preset condition for updating the parity bit is met, and the step S4 is performed; if yes, determining that the current system is in the non-idle state, and the step S1 is performed.

[0015] Optionally, the step S3 comprises:

[0016] S31": detecting whether the system has a task to be processed after writing the data; if no, determining that the current system is in the idle state, the preset condition for updating the parity bit is met, and the step S4 is performed; if yes, determining that the current system is in the non-idle state, and calculating the load in the non-idle state.

[0017] S32": determining whether the load is lower than the preset load; if yes, the preset condition for updating the parity bit is met, and the step S4 is performed; if no, the step S1 is performed.

[0018] Optionally, the step S31 comprises:

[0019] S311: detecting the update duration of the state of the flag bit in the plurality of stripes after writing the data, and determining whether the update duration reaches the preset duration; if yes, the preset condition for updating the parity bit is met, and the step S4 is performed; if no, detecting whether the system has a task to be processed; if no, determining that the current system is in the idle state, the preset condition for updating the parity bit is met, and the step S4 is performed; if yes, determining that the current system is in the non-idle state, and the step S1 is performed.

[0020] Optionally, the step S31 comprises:

[0021] S311': after writing data, detecting the update duration of the state of the mark bit in the plurality of stripes, and judging whether the update duration reaches a preset duration; if yes, the preset condition of updating the parity check bit is met, and the step S4 is executed; if no, judging whether the system has a task to be processed; if no, judging that the current system is in an idle state, the preset condition of updating the parity check bit is met, and the step S4 is executed; if yes, judging that the current system is in a non-idle state, and calculating the load in the non-idle state.

[0022] S312': judging whether the load is lower than a preset load; if yes, the preset condition of updating the parity check bit is met, and the step S4 is executed; if no, the step S1 is executed.

[0023] Optionally, the step S4 comprises:

[0024] S41: if the condition is met, sorting the update duration of the mark bit in all the stripes, reading data in the stripe with the longest update duration, calculating the corresponding parity check code, updating the calculated parity check code to the parity check bit of the stripe, and changing the mark bit of the stripe to a second state to indicate that the parity check bit of the corresponding stripe is in a valid state.

[0025] Optionally, the step S41 comprises:

[0026] S411: in the process of updating the parity check bit, detecting whether a new write instruction is accepted; if yes, the step S2 is executed; if no, reading and calculating the parity check code corresponding to all the stripes, updating the calculated parity check code to the parity check bit of the stripe, and changing the mark bit of the stripe to a second state to indicate that the parity check bit of the corresponding stripe is in a valid state.

[0027] The application further discloses a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to realize the operations in the parity check code updating method.

[0028] The application further discloses a solid state disk, comprising a controller and a storage area, wherein the controller comprises an exclusive or operation module, the storage area comprises a RAID system, the RAID system uses the parity check code updating method to update the parity check code in the stripe of the RAID system, and the exclusive or operation module calculates data in the stripe to obtain the parity check code to be updated.

[0029] Compared with the current method of writing data and performing parity check at the same time, the application detects whether the current state of the stripe meets the preset condition for updating the parity check bit after writing data, not directly checking during writing, and only performs parity check calculation after meeting the preset condition. If the preset condition is met, the data in the stripe is read, the corresponding parity check code is calculated, and the calculated parity check code is updated to the parity check bit of the stripe. At the same time, the mark bit of the stripe is changed to the second state to indicate that the parity check bit of the corresponding stripe is in the valid state. This avoids synchronous calculation of parity check during writing, increases the calculation burden, triggers additional data writing, aggravates the write amplification problem in the solid state disk, shortens the service life of the NAND Flash, and increases the energy consumption. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings included are part of the specification and illustrate embodiments of the present application and, together with the written description, serve to explain the principles behind the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0031] Figure 1 is a flowchart of the parity check code updating method of the first embodiment of the present application;

[0032] Figure 2 is a flowchart of the parity check code updating method of the second embodiment of the present application;

[0033] Figure 3 is a flowchart of the parity check code updating method of the third embodiment of the present application;

[0034] Figure 4 is a flowchart of the parity check code updating method of the fourth embodiment of the present application;

[0035] Figure 5 is a flowchart of the parity check code updating method of the fifth embodiment of the present application;

[0036] Figure 6 is a flowchart of the parity check code updating method of the sixth embodiment of the present application;

[0037] Figure 7 is a flowchart of the parity check code updating method of the seventh embodiment of the present application;

[0038] Figure 8 is a structure diagram of the solid state disk of the eighth embodiment of the present application.

[0039] Wherein, 100, solid state disk; 110, RAID system; 120, controller; 121, XOR operation module; 130, storage area; 140, stripe. DETAILED DESCRIPTION

[0040] It needs to be understood that the terms used herein, the specific structure and functional details disclosed, are only for the purpose of describing specific embodiments, and are representative, but the present application can be embodied in many alternative forms, and should not be interpreted as being limited to the embodiments described herein.

[0041] In the description of the present application, the terms "first", "second" are only for the purpose of description, and should not be understood as indicating relative importance, or implying the number of the indicated technical features. Therefore, unless otherwise specified, the features defined with "first", "second" can explicitly or implicitly include one or more of the features; the meaning of "multiple" is two or more. The term "includes" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof can exist or be added.

[0042] In addition, the terms indicating the orientation or positional relationship of "center", "transverse", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are described based on the orientation or relative position relationship shown in the drawings, and are only for the convenience of the simplified description of the present application, and do not indicate that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0043] In addition, unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0044] The present application will be described in detail below with reference to the accompanying drawings and optional embodiments.

[0045] As a first embodiment of the present application, a parity code updating method is disclosed, which is used in a RAID system inside a solid state disk, the RAID system includes a plurality of stripes, such as Figure 1 As shown, the parity code updating method includes the following steps:

[0046] S1: obtaining a new write instruction;

[0047] S2: Write the write data corresponding to the new write instruction into the data block of the corresponding stripe, and at the same time change the flag bit of the stripe to the first state to indicate that the parity bit of the corresponding stripe is in the invalid state.

[0048] S3: After writing data, check whether the current state of the stripe meets the preset conditions for updating the parity bit; and

[0049] S4: If the conditions are met, read the data in the strip, calculate the corresponding parity check code, update the parity check bit of the strip with the calculated parity check code, and change the flag bit of the strip to the second state to indicate that the parity check bit of the corresponding strip is in a valid state.

[0050] The first state and the second state are two opposing states. Generally, the first state is represented by the number 1 and the second state is represented by the number 0. That is, the number 1 or 0 is written on the mark. Of course, the first state can be represented by the number 0 and the second state can be represented by the number 1.

[0051] In this embodiment, the original parity check operation of writing data on the same time is abandoned. Instead, after writing data, the current state of the stripe is checked to see if it meets the preset conditions for updating the parity bit. Instead of checking during writing, parity calculation is only performed after the preset conditions are met. If the preset conditions are met, the data in the stripe is read, the corresponding parity code is calculated, and the calculated parity code is updated to the parity bit of the stripe. At the same time, the flag bit of the stripe is changed to the second state to indicate that the parity bit of the corresponding stripe is in a valid state. Part or all of the data is written into the RAID system. After the preset conditions for updating the parity bit are met, parity calculation is performed to obtain the parity code. In this way, no parity calculation is required during the data writing process, which greatly reduces the burden of real-time writing and maintains high write performance in random writing scenarios. Especially in the case of 4KB random writing, because the parity calculation is completely delayed, this reduces the CPU burden on the solid-state drive (SSD) controller and reduces energy consumption.

[0052] like Figure 2 As shown, as a second embodiment of this application, it is a further refinement and improvement of the first embodiment described above, and a further limitation on the preset conditions. Step S3 includes:

[0053] S31: After writing data, detect the update duration of the status of the marker bits in multiple stripes and determine whether the update duration has reached the preset duration; if yes, it meets the preset condition for updating the parity bit and executes step S4; if no, execute step S1.

[0054] In the embodiment, the judgment of the preset condition is mainly through detecting the update duration of the state of the mark bit in the plurality of stripes. When the update duration reaches the preset duration, it is judged that the timeout is met, and the condition of updating the parity check bit is met. At this time, the data in the stripe needs to be read, and the corresponding parity check code is calculated, and the calculated parity check code is updated to the parity check bit of the stripe, and the mark bit of the stripe is changed to the second state to indicate that the parity check bit of the corresponding stripe is in the valid state. When the update duration does not reach the preset duration, step S1 is re-executed, that is, a new write instruction is obtained, and the cycle of steps S1 to S4 is entered again until the parity check code in all stripes is updated, and the process ends. The preset duration is generally set to 10s to 30s, and can be set according to the specific parameters of the device.

[0055] Specifically, the controller obtains a new write instruction, and calculates which data block block in the stripe Stripe of the RAID system needs to be updated at the write time. The embodiment mainly relates to RAID5. The write data corresponding to the new write instruction is written to the block of the corresponding RAID5 Stripe, and the dirty bit of the RAID5 Stripe is changed to 1 to indicate that the Parity bit is in the invalid state, and the time of updating the dirty bit is recorded. The firmware continuously detects the update duration of the dirty bit in each RAID5 Stripe, and judges whether the update duration reaches the preset timeout duration. If it is judged that a certain dirty bit reaches the timeout duration, the firmware immediately notifies the controller to immediately read the data in the RAID5 Stripe corresponding to the dirty bit, calculate the Parity check code using the XOR operation module, update the Parity bit in the RAID5 Stripe, and mark the dirty bit as 0 to indicate that the parity is in the valid state. Continue to detect whether there is another dirty bit marked as 1. If there is, judge whether the update duration of the dirty bit marked as 1 in the stripe currently detected reaches the preset timeout duration. If the dirty bit reaches the timeout duration, the firmware immediately notifies the controller to immediately read the data in the RAID5 Stripe corresponding to the dirty bit, calculate the Parity check code using the XOR operation module, update the Parity bit in the RAID5 Stripe, and mark the dirty bit as 0. Until all the checks in the current process are completed, the checking is ended. In addition, it needs to be explained that if there is no user data in the RAID5 Stripe, the Parity is meaningless, and the Dirty bit is set to 0. At this time, if the write instruction corresponding to the time is written, the Dirty bit is changed to 1, and the controller updates the Parity to achieve the data protection effect.

[0056] As Figure 3 shown, as the third embodiment of the present application, different from the above embodiments, the preset condition is to judge whether the system is idle, specifically, the step S3 comprises:

[0057] S31': after writing data, detecting whether the system has a task to be processed, if not, judging that the current system is in idle state, meeting the preset condition of updating the parity bit, and executing step S4; if yes, judging that the current system is in non-idle state, and executing step S1.

[0058] In the present embodiment, at the time of data writing, the parity calculation is not performed, and the parity calculation is completely delayed to the time when the system is idle. Whether the system has a task to be processed is detected, if not, judging that the current system is in idle state, meeting the preset condition of updating the parity bit, and executing step S4; if yes, judging that the current system is in non-idle state, and executing step S1, that is, obtaining a new write instruction, and entering the cycle of steps S1 to S4 again, until the parity code in all stripes is updated, and the process is ended. Since the parity calculation is delayed to the idle time, the problem of write amplification is reduced, especially for random write operation, the situation that the parity needs to be updated every time of writing is avoided, the writing efficiency is maintained, especially in the case of 4KB random write, because the parity calculation is completely delayed, the CPU burden of the SSD controller is reduced; in the present embodiment, no matter which step is performed, once a new read / write instruction is detected, the parity can be selected to be stopped, and the new read / write instruction is processed preferentially.

[0059] As Figure 4 shown, as the fourth embodiment of the present application, different from the above embodiments, in the present embodiment, whether the system has a task to be processed is detected preferentially, that is, whether the system is idle is judged, if the system is idle, it is judged that the preset condition is met, but if the system is in non-idle state, whether the preset condition is met is judged based on the load, specifically, the step S3 comprises:

[0060] S31": after writing data, detecting whether the system has a task to be processed, if not, judging that the current system is in idle state, meeting the preset condition of updating the parity bit, and executing step S4; if yes, judging that the current system is in non-idle state, and calculating the load in the non-idle state.

[0061] S32": judging whether the load is lower than the preset load, if yes, meeting the preset condition of updating the parity bit, and executing step S4; if not, executing step S1.

[0062] In the embodiment, it is judged whether the system is idle first. If it is idle, the data in the stripe is read, the corresponding parity code is calculated, the calculated parity code is updated to the parity bit of the stripe, and the mark bit of the stripe is changed to the second state to indicate that the parity bit of the corresponding stripe is in the valid state. If it is not idle, the parity calculation can also be performed on the premise of not affecting the problem of write amplification. For example, when the load is small, the parity calculation can be performed. In the embodiment, the load judgment is added. If the load is lower than the preset load, the parity calculation can also be performed. Of course, if the load exceeds the preset load, the process returns to the cycle of steps S1 to S4 again until the parity code in all stripes is updated, and the process ends, thereby reducing the problem of write amplification. The selection of the preset load is generally based on the transmission performance. For example, if the highest transmission performance is 7 GB / s, the load lower than 3 GB / s is considered as low load. Alternatively, if the system can process 2 million read or write per second, the read or write lower than 500,000 per second is considered as low load.

[0063] As shown in Figure 5 the fifth embodiment of the present application is a further refinement and improvement of the second embodiment. The embodiment considers that if the write-in and check-in are adopted without timeout, there is still a problem. Therefore, the system state detection is further performed on the stripe without timeout. Specifically, the step S31 includes:

[0064] S311: After writing data, the update duration of the state of the mark bit in the plurality of stripes is detected, and it is judged whether the update duration reaches the preset duration. If yes, the condition of updating the parity bit is met, and step S4 is performed. If no, it is detected whether there is a task to be processed. If no, it is judged that the current system is in the idle state, the condition of updating the parity bit is met, and step S4 is performed. If yes, it is judged that the current system is in the non-idle state, and step S1 is performed.

[0065] In the embodiment, once the update duration reaches the preset duration, the update must be performed, and the parity check is performed after the data is written regardless of whether the system is idle. Of course, if there is no timeout, whether the parity check is performed is further determined according to the state of the system. It is detected whether the system has a task to be processed. If not, it is determined that the current system is idle, which meets the preset condition of updating the parity check bit. The data in the stripe is read, the corresponding parity check code is calculated, the calculated parity check code is updated to the parity check bit of the stripe, and the flag bit of the stripe is changed to the second state to indicate that the parity check bit of the corresponding stripe is in the valid state. If yes, it is determined that the current system is not idle, and the process returns to steps S1 to S4 again. The cycle is performed until the parity check code in all stripes is updated, the write amplification is reduced, and the protection of the written data is improved.

[0066] As shown in Figure 6 the sixth embodiment of the present application is a further improvement and refinement of the second embodiment. Specifically, the step S31 includes:

[0067] S311': After the data is written, the update duration of the state of the flag bit in the plurality of stripes is detected, and it is determined whether the update duration reaches the preset duration. If yes, the preset condition of updating the parity check bit is met, and step S4 is performed. If not, it is detected whether the system has a task to be processed. If not, it is determined that the current system is idle, which meets the preset condition of updating the parity check bit, and step S4 is performed. If yes, it is determined that the current system is not idle, and the load under the non-idle state is calculated.

[0068] S312': It is determined whether the load is lower than the preset load. If yes, the preset condition of updating the parity check bit is met, and step S4 is performed. If not, step S1 is performed.

[0069] The embodiment is different from the fifth embodiment described above in that the parity check can be performed under any one of three conditions. First, the update duration of the mark bit in the plurality of bands is detected. If the update duration reaches a preset duration, the condition for updating the parity check bit is met, and step S4 is performed. If the preset duration is not reached, it is detected whether the system has a task to be processed. If the current system is in an idle state, the condition for updating the parity check bit is met, and step S4 is performed. If the system is not in an idle state, the load in the non-idle state is calculated. If the load is lower than a preset load, the condition for updating the parity check bit is met, and step S4 is performed. If the load is not lower than the preset load, step S1 is performed, and the cycle of steps S1 to S4 is entered again until the parity check code in all bands is updated, and the process ends. In the embodiment, once a new read / write instruction is detected, the parity check is stopped, and the new read / write instruction is processed preferentially.

[0070] As shown in Figure 7 the seventh embodiment of the present application is a further refinement and improvement of the fifth embodiment or the sixth embodiment described above. The step S4 includes:

[0071] S41: If the condition is met, the update duration of the mark bit in all bands is sorted, the data in the band with the longest update duration is read, the corresponding parity check code is calculated, the calculated parity check code is updated to the parity check bit of the band, and the mark bit of the band is changed to the second state to indicate that the parity check bit of the corresponding band is in the valid state.

[0072] When the check is performed, the parity check can be performed in sequence under the condition that the data is written and the preset condition is met. However, considering that some bands do not need to be checked immediately under the condition of checking in sequence, the update duration of the mark bit in all bands is generally sorted, the data in the band with the longest update duration is read, and the corresponding parity check code is calculated and updated to the parity check bit of the band.

[0073] Further, considering that a new write instruction can be received when the check is performed, the step S41 includes:

[0074] S411: In the process of updating the parity check bit, it is detected whether a new write instruction is received. If yes, step S2 is performed. If no, the parity check code corresponding to all bands is read and calculated, and the calculated parity check code is updated to the parity check bit of the band, and the mark bit of the band is changed to the second state to indicate that the parity check bit of the corresponding band is in the valid state.

[0075] In the embodiment, in the process of updating the parity check bit, it is also detected whether a new write instruction is received. If a new write instruction is detected, the new read / write instruction is processed preferentially. If it is a new write, the write data corresponding to the new write instruction is written into the data block of the corresponding stripe immediately, and the mark bit of the stripe is changed to the first state to indicate that the parity check bit of the corresponding stripe is in the invalid state. At this time, no parity check is performed to avoid write amplification. If there is no new write instruction, the parity check code of all stripes is read and calculated, and the calculated parity check code is updated to the parity check bit of the stripe. The process ends after the parity check code of all stripes is updated, reducing the problem of write amplification.

[0076] In addition, in any of the above embodiments, whether the timeout condition is met, or the idle condition is met, or the low load condition is met, as long as a new read / write instruction is detected, the parity check is stopped or the parity check is stopped directly, and the new read / write instruction is processed preferentially.

[0077] As shown in Figure 8 As an eighth embodiment of the present application, a solid state disk is disclosed, referring to Figure 8 The solid state disk 100 includes a controller 120 and a storage area 130. The controller 120 includes an XOR operation module 121. The storage area is provided with a RAID system 110. The RAID system 110 uses the parity check code updating method as described above to update the parity check code in the stripe of the RAID system. The XOR operation module calculates the data in the stripe to obtain the parity check code to be updated.

[0078] The controller (taking the NVMe interface as an example) takes part of the storage space as a place to place parity (check bits P0-Pn), the back-end module does not intervene in the RAID operation, and the XOR module is specially used to synchronize the parity. In addition, an NVRAM is configured for the NVMe module to store dirty information (flag bit 0 or 1). Assuming that the data in a stripe is 4KB, a RAID5 stripe is 8 data blocks (32KB). Each stripe is matched with a parity (4KB), and a flag bit is also configured. When the flag bit is '1', it indicates that the stripe data and the parity do not match. When the controller is working, the controller obtains a new write instruction, the FTL in the controller judges the write event corresponding to the new write instruction, and calculates which data block in which stripe in the RAID system needs to be updated to which data block in the stripe; when the controller is idle, the synchronization work is performed for the stripe with the dirty being '1', that is, all data in the stripe is read, XOR operation is performed, the corresponding parity is updated, and the dirty is set to 0.

[0079] Those skilled in the art can understand that all or part of the operations in the various methods of the above embodiments can be completed by instructions or controlled by instructions related to hardware, which can be stored in a computer readable storage medium and loaded and executed by a processor. Therefore, the present application discloses a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is executed by the processor to realize the operations in the parity updating method according to any one of the above.

[0080] The specific implementation of the above operations can refer to the previous embodiments, which will not be repeated here. The computer readable storage medium can include read only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0081] It should be noted that the steps involved in the present scheme are not limited to the order of execution, and the previous steps can be executed first, or executed later, or even executed simultaneously, as long as the present scheme can be implemented, which should be considered as belonging to the protection scope of the present application.

[0082] It should be noted that the inventive concept of the present application can form a very large number of embodiments, but the length of the application file is limited and cannot list them one by one, so under the premise of not conflicting, the above described various embodiments or various technical features can be combined to form new embodiments, and the combination of each embodiment or technical feature will enhance the original technical effect.

[0083] The above is a further detailed description of the present application in combination with specific optional embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions; for ordinary skilled persons in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as belonging to the protection scope of the present application.

Claims

1. A parity code updating method for a RAID system inside a solid state drive, the RAID system comprising a plurality of stripes, characterized in that, The parity check code updating method comprises the following steps: S1: obtaining a new write instruction; S2: writing the write data corresponding to the new write instruction into the data block of the corresponding stripe, and changing the mark bit of the stripe to a first state to indicate that the parity check bit of the corresponding stripe is in an invalid state; S3: after writing the data, detecting whether the current state of the stripe meets the preset condition for updating the parity check bit; and S4: if yes, reading the data in the stripe, calculating the corresponding parity check code, and updating the calculated parity check code to the parity check bit of the stripe, and changing the mark bit of the stripe to a second state to indicate that the parity check bit of the corresponding stripe is in a valid state; Wherein, the first state and the second state are two opposite states.

2. The method of updating a parity check code according to claim 1, wherein The step S3 comprises: S31: after writing the data, detecting the update duration of the state of the mark bit in the plurality of stripes, and judging whether the update duration reaches a preset duration; if yes, the preset condition for updating the parity check bit is met, and the step S4 is executed; if not, the step S1 is executed.

3. The method of updating a parity code according to claim 1, wherein, The step S3 comprises: S31': after writing the data, detecting whether the system has a task to be processed; if not, judging that the current system is in an idle state, the preset condition for updating the parity check bit is met, and the step S4 is executed; if yes, judging that the current system is in a non-idle state, and the step S1 is executed.

4. The method of updating a parity code of claim 1, wherein, The step S3 comprises: S31": after writing the data, detecting whether the system has a task to be processed; if not, judging that the current system is in an idle state, the preset condition for updating the parity check bit is met, and the step S4 is executed; if yes, judging that the current system is in a non-idle state, and calculating the load under the non-idle state; S32": judging whether the load is lower than a preset load; if yes, the preset condition for updating the parity check bit is met, and the step S4 is executed; if not, the step S1 is executed.

5. The method of updating a parity code according to claim 2, wherein, The step S31 comprises: S311: after writing the data, detecting the update duration of the state of the mark bit in the plurality of stripes, and judging whether the update duration reaches a preset duration; if yes, the preset condition for updating the parity check bit is met, and the step S4 is executed; if not, detecting whether the system has a task to be processed; if not, judging that the current system is in an idle state, the preset condition for updating the parity check bit is met, and the step S4 is executed; if yes, judging that the current system is in a non-idle state, and the step S1 is executed.

6. The method of updating a parity check code according to claim 2, wherein, The step S31 comprises: S311': after writing the data, detecting the update duration of the state of the mark bit in the plurality of stripes, and judging whether the update duration reaches a preset duration; if yes, the preset condition for updating the parity check bit is met, and the step S4 is executed; if not, detecting whether the system has a task to be processed; if not, judging that the current system is in an idle state, the preset condition for updating the parity check bit is met, and the step S4 is executed; if yes, judging that the current system is in a non-idle state, and calculating the load under the non-idle state; S312': judging whether the load is lower than a preset load, if yes, the condition of updating the parity bit is met, and step S4 is performed; if no, step S1 is performed.

7. The method of updating a parity check code according to claim 5 or 6, wherein The step S4 comprises: S41: if yes, sorting the update duration of the flag bit in all strips, reading the data in the strip with the longest update duration, and calculating the corresponding parity code, and updating the calculated parity code to the parity bit of the strip, and changing the flag bit of the strip to the second state to indicate that the parity bit of the corresponding strip is in the valid state.

8. The method of updating a parity code according to claim 7, wherein, The step S41 comprises: S411: in the process of updating the parity bit, detecting whether a new write instruction is received, if yes, step S2 is performed, if no, reading and calculating the parity code corresponding to all strips, and updating the calculated parity code to the parity bit of the strip, and changing the flag bit of the strip to the second state to indicate that the parity bit of the corresponding strip is in the valid state.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to realize the operations in the parity code updating method of any one of claims 1-8.

10. A solid state drive, comprising: The solid state disk comprises a controller and a storage area, the controller comprises an exclusive or operation module, the storage area comprises a RAID system, the RAID system uses the parity code updating method of any one of claims 1-8 to update the parity code in the strip of the RAID system, and the exclusive or operation module calculates the data in the strip to obtain the parity code to be updated.

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