Fast synchronous clock switching system based on digital phase locking

Abstract

The invention discloses a fast synchronous clock switching system based on digital phase locking, which belongs to the field of clock signal switching and comprises a clock monitoring unit, a clock switching unit, a clock conditioning unit, a clock synchronization unit and a clock distribution unit. The clock monitoring unit is used for monitoring the input state of an external input clock and synchronously forwarding the input state to the clock synchronization unit; the clock switching unit switches an external input clock channel according to an instruction issued by the clock synchronization unit; the clock conditioning unit is used for conditioning an input clock signal; the clock synchronization unit calibrates an external input clock and an overall synchronization signal through a digital phase-locked loop, so that the external input clock and the overall synchronization signal are quickly synchronized; and the clock distribution unit distributes multiple paths of synchronous clocks according to the input clock of the clock distribution unit, and synchronously calibrates the multiple paths of synchronous clocks. According to the invention, rapid switching can be completed, phase noise degradation is suppressed, digital phase-locked closed-loop synchronization is supported, and the working stability and reliability of the whole system are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of clock signal switching, in particular to a fast synchronous clock switching system based on digital phase-locked loop. BACKGROUND

[0002] In the fields of modern communication systems, radars, high-speed data acquisition and precision instruments, the stability and reliability of clock signals are crucial, especially for high-speed and high-frequency application scenarios, which often require clock to reach an ultra-low phase noise level of-150dBc / Hz@1MHz offset order. It is difficult to achieve the existing technical level.

[0003] For high-reliability application scenarios, multiple redundant clock designs are usually involved, and the system controls the switching of multiple clock channels according to the priority of the strategy. There are many traditional multi-channel clock switching methods, but they are prone to cause clock phase jumps, generate transient glitches, worsen phase noise, and cause inter-channel crosstalk. There is a lack of effective closed-loop calibration mechanism, and the clock synchronization accuracy gradually deteriorates after long-term work, making it difficult to ensure system stability. Therefore, how to realize the stability of multi-clock switching scheme still needs further research. SUMMARY

[0004] The purpose of the present application is to provide a fast synchronous clock switching system based on digital phase-locked loop to solve the problems in the background art.

[0005] To solve the above technical problems, the present application provides a fast synchronous clock switching system based on digital phase-locked loop, which comprises a clock monitoring unit, a clock switching unit, a clock conditioning unit, a clock synchronization unit and a clock distribution unit.

[0006] The clock monitoring unit monitors the input state of the external input clock Clkin1 and Clkin2 and synchronously forwards it to the clock synchronization unit.

[0007] The clock switching unit switches the external input clock channel according to the instruction issued by the clock synchronization unit.

[0008] The clock conditioning unit is used to condition the clock signal input by the clock switching unit.

[0009] The clock synchronization unit calibrates the external input clock and the overall synchronization signal Sync Clk through digital phase-locked loop, so as to quickly synchronize the external input clock and the overall synchronization signal Sync Clk.

[0010] The clock distribution unit distributes multiple synchronous clocks according to application requirements and input clocks, and synchronously calibrates them.

[0011] In an embodiment, the clock monitoring unit is composed of a detector, when the external clock is input, the detector monitors the signal change, when the clock synchronization unit detects the change of the monitoring signal, the output channel is switched according to the application program; when the clock monitoring unit has no external clock input, the monitoring signal output of the detector is the default level.

[0012] In an embodiment, the monitoring signal of the detector in the clock monitoring unit is an analog quantity, if the clock synchronization unit does not have an analog acquisition function, the analog level is converted into a digital level 1 or 0 that can be recognized by the clock synchronization unit through a comparator; if the clock synchronization unit has an analog acquisition function, the monitoring signal of the detector is matched with the analog voltage detection range of the clock synchronization unit by adding a voltage dividing circuit.

[0013] In an embodiment, the clock switching unit includes a first radio frequency switch, a second radio frequency switch, and a third radio frequency switch; the first radio frequency switch and the second radio frequency switch are connected in parallel, and then connected in series with the third radio frequency switch.

[0014] In an embodiment, the clock conditioning unit includes a low noise amplifier and a π-decay circuit, and the input power needs to be filtered to avoid deteriorating the phase noise index.

[0015] In an embodiment, the clock synchronization unit has a logic processing function and a digital phase-locked function.

[0016] The logic processing function is used to control the channel switching of the external input clock of the clock switching unit, when the single channel of the external clock is input, the single channel input clock is selected as the system input clock; when the double channels of the external clock are simultaneously input, the input clock channel is switched according to the priority set by the application program.

[0017] The digital phase-locked function is according to the clock synchronization demand of the system, the input clock of the clock synchronization unit is the output clock of the clock distribution unit, when the clock enters the clock synchronization unit, the internal synchronization clock is obtained after the digital phase-locked frequency division and frequency multiplication processing, the phase difference between the internal synchronization clock and the overall synchronization signal is measured by the phase-locked phase discriminator, the phase shifter of the clock distribution unit is controlled to ensure the periodic alignment of the two signals, so as to ensure the real-time synchronization of the output clock of the clock distribution unit and the overall synchronization signal, and realize the one-time synchronization calibration.

[0018] In an embodiment, one of the output clocks of the clock distribution unit is fed back to the clock synchronization unit, and the synchronization relationship is adjusted according to the clock edge alignment parameter between the feedback clock and the overall synchronization signal by the clock synchronization unit, so as to realize the one-time synchronization calibration.

[0019] In an embodiment, the clock distribution unit is provided with a single clock delay function, when each output clock Clk1, Clk2, …, CLKN is inconsistent with the synchronization delay requirement, the secondary synchronization calibration is realized through the auxiliary adjustment of the delay function.

[0020] In an embodiment, the fast synchronous clock switching system based on digital phase-locked loop further comprises a power supply unit for providing low noise power supply for the whole system.

[0021] The application provides a fast synchronous clock switching system based on digital phase-locked loop, which realizes the fast switching function among multiple input clocks through the cooperative work of comparators, digital phase-locked loops, phase detectors, phase shifters, distributors and power supplies. The whole switching system can be adjusted according to the actual situation of the clock synchronization unit and the number of input paths. The application can complete fast switching, suppress phase noise degradation and support digital phase-locked loop closed loop synchronization, and improves the working stability and reliability of the whole system. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a structure schematic diagram of a fast synchronous clock switching system based on digital phase-locked loop provided by the application.

[0023] Figure 2 is a flow schematic diagram of an internal and external clock automatic switching method provided by the application.

[0024] Figure 3 is a structure schematic diagram of a clock switching unit provided by the application.

[0025] Figure 4 is a structure schematic diagram of a clock monitoring unit / clock synchronization unit provided by the application.

[0026] Figure 5 is a time difference measurement principle schematic diagram provided by the application. DETAILED DESCRIPTION

[0027] The application provides a fast synchronous clock switching system based on digital phase-locked loop, which is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the application.

[0028] The application provides a fast synchronous clock switching system based on digital phase-locked loop, which is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the application. Figure 1 The application provides a fast synchronous clock switching system based on digital phase-locked loop, which is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the application.

[0029] The clock monitoring unit is used for monitoring the input state of the external input clock Clkin1, Clkin2, and synchronously forwarding to the clock synchronization unit; the clock switching unit switches the external input clock channel according to the instruction issued by the clock synchronization unit; the clock conditioning unit is used for conditioning the input clock signal and processing to the clock distribution unit; the clock synchronization unit calibrates the external input clock CLK0 and the overall synchronization signal Sync Clk through digital phase locking, so that the external input clock is quickly synchronized with the overall synchronization signal Sync Clk; the clock distribution unit distributes the multi-way synchronous clock according to the input clock of the unit, and synchronously calibrates. The power supply unit provides low-noise power supply for the whole system.

[0030] As shown in Figure 2 The flowchart of the automatic switching method of the internal and external clock is shown. The system includes two external input clocks Clkin1 and Clkin2, the clock monitoring unit monitors the state of the external input clock in real time, the clock synchronization unit completes the corresponding logic processing according to the real-time feedback information Logic Level1 and Logic Level2 of the clock monitoring unit, controls the clock switching unit to switch the external input clock channel, and the output clock of the clock switching unit after the channel switching is output to the clock conditioning unit after gain amplification and other processing, and then output to the clock distribution unit. The clock distribution unit is controlled by the clock synchronization unit to complete the multi-way target clock output, the clock synchronization is realized through the processes of phase locking, phase discrimination and phase shifting between the Clk0 fed back to the clock synchronization unit by the clock distribution unit and the overall synchronization signal, the clock distribution unit can assist in adjusting the single-channel delay, and the whole power supply system is provided by the low-dropout linear regulator (LDO).

[0031] As an embodiment of the present application, as shown in Figure 3 The clock switching unit is composed of at least three single-pole double-throw radio frequency switches: the first-level switch includes two radio frequency switches (first-level switch 1 and first-level switch 2), each radio frequency switch corresponds to an external input clock, that is, the first-level switch 1 corresponds to Clkin1, and the first-level switch 2 corresponds to Clkin2; the radio frequency switch is composed of two channels, which are connected with the external input clock Clkin1 / Clkin2 and the ground, respectively, when the system selects the first-level switch 1 as the external input clock, the output channel of the first-level switch 1 needs to be connected to Channel2, and vice versa, thereby reducing the mutual crosstalk between the clocks; the second-level switch is composed of one radio frequency switch, Channel1 and Channel2 of the second-level switch correspond to the output ClkinCH1 of the first-level switch 1 and the output ClkinCH2 of the first-level switch 2, respectively, and the system selects the external input clock through the selection signal Sel_3, and finally outputs to the clock conditioning unit.

[0032] As an embodiment of the present application, as shown in Figure 4As shown, the clock monitoring unit is composed of a detector and a comparator, when there is no external input clock, the detector outputs a default voltage, when there is an external input clock, the detection level changes with the amplitude of the external input clock (Clkin1, Clkin2). The detection level is sent to the comparator to compare with the comparison level, and then the comparison result is output to the clock synchronization unit.

[0033] In particular, when the clock synchronization unit has an analog voltage acquisition function, the comparator circuit part can be omitted, and the rest of the design remains unchanged.

[0034] As an embodiment of the present application, please continue to refer to Figure 4 The core of the clock synchronization unit is FPGA, which has frequency divider and phase detector functions inside, and the frequency division and phase detection are completed based on the phase-locked loop. When the feedback clock Clk0 of the clock distribution unit enters the phase detector through the phase-locked loop and frequency divider, the feedback clock Clk0 and the overall synchronization clock Sync Clk are phase-detected in real time, and then the phase shifter adjusts the phase according to the phase detection result and the pre-set synchronization threshold, to ensure that the output clock signals Clk0-ClkN are phase-aligned with the overall synchronization clock Sync Clk.

[0035] As an embodiment of the present application, as shown in Figure 5 The phase detector can be an internal phase detector of FPGA, or a special clock measurement chip (TDC), thereby realizing high-precision time difference measurement, and the measurement accuracy is as high as 80ps. In actual application, FPGA constructs an intermediate signal, and TDC measures Δt1 and Δt2 respectively, that is, Δt:

[0036] Δt=Δt2-Δt1

[0037] The obtained phase difference data Δt needs to be compared with the system set threshold, if it exceeds the threshold, the phase difference is compensated to the phase detector in the loop, and after phase shifting and phase locking, Δt returns to the range within the set threshold.

[0038] The above description is only a description of the preferred embodiment of the present application, and does not limit the scope of the present application. Any modification or modification made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A fast-synchronizing clock switching system based on digital phase locking, characterized by, The clock monitoring unit, the clock switching unit, the clock conditioning unit, the clock synchronization unit, and the clock distribution unit are included. The clock monitoring unit monitors the input state of the external input clock Clkin1 and Clkin2 and synchronously forwards to the clock synchronization unit. The clock switching unit switches the external input clock channel according to the instruction issued by the clock synchronization unit. The clock conditioning unit is used for conditioning the clock signal input by the clock switching unit. The clock synchronization unit calibrates the external input clock with the overall synchronization signal Sync Clk through digital phase-locked demarcation, so that the external input clock is quickly synchronized with the overall synchronization signal Sync Clk. The clock distribution unit distributes multiple synchronous clocks according to the application requirement and the input clock and synchronously calibrates.

2. A digital phase lock based fast synchronization clock switching system as recited in claim 1, wherein, The clock monitoring unit is composed of a detector. When the external clock is input, the detector monitors the signal change. When the clock synchronization unit detects the monitoring signal change, the output channel is switched according to the application program. When there is no external clock input, the monitoring signal output of the detector is the default level.

3. A digital phase lock based fast synchronization clock switching system as recited in claim 2, wherein, The monitoring signal of the detector in the clock monitoring unit is an analog quantity. If the clock synchronization unit does not have an analog acquisition function, the analog level is converted into a digital level 1 or 0 that can be recognized by the clock synchronization unit through a comparator. If the clock synchronization unit has an analog acquisition function, the monitoring signal of the detector is increased by a voltage dividing circuit to match the analog voltage detection range of the clock synchronization unit.

4. The digital phase lock based fast synchronization clock switching system as recited in claim 1, wherein, The clock switching unit includes a first radio frequency switch, a second radio frequency switch, and a third radio frequency switch. The first radio frequency switch and the second radio frequency switch are connected in parallel and are connected in series with the third radio frequency switch.

5. The digital phase lock based fast synchronization clock switching system as recited in claim 1, wherein, The clock conditioning unit includes a low-noise amplifier and a π-decay circuit. The input power needs to be filtered to avoid deteriorating the phase noise index.

6. The digital phase lock based fast synchronization clock switching system as recited in claim 1, wherein, The clock synchronization unit has a logic processing function and a digital phase-locked function. The logic processing function is used for controlling the channel switching of the external input clock of the clock switching unit. When the external clock is input in a single channel, the single channel input clock is selected as the system input clock. When the external clock is input in a double channel, the input clock channel is switched according to the priority set by the application program. The digital phase-locked function is used for ensuring the real-time synchronization of the output clock of the clock distribution unit with the overall synchronization signal. The input clock of the clock synchronization unit is the output clock of the clock distribution unit. After the digital phase-locked frequency division and frequency multiplication, the internal synchronization clock is obtained. The phase difference between the internal synchronization clock and the overall synchronization signal is measured by a phase-locked phase detector. The phase shifter of the clock distribution unit is controlled to ensure the periodic alignment of the two signals, so that the output clock of the clock distribution unit is synchronized with the overall synchronization signal in real time, and the one-time synchronization calibration is realized.

7. The digital phase lock based fast synchronization clock switching system as claimed in claim 1, wherein, One of the output clocks of the clock distribution unit is fed back to the clock synchronization unit. The clock synchronization unit adjusts the synchronization relationship according to the clock edge alignment parameter between the feedback clock and the overall synchronization signal, so that the one-time synchronization calibration is realized.

8. The digital phase lock based fast synchronization clock switching system as claimed in claim 1, wherein, The clock distribution unit has a single clock delay function. When the synchronization delay requirements of each output clock Clk1, Clk2, …, CLKN are inconsistent, the function is used for auxiliary adjustment, so that the two-time synchronization calibration is realized.

9. The digital phase lock based fast synchronization clock switching system as claimed in claim 7, wherein, The digital phase lock based fast synchronization clock switching system further comprises a power supply unit for providing low noise power supply for the whole system.

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