Communication circuit for reducing recoil noise of eye open monitor

Abstract

A communication circuit for reducing recoil noise of an eye open monitor comprises a first sampler, a second sampler and a pre-amplifier, the first output end and the second output end of the pre-amplifier are connected with the first input end and the second input end of the first sampler respectively, and the first input end and the second input end of the second sampler are connected with the first output end and the second output end of the pre-amplifier respectively. An input signal is applied to the preamplifier and a first input of the second sampler, respectively, and when an edge of the sub-clock precedes an edge of the master clock, the first sampler samples a data value by comparing the input signal with a second reference voltage at the edge of the sub-clock, the second sampler samples a data value by comparing the input signal with a first reference voltage at an edge of the master clock, and when an edge of the sub-clock lags the edge of the master clock, the second sampler samples a data value by comparing the input signal with a second reference voltage at an edge of the sub-clock, a first sampler samples a data value by comparing an input signal to a first reference voltage at an edge of a master clock.

Description

Technical Field

[0001] This disclosure relates to a communication circuit for reducing recoil noise in an eye-opening monitor. Background Technology

[0002] An eye opening monitor (EOM) is a tool used to evaluate the signal quality of high-speed signal transmitting and receiving devices or systems. Specifically, an EOM can quantitatively measure the performance of a communication channel, and the reliability of the communication system and data can be improved based on the data measured using the EOM. EOMs are mainly classified into 1D (checking signal quality on the time or voltage axis) and 2D (checking signal quality on the time and voltage axis) types, and the appropriate type can be selected based on the application and requirements.

[0003] In high-speed interface circuits, the eye of a signal is crucial for determining channel effects, system debugging, and signal integrity. Furthermore, during EOM (Extended Operating Memory) execution, the backlash from the previous clock cycle can enter the input of another sampler, potentially causing changes in the sampler's output value. Therefore, measures are needed to address this issue. See also... Figure 7 When a comparator is operating, a backlash occurs at the input signal terminal according to the clock signal. For eye-opening monitors, two or more comparators must be used, and the operating clock sequence of each comparator is different. Therefore, the backlash caused by the comparator that operates first may affect the other comparator.

[0004] The aforementioned background technology refers to technical information that the inventor possesses or obtains in the process of deriving the content of this disclosure, and does not necessarily mean that it is known technology that was disclosed to the public before the application for this disclosure was filed.

[0005] Citation List

[0006] Patent documents

[0007] (Patent Document 1) KR10-2275636 Summary of the Invention

[0008] One aspect of this disclosure is to provide a communication circuit capable of eye diagram monitoring while reducing backlash noise.

[0009] Another aspect of this disclosure is that it can reduce power consumption on the receiving side while also reducing recoil noise.

[0010] To achieve the above object, the embodiment of the present disclosure designs a communication circuit for reducing the kickback noise of an eye open monitor, the eye open monitor circuit is configured to measure information for generating an eye diagram for at least one point of a transmitting device or a receiving device, the communication circuit can comprise: a first sampler, a second sampler and a preamplifier, wherein the first and second outputs of the preamplifier are connected to the first and second inputs of the first sampler respectively, an input signal is applied to the first input of the preamplifier and the second sampler respectively, when the edge of a sub-clock precedes the edge of a main clock, the first sampler samples a data value by comparing the input signal with a second reference voltage at the edge of the sub-clock, and the second sampler samples a data value by comparing the input signal with a first reference voltage at the edge of the main clock, when the edge of the sub-clock lags behind the edge of the main clock, the second sampler samples a data value by comparing the input signal with the second reference voltage at the edge of the sub-clock, and the first sampler samples a data value by comparing the input signal with the first reference voltage at the edge of the main clock.

[0011] The communication circuit can further comprise: a first multiplexer, the output of which is connected to the second input of the preamplifier; a second multiplexer, the output of which is connected to the second input of the second sampler; a third multiplexer, the output of which is connected to the clock input of the first sampler; a fourth multiplexer, the output of which is connected to the clock input of the second sampler; a reference voltage generator, which generates the second reference voltage; and a phase interpolator, which generates the sub-clock, the first reference voltage is applied to the first input of the first multiplexer and the second multiplexer respectively, the second reference voltage is applied to the second input of the first multiplexer and the second multiplexer respectively, the main clock is applied to the first input of the third multiplexer and the fourth multiplexer respectively, and the sub-clock is applied to the second input of the third multiplexer and the fourth multiplexer respectively.

[0012] In addition, the communication circuit can further comprise: a retimer, which adjusts the timing of the output values of the first sampler and the second sampler to output the adjusted timing; and an XOR gate, which compares the output values of the retimer.

[0013] Further, the communication circuit can further include an XOR gate comparing the output value of the first sampler with the output value of the second sampler, and a flip-flop connected to an output of the XOR gate, wherein the flip-flop performs a function of selecting valid data other than garbage data from the output value of the XOR gate, the garbage data being generated due to a timing difference between the output value of the first sampler and the output value of the second sampler.

[0014] Further, the communication circuit can further include a post-processing device for eliminating a time axis error of the eye pattern caused by a delay time of the preamplifier through post-processing.

[0015] According to the embodiment of the disclosure, it is possible to provide a useful effect of being able to perform eye pattern monitoring in a high-speed communication environment while reducing kickback noise.

[0016] Further, according to another embodiment of the disclosure, it is possible to reduce power consumption at a receiving side while reducing kickback noise. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a graph for explaining an eye pattern;

[0018] Figure 2 is a graph schematically showing a communication circuit for reducing kickback noise of an eye open monitor according to an embodiment of the disclosure;

[0019] Figure 3 is a graph for explaining a relationship between a master clock and a slave clock;

[0020] Figure 4 is a graph for explaining an eye open monitoring circuit of a communication circuit for reducing kickback noise of an eye open monitor according to an embodiment of the disclosure;

[0021] Figure 5 is a graph for explaining an eye open monitoring circuit of a communication circuit for reducing kickback noise of an eye open monitor according to another embodiment of the disclosure;

[0022] Figure 6 is a graph for explaining signal timing of a communication circuit for reducing kickback noise of an eye open monitor according to an embodiment of the disclosure; and

[0023] Figure 7 is a graph for explaining kickback noise.

[0024] REFERENCE NUMERALS:

[0025] 2000: Communication circuit for reducing kickback noise of an eye open monitor

[0026] 2110: first sampler 2120: second sampler

[0027] 2130: preamplifier 2210: first multiplexer

[0028] 2220: second multiplexer 2230: reference voltage generator

[0029] 2310: third multiplexer 2320: fourth multiplexer

[0030] 2410, 2420: fifth multiplexer 2330: phase interpolator

[0031] 2500: eye opening monitoring circuit 2510: first flip-flop

[0032] 2520: second flip-flop 2530: XOR gate

[0033] 2540: counter 2560: third flip-flop

[0034] 2600: eye pattern generation unit MCLK: master clock

[0035] PCLK: sub clock DETAILED DESCRIPTION

[0036] The advantages and features of the present disclosure and a method of achieving the same will be clearly understood from the embodiments described below in detail in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. The embodiments are provided to perfect the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art. Throughout the specification, like drawing reference numerals represent the same elements.

[0037] It should be noted that the terms used herein are only used to describe the embodiments, and are not intended to limit the present disclosure. In the specification, unless explicitly stated otherwise, the singular form also includes the plural form. The terms "include" and / or "comprise" used in the specification are intended to express elements, steps, operations, and / or devices, and do not exclude the presence or addition of one or more other elements, steps, operations, and / or devices.

[0038] Although first, second, and the like are used to describe various devices or elements, the devices or elements are of course not limited to these terms. These terms are only used to distinguish one device or element from other devices or elements. Therefore, the first device or element mentioned below can of course be the second device or element within the technical concept of the present disclosure.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification are to be interpreted as is customary in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0040] Hereinafter, the configuration and operation effect of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0041] Figure 1 is a graph for explaining an eye pattern, Figure 2 is a graph schematically showing a communication circuit 2000 for reducing bounce noise of an eye open monitor according to an embodiment of the present disclosure, Figure 3 is a graph for explaining a relationship between a master clock MCLK and a slave clock PCLK, Figure 4 is a graph for explaining an eye open monitoring circuit 2500 of a communication circuit 2000 for reducing bounce noise of an eye open monitor according to an embodiment of the present disclosure, Figure 5 is a graph for explaining an eye open monitoring circuit 2500 of a communication circuit 2000 for reducing bounce noise of an eye open monitor according to another embodiment of the present disclosure, Figure 6 is a graph for explaining a signal timing of a communication circuit 2000 for reducing bounce noise of an eye open monitor according to an embodiment of the present disclosure, and Figure 7 is a graph for explaining bounce noise.

[0042] Referring to Figure 1 , a transmitter 1 and a receiver 2 can be connected in a wired manner through a communication channel 3. Figure 1 shows the shape of an eye pattern at a point observed by an eye open monitor 4 in Figure 1 and its related terms.

[0043] In one embodiment, Figure 2 The communication circuit 2000 for reducing bounce noise of an eye open monitor shown in FIG. 1 can include an eye open monitoring circuit 2500, and the eye open monitoring circuit 2500 can include a device for monitoring a waveform for a specific point of a signal receiving circuit. The eye open monitoring circuit 2500 can operate by receiving a clock signal, sample a waveform of a point to which the eye open monitor 4 is connected, and output a result thereof. Figure 1The eye opening monitor 4 shown is provided at the receiving end side for observing a distorted signal passing through a communication channel, but the scope of the present disclosure is not limited thereto. Further, the eye opening monitoring circuit 2500 can receive a signal between the equalizer and the clock data recovery circuit to monitor the eye opening. By monitoring the eye opening in this way, an eye pattern can be obtained, and this eye pattern can be utilized inside the receiver, for example, for adjusting the setting value of the equalizer. In addition, information related to the eye pattern can be provided to a PC or the like and used for purposes such as post-processing data of the input signal.

[0044] The communication circuit 2000 with reduced kickback noise of the eye opening monitor according to an embodiment of the present disclosure includes a first sampler 2110, a second sampler 2120, and a preamplifier 2130. In one embodiment, the communication circuit 2000 with reduced kickback noise of the eye opening monitor can further include a first multiplexer 2210, a second multiplexer 2220, a third multiplexer 2310, a fourth multiplexer 2320, a reference voltage generator 2230, a phase interpolator 2330, an XOR gate 2530, a counter 2540, and the like.

[0045] In one embodiment, the first sampler 2110 and the second sampler 2120 can each include a comparator. Here, one of the first sampler 2110 and the second sampler 2120 can output a result of comparing the input signal VI with a first reference voltage Vcm, and the other can output a result of comparing the input signal VI with a second reference voltage. In one embodiment, sampling can be performed by comparing the input signal with the first reference voltage at an edge of a main clock MCLK, and sampling can be performed by comparing the input signal with the second reference voltage at an edge of a sub clock PCLK. In one embodiment, when the edge of the sub clock PCLK precedes the edge of the main clock MCLK (when the edge of the sub clock is located in a region Al of Figure 3 of the preamplifier 2130 is connected to the input terminal. In addition, when the edge of the sub clock PCLK lags behind the edge of the main clock MCLK (when the edge of the sub clock is located in a region A2 of Figure 3In the case of the area A2, the main clock MCLK can be applied to a sampler connecting the output of the preamplifier 2130 to the input. In one embodiment, the preamplifier 2130 can receive the input signal and the first reference voltage and output it as is or after amplification. Meanwhile, the main clock MCLK can be a clock used by the receiver to recover data from the input signal. Also, the sub-clock PCLK can be used to search for the boundary line of the eye pattern and can be generated by a phase interpolator (PI) or the like. In the communication circuit 2000 according to the embodiment of the present application, which reduces the kickback noise of the eye opening monitor, the eye opening can be monitored in such a manner that the second reference voltage is changed while searching for the boundary line of the eye pattern at an arbitrary phase, the phase is changed when the boundary line is confirmed at the corresponding phase, and then the boundary line is searched again. Meanwhile, the data sampled by either of the first sampler 2110 and the second sampler 2120 by receiving the main clock MCLK can be used as the received data Do. To this end, the first sampler 2110 and the second sampler 2120 can be connected to fifth multiplexers 2410, 2420, which can receive a separate control signal to adjust the output value, and the control signal can be generated corresponding to the lead-lag relationship between the main clock MCLK and the sub-clock PCLK to be applied to the fifth multiplexers 2410, 2420.

[0046] In one embodiment, the first and second outputs of the preamplifier 2130 can be connected to the first and second inputs of the first sampler 2110, respectively. Also, the input signal can be applied to the first input of the preamplifier 2130, and the first or second reference voltage can be applied to the second input of the preamplifier 2130. To this end, the output of the first multiplexer 2210 can be connected to the second input of the preamplifier 2130, and the first and second reference voltages can be applied to the first and second inputs of the first multiplexer 2210, respectively. Here, the second reference voltage can be generated by the reference voltage generator 2230, and the output of the reference voltage generator 2230 can be connected to the second input of the first multiplexer 2210.

[0047] In one embodiment, the input signal can be applied to the first input of the second sampler 2120, and the first or second reference voltage can be applied to the second input of the second sampler 2120. To this end, the output of the second multiplexer 2220 can be connected to the second input of the second sampler 2120, and the first and second reference voltages can be applied to the first and second inputs of the second multiplexer 2220, respectively. Here, the second reference voltage can be generated by the reference voltage generator 2230, and the output of the reference voltage generator 2230 can be connected to the second input of the second multiplexer 2220.

[0048] In one embodiment, the output terminals of the third multiplexer 2310 and the fourth multiplexer 2320 can be connected to the clock input terminals of the first sampler 2110 and the second sampler 2120, respectively. In addition, a master clock MCLK can be applied to the first input terminals of the third multiplexer 2310 and the fourth multiplexer 2320, respectively, and a sub clock PCLK can be applied to the second input terminals of the third multiplexer 2310 and the fourth multiplexer 2320, respectively.

[0049] In one embodiment, when the edge of the sub clock PCLK precedes the edge of the master clock MCLK, the first sampler 2110 can sample the data value by comparing the input signal with the second reference voltage at the edge of the sub clock PCLK, and the second sampler 2120 can sample the data value by comparing the input signal with the first reference voltage at the edge of the master clock MCLK.

[0050] In one embodiment, when the edge of the sub clock PCLK lags behind the edge of the master clock MCLK, the second sampler 2120 can sample the data value by comparing the input signal with the second reference voltage at the edge of the sub clock PCLK, and the first sampler 2110 can sample the data value by comparing the input signal with the first reference voltage at the edge of the master clock MCLK.

[0051] In one embodiment, the first to fourth multiplexers can receive a separate control signal to adjust the output value, and the control signal can be applied to the first to fourth multiplexers to correspond to the lead-lag relationship between the master clock MCLK and the sub clock PCLK.

[0052] In one embodiment, the output value of the first sampler 2110 and the output value of the second sampler 2120 can be provided to the eye opening monitor circuit 2500 for eye opening monitoring.

[0053] Accordingly, the preamplifier 2130 can prevent the phenomenon in which the kickback generated by the pre-clock enters the input terminal of the sampler using the lag clock, and as a result, the communication circuit 2000 capable of performing eye pattern monitoring while reducing kickback noise can be implemented. Here, in one embodiment of the present disclosure, the time axis error of the eye pattern due to the delay time of the preamplifier 2130 can be removed by post-processing. Here, the post-processing process can be performed by a post-processing device such as the eye pattern generation unit 2600.

[0054] In one embodiment, after the eye opening monitoring is completed, the operation of the elements other than the elements on the path for data reception among the elements for eye opening can be suspended, thereby allowing the data receiver to operate with low power consumption. That is, according to one embodiment of the present disclosure, the kickback noise can be reduced by using the pre-amplifier 2130, and the power consumption can be reduced.

[0055] In one embodiment, the middle value of the input signal can be set as the first reference voltage. For example, if the minimum value of the input signal is 0V and the maximum value of the input signal is 100mV, 50mV can be set as the first reference voltage. However, if it is a value between the minimum value and the maximum value of the input signal, a value other than the middle value can be set as the first reference voltage. However, in this case, the accuracy of the judgment can be relatively reduced. In one embodiment, the second reference voltage can be set to deviate from the first reference voltage. In another embodiment, the second reference voltage can be set independently of the first reference voltage. In addition, the second reference voltage can be generated by the reference voltage generator 2230, and when a control command signal output from the control logic block 2570 is applied to the reference voltage generator 2230, the reference voltage generator 2230 can set or change the second reference voltage to correspond to the control command signal. In one embodiment, the reference voltage generator 2230 can be implemented with a digital analog converter (DAC) such as a register DAC. In another embodiment, an additional element can be provided to generate an offset in the differential input transistor in which the comparison is performed inside the sampler (comparator), and a voltage offset can be generated by adjusting the bias current thereof.

[0056] Meanwhile, in Figure 2 the first reference voltage Vcm can be a single-ended signal or a differential signal. In one embodiment, when the first reference voltage Vcm is a single-ended signal, a reference input voltage must be present, and when the first reference voltage Vcm is a differential signal, the reference input voltage can be 0. In the communication circuit 2000 for reducing kickback noise according to an embodiment of the present disclosure, the first reference voltage is not limited to a single-ended signal, but can also be a differential signal.

[0057] In one embodiment, the communication circuit 2000 for reducing kickback noise can include an eye opening monitoring circuit 2500, and the eye opening monitoring circuit 2500 can include a first flip-flop 2510, a second flip-flop 2520, a comparison block, a counter 2540, etc. In one embodiment, the comparison block can be implemented as an XOR gate 2530, but is not limited thereto.

[0058] Referring to Figure 4, the eye opening monitoring circuit 2500 can include a first flip-flop 2510, a second flip-flop 2520, an XOR gate 2530, and a counter 2540. The first flip-flop 2510 and the second flip-flop 2520 can be connected to outputs of the first sampler 2110 and the second sampler 2120, respectively, and outputs of the first flip-flop 2510 and the second flip-flop 2520 can be connected to inputs of the XOR gate 2530. The counter 2540 can be connected to an output of the XOR gate 2530. In an embodiment, the XOR gate 2530 can compare two input values to output a comparison result. For example, the XOR gate 2530 can output 0 when the two input values are the same, and output 1 when the two input values are different, and the counter 2540 can count the number of 1s, and thus a value counted by the counter 2540 can be provided to the eye diagram generation unit 2600, etc. In an embodiment, the eye diagram generation unit 2600 can be implemented using a computer, etc. In an embodiment, outputs of the first sampler 2110 and the second sampler 2120 can be received by the first flip-flop 2510 and the second flip-flop 2520, respectively, and outputs of the first flip-flop 2510 and the second flip-flop 2520 can be adjusted by clock signals provided to the first flip-flop and the second flip-flop, and thus a problem caused by a timing difference between the output value of the first sampler and the output value of the second sampler can be solved. In this regard, the first flip-flop and the second flip-flop can be referred to as a retimer for adjusting a timing of the output value of the first sampler and the output value of the second sampler. An error caused by a timing difference between the output value of the first sampler and the output value of the second sampler can be prevented.

[0059] In another embodiment, referring to Figure 5 and Figure 6 , the respective outputs of the first sampler 2110 and the second sampler 2120 can be connected to the XOR gate 2530, and a third flip-flop 2560 can be connected to an output of the XOR gate 2530. In this regard, a clock signal provided to the third flip-flop 2560 can be adjusted to prevent an error caused by a timing difference between the output value of the first sampler 2110 and the output value of the second sampler 2120. In this regard, the timing difference between the output value of the first sampler 2110 and the output value of the second sampler 2120 can be caused by the timing difference Td1 between the master clock MCLK and the sub clock PCLK, and due to the timing difference, garbage data D1 can be generated at an output of the XOR gate 2530, and the third flip-flop 2560 can perform a function of outputting valid data D2 by removing the garbage data D1 from the comparison result value output from the XOR gate 2530.

[0060] In high-speed interface circuits, signal eye is critical for determining channel impact, system debugging and signal integrity. Since it is difficult to inspect the signal eye diagram from outside the chip in a chiplet interface, an eye open monitor (EOM) implemented on the chip can be used to test signal integrity on-chip. In one embodiment, the EOM can be implemented by sampling the input signal with two samplers in the receiving circuit and comparing the results. Here, one of the two samplers can sample the input signal, and the other sampler can sample the input signal by changing the reference voltage and clock. If the results of the two samplers are the same, the comparison result is 0, and if the results are different, the comparison result is 1. By counting the number of 1s, the boundary of the signal can be found. However, since the working clocks of the two samplers are different, the back-pulse generated by the previous clock can enter the input end of the other sampler, causing the output value of the sampler to change, so it is very important to eliminate the impact of the back-pulse. According to one embodiment of the present disclosure, the preamplifier 2130 can be used to block the impact of the previous clock, thereby performing eye open monitoring while reducing back-pulse noise. In addition, after the eye open monitoring is completed, the sampling for eye open monitoring can be stopped, and the operation of the elements in the eye open element except for the elements in the data receiving path can be suspended, thereby reducing the power consumption of the data receiver.

[0061] The present disclosure has been described above with reference to the embodiments shown in the drawings, but the embodiments are merely exemplary and are not limited to the above-described embodiments, and those skilled in the art should understand that various modifications and other embodiments equivalent thereto can be made. Therefore, the true protection scope of the present disclosure should be determined only by the appended claims.

Claims

1. A communication circuit that reduces kickback noise of an eye open monitor, comprising an eye open monitor circuit configured to measure information used to generate an eye pattern for at least one point of a transmitting device or a receiving device, the communication circuit comprising: a first sampler (2110), a second sampler (2120), and a preamplifier (2130), wherein first and second outputs of the preamplifier are connected to first and second inputs of the first sampler, respectively, wherein an input signal (VI) is applied to a first input of the preamplifier and the second sampler, respectively, wherein when an edge of a sub-clock (PCLK) precedes an edge of a main clock (MCLK), the first sampler samples a data value by comparing the input signal to a second reference voltage at the edge of the sub-clock, and the second sampler samples a data value by comparing the input signal to a first reference voltage (Vcm) at the edge of the main clock, and wherein when the edge of the sub-clock lags behind the edge of the main clock, the second sampler samples a data value by comparing the input signal to the second reference voltage at the edge of the sub-clock, and the first sampler samples a data value by comparing the input signal to the first reference voltage at the edge of the main clock.

2. The communication circuit according to claim 1, further comprising: a first multiplexer (2210) whose output is connected to a second input of the preamplifier (2130); a second multiplexer (2220) whose output is connected to a second input of the second sampler (2120); a third multiplexer (2310) whose output is connected to a clock input of the first sampler (2110); a fourth multiplexer (2320) whose output is connected to a clock input of the second sampler (2120); a reference voltage generator (2230) that generates the second reference voltage; and a phase interpolator (2330) that generates the sub-clock, wherein the first reference voltage is applied to first inputs of the first and second multiplexers, respectively, wherein the second reference voltage is applied to second inputs of the first and second multiplexers, respectively, wherein the main clock is applied to first inputs of the third and fourth multiplexers, respectively, and wherein the sub-clock is applied to second inputs of the third and fourth multiplexers, respectively.

3. The communication circuit according to claim 1, further comprising: a retimer that adjusts timing of output values of the first sampler and the second sampler to output adjusted timing; and a comparison block that compares the output values of the retimer.

4. The communication circuit according to claim 1, further comprising: a comparison block that compares output values of the first sampler and the second sampler. ​ ​ and a flip-flop connected to an output of the comparison block, wherein the flip-flop performs a function of selecting valid data other than garbage data from the output value of the comparison block, and wherein the garbage data is generated due to a timing difference between the output value of the first sampler and the output value of the second sampler.

5. The communication circuit according to claim 1, further comprising: a post-processing device that eliminates a time axis error of the eye diagram due to a delay time of the preamplifier by post-processing.

Images