Circular shift registers, data circular shift methods, and storage media

Abstract

This application provides a circular shift register, a data circular shift method, and a storage medium. The circular shift register includes a data input port, a data output port, a control port, and a multi-level processing network. The multi-level processing network is constructed using a hybrid of basic units consisting of 2x2 switching units or 2x1 multiplexers. Each processing unit includes multiple basic units, and the multiple basic units of each processing unit are of the same type. At least two processing units in the entire network use different types of basic units. The multiple basic units of each processing unit are independently controlled by a common control signal generated by the shift control word generation stage, enabling rapid circular shift operations. This circular shift register, with its multi-level parallel processing architecture, significantly improves data processing efficiency. While maintaining ultra-low latency and high parallelism, it reduces the fan-out load of control signals and global interconnect pressure, significantly reducing critical path latency and dynamic power consumption.

Description

Technical Field

[0001] This application relates to the field of communication transmission technology, specifically to a circular shift register, a data circular shifting method, and a storage medium. Background Technology

[0002] In fifth-generation (5G) and future communication systems, channel coding techniques are widely used to combat noise and interference during transmission in order to ensure the reliability of data transmission. Quasi-cyclic low-density parity-check (QC-LDPC) codes have become one of the core coding schemes in 5G and future communication standards due to their excellent error correction performance and structured design that is easy to implement in hardware.

[0003] The hardware decoder for QC-LDPC codes is a key component in implementing this encoding scheme, and its performance directly determines the throughput and latency of the communication system. Among the many operations of this decoder, cyclic shift is its core and frequently executed fundamental operation, the scale of which is determined by the expansion factor Z in the codeword structure. Traditional hardware implementations commonly use barrel shifters, which consist of cascaded log2(Z) level large-scale multiplexers (MUX). However, when the value of Z is large, the selection signal load of each multiplexer stage becomes heavy, and the global interconnects become too long, leading to a significant increase in signal transmission path delay, resulting in excessive critical path delay. Furthermore, the excessively long critical path not only makes timing difficult to converge, limiting further improvements in data processing throughput, but also increases power consumption and layout / routing complexity.

[0004] Therefore, existing implementations based on barrel shifters are insufficient to maintain excellent timing characteristics while meeting the requirements of high-throughput applications, and a low-latency, high-efficiency cyclic shifting hardware architecture is urgently needed. Summary of the Invention

[0005] This application provides a circular shift register, a data circular shifting method, and a storage medium, which can solve the technical problems of excessively long critical paths and tight timing caused by multi-level cascading and global interconnection in traditional barrel shifters.

[0006] In a first aspect, embodiments of this application provide a circular shift register, including:

[0007] The data input port is used to receive an input vector with a bit width of Z;

[0008] The data output port is used to output the result vector after cyclic shifting with a bit width of Z;

[0009] The control port is used to receive shift control words with a bit width of K, where K = log2(Z);

[0010] A multi-level processing network includes K cascaded processing units, each of which contains multiple basic units. The multiple basic units of each processing unit are independently controlled by a common level control signal, which is generated by one or more bits of the shift control word. The multi-level processing network is used to ensure that, under the control of the level control signal, the input vector achieves a cyclic shift of K bits after being selected by the multiple basic units of each processing unit.

[0011] The basic unit includes two types: a 2x2 switching unit and a 2x1 multiplexer. The basic units of each processing unit are of the same type, and at least two processing units use basic units of different types.

[0012] In some embodiments, in the K-level cascaded processing units, the first K-1 levels of processing units adopt an Omega network topology, each level consists of Z / 2 of the 2x2 switching units, and the K-level processing unit consists of Z of the 2x1 multiplexers.

[0013] Bits 0 to K-2 of the shift control word serve as level control signals for the first K-1 level processing units, independently controlling the switching units in the first K-1 level processing units; bit K-1 of the shift control word serves as the level control signal for the K level processing unit, controlling the multiplexer in the K level processing unit.

[0014] In some embodiments, in the first K-1 stage processing units, the interconnection relationship between the k-th stage switching unit and the k+1-th stage switching unit is defined by a perfect shuffle permutation function; where k=1,2,…,K-1.

[0015] In some embodiments, in the K-level cascaded processing units, the first-level processing unit consists of Z 2x1 multiplexers, and the subsequent K-1 level processing units adopt a Banyan network topology, with each level consisting of Z / 2 2x2 switching units;

[0016] The 0th bit of the shift control word serves as the level control signal for the first-level processing unit, controlling the multiplexer in the first-level processing unit; the 1st to K-1th bits of the shift control word serve as the level control signals for the next K-1 level processing units, independently controlling the switching units in the next K-1 level processing units.

[0017] In some embodiments, in the subsequent K-1 level processing unit, the interconnection relationship between the k-th level switching unit and the k+1-th level switching unit is defined by a preset rule; where k=2,3,…,K;

[0018] The preset rules include butterfly displacement, mixed shuffling displacement, or custom displacement rules.

[0019] In some embodiments, each of the 2x2 switching units consists of two 2x1 multiplexers configured in either pass-through or crossover mode according to the stage control signal.

[0020] In some embodiments, the control port is further configured to receive a direction control signal characterizing the cyclic shift direction; the multi-level processing network is further configured to select to perform a cyclic left shift or a cyclic right shift operation based on the direction control signal.

[0021] Secondly, embodiments of this application provide a data cyclic shifting method, including:

[0022] Obtain an input vector with a bit width of Z and a shift control word with a bit width of K; where K = log2(Z);

[0023] The input vector is input into a pre-constructed multi-level processing network, and the basic unit in the current processing unit is controlled to perform a shift operation according to the level control signal of each level of the multi-level processing network.

[0024] Generate and output a result vector with a width of Z that has completed a K-bit cyclic shift;

[0025] The multi-level processing network includes K-level cascaded processing units, each level containing multiple basic units; the multiple basic units of each level processing unit are independently controlled by a common level control signal, which is generated by one or more bits of the shift control word; the basic units include two types: 2x2 switching units and 2x1 multiplexers, and the multiple basic units of each level processing unit are of the same type.

[0026] In some embodiments, when the basic unit in the current processing unit is a 2x2 switching unit, controlling the basic unit in the current processing unit to perform a shift operation includes:

[0027] When the level control signal is at the first level, a pair of input data is directly output;

[0028] When the level control signal is at the second level, a pair of input data will be output in a cross manner;

[0029] When the basic unit in the current processing unit is a 2x1 multiplexer, the control of the basic unit in the current processing unit to perform a shift operation includes:

[0030] Based on the logic level of the stage control signal, select one of the two input data sources for output.

[0031] Thirdly, embodiments of this application provide a data cyclic shifting apparatus, which includes at least a memory and a processor; the memory is used to store programs or instructions executed by a computer, and the processor is used to execute the programs or instructions executed by the computer to implement the data cyclic shifting method as described in any embodiment of the second aspect.

[0032] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the data cyclic shifting method as described in any embodiment of the second aspect.

[0033] The circular shift register and data circular shift method provided in this application employ a multi-level processing network constructed from a hybrid of 2x2 switching units and 2x1 multiplexers, combined with control signals generated by the shift control word generation stage. This approach not only grants the system high flexibility, allowing for flexible adjustment of shift operations based on different scenario requirements, but also significantly improves data processing efficiency through a multi-level parallel processing architecture, enabling rapid circular shifting of K bits. While maintaining ultra-low latency and high parallelism, compared to traditional pure multiplexer structures, the 2x2 switching unit greatly reduces the fan-out load of control signals and global interconnect pressure, thereby reducing critical path latency and dynamic power consumption, and making timing more convergent. The multiplexer ensures the accuracy and flexibility of the shift function, reducing overall hardware implementation complexity, facilitating chip integration, and effectively controlling costs.

[0034] In addition, this application also provides a computer-readable storage medium that has the same beneficial effects as the verification method with randomization effect described above. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0036] Figure 1 A schematic diagram of the structure of a circular shift register is provided for one embodiment of this application.

[0037] Figure 2 This is a schematic diagram of the structure of a 2x2 switching unit provided in one embodiment of this application.

[0038] Figure 3 This is a schematic diagram of the structure of a circular shift register provided in another embodiment of this application.

[0039] Figure 4 This is a schematic diagram of the structure of a circular shift register provided in another embodiment of this application.

[0040] Figure 5This is a flowchart of a data cyclic shifting method provided in one embodiment of this application.

[0041] Figure 6 This is a schematic diagram of the structure of a data cyclic shifting device provided in one embodiment of this application.

[0042] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0043] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0044] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0045] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages).

[0046] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0047] Figure 1 A schematic diagram of a circular shift register is provided for one embodiment of this application. For example... Figure 1 As shown, the cyclic shift register provided in this embodiment includes a data input port 10, a data output port 20, a control port 30, and a multi-level processing network 40 connected between the data input port 10 and the data output port 20.

[0048] In this embodiment, the data input port 10 is used to receive an input vector with a bit width of Z.

[0049] Data input port 10 is the interface between the circular shift register and the external data source. Its main function is to receive an input vector with a bit width of Z, which is the set of data to be shifted. The bit width Z defines the maximum amount of data the system can process at one time; for example, Z=32 means that the register can process a 32-bit vector simultaneously. In actual circuits, data input port 10 is not a simple interface; it is usually followed by an input buffer register to temporarily store the input data under clock control, ensuring that the input data remains stable during the shift operation and avoiding calculation errors caused by input changes.

[0050] Data output port 20 is used to output the result vector after cyclic shifting with a bit width of Z.

[0051] Data output port 20 is responsible for outputting the result vector after cyclic shifting to external devices or systems. The bit width of the output data remains the same as the input, still Z bits. The difference is that the content of the output data has been rearranged according to the control signal. In communication systems, the data after cyclic shifting may be used for signal modulation, encoding, and other processes. Data output port 20 can send the processed data out in a timely and accurate manner to meet the real-time requirements of the system and ensure the normal operation of the entire system. In actual circuits, similar to the input port, the output port is often equipped with an output buffer to latch the final result, ensuring that it can be stably read by downstream circuits in the next clock cycle.

[0052] Control port 30 is used to receive a shift control word with a bit width of K, where K = log2(Z).

[0053] The circular shift operation involves cyclically shifting Z input data bits to achieve the desired output data order. The shift control word is the key parameter controlling the circular shift operation, determining the number of bits the input vector needs to be shifted. There are Z possible shift positions (from 0 to Z-1 bits) for cyclic shifting Z data bits, and K bits can represent exactly 2^K states. Therefore, K = log2(Z) is the minimum and sufficient control bit width. The shift control word is a binary number whose value directly represents the requested number of bits for the circular shift. By changing the value of the shift control word, the degree of the circular shift can be flexibly controlled to meet different data shift requirements. For example, for a system with Z = 8 (K = 3), the control word "101" (decimal 5) indicates a request for a circular right (or left) shift of 5 bits.

[0054] The multi-level processing network 40 is used to achieve a cyclic shift of K bits after the input vector is selected by multiple basic units in each processing level, under the control of the level control signal. The multi-level processing network 40 includes K cascaded processing units, each processing level containing multiple basic units; the multiple basic units of each processing level are independently controlled by a common level control signal, which is generated by one or more bits in the shift control word.

[0055] The multi-stage processing network 40 is the core execution component of the circular shift register, responsible for the specific task of cyclically shifting the input vector. In this embodiment, the structure of the multi-stage processing network 40 is a pipelined network composed of K-stage processing units. Each stage is responsible for completing a shift operation of a specific "granularity," such as the i-th stage being responsible for shifting or not shifting 2^i bits. All K stages are connected in series, and through inter-stage interconnection, they work together to complete any shift amount from 0 to (Z-1) bits. This multi-stage cascaded structure is a hallmark of barrel shifters, sacrificing a small amount of gate latency in exchange for extremely high parallel processing speed, achieving a huge leap in performance compared to traditional serial shift registers.

[0056] Furthermore, each processing unit comprises multiple basic units, which are of the same type and operate in parallel. The basic units within each processing unit share the same level control signal, meaning they are independently controlled by a common level control signal. This level control signal is generated by one or more bits of a shift control word, enabling precise control of each processing unit based on the shift control word. For example, in the simplest design, the control signal for the i-th level (i starting from 0) is directly equal to the i-th bit of the control word. If this bit is '1', all units in this level perform a shift operation; if it is '0', it remains pass-through.

[0057] In this embodiment, the basic units include two types: 2x2 switching units (SW) and 2x1 multiplexers (MUX). Multiple basic units of each processing unit are of the same type, and at least two processing units use different types of basic units.

[0058] The basic unit is the most fundamental switching switch that constitutes the network. In this embodiment, the basic unit can be either a 2x2 switching unit (SW) or a 2x1 multiplexer (MUX). The 2x2 switching unit (SW) is a highly symmetrical unit with two inputs and two outputs. Based on a control signal, it can switch between two states: pass-through (input A → output A, input B → output B) and crossover (input A → output B, input B → output A), allowing it to exchange input data. The 2x1 multiplexer (MUX) has two data inputs, one data output, and a control signal. Based on the control signal, it selects one of the two inputs to connect to the output. Through the combination and coordinated operation of these basic units, a partial shift operation is performed on the input vector in each processing unit. After continuous processing by K processing units, the input vector is finally cyclically shifted by K bits, completing the entire cyclic shift function.

[0059] In this embodiment, the smallest processing unit, or basic unit, in the multi-level processing network 40 does not necessarily have to use the same type of unit in all levels. Instead, it can be flexibly configured according to the design goals, with at least two levels of processing units using different types of basic units. That is to say, in the entire multi-level processing network 40, there are at least two levels of processing units that use different types of basic units. By combining and matching different types of basic units at different levels, the cyclic shift operation of the input vector can be implemented more flexibly and efficiently, meeting diverse data processing needs.

[0060] A multi-stage processing network 40 is constructed by hybridizing 2x2 switching units (SWs) and 2x1 multiplexers (MUXs), primarily to alleviate the signal load and wiring bottlenecks faced by traditional pure MUX structures. Specifically, symmetrically interconnected 2x2 switching units (SWs) can be used in the front-end (high-level control signal stage). Their key advantage is that the stage control signal only needs to drive a simple switching switch, rather than a multi-input multiplexer (MUX), which greatly reduces the fan-out load of the control signal and significantly lowers the transmission delay and dynamic power consumption of this stage. In the back-end (low-level control signal stage), 2x1 multiplexers (MUXs) continue to be used because their structure is more straightforward for implementing fine shifting. This hybrid approach breaks the deadlock of high load delays at each stage in a pure MUX structure. By optimizing the first few stages with the heaviest critical path, the overall critical path delay is effectively shortened, making timing more convergent.

[0061] In summary, the circular shift register provided in this embodiment, by employing a multi-level processing network constructed from a hybrid of 2x2 switching units and 2x1 multiplexers, and in conjunction with control signals from the shift control word generation stage, shortens the critical path and ensures a higher operating clock frequency in terms of timing performance by decomposing the traditional large MUX chain into numerous parallel and shallowly logic-sparse micro-switching units. In terms of physical implementation, the highly regular and repetitive underlying units greatly optimize the routing complexity and latency issues of VLSI. At the same time, it is fully compatible with the functional characteristics of traditional barrel shifters, and can seamlessly replace the shift modules in the existing architecture without modifying the upper-level architecture during expansion. It is an optimized solution that combines high performance, high integrability, and high compatibility.

[0062] In some embodiments, each 2x2 switching unit SW consists of two 2x1 multiplexers MUX, configured in cut-through or cross-connect mode according to the stage control signal.

[0063] Figure 2 This is a schematic diagram of the structure of a 2x2 switching unit SW provided in one embodiment of this application. Figure 2 As shown, the two MUXs share the same level control signal, but their input connections are reversed. One MUX selects input X0 when the control signal S is 0 and selects input X1 when S is 1; the other is configured to select input X1 when the control signal S is 0 and select input X0 when S is 1. This symmetrical connection allows the entire composite unit to seamlessly switch between through mode (X0→Y0, X1→Y1) and cross mode (X0→Y1, X1→Y0) under the control signal.

[0064] In some embodiments, the 2x2 switching unit SW can also adopt a transmission gate structure, or use NAND gates or NOR gates to build a pure combinational logic structure based on logic gates. The function implemented is the controllable interconnection (straight-through or cross-connection) of two data paths, which will not be described in detail here.

[0065] In some embodiments, the control port 30 is also used to receive a direction control signal that characterizes the direction of the cyclic shift; the multi-level processing network 40 is also used to select to perform a cyclic left shift or a cyclic right shift operation based on the direction control signal.

[0066] In this embodiment, the function of the control port 30 of the circular shift register is expanded. In addition to receiving a shift control word with a bit width of K (K = log2(Z)) to determine the number of cyclic shift bits, it can also receive a direction control signal used to characterize the cyclic shift direction, thus adding a direction control function to the circular shift register and upgrading it from a single-direction shifter to a general-purpose bidirectional circular shifter.

[0067] For example, the direction control signal, as a global signal, uses logical operations to "reinterpret" or "modulate" the meaning of the original stage control signals. Specifically, the system logically combines the received direction control signal (e.g., 0 for right shift, 1 for left shift) with each bit in the shift control word (i.e., the original stage control signal), and uses the result to actually control the 2x2 switching unit (SW) or multiplexer (MUX) of each stage. Under the control of the direction signal, the same set of stage control signals produces opposite responses: an operation that originally performed a right shift of 2^i bits is "converted" to a left shift of 2^i bits when the direction signal is valid. This design eliminates the need to copy or add extra data path hardware, requiring only minimal additional control logic to achieve powerful bidirectional shift functionality, greatly improving hardware utilization and functional flexibility, and meeting the needs of modern processor instruction sets for various operations such as left and right shifts.

[0068] In some embodiments, in the circular shift register, the first K-1 cascaded processing units employ an Omega network topology, with each stage consisting of Z / 2 2x2 switching units (SWs), and the Kth stage processing unit consisting of Z 2x1 multiplexers (MUXs). Bits 0 to K-2 of the shift control word serve as the stage control signals for the first K-1 processing units, independently controlling the switching units (SWs) within those units; bit K-1 of the shift control word serves as the stage control signal for the Kth stage processing unit, controlling the multiplexers (MUXs) within that unit.

[0069] Omega networks are a classic multi-level interconnection network topology, composed of multiple levels of switching units. Each level includes a fully shuffled topology line (i.e., a fully shuffled connection) and a row of controllable four-function switching units (supporting direct connection, switching, upcast, and downcast operations). Its core feature is the use of a fully shuffled mode for inter-level connections. This means that input data undergoes a binary bit cyclic left shift operation before entering the next level, ensuring uniform data distribution. The network operates through unit control; each switching unit independently receives control signals and automatically sets its status based on the binary bit value of the target address, enabling path selection from the source node to the target node.

[0070] In this embodiment, the efficient and well-organized interconnection characteristics of the Omega network are used to complete most of the coarse-grained shifting. Then, a final multiplexer (MUX) stage is used to correct the inherent limitations of the Omega network and achieve precise final output selection. Specifically, the first K-1 stages constitute a standard Omega network, with each stage having Z / 2 2x2 switching units (SWs), independently controlled by the lower bits (bits 0 to K-2) of the shift control word. These stages work together to efficiently move any input bit to the vicinity of the target region. Considering that the standard Omega network may have a fixed deviation in its output position or be unable to directly achieve precise selection in the final step when implementing cyclic shifting, the Kth stage (the last stage) is designed as an array of Z 2x1 multiplexers (MUXs), uniformly controlled by the highest bit (bit K-1) of the control word. This stage acts as a fine tuner; each MUX selects one of the two possible candidate results from the Omega network output as the final output, thus perfectly solving the boundary problem of cyclic shifting and ensuring that each bit can be precisely cyclically moved to the specified final position.

[0071] In some embodiments, in the first K-1 stage processing units, the interconnection relationship between the k-th stage switching unit SW and the k+1-th stage switching unit SW is defined by a perfect shuffle permutation function; where k=1,2,…,K-1.

[0072] In this embodiment, after all the switching units (SWs) at level k have processed the data, their output is not directly sent to the corresponding port of the next level. Instead, it undergoes a fixed rearrangement process called "Perfect Shuffle" before being used as the input of the (k+1)th level switching unit (SW). In other words, the connection between the switching units (SWs) at levels k and k+1 is precisely defined by the Perfect Shuffle permutation function. The Perfect Shuffle function is defined as follows: for a Z-bit output vector, treat it as a deck of cards. First, divide it evenly into two stacks (each with Z / 2 bits). Then, like shuffling, take one bit from each stack alternately and recombine them. Simply put, the Perfect Shuffle permutation function is like a "data allocation guide." Based on specific mathematical logic, it precisely allocates the output data of the switching unit (SW) at level k to the input port of the corresponding switching unit (SW) at level k+1 in a completely shuffled manner. This ensures that data can flow and be transferred in an orderly and efficient manner between multiple processing units, thereby ensuring that the entire circular shift register can perform the circular shift operation of data as designed.

[0073] Figure 3 This is a schematic diagram of the structure of a circular shift register provided in another embodiment of this application. Figure 3As shown, the circular shift register provided in this embodiment can handle the circular shift of 8 bits of data (bit width Z=8). This circular shift register has three cascaded processing units. The first two processing units adopt an Omega network topology, with each stage consisting of Z / 2=4 2x2 switching units (SW). The third processing unit consists of eight 2x1 multiplexers (MUX). Bits 0 and 1 of the shift control word serve as the stage control signals for the first two processing units, independently controlling the switching units (SW) in those units. Bit 2 of the shift control word serves as the stage control signal for the third processing unit, controlling the multiplexers (MUX) in that unit.

[0074] For a specific example, when the control word received by control port 30 is in binary form (S2,S1,S0) = (1,0,1), which is 5 in decimal, it means that the input vector needs to be cyclically shifted right by 5 bits. When the input vector is [D0, D1, ..., D7], the register will operate on the input vector according to the preset shift logic. After cyclically shifting right by 5 bits, the final output vector is [D3, D4, D5, D6, D7, D0, D1, D2].

[0075] In some embodiments, within the circular shift register, in the K-stage cascaded processing units, the first-stage processing unit consists of Z 2x1 multiplexers (MUXs), and the subsequent K-1 stage processing units employ a Banyan network topology, with each stage consisting of Z / 2 2x2 switching units (SWs). The 0th bit of the shift control word serves as the stage control signal for the first-stage processing unit, controlling the multiplexers (MUXs) within it; the 1st to K-1th bits of the shift control word serve as the stage control signals for the subsequent K-1 stage processing units, independently controlling the switching units (SWs) within each of the subsequent K-1 stage processing units.

[0076] Banyan networks are multi-stage space-division switching networks based on a tree structure. They employ 2x2 switching units interconnected in a butterfly configuration, featuring single-path operation, self-routing capabilities, and scalability. Their core mechanism uses the binary encoding of the destination address to control the state of each switching unit, enabling automatic data routing from input to output ports. Inter-stage connections follow fixed rules such as butterfly permutation. Each switching unit can independently make routing decisions (straight-through or cross-connect) based on a specific bit of the destination output address (usually the bit corresponding to its stage), thus precisely routing any input to a specified output. This distributed self-routing control mechanism avoids complex global scheduling, resulting in highly efficient hardware implementation.

[0077] In contrast to the previous embodiment, fine-grained shifting is performed first, while large-scale routing is performed last. Specifically, the first-stage processing unit consists of a large array of Z-to-1 multiplexers (MUX), uniformly controlled by the least significant bit (bit 0) of the shift control word. The function of this stage is to directly implement the smallest granularity (1 bit) cyclic shift, which can cyclically shift the entire input vector by 0 or 1 bits at a time, thereby solving the path complexity problem that may exist when implementing single-bit shifts in pure switching networks. Subsequently, the next K-1 stages adopt a 2x2 switching unit (SW) array based on the Banyan network topology, controlled by the high-order bits (bits 1 to K-1) of the control word. This network is responsible for completing the remaining coarse-grained shifts with steps of powers of 2 (2, 4, 8...). This "fine-first, coarse-first" cascading order allows the first-stage MUX array to greatly simplify the input mode of the subsequent Banyan network and optimize the data path, thus potentially achieving better timing performance and lower routing complexity overall than "Omega first, MUX later" or other structures.

[0078] In some embodiments, in the subsequent K-1 level processing units, the interconnection relationship between the k-th level switching unit SW and the k+1-th level switching unit SW is defined by a preset rule; where k=2,3,…,K.

[0079] In this embodiment, after all switching units (SWs) at level k have processed their data, the connection between each output port of a SW and the input port of a specific switching unit (SW) at level k+1 is strictly defined by a predetermined mathematical mapping rule (or permutation function). Common rules of this kind include butterfly permutation, shuffle permutation, or other custom permutation rules. For example, in butterfly permutation, the connection is determined by performing specific bitwise operations (such as XOR operations) on the binary addresses of the output ports. This predefined, rule-based interconnection pattern is the foundation for the efficient self-routing capabilities of the Banyan network structure.

[0080] Figure 4 This is a schematic diagram of the structure of a circular shift register provided in another embodiment of this application. Figure 4As shown, the circular shift register provided in this embodiment can handle the circular shift of 8 bits of data (bit width Z=8). This circular shift register has three cascaded processing units. The first-stage processing unit consists of eight 2x1 multiplexers (MUX). The latter two stages employ a Banyan network topology, with each stage consisting of Z / 2=4 2x2 switching units (SW). The 0th bit of the shift control word serves as the stage control signal for the first-stage processing unit, controlling the multiplexers (MUX) within it. The 1st and 2nd bits of the shift control word serve as the stage control signals for the latter two stages, independently controlling the switching units (SW) within each stage.

[0081] It is worth noting that both of the aforementioned multi-stage processing networks 40 with different architectures possess strong scalability. For larger bit widths Z (such as 16-bit, 32-bit, 64-bit, and even 1024-bit), expansion can be achieved by strictly adhering to the same design principles, namely, expanding the number of stages K to log2(Z). The number of 2x2 switching units SW in stage K-1 is then expanded to Z / 2, ensuring sufficient data exchange between stages. The number of 2x1 multiplexers MUX in another stage is expanded to Z, thus fully constructing a circular shift register system capable of processing larger bit widths. This expansion method ensures that the growth of hardware resources is linearly related to the bit width Z, while the latency of the critical path only increases logarithmically. This allows the design to maintain excellent timing characteristics, controllable power consumption and area, and orderly layout and routing even when dealing with high-bit-width, high-performance computing requirements.

[0082] Figure 5 This is a flowchart illustrating a data cyclic shifting method provided in one embodiment of this application. Figure 5 As shown, the data cyclic shifting method provided in this embodiment can be applied to the processor or controller in the cyclic shift register described in any of the above embodiments, and the multi-level processing network 40 is controlled by a program or instruction to perform the data cyclic shifting process. As mentioned above, the multi-level processing network 40 includes K cascaded processing units, each level containing multiple basic units; the multiple basic units of each level processing unit are independently controlled by a common level control signal, which is generated by one or more bits in the shift control word; the basic units include two types: 2x2 switching units (SW) and 2x1 multiplexers (MUX), the multiple basic units of each level processing unit are of the same type, and at least two levels of processing units use different types of basic units.

[0083] This data cyclic shifting method specifically includes the following steps:

[0084] Step S510: Obtain an input vector with a bit width of Z and a shift control word with a bit width of K; where K = log2(Z).

[0085] Step S520: Input the input vector into the pre-constructed multi-level processing network, and control the basic unit in the current processing unit to perform shift operation according to the level control signal of each level of the multi-level processing network.

[0086] Step S530: Generate and output the result vector with a bit width of Z after completing the K-bit cyclic shift.

[0087] In this embodiment, when performing data cyclic shifting, the system first receives an input data vector with a bit width of Z and a shift control word with a bit width of K from an external data source or internal storage unit, completing data loading and instruction parsing. The bit width of the shift control word is related to the bit width of the data to be processed, and the value of K is expressed by the formula K = The exact value of log2(Z) is calculated. The obtained input vector is then input into the pre-constructed multi-level processing network 40. Each processing unit of the network receives a level control signal generated by a specific position in the total shift control word. The multi-level processing network 40 independently and in parallel executes the corresponding shift operation (such as pass-through or switching) of the basic unit (such as the switching unit SW or the multiplexer MUX) in the processing unit according to the level control signal corresponding to each level. Each level completes a shift with a power of 2 granularity. The multi-level cascaded operation completes the complex cyclic shift. Finally, the data processed by the last level is latched and output to form a result vector with a bit width of Z that has completed a specified K-bit cyclic shift. This completes a single-cycle, low-latency, high-throughput shift operation. The output result vector can be further used or processed by subsequent circuit modules or processing units.

[0088] In some embodiments, if the basic unit in this level of processing unit is a 2x2 switching unit, then the basic unit in this level of processing unit is controlled to perform a shift operation, specifically including:

[0089] When the level control signal is at the first level, a pair of input data is output directly; when the level control signal is at the second level, a pair of input data is output crosswise.

[0090] Understandably, the basic unit of this processing level is a 2x2 switching unit. Based on its working principle, the 2x2 switching unit processes a pair of input data simultaneously and can switch between two defined operating modes according to the level of the received level control signal. Specifically, when the level control signal is at the first level (e.g., logic '0'), the unit operates in pass-through mode, directly sending input data X0 and X1 to the corresponding output ports (X0→Y0, X1→Y1), thus achieving pass-through data transmission without changing the corresponding positional relationship between the input and output ports. When the level control signal is at the second level (e.g., logic '1'), the unit switches to crossover mode, swapping the paths of the input data before outputting (X0→Y1, X1→Y0), thus achieving crossover processing, so that data originally in the first input port is output to the second output port, and data originally in the second input port is output to the first output port. A single switching unit performs the function of exchanging data between two local bits, while all Z / 2 switching units in the entire first stage work together under the same control signal. Through this level-controlled pass-through or cross-output method, the global cyclic shift operation is achieved.

[0091] If the basic unit in this processing unit is a 2x1 multiplexer, then the basic unit in this processing unit is controlled to perform a shift operation, specifically including:

[0092] Based on the logic level of the stage control signal, select one of the two input data sources for output.

[0093] Understandably, when the basic unit of this level of processing is a 2x1 multiplexer (MUX), based on its working principle, each 2x1 multiplexer (MUX) has two input data sources (usually from two different outputs of the previous stage network) and a stage control signal (generated by a bit of the total shift control word). During operation, it does not modify or perform any calculations on the data. Based on the logic level of the stage control signal, it selects one of its two input data sources and directly transmits the selected data to its output port. Specifically, when the stage control signal is low (0), it selects and outputs the first input data source; when the signal is high (1), it selects and outputs the second input data source. In the entire first-level processing unit, all Z (or Z / 2) MUXs execute this selection operation in parallel and independently, but are directed by the same stage control signal. By carefully configuring the connection method of the two input sources for each MUX (e.g., one connected to corresponding bit data, and the other to cyclic data separated by several bits), the coordinated selection operation of the entire stage of MUXs can jointly realize the cyclic shift function of a specific step size specified by that stage.

[0094] Figure 6This is a schematic diagram of the structure of a data cyclic shifting device provided in one embodiment of this application. Figure 6 As shown, the data cyclic shifting device described in this embodiment includes at least a memory 610 and a processor 620, which can be connected via a bus.

[0095] In this embodiment, the memory 610 is used to store computer execution instructions or commands.

[0096] The memory 610 may include volatile memory or non-volatile memory, or it may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM).

[0097] Memory 610 includes, but is not limited to, these and any other suitable types of memory.

[0098] In this embodiment, the processor 620 is used to execute computer programs or instructions to implement the various processes of any embodiment of the above-described data cyclic shifting method and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0099] The processor 620 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0100] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of any embodiment of the above-described data cyclic shifting method and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0101] The processor may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0102] Readable storage media include computer-readable storage media such as computer read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0103] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0104] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art, under the guidance of this application, can make several simple deductions, modifications or substitutions based on the spirit of this application and the scope of protection of the claims without departing from the spirit of this application and the claims. All of these are within the protection scope of this application.

Claims

1. A cyclic shift register, characterized by, include: The data input port is used to receive an input vector with a bit width of Z; The data output port is used to output the result vector after cyclic shifting with a bit width of Z; The control port is used to receive a shift control word with a bit width of K, where K = log2(Z); A multi-level processing network includes K cascaded processing units, each of which contains multiple basic units. The multiple basic units of each processing unit are independently controlled by a common level control signal, which is generated by one or more bits of the shift control word. The multi-level processing network is used to ensure that, under the control of the level control signal, the input vector achieves a cyclic shift of K bits after being selected by the multiple basic units of each processing unit. The basic unit includes two types: a 2x2 switching unit and a 2x1 multiplexer. The basic units of each processing unit are of the same type, and at least two processing units use basic units of different types.

2. The cyclic shift register of claim 1, wherein, In the K-level cascaded processing units, the first K-1 levels of processing units adopt the Omega network topology, each level consists of Z / 2 of the 2x2 switching units, and the K-level processing unit consists of Z of the 2x1 multiplexers. Bits 0 to K-2 of the shift control word serve as level control signals for the first K-1 level processing units, independently controlling the switching units in the first K-1 level processing units; bit K-1 of the shift control word serves as the level control signal for the K level processing unit, controlling the multiplexer in the K level processing unit.

3. The cyclic shift register of claim 2, wherein, In the first K-1 level processing units, the interconnection relationship between the k-th level switching unit and the k+1-th level switching unit is defined by the perfect shuffle permutation function; where k=1,2,…,K-1.

4. The cyclic shift register of claim 1, wherein, In the K-level cascaded processing units, the first-level processing unit consists of Z 2x1 multiplexers, and the subsequent K-1 level processing units adopt a Banyan network topology, with each level consisting of Z / 2 2x2 switching units. The 0th bit of the shift control word serves as the level control signal for the first-level processing unit, controlling the multiplexer in the first-level processing unit; the 1st to K-1th bits of the shift control word serve as the level control signals for the next K-1 level processing units, independently controlling the switching units in the next K-1 level processing units.

5. The cyclic shift register of claim 4, wherein, In the K-1 level processing unit, the interconnection relationship between the k-th level switching unit and the k+1-th level switching unit is defined by a preset rule; where k = 2, 3, ..., K. The preset rules include butterfly displacement, mixed shuffling displacement, or custom displacement rules.

6. The cyclic shift register of claim 1, wherein, Each of the 2x2 switching units consists of two 2x1 multiplexers, configured in either pass-through or crossover mode according to the stage control signal.

7. The cyclic shift register of claim 1, wherein, The control port is also used to receive a direction control signal that characterizes the direction of the cyclic shift; the multi-level processing network is also used to select to perform a cyclic left shift or a cyclic right shift operation according to the direction control signal.

8. A method of cyclically shifting data, the method comprising: include: Obtain an input vector with a bit width of Z and a shift control word with a bit width of K; where K = log2(Z); inputting the input vector into a pre-constructed multi-stage processing network, and controlling a basic unit in the current stage processing unit to perform a shift operation according to a stage control signal of a corresponding stage of each stage of the multi-stage processing network; generating and outputting a result vector with a bit width of Z and which has completed K-bit cyclic shift; wherein the multi-stage processing network comprises K stages of cascaded processing units, each stage comprising a plurality of basic units; the plurality of basic units of each stage of processing units are independently controlled by a common stage control signal, the stage control signal being generated by one or more bits in the shift control word; the basic units comprise two types of 2x2 cross-over units and 2x1 multiplexers, and the plurality of basic units of each stage of processing units are of the same type.

9. The data cyclic shift method of claim 8, wherein, when the basic unit in the current stage processing unit is a 2x2 cross-over unit, the control of the basic unit in the current stage processing unit to perform a shift operation comprises: when the stage control signal is at a first level, outputting a pair of input data directly; when the stage control signal is at a second level, outputting a pair of input data in a crossed manner; when the basic unit in the current stage processing unit is a 2x1 multiplexer, the control of the basic unit in the current stage processing unit to perform a shift operation comprises: selecting one of two input data sources to output according to a logic level of the stage control signal.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer execution instructions, and the computer execution instructions are used to implement the data cyclic shift method according to any one of claims 8 or 9 when executed by the processor.

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