Metal gate and method of manufacturing the same

Abstract

The application provides a metal gate and a preparation method thereof. The preparation method comprises the following steps: depositing a first metal material, dry etching the first metal material in a second part of a groove to remove the protrusion, expanding the opening size of the groove, and filling a second metal material to form a metal gate. The application solves the gap defect in the metal gate, increases the stability of the metal gate, and reduces the difference in pattern loading.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a metal gate and a preparation method thereof. BACKGROUND

[0002] With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistor is also getting smaller and smaller. In the case of continuously reducing the feature size of MOS transistor, in order to reduce the parasitic capacitance of MOS transistor gate and improve the device speed, the gate stack structure of high-K gate dielectric layer and metal gate electrode is introduced into the MOS transistor. In order to avoid the influence of the metal material of the metal gate electrode on other structures of the transistor, the gate stack structure of the metal gate electrode and the high-K gate dielectric layer is usually made by a dummy gate replacement process.

[0003] In the 28nm node, after the dummy gate is removed and the groove is formed, several barrier layers need to be deposited to adjust the threshold voltage, then the metal material is deposited, and finally the metal material is planarized to form the metal gate 1. When the barrier layer is deposited, the deposition rate at the groove opening is faster than that at other positions of the groove due to the easier nucleation at the groove opening, causing the barrier material at the groove opening to protrude, thereby reducing the groove opening size. Thus, when the metal material is deposited, it is easy to leave a gap defect (such as shown in FIG. 1) when the metal material fills the groove. Figure 1 SUMMARY

[0004] The purpose of the present application is to provide a metal gate and a preparation method thereof, which can solve the gap defect in the metal gate.

[0005] In order to solve the above problems, the present application provides a preparation method of a metal gate, comprising the following steps:

[0006] providing a semiconductor substrate, a dummy gate is formed on the semiconductor substrate, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate;

[0007] removing the dummy gate to form a groove, and forming a work function layer on the inner wall of the groove, and filling a first metal material in the groove, wherein the groove comprises a first part and a second part which are connected to each other from bottom to top, the work function layer forms a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, and there is a filling gap in the second part;

[0008] dry etching the first metal material to expose the second part, and also expose the interlayer dielectric layer;

[0009] ​Depositing a second metal material in the second part, the second metal material also covering the interlayer dielectric layer, and performing a planarization process on the second metal material to expose the interlayer dielectric layer, thereby forming a metal gate.

[0010] Optionally, the depth of the second part is 1 / 3-2 / 3 of the total depth of the groove.

[0011] Optionally, the work function layer comprises a tantalum nitride layer and a titanium aluminum layer, the tantalum nitride layer covering the inner wall of the groove, and the titanium aluminum layer covering the tantalum nitride layer.

[0012] Further, the specific method of dry etching the first metal material is:

[0013] The first metal material is etched by a physical dry etching process to expose the tantalum nitride layer and remove the protrusion;

[0014] The first metal material is etched by a chemical dry etching process to expose the second part.

[0015] Further, the process parameters of the physical dry etching process are: the etching gas comprises a mixed gas of HBr and Cl2, wherein the gas flow of HBr is 30 sccm-60 sccm, the gas flow of Cl2 is 20 sccm-40 sccm, the process voltage is 5 mTorr-15 mTorr, and the bias power is 100 W-200 W.

[0016] Further, the process parameters of the chemical dry etching process are: the etching gas comprises a mixed gas of HBr and Cl2, wherein the gas flow of HBr is 60 sccm-80 sccm, the gas flow of Cl2 is 10 sccm-20 sccm, the process voltage is 20 mTorr-40 mTorr, and the bias power is 10 W-50 W.

[0017] Optionally, the specific method of forming the metal gate is:

[0018] Filling a second metal material in the second part, the second metal material also covering the interlayer dielectric layer;

[0019] The surface of the second metal material is planarized by a chemical mechanical polishing process to expose the interlayer dielectric layer.

[0020] Optionally, the material selection of the first metal material is the same as that of the second metal material.

[0021] Further, the material selection of the first metal material and the material selection of the second metal material are both aluminum.

[0022] In another aspect, the present application also provides a metal gate prepared by the preparation method of the metal gate.

[0023] Compared with the prior art, the present application has the following unexpected technical effects:

[0024] The present application provides a metal gate and a preparation method thereof, the preparation method comprising the following steps: providing a semiconductor substrate, the semiconductor substrate being formed with a dummy gate, and an interlayer dielectric layer being formed on the semiconductor substrate outside the dummy gate; removing the dummy gate to form a groove, and forming a work function layer on the inner wall of the groove, while filling a first metal material in the groove, wherein the groove comprises a first part and a second part which are in communication in sequence from bottom to top, and the work function layer is formed with a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, while there is a filling gap in the second part; dry etching the first metal material to expose the second part, while also exposing the interlayer dielectric layer; depositing a second metal material in the second part, the second metal material also covering the interlayer dielectric layer, and performing a planarization treatment on the second metal material to expose the interlayer dielectric layer, thereby forming a metal gate. The present application expands the opening size of the groove by dry etching the first metal material to remove the protrusion, and then forms a metal gate by filling a second metal material, thereby solving the gap defect in the metal gate, increasing the stability of the metal gate, and reducing the difference in pattern loading effect. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is a structural schematic diagram of a metal gate.

[0026] Figure 2 It is a flowchart of a preparation method of a metal gate provided by an embodiment of the present application.

[0027] Figure 3 It is a structural schematic diagram of a semiconductor substrate provided by an embodiment of the present application.

[0028] Figure 4 It is a structural schematic diagram after forming a work function layer by an embodiment of the present application.

[0029] Figure 5 It is a structural schematic diagram after filling a first metal material by an embodiment of the present application.

[0030] Figure 6 It is a structural schematic diagram after a dry etching process by an embodiment of the present application.

[0031] Figure 7This is a schematic diagram of the structure after filling with a second metallic material according to an embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram of the structure after forming a metal gate according to an embodiment of the present invention.

[0033] Explanation of reference numerals in the attached figures:

[0034] Figure 1 middle:

[0035] Metal gate; a-gap;

[0036] Figures 3-8 middle:

[0037] 100 - Substrate; 110 - Dielectric layer; 120 - Interlayer dielectric layer; 130 - Groove; 131 - First portion; 132 - Second portion; 140 - Work function layer; 150 - Metal gate; 151 - First metal material; 152 - Second metal material; b - Fill gap. Detailed Implementation

[0038] The following will provide a more detailed description of a metal gate and its fabrication method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0039] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0040] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0041] like Figure 2 As shown, this embodiment provides a method for fabricating a metal gate, including the following steps:

[0042] Step S1: providing a semiconductor substrate, a dummy gate is formed on the semiconductor substrate, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate;

[0043] Step S2: removing the dummy gate to form a groove, and forming a work function layer on the inner wall of the groove, while filling a first metal material in the groove, wherein the groove comprises a first part and a second part which are in communication with each other from bottom to top, the work function layer is formed with a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, while there is a filling gap in the second part;

[0044] Step S3: dry etching the first metal material to expose the second part, and also expose the interlayer dielectric layer;

[0045] Step S4: depositing a second metal material in the second part, the second metal material also covers the interlayer dielectric layer, and performing a planarization process on the second metal material to expose the interlayer dielectric layer, thereby forming a metal gate.

[0046] The following will be described in detail Figures 3-8 The preparation method of the metal gate provided in the embodiment will be described in detail.

[0047] As Figure 3 shown, first, step S1 is performed, a semiconductor substrate is provided, a dummy gate is formed on the semiconductor substrate, and an interlayer dielectric layer 120 is formed on the semiconductor substrate outside the dummy gate.

[0048] This step specifically includes:

[0049] First, a semiconductor substrate is provided, which includes a substrate 100 and a dielectric layer 110, the substrate 100 can be a single crystal silicon substrate or a silicon-on-insulator, and the substrate 100 is defined with areas forming MOS transistors, and the MOS transistor areas are insulated by shallow trench isolation (STI).

[0050] Then, the dielectric layer 110 is formed on the surface of the substrate 100. The dielectric layer 110 includes a gate oxide layer and a high-k dielectric layer. The material of the gate oxide layer can be silicon oxide, and the high-k dielectric layer can be formed by a deposition method with good step coverage, such as chemical vapor deposition or atomic layer deposition process; the high-k dielectric layer 110 can include HfO2, HfSiO, HfON, La2O3, LaAlO, Al2O3, ZrO2, ZrSiO, TiO2 or Y2O3. The above high-k dielectric layer 110 can improve the electrical properties of the dielectric layer 110.

[0051] Then, a dummy gate is formed on the dielectric layer 110, and an insulating sidewall is formed on the side of the dummy gate. The material of the dummy gate is polysilicon, and the material of the insulating sidewall can be silicon oxide, silicon nitride or a composite structure thereof, which can be formed by a conventional sidewall process.

[0052] Then, ion implantation is performed in the substrate 100 on both sides of the dummy gate to form the source and the drain. Different ion implantation processes of different doping types are performed in corresponding regions according to the type of MOS transistor. Specifically, a photoresist mask is first made to define the source and drain regions, and then N-type ion implantation is performed on both sides of the dummy gate to form the source and drain of the NMOS transistor. The above steps are repeated to perform P-type ion implantation to form the source and drain of the PMOS transistor.

[0053] Then, a dielectric layer 120 is deposited on the surface of the semiconductor substrate (specifically, the dielectric layer 110), and then the surface of the dielectric layer 120 is planarized to thin the thickness thereof until the dummy gate is exposed. The material of the dielectric layer 120 is selected to be silicon oxide or silicon nitride, and the dielectric layer 120 is thinned by chemical mechanical grinding.

[0054] Please refer to Figures 3-5 , then step S2 is performed to remove the dummy gate to form a recess 130, form a work function layer 140 on the inner wall of the recess 130, and fill a first metal material 151 in the recess 130. The recess 130 sequentially includes a first portion 131 and a second portion 132 that are in communication from bottom to top, the work function layer 140 forms a protrusion at the opening of the recess 130, and the first metal material 151 also covers the dielectric layer 120 while there is a filling gap b in the second portion 132.

[0055] This step specifically includes:

[0056] As shown in Figure 3 , first, the dummy gate is removed to form a recess 130. Specifically, since the material of the dummy gate in this embodiment is single silicon, and the material of the dielectric layer 120 is silicon oxide or silicon nitride, the dielectric layer 120 can be directly used as a hard mask to remove the dummy gate by selective dry etching until the dielectric layer 110 is exposed, thereby forming the recess 130. The recess 130 sequentially includes a first portion 131 and a second portion 132 that are in communication from bottom to top, and the depth of the second portion 132 is 1 / 3 to 2 / 3 of the total depth of the recess 130.

[0057] As shown in Figure 4As shown, a work function layer 140 is then formed on the inner wall of the groove 130 by a deposition process. The work function layer 140 is a stack of multiple film layers, such as a tantalum nitride layer and a titanium aluminum layer. The tantalum nitride layer covers the inner wall of the groove 130, and the titanium aluminum layer covers the tantalum nitride layer.

[0058] As the process technology nodes continue to shrink, such as when the process technology nodes shrink to 32nm, 28nm and below 22nm, the critical dimension (CD) of the groove 130 will become smaller and smaller. In addition, before filling the metal gate 150, a stacked work function layer 140 is deposited in the groove 130, which will further reduce the width of the groove 130 in the area filled by the metal gate 150. In particular, at the opening of the groove 130, the accumulation of the work function layer 140 forms a protrusion.

[0059] like Figure 5 As shown, next, a first metal material 151 is filled into the groove 130, and the first metal material 151 covers the interlayer dielectric layer 120. A filling gap b exists in the second portion 132. The first metal material 151 is made of aluminum.

[0060] As the width of the groove 130 is further reduced, especially at the opening of the groove 130, the accumulation of the work function layer 140 forms a protrusion. Therefore, a filling gap b is formed in the second portion 132 of the groove 130, which can affect device performance or even cause device failure.

[0061] like Figure 6 As shown, step S3 is then performed, in which the first metal material 151 is dry etched to expose the second portion 132, and also to expose the interlayer dielectric layer 120.

[0062] This step specifically includes:

[0063] First, the first metal material 151 is etched using a physical dry etching process to expose the work function layer 140 on the interlayer dielectric layer 120. Then, the titanium aluminum layer in the work function layer 140 is further etched using a physical dry etching process to expose the tantalum nitride layer. At the same time, the protrusion formed by the work function layer 140 at the opening of the groove 130 is removed to enlarge the opening size of the groove 130 that was reduced due to the deposition of the work function layer 140.

[0064] The process parameters of the physical dry etching process are as follows: the etching gas includes but is not limited to a mixed gas of HBr and Cl2, the gas flow of HBr is 30 sccm-60 sccm, the gas flow of Cl2 is 20 sccm-40 sccm, the process voltage is 5 mTorr-15 mTorr, and the bias power is 100 W-200 W.

[0065] Then, the first metal material 151 layer is etched by a chemical dry etching process to expose the second part 132 of the groove 130. Specifically, the first metal material 151 in the second part 132 of the groove 130 is removed by isotropic etching of the chemical dry etching process, and the tantalum nitride layer on the interlayer dielectric layer 120 is also removed to expose the interlayer dielectric layer 120. Since the gap b is located in the second part 132 of the groove 130, this step ensures that the gap b is completely removed.

[0066] The process parameters of the chemical dry etching process are as follows: the etching gas includes but is not limited to a mixed gas of HBr and Cl2, the gas flow of HBr is 60 sccm-80 sccm, the gas flow of Cl2 is 10 sccm-20 sccm, the process voltage is 20 mTorr-40 mTorr, and the bias power is 10 W-50 W.

[0067] This step ensures that the physical dry etching and the chemical dry etching cooperate to prevent the work function layer 140 from being excessively consumed at the sidewall of the groove 130 by using different combinations of HBr+Cl2 and different bias (bias). At the same time, the physical dry etching and the chemical dry etching in this step have a high etching selectivity to the material (such as silicon nitride and silicon oxide) of the interlayer dielectric layer 120, so that the interlayer dielectric layer 120 and the insulating sidewall are not damaged during the dry etching process, and therefore the height of the metal gate 150 formed subsequently is not lost.

[0068] Please refer to Figures 7-8 , then step S4 is performed, a second metal material 152 is deposited in the second part 132, the second metal material 152 also covers the interlayer dielectric layer 120, and the second metal material 152 is planarized to expose the interlayer dielectric layer 120, thereby forming a metal gate 150.

[0069] This step specifically includes:

[0070] As Figure 7As shown, first, the second metal material 152 is filled in the second part 132, and the second metal material 152 also covers the interlayer dielectric layer 120, at this time, since the opening of the groove 130 is opened, so that after the second metal material filling, there is no filling gap b in the groove 130.

[0071] As shown, the surface of the second metal material 152 is planarized by a chemical mechanical polishing process to thin the second metal material 152, and at the same time, the interlayer dielectric layer 120 is also exposed, at this time, only the metal material is retained in the groove 130, that is, the first part 131 retains the first metal material 151, and the second part 132 retains the second metal material 152, and the first metal material 151 and the second metal material 152 in the groove 130 together form the metal gate 150. Figure 8

[0072] In this step, the metal gate 150 formed does not have a filling gap b, which can increase the stability of the metal gate 150, and can also reduce the difference in pattern loading.

[0073] The embodiment also provides a metal gate 150 prepared by the above process.

[0074] In summary, the present application provides a metal gate and a preparation method thereof, the preparation method comprising the following steps: providing a semiconductor substrate, the semiconductor substrate being formed with a dummy gate, and the semiconductor substrate outside the dummy gate being formed with an interlayer dielectric layer; removing the dummy gate to form a groove, and forming a work function layer on the inner wall of the groove, and filling a first metal material in the groove, wherein the groove comprises a first part and a second part which are in communication in sequence from bottom to top, and the work function layer is formed with a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, and there is a filling gap in the second part; dry etching the first metal material to expose the second part, and also expose the interlayer dielectric layer; depositing a second metal material in the second part, the second metal material also covering the interlayer dielectric layer, and planarizing the second metal material to expose the interlayer dielectric layer, thereby forming a metal gate. The present application expands the opening size of the groove by dry etching the first metal material to remove the protrusion, and then forms a metal gate by filling a second metal material, which solves the gap defect in the metal gate, can increase the stability of the metal gate, and can also reduce the difference in pattern loading.

[0075] ​Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0076] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for fabricating a metal gate, characterized in that, Includes the following steps: A semiconductor substrate is provided, on which a dummy gate is formed, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate; The dummy gate is removed to form a groove, and a work function layer is formed on the inner wall of the groove. At the same time, a first metal material is filled in the groove. The groove includes a first part and a second part that are interconnected from bottom to top. The work function layer has a protrusion at the opening of the groove. The first metal material also covers the interlayer dielectric layer, and there is a filling gap in the second part. The first metal material is dry-etched to expose the second portion, and also to expose the interlayer dielectric layer; In the second part, a second metal material is deposited, which also covers the interlayer dielectric layer, and the second metal material is planarized to expose the interlayer dielectric layer, thereby forming a metal gate.

2. The method for fabricating a metal gate according to claim 1, characterized in that, The depth of the second part is 1 / 3 to 2 / 3 of the total depth of the groove.

3. The method for fabricating a metal gate according to claim 1, characterized in that, The work function layer includes a tantalum nitride layer and a titanium aluminum layer, wherein the tantalum nitride layer covers the inner wall of the groove, and the titanium aluminum layer covers the tantalum nitride layer.

4. The method for fabricating a metal gate according to claim 3, characterized in that, The specific method for dry etching of the first metal material is as follows: The first metal material is etched using a physical dry etching process to expose the tantalum nitride layer and remove the protrusions. The first metal material is etched using a chemical dry etching process to expose the second portion.

5. The method for fabricating a metal gate as described in claim 4, characterized in that, The process parameters for the physical dry etching process are as follows: the etching gas includes a mixture of HBr and Cl2, wherein the gas flow rate of HBr is 30 sccm ~ 60 sccm, the gas flow rate of Cl2 is 20 sccm ~ 40 sccm, the process voltage is 5 mTorr ~ 15 mTorr, and the bias power is 100W ~ 200W.

6. The method for fabricating a metal gate according to claim 4, characterized in that, The process parameters for the chemical dry etching process are as follows: the etching gas includes a mixture of HBr and Cl2, wherein the gas flow rate of HBr is 60 sccm ~ 80 sccm, the gas flow rate of Cl2 is 10 sccm ~ 20 sccm, the process voltage is 20 mTorr ~ 40 mTorr, and the bias power is 10W ~ 50W.

7. The method for fabricating a metal gate according to claim 1, characterized in that, The specific method for forming the metal gate is as follows: The second part is filled with a second metallic material, which also covers the interlayer dielectric layer; The surface of the second metal material is planarized by a chemical mechanical polishing process, exposing the interlayer dielectric layer.

8. The method for fabricating a metal gate according to claim 1, characterized in that, The material selection for the first metal material is the same as that for the second metal material.

9. The method for fabricating a metal gate as described in claim 8, characterized in that, Both the first metal material and the second metal material are made of aluminum.

10. A metal gate, characterized in that, It is prepared by the method of preparing a metal gate as described in any one of claims 1 to 9.

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