High-robustness ESD (Electro-Static Discharge) protection device

Abstract

The invention provides a high-robustness ESD (Electro-Static Discharge) protection device which comprises a substrate, and an N-type well layer and a P-type well layer cover the surface of the substrate in parallel; the N-type well layer is covered with a first P-type doped layer and a second P-type doped layer, and the P-type well layer is covered with a first N-type doped layer, a second N-type doped layer and a third P-type doped layer; the first N-type doped layer is close to the second P-type doped layer, and a spacer region is arranged between the first N-type doped layer and the second N-type doped layer; a first groove is formed between the first P-type doped layer and the second P-type doped layer; a second groove is formed between the second P-type doped layer and the first N-type doped layer; a Zener doped layer is arranged in the N-type well layer, and the Zener doped layer is located between the first groove and the second groove. Through an SCR structure with Zener triggering and NMOS auxiliary discharging, lower triggering voltage, moderate holding voltage and higher unit area robustness are achieved, and the problem that a traditional ESD device is insufficient in performance is effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit electrostatic discharge protection, and particularly relates to a high-robustness ESD protection device. BACKGROUND

[0002] Electrostatic discharge (ESD) is a common natural phenomenon in integrated circuits, although the charging quantity of an ESD event is small, but due to its fast rising speed, large current and other characteristics, it can cause the internal temperature of the chip to rise sharply. Therefore, a very weak electrostatic voltage can cause irreversible damage in the integrated circuit. Especially with the rapid development of integrated circuits and semiconductor technology, the ESD design window is continuously narrowed with the reduction of line width, and the miniaturization of feature size puts higher requirements on ESD protection.

[0003] Diode, gate-grounded NMOS (GGNMOS), and thyristor (SCR) are three commonly used ESD protection devices, among which SCR has higher current carrying capacity per unit area and lower capacitance, and has always been a research hotspot in the industry. However, the traditional SCR has the problems of too high trigger voltage and too low holding voltage, which makes it cannot be directly used in actual products, typical examples are 5V working voltage applications.

[0004] To solve the above problems, some auxiliary triggering methods can be used to reduce the trigger voltage of the SCR, and the length of the SCR device is increased to improve the holding voltage. However, increasing the length of the device increases the layout area, resulting in a decrease in robustness per unit area, and an increase in cost to achieve the same protection capability. Therefore, it is necessary to design a new device structure to improve the robustness per unit area. SUMMARY

[0005] The purpose of the present application is to solve the technical problem that the ESD protection device in the prior art is difficult to guarantee the robustness and discharge capacity while improving the holding voltage.

[0006] In a first aspect of the present application, a high-robustness ESD protection device is provided, comprising: a substrate; a surface of the substrate is covered by a N-type well layer and a P-type well layer side by side; a first P-type doped layer and a second P-type doped layer are covered on the N-type well layer, and a first N-type doped layer, a second N-type doped layer and a third P-type doped layer are covered on the P-type well layer; the first N-type doped layer is close to the second P-type doped layer, and a spacing region is provided between the first N-type doped layer and the second N-type doped layer; a first trench is provided between the first P-type doped layer and the second P-type doped layer; a second trench is provided between the second P-type doped layer and the first N-type doped layer; and a third trench is provided between the second N-type doped layer and the third P-type doped layer; The N-type well layer is provided with a Zener doped layer, and the Zener doped layer is located between the first trench and the second trench.

[0007] Further, the Zener doped layer is N-type doped, and the doping concentration is higher than that of the N-type well layer.

[0008] Further, the surface of the P-type well layer is provided with a gate structure, and the gate structure is arranged on the interval between the first N-type doped layer and the second N-type doped layer.

[0009] Further, the first P-type doped layer and the N-type doped layer are commonly connected to an anode through a metal connecting line; The second P-type doped layer, the gate structure, the second N-type doped layer and the third P-type doped layer are commonly connected to a cathode through a metal connecting line.

[0010] Further, the first N-type doped layer, the gate structure, the second N-type doped layer and the P-type well layer commonly constitute an NMOS transistor.

[0011] Further, the second P-type doped layer and the Zener doped layer form a Zener diode.

[0012] Further, the first P-type doped layer and the N-type well layer constitute an anode diode; The first P-type doped layer, the N-type well layer and the P-type well layer constitute a parasitic PNP transistor; The N-type well layer, the P-type well layer and the second N-type doped layer constitute a first parasitic NPN transistor; The parasitic PNP transistor and the first parasitic NPN transistor constitute an SCR structure; The first N-type doped layer, the second N-type doped layer and the P-type well layer constitute a second parasitic NPN transistor.

[0013] Further, the anode diode and the Zener diode constitute a trigger path; The SCR structure constitutes a main discharge path; The second parasitic NPN transistor constitutes an auxiliary discharge path.

[0014] In the second aspect of the present application, a high-robustness ESD protection method is provided, and the ESD protection device with high-robustness holding voltage is used, when the ESD voltage reaches the sum of the anode diode forward conduction voltage and the Zener breakdown voltage, the trigger path constituted by the first P-type doped layer, the N-type well layer, the Zener doped layer and the second P-type doped layer is turned on. When the ESD voltage is further increased, a second trigger path composed of the first P-type doped layer, the N-type well layer, the P-type well layer and the second N-type doped layer is turned on, and An auxiliary trigger path composed of the first N-type doped layer, the P-type well layer and the second N-type doped layer is turned on.

[0015] Further, in the first trigger path, the current flows from the first P-type doped layer, through the N-type well layer and the Zener doped layer, to the second P-type doped layer; In the second trigger path, the current flows from the second P-type doped layer, through the N-type well layer and the P-type well layer, to the second N-type doped layer; In the auxiliary trigger path, the current flows from the first N-type doped layer, through the P-type well layer, to the second N-type doped layer.

[0016] Compared with the prior art, the present application has at least the following beneficial effects: through the parallel layout of the N-type well layer and the P-type well layer and the design of the multi-layer doped structure, combined with the layered isolation configuration of the first, second and third trenches, the lower trigger voltage, moderate holding voltage and higher unit area robustness are organically unified while maintaining the compact layout area. The trigger voltage is reduced by using the Zener structure, the device area utilization rate is improved by the NMOS transistor, and the multiple cooperative discharge mechanism of the Zener branch, the GGNMOS branch and the SCR branch is formed in the ESD event, thereby improving the current carrying capacity and thermal stability per unit area, and effectively solving the technical problems of the traditional SCR device, such as the too high trigger voltage, the too low holding voltage and the low protection efficiency per unit area. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by the provided drawings without creative labor for those skilled in the art.

[0018] Figure 1 is a cross-sectional view of a traditional GGNMOS device; Figure 2 is a cross-sectional view of a traditional SCR device with holding voltage; Figure 3 is a cross-sectional view of an ESD protection device in an embodiment of the present application; Figure 4 is a schematic diagram of the discharge path of the ESD protection device in an embodiment of the present application when working; Figure 5Figure 3 is a voltage-current characteristic comparison chart of an ESD protection device and a GGNMOS under ESD simulation in an embodiment of the present application; Figure 6 Figure 4 is a lattice temperature comparison chart of an ESD protection device and a GGNMOS under ESD simulation in an embodiment of the present application.

[0019] 1-substrate; 2-N-type well layer; 3-P-type well layer; 4-first trench; 5-second trench; 6-third trench; 7-gate structure; 8-first P-type doped layer; 9-second P-type doped layer; 10-first N-type doped layer; 11-second N-type doped layer; 12-third P-type doped layer; 13-Zener doped layer. DETAILED DESCRIPTION

[0020] The application now being generally described, it will be understood that certain embodiments of the application can be amended to include some or all of the features disclosed herein without departing from the scope of the application. Therefore, the following examples are set forth by way of example and are not meant to be limiting on the scope of the application. Various publications, patents, and patent documents are cited in this document. The disclosure content of each of these is incorporated by reference in its entirety for all purposes.

[0021] It should be noted that, in the present document, the terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. In addition, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or apparatus.

[0022] The application is described in more detail in the following paragraphs with reference to the attached drawings. The advantages and features of the application will become more apparent from the following description, taken in conjunction with the accompanying drawings. It should be noted that the drawings are in extremely simplified form and are not drawn to precise scale, and are merely used to facilitate, clarify and aid understanding of the principles of the embodiments of the application.

[0023] Reference should be made to Figure 1The cross-sectional view of a traditional GGNMOS is connected with an electrical anode at the drain end of the NMOS; the gate is connected with the source end, and the gate and the source are connected with an electrical cathode, thereby forming a GGNMOS. The parasitic NPN transistor in the GGNMOS is composed of an N+ implantation region (equivalent to an emitter) connected with the electrical cathode, a P well (equivalent to a base), and an N+ implantation region (equivalent to a collector) connected with the electrical anode. When an ESD event occurs, the anode potential rises rapidly, and when the avalanche breakdown voltage of the N+ / P well is reached, the current flows through the P well, causing a voltage drop. At this time, the collector junction of the parasitic NPN transistor is reverse-biased, and the emitter junction is forward-biased, causing the parasitic NPN transistor to turn on and discharge the ESD current. The GGNMOS is widely used and is often used in ESD protection in medium and high voltage (for example, 5V), but its protection efficiency per unit area is low.

[0024] Please refer to Figure 2 The cross-sectional view of a traditional holding voltage SCR device is shown. The Zener diode layer and the upper P+ implantation region form a Zener diode, which forms a Zener trigger path with the P+ / N well structure formed by the P+ implantation region connected with the electrical anode and the lower N well. The parasitic PNP transistor in the SCR is composed of a P+ implantation region (equivalent to an emitter) connected with the electrical anode, an N well (equivalent to a base) below the P+ implantation region connected with the electrical anode, and a P well (equivalent to a collector). The parasitic NPN transistor is composed of an N well (equivalent to a collector), a P well (equivalent to a base), and an N+ implantation region (equivalent to an emitter) connected with the electrical cathode. When an ESD event occurs, the anode potential rises rapidly, and when the sum of the forward bias voltage of the P+ / N well and the reverse bias voltage of the Zener diode is reached, the Zener trigger path is turned on. At this time, the base-emitter junction of the parasitic PNP transistor is forward-biased, causing the PNP transistor to turn on. At the same time, the collector junction of the parasitic NPN transistor is reverse-biased, and the emitter junction is forward-biased, causing the NPN transistor to turn on. Finally, the PNP and NPN transistors form a positive feedback path to quickly discharge a large amount of ESD current. In order to obtain sufficient holding voltage, sufficient anode-cathode spacing must be ensured, thereby increasing the area of the device.

[0025] Embodiment one This embodiment provides a high-robustness ESD protection device, please refer to Figures 3-4 , which comprises a substrate 1.

[0026] The surface of the substrate 1 is covered with an N-type well layer 2 and a P-type well layer 3 side by side.

[0027] The N-type well layer 2 is covered with a first P-type doped layer 8 and a second P-type doped layer 9, and the P-type well layer 3 is covered with a first N-type doped layer 10, a second N-type doped layer 11, and a third P-type doped layer 12; the first N-type doped layer 10 is close to the second P-type doped layer 9, and a spacing region is provided between the first N-type doped layer 10 and the second N-type doped layer 11.

[0028] The first P-type doped layer 8 is provided with the first trench 4 between the second P-type doped layer 9.

[0029] The second P-type doped layer 9 is provided with the second trench 5 between the first N-type doped layer 10. The second N-type doped layer 11 is provided with the third trench 6 between the third P-type doped layer 12.

[0030] The N-type well layer 2 is provided with the Zener doped layer 13 between the first trench 4 and the second trench 5.

[0031] Specifically, the substrate 1 can adopt a silicon substrate 1 or an SOI substrate 1, wherein the N-type well layer 2 and the P-type well layer 3 are formed by ion implantation or diffusion process. The width of the spacing region can be adjusted according to the performance requirements of the device.

[0032] By the multi-trench structure and the composite doped layer design, multiple ESD protection paths are realized while keeping a small layout area. The second trench 5 and the third trench 6 form a cooperative protection structure. By optimizing the trench position and the doping distribution, the holding voltage and the robustness of the device are effectively improved, and the contradiction between the trigger voltage and the holding voltage of the traditional ESD protection device in the miniaturization process is solved. Compared with the device with a single protection structure, the design has better ESD protection performance in the same area.

[0033] Further, the N-type well layer 2 is provided with the Zener doped layer 13 between the first trench 4 and the second trench 5.

[0034] The Zener doped layer 13 is N-type heavy doping, and the doping concentration is higher than that of the N-type well layer 2.

[0035] Further, the surface of the P-type well layer 3 is provided with the gate structure 7, and the gate structure 7 is placed on the spacing region. The spacing region refers to the undoped region (i.e. a part of the P-type well layer 3 close to the upper surface) reserved between the first N-type doped layer 10 and the second N-type doped layer 11.

[0036] In the embodiment, please refer to Figure 3 The first P-type doped layer 8 and the first N-type doped layer 10 are commonly connected to the anode through the metal connecting line. The second P-type doped layer 9, the gate structure 7, the second N-type doped layer 11 and the third P-type doped layer 12 are commonly connected to the cathode through the metal connecting line.

[0037] Further, the second P-type doped layer 9 and the Zener doped layer 13 form a Zener diode.

[0038] By setting a high-concentration Zener doped layer 13 in the N-type well layer 2, a Zener diode structure is formed with the adjacent second P-type doped layer 9. When the ESD voltage reaches the Zener breakdown voltage, the diode is first turned on to form a trigger path, thereby effectively reducing the trigger voltage of the device. Compared with the traditional SCR structure, this design can maintain the original high-current processing capability of the SCR while improving the trigger characteristics of the device through the auxiliary trigger mechanism of the Zener diode.

[0039] Further, the first N-type doped layer 10, the gate structure 7, the second N-type doped layer 11, and the P-type well layer 3 together constitute an NMOS transistor. In this embodiment, the NMOS transistor is selected from the standard devices in the process library, and its size can be adjusted as needed.

[0040] Specifically, the first N-type doped layer 10, the second N-type doped layer 11, and the P-type well layer 3 form a PN junction; the gate structure 7 is placed on the spacing area, and the conduction state of the channel area can be controlled by applying a gate voltage. Thus, the three together constitute an NMOS transistor structure with a source, a drain, and a gate. By setting the gate structure 7 in the spacing area, the first N-type doped layer 10, the second N-type doped layer 11, the gate structure 7, and the P-type well layer 3 together constitute an NMOS transistor. By introducing the NMOS transistor, a discharge path is added, and the area utilization of the device is improved.

[0041] Further, the first P-type doped layer 8, the N-type well layer 2, and the P-type well layer 3 constitute a parasitic PNP transistor.

[0042] The N-type well layer 2, the P-type well layer 3, and the second N-type doped layer 11 constitute a first parasitic NPN transistor.

[0043] The parasitic PNP transistor and the first parasitic NPN transistor constitute an SCR structure.

[0044] Specifically, the SCR structure is composed of a parasitic PNP transistor. The first P-type doped layer 8 (equivalent to an emitter region), the N-type well layer 2 (equivalent to a base region), and the P-type well layer 3 (equivalent to a collector region) together constitute a parasitic PNP transistor. The N-type well layer 2 (equivalent to a collector region), the P-type well layer (equivalent to a collector region), and the second N-type doped layer 11 (equivalent to an emitter region) together constitute a first parasitic NPN transistor. The parasitic PNP transistor and the first parasitic NPN transistor together constitute an SCR structure. Further, the thickness of each layer can be adjusted according to actual process conditions.

[0045] In this embodiment, please refer to Figure 4, the first P-type doped layer 8 and the N-type well layer 2 form an anode diode. The first N-type doped layer 10, the second N-type doped layer 11 and the P-type well layer 3 form a second parasitic NPN transistor.

[0046] The anode diode and the Zener diode form a trigger path. The SCR structure forms a main discharge path. The second parasitic NPN transistor forms an auxiliary discharge path.

[0047] Embodiment two The embodiment provides a high-robustness ESD protection method, which adopts a high-robustness ESD protection device as described in embodiment one, When the ESD voltage reaches the sum of the forward conduction voltage of the anode diode and the breakdown voltage of the Zener diode, the trigger path formed by the first P-type doped layer 8, the N-type well layer 2, the Zener doped layer 13 and the second P-type doped layer 9 is turned on, that is, the anode diode and the Zener diode are turned on.

[0048] When the ESD voltage is further increased, the main discharge path formed by the first P-type doped layer 8, the N-type well layer 2, the P-type well layer 3 and the second N-type doped layer 11 is turned on, that is, the SCR structure is turned on.

[0049] And the auxiliary discharge path formed by the first N-type doped layer 10, the P-type well layer 3 and the second N-type doped layer 11 is turned on, that is, the second parasitic NPN transistor is turned on.

[0050] Further, in the trigger path, the current flows from the first P-type doped layer 8 to the second P-type doped layer 9 through the N-type well layer 2 and the Zener doped layer 13.

[0051] In the main discharge path, the current flows from the second P-type doped layer 9 to the second N-type doped layer 11 through the N-type well layer 2 and the P-type well layer 3. In the auxiliary discharge path, the current flows from the first N-type doped layer 10 to the second N-type doped layer 11 through the P-type well layer 3.

[0052] Specifically, when an ESD event occurs, the anode voltage rises quickly, and when it reaches the sum of the forward conduction voltage of the anode diode and the reverse bias voltage of the Zener diode, the trigger path is turned on. Since the Zener layer has a high doping concentration, its reverse breakdown voltage is lower, which reduces the trigger voltage of the device.

[0053] When the voltage is further increased to the N+ / P well avalanche breakdown voltage, the GGNMOS branch opens and the trigger path discharges a small current together. The positive bias P+ / N well in the trigger path is the base-emitter junction of a parasitic PNP transistor, which is in the on state when the N well has current injection; the P-type well layer 3 in the auxiliary discharge path is the base-emitter junction of a second parasitic NPN transistor, which is in the on state when the P-type well layer 3 has current injection. At this time, a positive feedback path is formed, and the SCR branch is turned on to discharge a large amount of ESD current. At the same time, the GGNMOS branch and the Zener branch act as shunt, and discharge together with the SCR branch to improve the overall current discharge capability of the device.

[0054] The following is discussed with specific simulation experiments: Please refer to Figures 5-6 , the rising time is 10 ns, and the pulse width is 100 ns to simulate the trigger characteristics of the device under ESD events. The average value of voltage and current between 70 ns and 90 ns is taken, and the simulation data is recorded and plotted into a voltage-current curve. The simulation curve of voltage-current is shown in Figure 5 , it can be seen that the trigger voltage of GGNMOS is 8.2 V, and the holding voltage is 6.8 V; the trigger voltage of the ESD protection device in the embodiment is 6.9 V, and when the voltage increases to 7.3 V, a weak hysteresis occurs, and the holding voltage is 7 V. Compared with GGNMOS, the trigger voltage of the ESD protection device in the embodiment is lower.

[0055] The total length of the GGNMOS device is 7.5 μm, and the total length of the ESD protection device in the embodiment is 12.5 μm, and the width of both devices is 50 μm, so the area of the SCR device in the embodiment is about 1.67 times that of the GGNMOS device. In order to compare the current discharge capacity per unit area, the current applied to the ESD protection device in the embodiment is 1.67 times that applied to the GGNMOS. Therefore, 0.6 A of ESD-like pulse is applied to GGNMOS, and 1 A of ESD-like pulse is applied to the ESD protection device. The simulation results are shown in Figure 6 , it can be seen that the maximum lattice temperature of GGNMOS under ESD simulation with a current of 0.6 A is 1435 K, and the device is close to failure; the maximum lattice temperature of the ESD protection device in the embodiment under ESD simulation with a current of 1 A is 403 K, which is significantly lower than that of GGNMOS. Therefore, compared with GGNMOS, the failure current of the ESD protection device in the embodiment is higher, and the current discharge capacity per unit area is stronger.

[0056] In summary, the ESD protection device in the application utilizes the Zener structure and the GGNMOS structure to trigger the SCR to be turned on. After the SCR is turned on, the GGNMOS branch, the Zener branch and the SCR branch discharge the current together. Compared with the traditional GGNMOS device, the SCR device in the application has a lower trigger voltage, a stronger discharge capacity per unit area, and a suitable holding voltage, and can be used for ESD protection in the case of medium and high working voltage (for example, 5V).

[0057] The above application of specific examples to the application is described, only for the help to understand the application, and not to limit the application. For the skilled in the art to which the application belongs, according to the idea of the application, a number of simple deductions, deformation or replacement can be made.

Claims

1. A high-robustness ESD protection device, characterized in that, Comprise: a substrate; a surface of the substrate is covered by a N-type well layer and a P-type well layer side by side; a first P-type doped layer and a second P-type doped layer are covered on the N-type well layer, and a first N-type doped layer, a second N-type doped layer and a third P-type doped layer are covered on the P-type well layer; the first N-type doped layer is close to the second P-type doped layer, and a spacing region is provided between the first N-type doped layer and the second N-type doped layer; a first trench is provided between the first P-type doped layer and the second P-type doped layer; a second trench is provided between the second P-type doped layer and the first N-type doped layer; and a third trench is provided between the second N-type doped layer and the third P-type doped layer; a Zener doped layer is provided in the N-type well layer, and the Zener doped layer is located between the first trench and the second trench.

2. The high robust ESD protection device of claim 1, wherein, The Zener doped layer is N-type doped, and the doping concentration of the Zener doped layer is higher than the doping concentration of the N-type well layer.

3. The high robust ESD protection device of claim 1, wherein, A gate structure is provided on the surface of the P-type well layer, and the gate structure is located on the spacing region.

4. The high-robustness ESD protection device of claim 3, wherein: the first P-type doped layer and the N-type doped layer are commonly connected to an anode through a metal connecting line; the second P-type doped layer, the gate structure, the second N-type doped layer and the third P-type doped layer are commonly connected to a cathode through a metal connecting line.

5. The high robust ESD protection device of claim 3, wherein, the first N-type doped layer, the gate structure, the second N-type doped layer and the P-type well layer together form an NMOS transistor.

6. The high robust ESD protection device of claim 1, wherein, the second P-type doped layer and the Zener doped layer form a Zener diode.

7. The high-robustness ESD protection device of claim 6, wherein: the first P-type doped layer and the N-type well layer form an anode diode; the first P-type doped layer, the N-type well layer and the P-type well layer form a parasitic PNP transistor; the N-type well layer, the P-type well layer and the second N-type doped layer form a first parasitic NPN transistor; the parasitic PNP transistor and the first parasitic NPN transistor form an SCR structure; the first N-type doped layer, the second N-type doped layer and the P-type well layer form a second parasitic NPN transistor.

8. The high-robustness ESD protection device of claim 7, wherein: the anode diode and the Zener diode form a trigger path; the SCR structure forms a main discharge path; the second parasitic NPN transistor forms an auxiliary discharge path.

9. A high-robustness ESD protection method using the high-robustness ESD protection device of any one of claims 1-8, wherein: when the ESD voltage reaches the sum of the forward conduction voltage of the anode diode and the Zener breakdown voltage, the trigger path formed by the first P-type doped layer, the N-type well layer, the Zener doped layer and the second P-type doped layer is turned on; when the ESD voltage is further increased, the main discharge path formed by the first P-type doped layer, the N-type well layer, the P-type well layer and the second N-type doped layer is turned on, and The first N-type doped layer, the P-type well layer and the second N-type doped layer constitute an auxiliary discharge path.

10. The high robust ESD protection method of claim 9, wherein, In the trigger path, the current flows from the first P-type doped layer, through the N-type well layer, the Zener doped layer, to the second P-type doped layer; In the main discharge path, the current flows from the second P-type doped layer, through the N-type well layer, the P-type well layer, to the second N-type doped layer; In the auxiliary discharge path, the current flows from the first N-type doped layer, through the P-type well layer, to the second N-type doped layer.

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