A multi-channel aging test system for micro-display devices

Abstract

This application discloses a multi-channel aging test system for microdisplay devices, which improves the versatility of aging test systems for microdisplay devices and the changeover efficiency of production lines. The system includes: a main control unit, several FPGA units, a multi-channel power supply cluster unit, and a PPMU unit. The main control unit is connected to the FPGA units and receives external commands to control the FPGA units to execute test procedures on different models of microdisplay devices. The FPGA units provide programmable control signals to the microdisplay devices, the multi-channel power supply cluster unit provides multi-channel programmable constant voltage sources to the microdisplay devices, and the PPMU unit provides microampere-level constant current sources and voltage sampling to the microdisplay devices. The PPMU unit applies a preset microampere-level constant current to the interface and samples the response voltage generated by the current acting on the interface for open / short circuit detection.

Description

Technical Field

[0001] This application relates to the field of automated testing technology, and in particular to a multi-channel aging test system for micro-display devices. Background Technology

[0002] The performance and long-term reliability of microdisplay devices are crucial. To ensure the quality of products leaving the factory and to screen out devices that may fail prematurely, aging tests are required during the production process of microdisplay devices. Aging tests specifically assess the stability and lifespan of devices by simulating the electrical and thermal stresses they experience under long-term operating conditions.

[0003] In existing technologies, aging test systems for microdisplay devices typically consist of a host computer paired with one or more test boards equipped with precision voltage output and data acquisition functions. These boards provide the required constant voltage to the connected microdisplay devices according to a preset program, driving them to light up and operate continuously. Simultaneously, the system's acquisition unit periodically or continuously monitors the voltage and current of each device, recording the data for subsequent analysis to determine the device's qualification.

[0004] However, traditional aging test systems have limited driving capabilities, allowing only a small number of microdisplay devices to be tested at a time. Furthermore, their hardware and software are typically highly customized for specific device models, meaning a single machine can only perform aging tests on one type of device at a time. When the production line needs to switch to testing different device models, the equipment must be completely shut down, the entire aging test system module physically removed from the equipment, replaced with a different system suitable for the new model, and finally the program reloaded and run. This frequent downtime and manual replacement process results in significant equipment downtime and labor costs, leading to extremely low testing efficiency and failing to meet the production demands of modern automated production lines. Summary of the Invention

[0005] This application provides a multi-channel aging test system for micro-display devices, which improves the versatility of aging test systems for micro-display devices and the changeover efficiency of production lines.

[0006] This application provides a multi-channel aging test system for microdisplay devices, comprising:

[0007] The system includes a main control unit, several FPGA units, a multi-channel power supply cluster unit, and a PPMU unit.

[0008] The main control unit is connected to the FPGA unit. The main control unit is used to receive external instructions and control the plurality of FPGA units to perform test processes on different models of micro-display devices.

[0009] The FPGA unit is used to provide programmable control signals to the microdisplay device according to the test process. The FPGA unit is connected to the multi-channel power supply cluster unit and the PPMU unit. The multi-channel power supply cluster unit is used to provide a multi-channel programmable constant voltage source to the microdisplay device. The PPMU unit is used to provide a microamp-level constant current source and voltage sampling to the microdisplay device.

[0010] During the pre-detection phase, the FPGA unit connects the interface of the micro-display device to the PPMU unit, and the PPMU unit applies a preset microampere level constant current to the interface and samples the response voltage generated by the current acting on the interface to determine whether the interface has open circuit or short circuit defects.

[0011] During the aging test phase, once it is determined that the interface does not have open or short circuit defects, the FPGA unit connects the interface to the multi-channel power supply cluster unit, and provides the micro-display device with the corresponding aging test voltage and control signal through the multi-channel power supply cluster unit and the FPGA unit to perform the aging test.

[0012] Optionally, each constant voltage source of the multi-channel power supply cluster unit includes a front-end Buck power supply, a rear-end linear power supply, and a remote compensation circuit. The FPGA unit controls the front-end Buck power supply and the rear-end linear power supply to work together, and performs real-time compensation for voltage loss at the remote end of the interface through the remote compensation circuit.

[0013] Optionally, each constant voltage source of the multi-channel power cluster unit further includes a discharge circuit controlled by the FPGA unit, which is used to quickly release residual charge on the interface after the aging test.

[0014] Optionally, the FPGA unit controls a relay array to switch the connection of the interface between the PPMU unit and the multi-channel power cluster unit.

[0015] Optionally, the PPMU unit provides constant current sources and voltage sampling for different channels in a polling manner.

[0016] Optionally, the FPGA unit is also used to monitor the current and / or voltage flowing through each channel in real time during the aging test phase, and when an abnormality is detected in the current or voltage of any channel, control the multi-channel power cluster unit to shut off the voltage output of that channel.

[0017] Optionally, the multi-channel aging test system further includes an Ethernet communication unit;

[0018] The main control unit is connected to the host computer through the Ethernet communication unit. The main control unit is used to receive the test scripts sent by the host computer and upload the real-time voltage data, real-time current data of each channel and the detection results of the PPMU unit to the host computer. The test scripts define the output voltage values, power-on sequence, test duration and device models of different channels.

[0019] Optionally, the main control unit is also used to receive firmware programs sent by the host computer and update the logic program of the FPGA unit online through the internal communication bus.

[0020] Optionally, the multi-channel aging test system also includes a test fixture.

[0021] The machine test fixture is used to carry the micro-display device and is connected to the interface of the micro-display device using probes and a quick-release structure.

[0022] Optionally, the multi-channel aging test system further includes an aging furnace, and the test fixture is disposed inside the aging furnace.

[0023] As can be seen from the above technical solutions, this application has the following advantages:

[0024] By setting up a multi-channel power supply cluster unit, parallel processing of multiple microdisplay devices is achieved, directly increasing the number of devices required for a single aging test. The main control unit in the system receives external commands and controls the programmable FPGA unit and the multi-channel power supply cluster unit, allowing the system's control signals, timing, and voltage sources to be flexibly adjusted according to the commands. This ensures compatibility with the testing processes of different microdisplay device models without hardware changes, improving the versatility of the aging test system and the changeover efficiency of the production line. The system also integrates a PPMU unit, which performs pre-detection of open-circuit or short-circuit defects in the devices before the formal aging test. This can eliminate defective microdisplay devices in advance, avoiding the consumption of lengthy aging test time and energy on known defective products, thereby improving the overall efficiency and effectiveness of the aging test. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of an embodiment of the multi-channel aging test system for micro-display devices provided in this application;

[0027] Figure 2 This is a schematic diagram of the system framework of one embodiment of the multi-channel aging test system for microdisplay devices provided in this application. Detailed Implementation

[0028] This application provides a multi-channel aging test system for micro-display devices, which improves the versatility of aging test systems for micro-display devices and the changeover efficiency of production lines.

[0029] Please see Figure 1 and Figure 2 , Figure 1 This is one embodiment of the multi-channel aging test system for microdisplay devices provided in this application. Figure 2 This is a schematic diagram of the system framework of an embodiment of the multi-channel aging test system for microdisplay devices provided in this application. The system includes:

[0030] Main control unit 1, several FPGA units 2, multi-channel power supply cluster unit 3, and PPMU unit 4;

[0031] The main control unit 1 is connected to the FPGA unit 2. The main control unit 1 is used to receive external instructions and control several FPGA units 2 to perform test procedures on different types of micro-display devices.

[0032] FPGA unit 2 is used to provide programmable control signals for the microdisplay device according to the test process. FPGA unit 2 is connected to multi-channel power supply cluster unit 3 and PPMU unit 4. Multi-channel power supply cluster unit 3 is used to provide multi-channel programmable constant voltage source for the microdisplay device. PPMU unit 4 is used to provide microamp-level constant current source and voltage sampling for the microdisplay device.

[0033] During the pre-detection phase, FPGA unit 2 connects the interface of the micro-display device to PPMU unit 4. PPMU unit 4 applies a preset microampere level constant current to the interface and samples the response voltage generated by the current acting on the interface to determine whether there is an open circuit or short circuit defect in the interface.

[0034] During the aging test phase, once it is confirmed that there are no open or short circuit defects in the interface, FPGA unit 2 connects the interface to multi-channel power cluster unit 3. Through multi-channel power cluster unit 3 and FPGA unit 2, the corresponding aging test voltage and control signal are provided to the micro-display device for aging test.

[0035] Specifically, the main control unit 1, acting as the system's task scheduling center, is connected to several FPGA units 2. The main control unit 1 receives instructions from external devices (such as the host computer 6) and, based on these instructions, distributes tasks to the FPGA units 2 to coordinate and initiate the entire test process. The FPGA units 2, acting as the system's logic controllers, receive instructions from the main control unit 1 and are responsible for executing specific test steps. Each FPGA unit 2 independently controls a portion of the channels, including power regulation, signal generation, and data acquisition. The specific functions of the FPGA units 2 include: generating and providing programmable control signals such as timing and data to the microdisplay device under test according to the test process; and acting as the direct controller for lower-level functional units, connecting to the multi-channel power supply cluster unit 3 and the PPMU unit 4 to manage their operating status.

[0036] The multi-channel power supply cluster unit 3 serves as the power supply module for aging tests. Its function is to provide multiple, independently programmable constant voltage sources for multiple microdisplay devices. The voltage value of each constant voltage source is set by the FPGA unit 2 according to the test requirements. In some specific embodiments, this multi-channel power supply cluster unit 3 can generate 512 independent output channels. Compared with traditional solutions that can only drive single-digit or double-digit devices, a single test can cover a larger number of devices, fundamentally solving the problem of low test throughput. Specifically, the multi-channel power supply cluster unit 3 can adopt a 220V AC mains input, forming a high-power DC power bus through an internal AC / DC conversion module. This ensures that when all channels are operating at full load simultaneously, the system can still provide output capacity of kilowatts or higher, avoiding system crashes or performance degradation due to excessive load and guaranteeing the reliability of large-scale parallel testing. The hardware design of the multi-channel power supply cluster unit 3 is inherently highly adaptable. Each output can be adjusted with high precision over a wide range. For example, it is designed to cover multiple ranges from -2V to 4.5V, with a step size of 100mV, an accuracy better than ±10mV, and a ripple of less than 10mV. This means that the same physical test channel can output 1.2V in one test according to the script, and 2.5V in the next test, thus being compatible with device types with different operating voltages, without the need to prepare different hardware systems for different voltage requirements.

[0037] The function of PPMU unit 4 is to provide a constant current source with an accuracy in the microamp (μA) level and voltage sampling. Since this current is in the microamp level, it will not cause irreversible damage to the power supply and signal interface of the micro display device, and can perform non-destructive electrical characteristic detection of the micro display device interface.

[0038] In this embodiment, the multi-channel aging test system operates on a phased, sequential testing process. This ensures that only qualified products proceed to the time-consuming aging test phase, avoiding the waste of time and energy on known defective products. The specific process is as follows:

[0039] 1. Pre-detection phase: After the test begins, the system first enters this phase. FPGA unit 2 controls the internal signal path to establish a connection between the designated interface of the microdisplay device under test and the output of PPMU unit 4. Subsequently, FPGA unit 2 instructs PPMU unit 4 to output a preset microamp-level constant current to the interface. Simultaneously, PPMU unit 4 samples the response voltage generated on the interface under this current. By analyzing this response voltage value, the system can accurately determine whether there is a physical open circuit or short circuit defect in the interface, thus achieving open / short circuit detection. For example, too low a voltage may indicate a short circuit, while too high or infinite voltage indicates an open circuit. PPMU unit 4 collects the interface voltage and current of the power supply and signals of the microdisplay device and reports them to the main control unit 1 for judgment. When an open circuit or short circuit defect is determined, an alarm is triggered and the channel location is indicated, facilitating the removal and investigation of microdisplay devices in that channel.

[0040] 2. Aging Test Phase: The system will only enter this phase if the pre-test phase indicates that the interface is normal, i.e., there are no open or short circuit defects. FPGA unit 2 first switches the control signal path, disconnecting the microdisplay device interface from PPMU unit 4 and connecting it to the corresponding channel on the multi-channel power supply cluster unit 3. Next, according to the test procedure settings, FPGA unit 2 sends a control signal to instruct the multi-channel power supply cluster unit 3 to output a specific aging test voltage to the interface. The microdisplay device then begins a long-term aging test under this voltage.

[0041] In this embodiment, by setting up a multi-channel power supply cluster unit 3, parallel processing of multiple microdisplay devices is achieved, directly increasing the number of devices required for a single aging test. The main control unit 1 in the system receives external instructions and controls the programmable FPGA unit 2 and the multi-channel power supply cluster unit 3, enabling the system's control signals, timing, and voltage sources to be flexibly adjusted according to the instructions. This allows for compatibility with the testing processes of different microdisplay device models without hardware changes, improving the versatility of the aging test system and the changeover efficiency of the production line. The system also integrates a PPMU unit 4, which performs pre-detection of open-circuit or short-circuit defects in the devices before the formal aging test. This can eliminate defective microdisplay devices in advance, avoiding the consumption of lengthy aging test time and energy on known defective products, thereby improving the overall efficiency and effectiveness of the aging test.

[0042] Optionally, each constant voltage source of the multi-channel power supply cluster unit 3 includes a front-end Buck power supply, a rear-end linear power supply, and a remote compensation circuit. The FPGA unit 2 controls the front-end Buck power supply and the rear-end linear power supply to work together, and performs real-time compensation for voltage loss at the remote end of the interface through the remote compensation circuit.

[0043] In this embodiment, each constant voltage source of the multi-channel power supply cluster unit 3 includes a pre-stage Buck power supply, a post-stage linear power supply, and a remote compensation circuit. The pre-stage Buck power supply is a switching buck regulator, primarily used for efficient initial voltage conversion, reducing the DC power bus voltage within the system to an intermediate voltage value. Under the control of the FPGA unit 2, this intermediate voltage value is set slightly higher than the target voltage to be output to the microdisplay device. The advantages of the pre-stage Buck power supply are high energy conversion efficiency and low heat generation, making it suitable for providing high-current pre-processing for subsequent large-scale parallel circuits. The post-stage linear power supply is a low-dropout linear regulator, primarily used for precise voltage adjustment and noise suppression. Considering that voltage drop inevitably occurs when current flows through the test cables and probes, causing the actual voltage received by the device to be lower than the power supply's output voltage, thus affecting the aging test results, the remote compensation circuit is a key feedback loop for voltage control. Its function is to solve the line voltage loss problem between the power supply output and the remote load, i.e., the microdisplay device interface.

[0044] Under the unified control of FPGA unit 2, the front-end Buck power supply, the rear-end linear power supply, and the remote compensation circuit work together to achieve precise remote voltage supply. When the system needs to output a specified voltage (e.g., 3.30V) for a certain channel, the FPGA first controls the front-end Buck power supply through a digital-to-analog converter (DAC) to output a slightly higher stable voltage (e.g., 3.6V). This 3.6V voltage is then fed into the rear-end linear power supply. Under the control of the FPGA, the linear power supply precisely adjusts this voltage to the target value of 3.30V, effectively suppressing (filtering out) the switching ripple from the front-end Buck power supply in the process. Simultaneously, the remote compensation circuit monitors the voltage at the microdisplay device interface in real time. If, due to line losses, the actual voltage at this point is 3.28V, the remote compensation circuit generates a compensation signal. This signal is fed back to the FPGA or directly adjusts the power control loop to fine-tune the output of the front-end and / or rear-end power supplies in real time, slightly increasing it until the voltage at the remote device interface is precisely compensated to the target 3.30V. This closed-loop control process ensures that each microdisplay device receives a highly accurate and stable aging test voltage, regardless of changes in load current or cable length, thus guaranteeing the consistency of aging test results.

[0045] Optionally, each constant voltage source of the multi-channel power cluster unit 3 also includes a discharge circuit controlled by the FPGA unit 2, which is used to quickly release residual charge on the interface after the aging test.

[0046] In this embodiment, each constant voltage source of the multi-channel power supply cluster unit 3 also includes a discharge circuit, which is independently controlled by the FPGA unit 2. Its function is to provide a temporary low-impedance discharge path between the power output terminal and ground after the main power supply of the aging test is turned off, so as to quickly release the residual charge on the test interface and the internal capacitor of the connected micro-display device. Specifically, when the aging test reaches the preset time or is terminated early by an instruction, the main control unit 1 will send a test end instruction to the FPGA unit 2. The FPGA unit 2 first controls the front-end Buck power supply and the rear-end linear power supply in the multi-channel power supply cluster unit 3 to stop working, and then immediately outputs a control signal to activate the discharge circuit of the corresponding channel. After the discharge circuit is activated, it is equivalent to instantly connecting a discharge resistor between the interface of the micro-display device and ground, providing a fast path for the residual charge on the interface to flow to ground, so that the interface voltage can drop rapidly from the working voltage to a safe level close to zero volts in a very short time, which is much faster than natural decay.

[0047] By incorporating a discharge circuit, it is ensured that the interface of the microdisplay device is in a safe, de-energized state when the operator or automated equipment handles it, effectively preventing electrostatic discharge damage caused by residual voltage and protecting the microdisplay device. Furthermore, rapid discharge shortens the waiting time from the end of the test to the safe commencement of the next operation, reducing the cycle time of the test station and thus improving the throughput of the entire aging test system.

[0048] Optionally, FPGA unit 2 controls the relay array to switch the interface between PPMU unit 4 and multi-channel power cluster unit 3.

[0049] In this embodiment, FPGA unit 2 controls the relay array via LVDS / SPI communication, with each test channel corresponding to one or more relays in the array. The core characteristic of a relay is that when its coil is not energized, the internal contacts are physically open, providing extremely high electrical isolation; when the coil is energized, the internal contacts close, forming a conductive path with extremely low resistance. FPGA unit 2, acting as the direct drive controller for the relay array, outputs high / low level signals to the control terminals of each relay in the array through its numerous programmable I / O pins, thereby precisely controlling the closed and open states of each relay and enabling the switching of the interface between PPMU unit 4 and multi-channel power supply cluster unit 3.

[0050] When the testing process enters the pre-testing phase, FPGA unit 2 issues specific commands to the relay array. For each channel, the FPGA controls its corresponding relay to close the path connected to PPMU unit 4, while simultaneously disconnecting the path connected to the multi-channel power supply cluster unit 3. At this time, the interface of the microdisplay device is only connected to PPMU unit 4. The physical isolation characteristics of the relays ensure that the high voltage and high current of the multi-channel power supply cluster unit 3 do not leak into the measurement circuit of PPMU unit 4, thereby protecting PPMU unit 4 and ensuring the accuracy of microampere-level measurements. After the pre-testing is completed and the results are normal, FPGA unit 2 issues new commands to reconfigure the relay array. For each channel, the FPGA controls its corresponding relay to disconnect the path connected to PPMU unit 4, while simultaneously closing the path connected to the multi-channel power supply cluster unit 3, for aging testing.

[0051] Optionally, PPMU unit 4 uses a polling method to provide constant current sources and voltage sampling for different channels.

[0052] In this embodiment, to reduce the number of channels, the PPMU unit 4 can use a round-robin method for current output and voltage sampling. Instead of equipping each channel with an independent circuit, the system uses a few shared circuits. These shared circuits are then sequentially connected to each channel under test via a multiplexer, performing open / short circuit detection one by one. This round-robin method, through hardware multiplexing, can significantly save circuit board space and contributes to the miniaturization and high-density integration of the device.

[0053] Optionally, FPGA unit 2 is also used to monitor the current and / or voltage flowing through each channel in real time during the aging test phase. When an abnormality is detected in the current or voltage of any channel, the multi-channel power cluster unit 3 is controlled to shut down the voltage output of the channel.

[0054] In this embodiment, FPGA unit 2 continuously collects and checks the real-time current and / or voltage data flowing through each independent test channel during the aging test. FPGA unit 2 can preset one or more normal current / voltage threshold ranges. Once it detects that the real-time data of any channel exceeds this safe range—for example, a sudden surge in current far exceeding the normal operating current or an abnormal voltage drop—FPGA unit 2 immediately identifies this as an anomaly and sends a command to multi-channel power cluster unit 3 to shut down the voltage output of the specific channel where the anomaly occurred, thereby protecting the downstream microdisplay devices.

[0055] Optionally, the multi-channel aging test system also includes an Ethernet communication unit 5;

[0056] The main control unit 1 is connected to the host computer 6 via the Ethernet communication unit 5. The main control unit 1 is used to receive the test scripts sent by the host computer 6 and upload the real-time voltage data, real-time current data and detection results of each channel and the PPMU unit 4 to the host computer 6. The test scripts define the output voltage values, power-on sequence, test duration and device models of different channels.

[0057] Optionally, the main control unit 1 is also used to receive the firmware program sent by the host computer 6 and update the logic program of the FPGA unit 2 online through the internal communication bus.

[0058] In this embodiment, the Ethernet communication unit 5 is the physical and logical interface for the system to connect to external networks. Ethernet, with its advantages of high speed, high stability, long transmission distance, and high standardization, can reliably integrate into modern factory network environments. The host computer 6 is an external computer, typically an industrial control computer (IPC) or a regular personal computer (PC). The host computer 6 is used for creating, distributing, monitoring, and analyzing and storing test tasks and results. Specifically, the host computer 6 sends a test script containing complete test definitions to the main control unit 1 within the system via the Ethernet communication unit 5. The test script defines at least the precise output voltage value for each channel; the power-on sequence for controlling multiple power channels to turn on in a specific order; the test duration of the aging process; and the device model used to identify and distinguish the product types being tested on different channels, enabling the system to perform mixed testing on different device models simultaneously. The main control unit 1 then sends various types of data generated within the system back to the host computer 6 via the Ethernet communication unit 5, specifically including the detection results from the PPMU unit 4 and the real-time voltage and current data for each channel. The testing process is no longer determined by fixed hardware, but by flexible and variable test scripts, enabling the system to quickly adapt to the testing needs of different products without any hardware modifications.

[0059] Furthermore, the main control unit 1 is also used to receive firmware programs from the host computer 6. The firmware program defines the behavior and connection methods of all logic gates within the FPGA unit 2, determining the specific functions of the FPGA unit 2 as a hardware controller. After receiving the firmware program, the main control unit 1 writes it into the designated FPGA unit 2 via the internal communication bus according to a specific programming sequence, thereby erasing the old logic and configuring the new logic. This allows the host computer 6 to upgrade the program inside the board online, enabling future aging tests for other product types.

[0060] Optionally, the multi-channel aging test system also includes a test fixture 7;

[0061] The test fixture 7 is used to carry the micro-display device and is connected to the interface of the micro-display device using probes and a quick-release structure.

[0062] Optionally, the multi-channel aging test system also includes an aging furnace 8, with the test fixture 7 located inside the aging furnace 8.

[0063] In this embodiment, the machine test fixture 7 serves to support and precisely position the microdisplay device. The interface between the machine test fixture 7 and the microdisplay device employs a probe and quick-release structure, directly making electrical contact with the interface pads or pins of the microdisplay device. Without the need for manual connector fastening, operators or automated robotic arms can quickly load and unload entire batches of devices in one go, significantly reducing auxiliary time for loading and unloading, greatly improving efficiency, and reducing connector wear.

[0064] The aging furnace 8 is a sealed device capable of providing and maintaining a specific high-temperature environment. It is equipped with a heating system and a temperature control system, allowing for precise temperature control at a specific high-temperature point according to aging test requirements. By placing the test fixture 7 inside the aging furnace 8, electrical and thermal stresses can be applied simultaneously to the micro-display device. The effect of this combined stress is far greater than that of a single stress, enabling more effective and rapid screening of device reliability defects, such as material degradation, increased leakage current, and connection point failure.

[0065] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0067] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0068] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0069] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A multi-channel burn-in test system for microdisplay devices, characterized by, The multi-channel aging test system comprises a master control unit, a plurality of FPGA units, a multi-channel power supply cluster unit and a PPMU unit; The master control unit is connected with the FPGA units, and is configured to receive external instructions and control the plurality of FPGA units to execute a test flow for different types of micro display devices; The FPGA units are configured to provide programmable control signals for the micro display devices according to the test flow, and are connected with the multi-channel power supply cluster unit and the PPMU unit, the multi-channel power supply cluster unit is configured to provide a plurality of programmable constant voltage sources for the micro display devices, and the PPMU unit is configured to provide a micro-ampere level constant current source and voltage back sampling for the micro display devices; Each constant voltage source of the multi-channel power supply cluster unit comprises a front-stage Buck power supply, a rear-stage linear power supply and a remote compensation circuit, the FPGA units control the front-stage Buck power supply and the rear-stage linear power supply to work cooperatively, and compensate the voltage loss at the remote end of the interface in real time through the remote compensation circuit; when a specified voltage needs to be output, the FPGA units control the front-stage Buck power supply to output a stable voltage higher than the specified voltage through a digital-to-analog converter, and send the stable voltage to the rear-stage linear power supply, and the rear-stage linear power supply adjusts the stable voltage to the specified voltage and filters the switching ripple from the front-stage Buck power supply under the control of the FPGA units; In the pre-detection stage, the FPGA units connect the interface of the micro display device to the PPMU unit, apply a preset micro-ampere level constant current to the interface through the PPMU unit, and back sample the response voltage generated by the constant current acting on the interface, to determine whether the interface has open circuit or short circuit defects; In the aging test stage, after it is determined that the interface does not have open circuit and short circuit defects, the FPGA units connect the interface to the multi-channel power supply cluster unit, and provide corresponding aging test voltage and control signals for the micro display device through the multi-channel power supply cluster unit and the FPGA units to perform aging test.

2. The multi-channel burn-in test system of claim 1, wherein, Each constant voltage source of the multi-channel power supply cluster unit further comprises a bleeder circuit controlled by the FPGA units, and the bleeder circuit is configured to quickly release the residual charge on the interface after the aging test is completed.

3. The multi-channel burn-in test system of claim 1, wherein, The FPGA units control a relay array to realize the connection switching of the interface between the PPMU unit and the multi-channel power supply cluster unit.

4. The multi-channel burn-in test system of claim 1, wherein, The PPMU unit provides the constant current source and voltage back sampling of different channels in a round-robin manner.

5. The multi-channel burn-in test system of claim 1, wherein, The FPGA units are further configured to monitor the current and / or voltage flowing through each channel in real time in the aging test stage, and control the multi-channel power supply cluster unit to turn off the voltage output of the channel when the current or voltage of any channel is found to be abnormal.

6. The multi-channel burn-in test system of claim 1, wherein, The multi-channel aging test system further comprises an Ethernet communication unit. The master control unit is connected with a host computer through the Ethernet communication unit, the master control unit is used for receiving a test script issued by the host computer, and real-time voltage data, real-time current data of each channel and detection results of the PPMU unit are uploaded to the host computer, and the test script defines output voltage values of different channels, power-on timing, test duration and device model.

7. The multi-channel burn-in test system of claim 6, wherein, The master control unit is also used for receiving a firmware program issued by the host computer, and updating logic programs of the FPGA unit online through an internal communication bus.

8. The multi-pass burn-in test system of any one of claims 1-7, wherein, The multi-channel aging test system further comprises a machine test fixture. The machine test fixture is used for carrying the micro display device, and adopts a probe and a quick release structure to connect with an interface of the micro display device.

9. The multi-channel burn-in test system of claim 8, wherein, The multi-channel aging test system further comprises an aging furnace, and the machine test fixture is arranged in the interior of the aging furnace.

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