Dynamic grid voltage reliability evaluation method and device

Abstract

The invention relates to the technical field of dynamic grid voltage reliability evaluation, and particularly discloses a dynamic grid voltage reliability evaluation method and device. Comprising the steps of test configuration instruction generation, device installation and initial test, voltage scanning monitoring, anomaly detection and fault response, automatic ejection isolation, circuit recombination and switching, test data set generation and evaluation termination and report generation. Millisecond-level rapid physical isolation of a fault device is realized by integrating a sheet melting trigger mechanism and an ejection isolation mechanism, a standby scheme can be seamlessly connected without interrupting a test by adopting a linkage strategy of automatically switching a standby container, and a continuous test data set is generated by dynamically adjusting voltage stepping and monitoring current change, so that the test efficiency is improved. Calculating a reliability index, and outputting an evaluation report; according to the invention, the problems of slow response and low resource utilization rate of the traditional test are effectively solved, and a reliable solution is provided for the reliability evaluation of the dynamic grid voltage of the semiconductor device.

Description

Technical Field

[0001] This invention belongs to the field of dynamic gate voltage reliability assessment technology, and relates to a method and apparatus for dynamic gate voltage reliability assessment. Background Technology

[0002] Currently, semiconductor devices are facing unprecedented challenges in the field of dynamic gate voltage testing. Under traditional testing methods, devices are highly susceptible to irreversible and permanent damage due to overload or breakdown, which has become a key factor restricting the accuracy of the testing process and results. If a faulty device is not quickly and effectively isolated, it will not only immediately interrupt the testing process, resulting in a significant waste of valuable testing resources such as time, equipment, and manpower, but may also cause the entire reliability assessment to fail, making it impossible to draw accurate and reliable conclusions. Especially under extreme testing conditions such as high-voltage scanning, the limitations of traditional testing methods are fully exposed; they are unable to respond to sudden faults in real time and accurately, highlighting the obvious inadequacy of existing technologies in dealing with complex and ever-changing testing scenarios.

[0003] Currently, most solutions used in the industry remain at a rudimentary stage, relying on manual intervention by testers. For example, after a fault is detected, the failed component needs to be manually disassembled and replaced with a spare, or a soft disconnect operation can be performed using an electronic relay. However, these methods suffer from significant response delays and cannot meet the stringent efficiency and real-time requirements of modern high-speed automated testing environments. Manual or semi-automatic switching processes not only significantly extend the overall evaluation time and reduce testing efficiency but also lead to severely low resource utilization, failing to achieve rapid isolation of fault points and seamless integration with backup solutions. This inefficient approach severely restricts the overall success rate and reliability of testing, exposing significant shortcomings in the automation and efficiency of existing technologies.

[0004] Crucially, when facing the cutting-edge field of high-speed, high-voltage dynamic gate voltage testing, traditional testing methods fall far short of ideal performance in terms of response speed and hardware resource utilization. Excessive response delays often force multiple interruptions to the testing process, severely impacting the continuity and stability of the test. Furthermore, insufficient resource utilization further exacerbates testing costs and time consumption, significantly reducing overall testing efficiency. These shortcomings clearly demonstrate that traditional testing methods are inadequate to meet the high standards and stringent requirements of modern semiconductor device dynamic gate voltage testing, necessitating a more efficient, automated, and reliable testing solution to fill this technological gap. Summary of the Invention

[0005] In view of this, in order to solve the problems mentioned in the background art, a dynamic gate voltage reliability assessment method and apparatus are proposed.

[0006] The objective of this invention can be achieved through the following technical solution: The first aspect of this invention provides a dynamic gate voltage reliability assessment method, including: S1, test configuration instruction generation: generating a test configuration instruction containing device location identifier and voltage sequence.

[0007] S2. Device Installation and Initial Testing: Based on the test configuration instructions, the semiconductor device is fixed and an initial gate voltage is applied to generate device response data containing real-time current values.

[0008] S3. Voltage Scan Monitoring: Performs voltage scanning based on device response data and dynamically adjusts the voltage step to generate continuous voltage scan monitoring results.

[0009] S4. Anomaly Detection and Fault Response: Analyze the continuous voltage scan monitoring results, and when the current exceeds the preset safety threshold, generate a fault response control signal containing the fault location.

[0010] S5. Automatic ejection isolation: In response to the fault response control signal, eject the container containing the faulty semiconductor device to the isolation space and achieve physical locking, generating isolation confirmation information containing the isolation status.

[0011] S6. Circuit Reorganization and Switching: Based on the isolation confirmation information, disconnect the circuit connection of the fault point and activate the backup container interface to generate a backup activation state containing the new target location.

[0012] S7. Test Dataset Generation: Based on the standby active state, repeatedly scan the voltage of the new target semiconductor in the standby container to generate a continuous test dataset.

[0013] S8. Assessment Termination and Report Generation: Calculate reliability metrics based on the continuous test dataset and generate the final assessment report.

[0014] A second aspect of the present invention provides a dynamic gate voltage reliability assessment device, comprising: a test configuration instruction generation module for generating test configuration instructions including device location identifiers and voltage sequences.

[0015] The device mounting and initial testing module fixes the semiconductor device and applies an initial gate voltage based on the test configuration instructions, generating device response data that includes real-time current values.

[0016] The voltage scan monitoring module performs voltage scanning based on device response data and dynamically adjusts the voltage step to generate continuous voltage scan monitoring results.

[0017] The anomaly detection and fault response module analyzes the continuous voltage scan monitoring results and generates a fault response control signal containing the fault location when the current exceeds a preset safety threshold.

[0018] The automatic ejection isolation module responds to the fault response control signal, ejects the container containing the faulty semiconductor device into the isolation space and physically locks it, generating isolation confirmation information containing the isolation status.

[0019] The circuit reconfiguration and switching module disconnects the circuit connection at the fault point based on the isolation confirmation information and activates the backup container interface, generating a backup activation state that includes the new target location.

[0020] The test dataset generation module generates a continuous test dataset by repeatedly scanning the voltage of a new target semiconductor in a standby container based on the standby activation state.

[0021] The assessment termination and report generation module calculates reliability metrics based on the continuous test dataset and generates the final assessment report.

[0022] Compared with the prior art, the embodiments of the present invention have at least the following advantages or beneficial effects: (1) By integrating the thin sheet melting trigger mechanism and the ejection isolation mechanism, the response time of the physically isolated faulty device is significantly shortened, avoiding the chain risk caused by circuit overheating, ensuring that the system completes fault handling within milliseconds, and improving safety and real-time response capability.

[0023] (2) The present invention significantly improves the utilization rate of hardware resources through the linkage mechanism of automatically switching to the backup container. The test process can continuously utilize the same voltage source and acquisition system without interruption, eliminating the gap time of the traditional replacement scheme, and fundamentally optimizing the utilization efficiency of the test equipment.

[0024] (3) The present invention simplifies the operation complexity by quickly starting the backup device scan through dynamic reconfiguration circuit, achieves seamless test continuity, reduces the overall evaluation time, ensures the complete generation of high continuity test dataset, and provides a more reliable basis for reliability analysis. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the method steps of the present invention.

[0027] Figure 2 This is a schematic diagram of the system structure connection of the present invention.

[0028] Figure 3 This diagram illustrates a continuous technical reproduction chain for the entire process of this invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Please see Figure 1 and Figure 3 As shown, the first aspect of the present invention provides a dynamic gate voltage reliability assessment method, including: S1, test configuration instruction generation: generating a test configuration instruction containing device location identifiers and voltage sequences.

[0031] In a specific embodiment of the present invention, the specific process of generating a test configuration instruction containing device location identifiers and voltage sequences is as follows: receiving input device type and target voltage change pattern to define test requirements.

[0032] Based on the device dimensions in the test requirements, select and activate a replaceable container location on the test board.

[0033] Establish an interface connection between the test system and the test voltage source, integrate the activated replaceable container position generator device position identifier, integrate the target voltage change mode to generate a voltage sequence, and together form the test configuration command.

[0034] It should be noted that the operation flow of step S1 begins with user input and proceeds step by step to generate test configuration instructions. First, the user inputs the device type and target voltage variation mode through the test system's input interface. This input defines the test requirements. The device type specifies the specific category of the semiconductor device, and the target voltage variation mode defines the starting value, ending value, and stepping method of the gate voltage. Based on the input device size, the system identifies and activates the corresponding replaceable container position from a predefined test board. The test board is designed to contain multiple replaceable container positions, each with a unique identifier. Next, the system establishes an interface connection, connecting the test system interface to the test voltage source via a standard communication protocol such as SPI, and verifies the availability of the test voltage source. If the test voltage source is available, the system's internal logic processes the input parameters and generates test configuration instructions. This instruction is a data structure containing two core elements: a device position identifier corresponding to the activated replaceable container position, and a voltage sequence specifying the list of scan points for the gate voltage. The entire process ensures a continuous technical reproducibility chain from input operation to output result: input device type and target voltage change mode trigger size matching logic, size matching activates position selection, interface connection verifies power status, and finally data integration generates test configuration instructions.

[0035] The target voltage change mode is characterized by its voltage scan range and step parameters, such as a starting voltage of 0V, an ending voltage of 5V, and a step value of 0.1V. These parameters define the time-series data required for the test and are set based on user input or a preset test protocol. The replaceable container position is characterized by its mounting slot identifier on the test board, such as coordinates A1 or B2. This identifier is used to physically locate the device and is set based on the test board's grid layout. The test configuration instruction is characterized by a data structure containing the device position identifier and voltage sequence. This data structure provides configuration information for subsequent tests and is generated as step outputs based on the integrated input parameters. The device position identifier is characterized by a unique code for the replaceable container position, such as a string ID or numerical coordinates. This code specifies the position in the test instruction and is set based on the position selection logic.

[0036] S2. Device Installation and Initial Testing: Based on the test configuration instructions, the semiconductor device is fixed and an initial gate voltage is applied to generate device response data containing real-time current values.

[0037] In a specific embodiment of the present invention, the specific process of generating device response data containing real-time current values ​​is as follows: the semiconductor device is installed into a replaceable container specified by the device location identifier through a quick blind-plug interface.

[0038] The initial gate voltage is the starting voltage in the voltage sequence applied to the semiconductor device.

[0039] The real-time current value and temperature response after the initial gate voltage is applied are collected and together constitute the device response data.

[0040] It should be noted that the operation process of step S2 begins with receiving the test configuration command and proceeds step by step to generate device response data. First, according to the device location identifier A1 in the test configuration command, the semiconductor device is physically inserted into the corresponding replaceable container, and the installation is completed through a quick blind mating interface. The quick blind mating interface adopts a flexible probe array design to achieve multi-channel electrical contact self-alignment at the moment of insertion. Next, an initial gate voltage is applied to the device. This voltage value is directly taken from the starting value of 0V in the voltage sequence in the test configuration command, simulating the actual operating conditions of the device power-on. After the voltage is applied, the real-time current value of the device's source pin is collected by a high-precision current sensor, and the surface temperature response of the device is collected by a miniature thermocouple. Finally, the current and temperature data are integrated into the device response data output.

[0041] S3. Voltage Scan Monitoring: Performs voltage scanning based on device response data and dynamically adjusts the voltage step to generate continuous voltage scan monitoring results.

[0042] In a specific embodiment of the present invention, the specific process of generating continuous voltage scan monitoring results is as follows: the initial current change rate is calculated based on the real-time current value in the device response data.

[0043] The voltage step value is dynamically adjusted according to the rate of change of current, and the gate voltage is continuously applied according to the voltage sequence.

[0044] The system measures the current and energy changes at each voltage step in real time and integrates them to generate continuous voltage scan monitoring results that include voltage-current curves.

[0045] It should be noted that the operation process of step S3 begins with receiving the device response data and proceeds step by step to generate continuous voltage scan monitoring results. First, based on the real-time current value in the device response data, the system determines that the device is in the off state and initiates the gate voltage scan program: starting from the voltage sequence start point of 0V in the test configuration command, the voltage is gradually increased according to preset step values. When the current change rate exceeds the set current change rate threshold, it automatically switches to a fine step with a set reference. After each voltage adjustment, the device current value is measured in real time using a high sampling rate current sensor, and the energy change data E=∫V×Idt is calculated simultaneously, where V is the real-time gate voltage, I is the measured current value, and the integration time t is fixed at 100ms. The scan continues until the entire voltage sequence range of 5V is covered. The voltage values, current values, and corresponding energy data of all scan points are integrated in chronological order, ultimately generating a continuous voltage-current curve with voltage on the horizontal axis and current on the vertical axis as the monitoring result.

[0046] In one specific embodiment of the present invention, the preset step value can be 0.1V. This value takes into account the conventional scanning range and efficiency of semiconductor devices in dynamic gate voltage testing, ensuring that device characteristic changes can be effectively captured in a wide voltage range while maintaining a reasonable test time. The set current change rate threshold can be 10μA / V, determined based on multiple sets of device conduction characteristic test data. The set reference fine step value can be 0.05V, which is based on in-depth analysis of multiple sets of device conduction characteristic test data. Especially in the voltage region close to the device threshold voltage or where sudden changes may occur, a finer step can more accurately depict the electrical characteristic curve of the device.

[0047] Among them, the characteristic attribute of current change rate is the ratio of the current difference between adjacent voltage points to the voltage step, which is used to dynamically adjust the step strategy; energy change data: the characteristic attribute is the energy integral value during a single voltage scan, in joules, which is used to evaluate the thermal accumulation effect of the device and is calculated by integrating the voltage-current product over time; voltage-current curve: the characteristic attribute is a two-dimensional graph visualizing the electrical characteristics of the device, including the original data of the scan points and the fitted connection, which serves as the core output of the monitoring results; continuous voltage scan monitoring results: the characteristic attribute is a structured dataset containing the voltage, current, and energy values ​​and the generated curves of the complete scan sequence, which is used for subsequent anomaly detection.

[0048] S4. Anomaly Detection and Fault Response: Analyze the continuous voltage scan monitoring results, and when the current exceeds the preset safety threshold, generate a fault response control signal containing the fault location.

[0049] In a specific embodiment of the present invention, the specific process of generating a fault response control signal containing the fault location is as follows: the current value in the continuous voltage scan monitoring result is compared with a preset safety threshold to identify the event exceeding the standard.

[0050] The abnormal current generated by the excessive event flows through a specially made thin sheet, causing the sheet to melt due to the current-heat conversion.

[0051] The melting of the specially made thin sheet directly triggers a mechanical ejection signal, and the device position identifier is encoded into the ejection signal, together forming a fault response control signal.

[0052] It should be noted that the operation process of step S4 begins with receiving the continuous voltage scan monitoring results and proceeds step by step to generate a fault response control signal. First, the system reads the current values ​​from the monitoring results point by point and compares each current value with a preset safety threshold in real time. When a current value exceeds the preset safety threshold, it is immediately identified as an over-limit event; for example, a current of 1.0 mA at the 5V scan point triggers an over-limit flag. The over-limit event activates the current-heat conversion mechanism: the abnormal current flows through a specially designed thin sheet connected in series in the test circuit. The sheet is made of tin-bismuth alloy and has a resistance of 50 milliohms. The Joule heat generated by the current causes the sheet temperature to rise to its melting point of 120 degrees Celsius within a specific time, causing the sheet to completely melt and break. The breakage of the sheet releases the mechanical constraint of the pre-compressed spring, which pushes the trigger rod to generate a 5 mm displacement ejection signal. The ejection signal directly drives the signal encoding module through hardwiring, converting the device position identifier A1 in the test configuration command into a binary position code, and finally outputting a fault response control signal containing the fault position code.

[0053] In one specific embodiment of the present invention, the preset safety threshold can be 0.8 mA, which is used to determine the device failure boundary and is set based on the semiconductor device breakdown current safety factor.

[0054] It should also be noted that the characteristic attribute of the over-limit event is a digital trigger signal, which outputs a high level when the current exceeds the threshold to activate the fuse mechanism, and is generated in real time by a comparator circuit; the characteristic attribute of the specially made thin sheet is a thermoplastic mechanical fuse element, with dimensions of 5 mm x 2 mm x 0.1 mm and a melting point of 120 degrees Celsius, used to convert electrical energy into mechanical energy, and designed based on the fuse time-current characteristic curve; the characteristic attribute of the ejection signal is a mechanical displacement pulse, with a stroke of 5 mm and a thrust of 10 Newtons, used to directly drive the physical mechanism, and is generated by a spring energy storage mechanism; the characteristic attribute of the fault response control signal is a digitally encoded signal, containing a 16-bit position code and a fault status bit, which serves as a step output to drive the subsequent ejection mechanism.

[0055] S5. Automatic ejection isolation: In response to the fault response control signal, eject the container containing the faulty semiconductor device to the isolation space and achieve physical locking, generating isolation confirmation information containing the isolation status.

[0056] In a specific embodiment of the present invention, the specific process of generating isolation confirmation information containing the isolation status is as follows: the ejection mechanism is driven by the fault response control signal to release the pre-stored energy and push the replaceable container to move along the guide slide.

[0057] Once the replaceable container is moved to the isolation space, the locking mechanism automatically fastens the container to achieve physical locking.

[0058] The physical lock causes the electrical connection between the container and the test system to be disconnected, and an isolation confirmation message is generated based on the electrical connection disconnection state and the physical lock state.

[0059] It should be noted that the operation process of step S5 begins with receiving the fault response control signal and proceeds step by step to generate isolation confirmation information. First, the 16-bit position code in the fault response control signal is recognized by the ejection mechanism decoding module, locating the replaceable container position A1. The ejection mechanism immediately releases the pre-stored compressed spring energy, and the spring pushes the piston rod to strike the bottom of the target container at a set speed, causing the container to move along a 45-degree inclined guide slide. The guide slide surface is coated with a low-friction coefficient material to ensure that the container slides to the entrance of the isolation space. The instant the container fully enters the isolation space, the electromagnetic claws of the locking mechanism automatically engage with the grooves on the side wall of the container, applying clamping force to achieve physical locking, while the sealing ring expands to fill the gap, forming an airtight isolation. After locking is completed, the elastic electrical connector at the bottom of the container is forcibly separated by the mechanical pull rod, disconnecting all electrical connection paths. The system detects the electrical connection disconnection status and the position locking status, and integrates them to generate isolation confirmation information containing the fault position A1 and the isolation status code.

[0060] In one specific embodiment of the present invention, the set speed can be 0.5 m / s. This value is based on ensuring that the replaceable container can move stably and quickly to the isolation space on the guide slide. The speed of 0.5 m / s can effectively utilize the component of gravitational acceleration to optimize the movement time and avoid the test process being prolonged due to the speed being too slow. It can also prevent mechanical impact or inaccurate container positioning caused by the speed being too fast, thereby ensuring the reliable execution of the automatic ejection isolation mechanism and improving the overall test efficiency.

[0061] The guide slide is characterized by a 45-degree inclined metal guide rail, which is used to control the movement trajectory of the container and optimize the movement time based on the component of gravitational acceleration. The locking mechanism is characterized by an electromagnetic mechanical composite device, which includes a neodymium magnet claw excited by current, for permanent fixation. The physical locking is characterized by an irreversible mechanical constraint state, which is achieved by the claw embedding into the container groove, ensuring that it cannot be released without external force.

[0062] S6. Circuit Reorganization and Switching: Based on the isolation confirmation information, disconnect the circuit connection of the fault point and activate the backup container interface to generate a backup activation state containing the new target location.

[0063] In a specific embodiment of the present invention, the specific process of generating a standby active state containing a new target location is as follows: based on the fault location in the isolation confirmation information, the voltage source path of the corresponding interface is disconnected by the automatic switching circuit.

[0064] The automatic switching circuit redirects the voltage source path to a preset backup container interface.

[0065] After verifying the electrical connection status of the standby container interface, a standby activation status containing the location of the standby container interface is generated.

[0066] It should be noted that the operation process of step S6 begins with receiving the isolation confirmation information and proceeds step by step to generate a standby active state. First, the system parses the fault location code A1 and the power failure confirmation flag in the isolation confirmation information, and controls the automatic switching circuit to disconnect the electrical connection of the fault point A1, including cutting off the voltage supply line and the data acquisition line. The moment the fault point is disconnected, the position switching logic is triggered, and the adjacent replaceable position B1 on the test board is automatically enabled as the standby container interface. Next, the voltage source output path is redirected: the voltage output line originally pointing to A1 is physically transferred to the B1 interface through the relay array, and the current sensor acquisition channel is simultaneously adjusted to B1. After the path adjustment, the system verifies the on / off status of the standby interface. When the resistance value of the B1 interface is detected to be less than the set reference resistance value and the voltage transmission error is lower than the set voltage transmission error threshold, the redirection is determined to be successful. Finally, a standby active state containing the new target location B1 identifier and the ready flag is generated.

[0067] In one specific embodiment of the present invention, the set reference resistor value can be 1 ohm, which is based on considerations of circuit connection stability and signal integrity. A resistance value of 1 ohm can effectively monitor the electrical connection status of the backup container interface, ensuring good contact and that signal transmission loss is within an acceptable range. The set voltage transmission error threshold can be 0.1%, which is based on the requirements of high-precision testing. An error threshold of 0.1% can strictly guarantee the transmission accuracy of the voltage source when redirected to the backup container interface, avoiding distortion of test results due to voltage deviation, thereby improving the overall reliability and repeatability of the test.

[0068] Among them, the characteristic attribute of the backup container interface is the replaceable container electrical connection point to be activated, which has the same probe array as the fault location to ensure parameter consistency, and the adjacency relationship is set according to the test board topology diagram; the backup activation status is a data structure containing location identifier and electrical parameters, which is used as a step output to confirm that the new target is ready.

[0069] S7. Test Dataset Generation: Based on the standby active state, repeatedly scan the voltage of the new target semiconductor in the standby container to generate a continuous test dataset.

[0070] In a specific embodiment of the present invention, the process of generating a continuous test dataset is as follows: the same voltage sequence is applied to the new target semiconductor for scanning.

[0071] A high-precision current sensor, redirected to a preset backup container interface, acquires and stores response current data in real time, while recording timestamps and corresponding voltage values.

[0072] Combine all test point data to generate a continuous test dataset.

[0073] It should be noted that the operation process of step S7 begins with receiving the standby active state and proceeds step by step to generate a continuous test dataset. First, the system parses the location identifier B1 and the ready flag in the standby active state to confirm that the standby container interface is ready. The test controller retrieves the voltage sequence 0V1V2V3V4V5V from the original test configuration command generated in S1 and applies the exact same voltage scan sequence to the new target semiconductor device at location B1: starting from 0V, the voltage is gradually increased to a 5V termination value with preset step values. During the scan, the response current data is collected in real time by a high-precision current sensor redirected to B1, while recording the timestamp and corresponding voltage value. The current data of all scan points are stored in non-volatile memory in the order of application, forming an ordered data chain. Finally, all scan data at location B1 is integrated with the test records of the previous normal device, sorted by time axis, and a continuous test dataset containing test trajectories of multiple devices is generated.

[0074] Among them, the characteristic attribute of the new target semiconductor is the device under test in the spare container, with model parameters consistent with the original device, used to continue the test process, and deployed according to the location selected by the automatic switching circuit; the characteristic attribute of the continuous test dataset is a structured database table, containing a four-dimensional data matrix of location identifier, timestamp, voltage value, and current value.

[0075] S8. Assessment Termination and Report Generation: Calculate reliability metrics based on the continuous test dataset and generate the final assessment report.

[0076] In a specific embodiment of the present invention, the specific process of generating the final evaluation report is as follows: check the continuous test dataset to confirm that all test points have been evaluated.

[0077] It should be noted that the system checks the test progress status by traversing the voltage scan records corresponding to all position markers in the continuous test dataset to verify whether the voltage sequence range of 0V to 5V defined in the test configuration command is fully covered. If there are any incomplete test points, the voltage source is immediately invoked to complete the test at that point; when all test points are completed, the analysis program is started.

[0078] The failure rate of semiconductor devices is calculated based on the number of out-of-range events and the total number of test points recorded in the continuous test dataset.

[0079] It should be noted that the formula for calculating the failure rate of semiconductor devices is as follows: Where Ns is the number of events exceeding the standard, that is, the number of test points where the current exceeds the preset safety threshold, and Nt is the total number of test points.

[0080] Based on the voltage scan range and step value, the life index of the semiconductor device is calculated, and the failure rate and life index are integrated to generate a final evaluation report containing the failure rate value, life index and reliability level.

[0081] It should be noted that the formula for calculating the lifetime index of semiconductor devices is as follows: Where B is the base lifespan, set according to the semiconductor device factory testing standards, ΔV m ax is the maximum voltage offset, ΔV a vg is the average voltage step value; and the reliability level of the semiconductor device is determined based on the failure rate and lifespan indicators; a final evaluation report in encrypted PDF format containing failure rate values, lifespan indicators, and reliability level is generated.

[0082] It should also be noted that the specific method for determining the reliability level of a semiconductor device based on failure rate and lifespan indicators is as follows: the failure rate and lifespan indicators are compared with the failure rate range and lifespan indicator range corresponding to each reliability level stored in the database. When both the failure rate and lifespan indicators are within the failure rate range and lifespan indicator range corresponding to a certain reliability level, then that reliability level is taken as the reliability level of the semiconductor device.

[0083] Reference Figure 2 As shown, the second aspect of the present invention provides a dynamic gate voltage reliability evaluation device, comprising: a test configuration instruction generation module, a device installation and initial test module, a voltage scan monitoring module, an anomaly detection and fault response module, an automatic ejection isolation module, a circuit reconfiguration and switching module, a test dataset generation module, an evaluation termination and report generation module, and a database.

[0084] It should be noted that the present invention also includes a database for storing the failure rate range and lifespan index range corresponding to each reliability level.

[0085] The test configuration instruction generation module and the device installation are connected to the initial test module. The device installation is connected to the initial test module and the voltage scan monitoring module. The voltage scan monitoring module is connected to the anomaly detection and fault response module. The anomaly detection and fault response module is connected to the automatic ejection isolation module. The automatic ejection isolation module is connected to the circuit reconfiguration and switching module. The circuit reconfiguration and switching module is connected to the test dataset generation module. The anomaly detection and fault response module, the database, and the test dataset generation module are all connected to the evaluation termination and report generation module.

[0086] The test configuration instruction generation module generates test configuration instructions that include device location identifiers and voltage sequences.

[0087] The device mounting and initial testing module fixes the semiconductor device and applies an initial gate voltage based on the test configuration instructions, generating device response data containing real-time current values.

[0088] The voltage scan monitoring module performs voltage scanning based on device response data and dynamically adjusts the voltage step to generate continuous voltage scan monitoring results.

[0089] The anomaly detection and fault response module analyzes the continuous voltage scan monitoring results and generates a fault response control signal containing the fault location when the current exceeds a preset safety threshold.

[0090] The automatic ejection isolation module responds to the fault response control signal, ejects the container containing the faulty semiconductor device to the isolation space and achieves physical locking, and generates isolation confirmation information containing the isolation status.

[0091] The circuit reconfiguration and switching module disconnects the circuit connection at the fault point based on the isolation confirmation information and activates the backup container interface, generating a backup activation state that includes the new target location.

[0092] The test dataset generation module generates a continuous test dataset by repeatedly scanning the voltage of the new target semiconductor in the standby container based on the standby activation state.

[0093] The assessment termination and report generation module calculates reliability indicators based on the continuous test dataset and generates a final assessment report.

[0094] The above content is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described, or use similar methods to replace them, as long as they do not deviate from the concept of the invention or exceed the scope defined by the present invention, and all such modifications and additions should fall within the protection scope of the present invention.

Claims

1. A method for evaluating the reliability of dynamic gate voltage, characterized in that, include: S1. Test configuration instruction generation: Generates test configuration instructions containing device location identifiers and voltage sequences; S2. Device mounting and initial testing: Based on the test configuration instructions, the semiconductor device is fixed and an initial gate voltage is applied to generate device response data containing real-time current values; S3, Voltage Scan Monitoring: Performs voltage scanning based on device response data and dynamically adjusts the voltage step to generate continuous voltage scan monitoring results; S4. Anomaly Detection and Fault Response: Analyze the continuous voltage scan monitoring results, and when the current exceeds the preset safety threshold, generate a fault response control signal containing the fault location. S5. Automatic ejection isolation: In response to the fault response control signal, eject the container containing the faulty semiconductor device to the isolation space and achieve physical locking, and generate isolation confirmation information containing the isolation status. S6. Circuit Reorganization and Switching: Based on the isolation confirmation information, disconnect the circuit connection of the fault point and activate the backup container interface to generate a backup activation state containing the new target location. S7. Test Dataset Generation: Based on the standby active state, repeatedly scan the voltage of the new target semiconductor in the standby container to generate a continuous test dataset; S8. Assessment Termination and Report Generation: Calculate reliability metrics based on the continuous test dataset and generate the final assessment report.

2. The dynamic gate voltage reliability assessment method according to claim 1, characterized in that: The specific process for generating test configuration instructions containing device location identifiers and voltage sequences is as follows: Receive input device type and target voltage variation pattern to define test requirements; Based on the device dimensions in the test requirements, select and activate a replaceable container location on the test board; Establish an interface connection between the test system and the test voltage source, integrate the activated replaceable container position generator device position identifier, integrate the target voltage change mode to generate a voltage sequence, and together form the test configuration command.

3. The dynamic gate voltage reliability assessment method according to claim 2, characterized in that: The specific process for generating device response data containing real-time current values ​​is as follows: Semiconductor devices are installed into replaceable containers designated by device location identifiers via a quick blind-mate interface. The initial gate voltage is obtained by applying the starting voltage in the voltage sequence to the semiconductor device. The real-time current value and temperature response after the initial gate voltage is applied are collected and together constitute the device response data.

4. The dynamic gate voltage reliability assessment method according to claim 3, characterized in that: The specific process for generating continuous voltage scan monitoring results is as follows: The initial current change rate is calculated based on the real-time current value in the device response data. The voltage step value is dynamically adjusted according to the rate of change of current, and the gate voltage is continuously applied according to the voltage sequence; The system measures the current and energy changes at each voltage step in real time and integrates them to generate continuous voltage scan monitoring results that include voltage-current curves.

5. The dynamic gate voltage reliability assessment method according to claim 4, characterized in that: The specific process for generating the fault response control signal containing the fault location is as follows: The current value in the continuous voltage scan monitoring results is compared with the preset safety threshold to identify events that exceed the limit; The abnormal current generated by the excessive event flows through a specially made thin sheet, causing the current-to-heat conversion and melting of the special thin sheet; The melting of the specially made thin sheet directly triggers a mechanical ejection signal, and the device position identifier is encoded into the ejection signal, together forming a fault response control signal.

6. The dynamic gate voltage reliability assessment method according to claim 1, characterized in that: The specific process for generating isolation confirmation information containing the isolation status is as follows: The fault response control signal drives the ejection mechanism to release pre-stored energy, which propels the replaceable container to move along the guide slide. Once the replaceable container is moved to the isolation space, the locking mechanism automatically latches the container to achieve physical locking; The physical lock causes the electrical connection between the container and the test system to be disconnected, and an isolation confirmation message is generated based on the electrical connection disconnection state and the physical lock state.

7. The dynamic gate voltage reliability assessment method according to claim 5, characterized in that: The specific process for generating a backup active state containing the new target location is as follows: Based on the fault location in the isolation confirmation information, the voltage source path of the corresponding interface is disconnected by the automatic switching circuit; The automatic switching circuit redirects the voltage source path to a preset backup container interface; After verifying the electrical connection status of the standby container interface, a standby activation status containing the location of the standby container interface is generated.

8. The dynamic gate voltage reliability assessment method according to claim 7, characterized in that: The specific process for generating the continuous test dataset is as follows: The same voltage sequence is applied to the new target semiconductor for scanning. A high-precision current sensor, redirected to a preset backup container interface, collects and stores response current data in real time, while recording timestamps and corresponding voltage values. Combine all test point data to generate a continuous test dataset.

9. The dynamic gate voltage reliability assessment method according to claim 8, characterized in that: The specific process for generating the final evaluation report is as follows: Check the continuous test dataset to confirm that all test points have been evaluated; The failure rate of semiconductor devices is calculated based on the number of out-of-range events and the total number of test points recorded in the continuous test dataset. Based on the voltage scan range and step value, the life index of the semiconductor device is calculated, and the failure rate and life index are integrated to generate a final evaluation report containing the failure rate value, life index and reliability level.

10. A dynamic gate voltage reliability assessment device, characterized in that, include: The test configuration instruction generation module generates test configuration instructions that include device location identifiers and voltage sequences. The device mounting and initial test module fixes the semiconductor device and applies an initial gate voltage based on the test configuration instructions, generating device response data containing real-time current values. The voltage scan monitoring module performs voltage scanning based on device response data and dynamically adjusts the voltage step to generate continuous voltage scan monitoring results. The anomaly detection and fault response module analyzes the continuous voltage scan monitoring results and generates a fault response control signal containing the fault location when the current exceeds the preset safety threshold. The automatic ejection isolation module responds to the fault response control signal, ejects the container containing the faulty semiconductor device to the isolation space and achieves physical locking, and generates isolation confirmation information containing the isolation status. The circuit reconfiguration and switching module disconnects the circuit connection at the fault point based on the isolation confirmation information and activates the backup container interface, generating a backup activation state that includes the new target location. The test dataset generation module generates a continuous test dataset by repeatedly scanning the voltage of a new target semiconductor in a standby container based on the standby activation state. The assessment termination and report generation module calculates reliability metrics based on the continuous test dataset and generates the final assessment report.

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