Chip debugging system and method

Abstract

The application provides a chip debugging system and method, a platform debugging controller monitors the power rail state of a target development board, after determining that the to-be-tested chip is powered on successfully, the state of a central processing unit is monitored, after determining that the central processing unit is started successfully and the operating system loading is completed, the to-be-tested chip is fed back to the host computer that the central processing unit is started successfully; the host computer sends a first type of log request to the platform debugging controller after the to-be-tested chip is started successfully, wherein the first type of log request comprises a first type of target event identifier; the platform debugging controller sends the first type of log request to the central processing unit, and feeds back the first type of target log fed back by the central processing unit to the host computer; the host computer performs debugging analysis on the central processing unit according to the first type of target log, and determines whether the central processing unit passes the debugging. The platform debugging controller automatically collects the related information of the to-be-tested chip and provides the host computer for analysis, so that the labor cost is reduced and the debugging efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip debugging, in particular to a chip debugging system and method. BACKGROUND

[0002] In the process of chip back-end testing and delivery to customers, it is necessary to analyze and collect logs of problems encountered in the chip verification process, including hardware debugging and log collection of the processor, to determine the specific location of the problem and track the status of the problem, to provide a basis for subsequent problem analysis and solutions.

[0003] Currently, it mainly relies on manual collection and manual determination, which not only consumes a lot of manpower and time, but also may cause determination errors. SUMMARY

[0004] The purpose of the present application is to provide a chip debugging system and method to improve the above problems.

[0005] In order to achieve the above purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0006] In a first aspect, the embodiments of the present application provide a chip debugging system, which comprises a platform debugging controller and an upper computer.

[0007] The input and output port of the platform debugging controller is connected to the target development board, the input and output port of the target development board is connected to the power supply rail on the target development board, the i-th power supply rail of the target development board is connected to the i-th power supply rail of the chip under test, and the first UART serial port of the platform debugging controller is connected to the central processing unit of the chip under test.

[0008] The platform debugging controller is used to monitor the power supply rail state of the target development board, to monitor the state of the central processing unit after determining that the chip under test is powered on successfully, and to feed back to the upper computer that the chip under test is started successfully after determining that the central processing unit is started successfully and completes operating system loading.

[0009] The upper computer is used to send a first type of log request to the platform debugging controller after the chip under test is started successfully, wherein the first type of log request comprises a first type of target event identifier.

[0010] The platform debugging controller is used to send the first type of log request to the central processing unit and feed back the first type of target log fed back by the central processing unit to the upper computer.

[0011] The upper computer is used to perform debugging analysis on the central processing unit according to the first type of target log, and to determine whether the central processing unit passes the debugging.

[0012] Optionally, the target development board is provided with a selector, the selector includes N inputs, the i-th input of the selector is connected to the i-th power rail of the target development board, the output of the selector is connected to the platform debugging controller through the input and output port of the target development board, and the control end of the selector is also connected to the platform debugging controller.

[0013] After the debugging starts, the platform debugging controller is configured to control the first input of the selector to be conductive with the output of the selector to obtain the level state of the first power rail of the target development board, and after the first power rail of the target development board jumps to high level, the N-th input of the selector is controlled to be conductive with the output of the selector to obtain the level state of the N-th power rail of the target development board, and if the N-th power rail jumps to high level within a preset time length range after the first power rail jumps, it is determined that the power-on is successful.

[0014] The first power rail of the target development board is a power-on start power rail, and the N-th power rail of the target development board is a completion state power rail.

[0015] Optionally, if the N-th power rail does not jump to high level within a preset time length range after the first power rail jumps, the platform debugging controller is configured to determine that the power-on fails, and control the selector to switch the conduction relationship in the selector to determine the fault power rail, and the fault power rail is the first power rail which remains low level.

[0016] Optionally, when it is determined that the power-on fails, the platform debugging controller is configured to control the X-th input of the selector to be conductive with the output of the selector to obtain the level state of the X-th power rail of the target development board, if the X-th power rail is high level, the selector from the X+1-th input to the N-1-th input is controlled to be conductive with the output of the selector to determine the fault power rail, and if the X-th power rail is low level, the selector from the X-1-th input to the 2nd input is controlled to be conductive with the output of the selector to determine the fault power rail, wherein X is the quotient of N divided by 2.

[0017] Optionally, the second UART serial port of the platform debugging controller is connected to the chip control unit of the chip to be tested.

[0018] After the first power rail of the target development board jumps to high level, the platform debugging controller is configured to monitor the state of the chip control unit to determine whether the chip control unit is successfully started, and if the chip control unit is successfully started, it is determined whether the chip control unit is loaded.

[0019] When the chip control unit is successfully started and loaded, it is determined that the chip control unit passes the debugging.

[0020] Optionally, a third UART serial port of the platform debugging controller is connected to a power distribution unit of the chip under test.

[0021] After a first power rail of the target development board jumps to a high level, the platform debugging controller is configured to monitor a state of the power distribution unit to determine whether the power distribution unit is successfully started, and to determine whether the power distribution unit is loaded completely if the power distribution unit is successfully started.

[0022] If the power distribution unit is successfully started and loaded completely, it is determined that the power distribution unit passes the debugging.

[0023] Optionally, a fourth UART serial port of the platform debugging controller is connected to a target processor of the chip under test.

[0024] The host computer is further configured to send a second type of log request to the platform debugging controller after the chip under test is successfully started, wherein the second type of log request comprises a second type of target event identifier.

[0025] The platform debugging controller is configured to send the second type of log request to the target processor and feed back a second type of target log fed back by the target processor to the host computer.

[0026] The host computer is configured to perform debugging analysis on the target processor according to the second type of target log to determine whether the target processor passes the debugging.

[0027] Optionally, the target development board is further configured to adjust an over-temperature identifier bit to an over-temperature protection state when it is detected that a chip temperature of the chip under test is higher than a target temperature.

[0028] The platform debugging controller is configured to monitor the over-temperature identifier bit of the target development board to determine whether over-temperature protection is triggered.

[0029] In a second aspect, an embodiment of the present application provides a chip debugging method applied to the chip debugging system, and the method comprises the following steps:

[0030] The platform debugging controller monitors a power rail state of the target development board, monitors a state of the central processor after it is determined that the chip under test is powered on successfully, and feeds back to the host computer that the chip under test is successfully started after it is determined that the central processor is successfully started and the operating system is loaded.

[0031] The host computer sends a first type of log request to the platform debugging controller after the chip under test is successfully started, wherein the first type of log request comprises a first type of target event identifier.

[0032] The platform debugging controller sends the first type of log request to the central processor, and feeds back the first type of target log fed back by the central processor to the host computer;

[0033] The host computer performs debugging analysis on the central processor according to the first type of target log, and determines whether the central processor passes the debugging.

[0034] In a third aspect, an embodiment of the present application provides a chip debugging method applied to a platform debugging controller in the chip debugging system, and the method comprises the following steps of:

[0035] The platform debugging controller monitors the power rail state of the target development board, monitors the state of the central processor after determining that the chip under test is powered on successfully, and feeds back to the host computer that the chip under test is started successfully after determining that the central processor is started successfully and the operating system loading is completed.

[0036] The platform debugging controller sends the first type of log request transmitted by the host computer to the central processor, and feeds back the first type of target log fed back by the central processor to the host computer, so that the host computer performs debugging analysis on the central processor according to the first type of target log, and determines whether the central processor passes the debugging, wherein the first type of log request comprises a first type of target event identifier.

[0037] Compared with the prior art, the chip debugging system and method provided by the embodiment of the present application, the platform debugging controller is connected to the input and output port of the target development board, the input and output port of the target development board is connected to the power rail on the target development board, the i-th power rail of the target development board is connected to the i-th power rail of the chip under test, and the first UART serial port of the platform debugging controller is connected to the central processor of the chip under test; the platform debugging controller is used for monitoring the power rail state of the target development board, monitoring the state of the central processor after determining that the chip under test is powered on successfully, and feeding back to the host computer that the chip under test is started successfully after determining that the central processor is started successfully and the operating system loading is completed; the host computer is used for sending a first type of log request to the platform debugging controller after the chip under test is started successfully, wherein the first type of log request comprises a first type of target event identifier; the platform debugging controller is used for sending the first type of log request to the central processor, and feeding back the first type of target log fed back by the central processor to the host computer; and the host computer is used for performing debugging analysis on the central processor according to the first type of target log, and determining whether the central processor passes the debugging. The platform debugging controller automatically collects the relevant information of the chip under test and provides the information to the host computer for analysis, thereby reducing the labor cost and improving the debugging efficiency.

[0038] In order to make the above objectives, characteristics and advantages of the present application more apparent, the following preferred embodiments are specifically described in detail below, together with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0040] Figure 1 The schematic diagram of the architecture of the chip debugging system provided by the embodiments of the present application.

[0041] Figure 2 The schematic diagram of the architecture of the chip debugging system provided by the embodiments of the present application.

[0042] Figure 3 The schematic diagram of the flow of the chip debugging method provided by the embodiments of the present application.

[0043] Figure 4 The schematic diagram of the flow of the chip debugging method provided by the embodiments of the present application. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the embodiments of the present application more apparent, the following will clearly and completely describe the technical solutions of the embodiments of the present application with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0045] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art on the basis of the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0046] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0047] It should be noted that, in this article, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0048] In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed, only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application.

[0049] In the description of the present application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set", "connect" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0050] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following examples and features in the examples can be combined with each other without conflict.

[0051] The chip debugging system provided by the embodiments of the present application provides a chip debugging system, please refer to Figure 1 , Figure 1 The chip debugging system provided by the embodiments of the present application provides one of the architecture schematic diagrams of the chip debugging system. The chip debugging system includes a platform debugging controller (also referred to as PDC), a host computer, and the platform debugging controller and the host computer are connected in wired communication or wireless communication.

[0052] The platform debugging controller is connected to the input and output port (GPIO) of the target development board, and the target development board is an engineering development board (EVB) on which the chip to be tested is deployed.

[0053] The input and output port of the target development board is connected to a power supply rail on the target development board, an i-th power supply rail of the target development board is connected to an i-th power supply rail of the chip under test (1≤i≤N, N is the total number of power supply rails of the chip under test), and the first UART serial port of the platform debugging controller is connected to a central processing unit of the chip under test.

[0054] The UART is an English name of Universal Asynchronous Receiver / Transmitter, and a Chinese name of a universal asynchronous receiver / transmitter.

[0055] The platform debugging controller is configured to monitor the state of the power supply rail of the target development board, to monitor the state of the central processing unit after determining that the chip under test is powered on successfully, and to feed back to the host computer that the chip under test is started successfully after determining that the central processing unit is started successfully and the operating system is loaded.

[0056] Optionally, the platform debugging controller monitors the state of the power supply rail of the target development board through the input and output port of the target development board, and the platform debugging controller can also determine whether the central processing unit is started successfully and loaded successfully according to the state of the register corresponding to the central processing unit.

[0057] The host computer is configured to send a first type of log request (corresponding to the central processing unit) to the platform debugging controller after the chip under test is started successfully, wherein the first type of log request comprises a first type of target event identifier.

[0058] The platform debugging controller is configured to send the first type of log request to the central processing unit and feed back the first type of target log fed back by the central processing unit to the host computer, and the first type of target log is a log record corresponding to the first type of target event.

[0059] The host computer is configured to analyze and debug the central processing unit according to the first type of target log, and to determine whether the central processing unit passes the debugging, if no error is found in all the first type of target log, the central processing unit is considered to pass the debugging.

[0060] In the chip debugging system provided in the embodiment of the application, the platform debugging controller automatically collects the relevant information of the chip under test and provides the information to the host computer for analysis, thereby reducing the labor cost and improving the debugging efficiency.

[0061] On the basis of the foregoing, regarding the specific process of determining whether the chip under test is powered on successfully, the embodiment of the application further provides an alternative implementation manner, please continue to refer to Figure 1 .

[0062] The target development board is provided with a selector, the selector includes N input ends, the i-th input end of the selector is connected to the i-th power supply rail of the target development board, the output end of the selector is connected to the platform debugging controller through the input and output port of the target development board, and the control end of the selector is also connected to the platform debugging controller.

[0063] After the debugging starts, the platform debugging controller is used for controlling the first input end of the selector to be conductive with the output end thereof, so as to obtain the level state of the first power supply rail of the target development board, after the first power supply rail of the target development board jumps to the high level (the start-up power-on state is opened), the N-th input end of the selector is controlled to be conductive with the output end thereof, so as to obtain the level state of the N-th power supply rail of the target development board, and if the N-th power supply rail jumps to the high level within a preset time length range after the first power supply rail jumps, it is determined that the power-on is successful.

[0064] The first power supply rail of the target development board is the start-up power supply rail, and the N-th power supply rail of the target development board is the completion state power supply rail.

[0065] If the N-th power supply rail does not jump to the high level within the preset time length range after the first power supply rail jumps, the platform debugging controller is used for determining that the power-on fails, and controlling the selector to switch the conduction relationship in the selector, so as to determine the fault power supply rail, and the fault power supply rail is the first power supply rail which remains at the low level.

[0066] On the basis of the foregoing, in order to quickly locate the problem, the embodiment of the application also provides an optional implementation, please refer to the following.

[0067] When it is determined that the power-on fails, the platform debugging controller is used for controlling the X-th input end of the selector to be conductive with the output end thereof, so as to obtain the level state of the X-th power supply rail of the target development board, if the X-th power supply rail is at the high level, the selector is controlled to be conductive from the X+1-th input end to the N-1-th input end with the output end thereof, so as to determine the fault power supply rail, and if the X-th power supply rail is at the low level, the selector is controlled to be conductive from the X-1-th input end to the second input end with the output end thereof, so as to determine the fault power supply rail, wherein X is the quotient of N divided by 2.

[0068] Please continue to refer to Figure 1 In an optional implementation, the second UART serial port of the platform debugging controller is connected to the chip control unit of the chip to be tested, and the chip control unit can be but is not limited to a microcontroller unit (MCU).

[0069] After the first power supply rail of the target development board jumps to the high level, the platform debugging controller is used for monitoring the state of the chip control unit, so as to determine whether the chip control unit is started successfully, and if the chip control unit is started successfully, whether the chip control unit is loaded completely is determined.

[0070] When the chip control unit is successfully started and the loading is completed, it is determined that the chip control unit passes the debugging, and when the chip control unit is not successfully started or the loading is not completed, it is indicated that the debugging of the chip control unit fails, and an error report of the chip control unit is generated.

[0071] Please continue to refer to Figure 1 In an optional embodiment, the third UART serial port of the platform debugging controller is connected to a power distribution unit of the chip to be tested, and the power distribution unit can be but is not limited to a microcontroller unit (MCU).

[0072] After the first power rail of the target development board jumps to high level, the platform debugging controller is used to monitor the state of the power distribution unit to determine whether the power distribution unit is successfully started, and if the power distribution unit is successfully started, whether the power distribution unit is loaded.

[0073] When the power distribution unit is successfully started and the loading is completed, it is determined that the power distribution unit passes the debugging, and when the power distribution unit is not successfully started or the loading is not completed, it is indicated that the debugging of the power distribution unit fails, and an error report of the power distribution unit is generated.

[0074] Please refer to Figure 2 , Figure 2 The second schematic diagram of the architecture of the chip debugging system provided by the embodiment of the application. The fourth UART serial port of the platform debugging controller is connected to a target processor of the chip to be tested, and the target processor can be but is not limited to a display processing unit (DPU), a neural network processing unit (NPU), a video processing unit (VPU) and a graphics processing unit (GPU).

[0075] The host computer is further used to send a second type of log request (corresponding to the target processor) to the platform debugging controller after the chip to be tested is successfully started, wherein the second type of log request comprises a second type of target event identifier.

[0076] The platform debugging controller is used to send the second type of log request to the target processor, and feed back the second type of target log fed back by the target processor to the host computer, and the second type of target log is a log record corresponding to the second type of target event.

[0077] The host computer is used to perform debugging analysis on the target processor according to the second type of target log, and determine whether the target processor passes the debugging, and if no error is found in all the second type of target log, it is considered that the target processor passes the debugging.

[0078] The chip debugging system provided by the embodiment of the application supports collecting the key register state of the corresponding IP (target processor), thereby confirming the health state of the sub-module. This helps to more comprehensively understand the system running situation, and provides support for subsequent rapid iteration and requirement expansion. Not only does it meet the current requirements, but also has good scalability, and can adapt to complex scenarios and diversified requirements that may appear in the future.

[0079] Please continue to refer to Figure 2 , and the target development board is further configured to adjust the over-temperature identification bit to an over-temperature protection state when detecting that the chip temperature of the chip under test is higher than the target temperature.

[0080] The platform debugging controller is configured to monitor the over-temperature identification bit of the target development board to determine whether to trigger over-temperature protection.

[0081] More GPIO controllers are deployed to collect the key level state of the board. For example, by detecting whether the chip triggers the over-temperature protection and other key signals, the problem diagnosis information is further enriched.

[0082] The embodiment of the application further provides a chip debugging method applied to the chip debugging system, please refer to Figure 3 , Figure 3 The chip debugging method provided by the embodiment of the application is shown in one of the flowcharts. The chip debugging method comprises: S11, S21, S12, S22, and is specifically described as follows.

[0083] S11, the platform debugging controller monitors the power rail state of the target development board, monitors the state of the central processor after determining that the chip under test is powered on successfully, and feeds back to the host computer that the chip under test is started successfully after determining that the central processor is started successfully and the operating system loading is completed.

[0084] S21, the host computer sends a first type of log request to the platform debugging controller after the chip under test is started successfully, wherein the first type of log request comprises a first type of target event identification.

[0085] S12, the platform debugging controller sends the first type of log request to the central processor, and feeds back the first type of target log fed back by the central processor to the host computer.

[0086] S22, the host computer performs debugging analysis on the central processor according to the first type of target log, and determines whether the central processor passes the debugging.

[0087] The embodiment of the application further provides a chip debugging method applied to the platform debugging controller in the chip debugging system, please refer to Figure 4 , Figure 4The second flowchart of the chip debugging method provided by the embodiment of the present application is shown in the figure. The chip debugging method comprises the following steps.

[0088] In S31, the platform debugging controller monitors the power rail state of the target development board. After determining that the chip under test is powered on successfully, the platform debugging controller monitors the state of the central processor. After determining that the central processor is started successfully and the operating system loading is completed, the platform debugging controller feeds back to the host computer that the chip under test is started successfully.

[0089] In S32, the platform debugging controller sends the first type of log request transmitted by the host computer to the central processor, and feeds back the first type of target log fed back by the central processor to the host computer, so that the host computer performs debugging analysis on the central processor according to the first type of target log to determine whether the central processor passes the debugging. The first type of log request comprises a first type of target event identifier.

[0090] In summary, the chip debugging system and method provided by the embodiment of the present application is characterized in that the platform debugging controller is connected to the input and output port of the target development board, the input and output port of the target development board is connected to the power rail on the target development board, the i-th power rail of the target development board is connected to the i-th power rail of the chip under test, and the first UART serial port of the platform debugging controller is connected to the central processor of the chip under test. The platform debugging controller is configured to monitor the power rail state of the target development board. After determining that the chip under test is powered on successfully, the platform debugging controller monitors the state of the central processor. After determining that the central processor is started successfully and the operating system loading is completed, the platform debugging controller feeds back to the host computer that the chip under test is started successfully. The host computer is configured to send the first type of log request to the platform debugging controller after the chip under test is started successfully, wherein the first type of log request comprises a first type of target event identifier. The platform debugging controller is configured to send the first type of log request to the central processor, and feed back the first type of target log fed back by the central processor to the host computer. The host computer is configured to perform debugging analysis on the central processor according to the first type of target log to determine whether the central processor passes the debugging. The platform debugging controller automatically collects the relevant information of the chip under test and provides the information to the host computer for analysis, thereby reducing the labor cost and improving the debugging efficiency.

[0091] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0092] It will be apparent to those skilled in the art that the application is not limited to the details of the above-exemplified embodiments and that the present application can be implemented in other particular forms without departing from the spirit or essential characteristics of the present application. The embodiments should therefore be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the above description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims with respect to the figures of the patent document.

Claims

1. A chip debug system, characterized by, The chip debugging system comprises a platform debugging controller and a host computer; The input and output port of the platform debugging controller is connected to a target development board, the input and output port of the target development board is connected to a power supply rail on the target development board, the i-th power supply rail of the target development board is connected to the i-th power supply rail of a chip under test, and the first UART serial port of the platform debugging controller is connected to a central processing unit of the chip under test; The platform debugging controller is configured to monitor the state of the power supply rail of the target development board, monitor the state of the central processing unit after determining that the chip under test is powered on successfully, and feed back to the host computer that the chip under test is started successfully after determining that the central processing unit is started successfully and the operating system loading is completed. The host computer is configured to send a first type of log request to the platform debugging controller after the chip under test is started successfully, wherein the first type of log request comprises a first type of target event identifier. The platform debugging controller is configured to send the first type of log request to the central processing unit and feed back the first type of target log fed back by the central processing unit to the host computer. The host computer is configured to debug and analyze the central processing unit according to the first type of target log and determine whether the central processing unit passes the debugging.

2. The chip debug system of claim 1, wherein, The target development board is provided with a selector, the selector comprises N input ends, the i-th input end of the selector is connected to the i-th power supply rail of the target development board, the output end of the selector is connected to the platform debugging controller through the input and output port of the target development board, and the control end of the selector is also connected to the platform debugging controller. After the debugging starts, the platform debugging controller is configured to control the first input end of the selector to be conductive with the output end thereof to obtain the level state of the first power supply rail of the target development board, control the N-th input end of the selector to be conductive with the output end thereof to obtain the level state of the N-th power supply rail of the target development board after the first power supply rail of the target development board jumps to high level, and determine that the power-on is successful if the N-th power supply rail jumps to high level within a preset time length range after the first power supply rail jumps. The first power supply rail of the target development board is a power-on start power supply rail, and the N-th power supply rail of the target development board is a completion state power supply rail.

3. The chip debug system of claim 2, wherein, If the N-th power supply rail does not jump to high level within the preset time length range after the first power supply rail jumps, the platform debugging controller is configured to determine that the power-on fails, control the selector to switch the conduction relationship in the selector, and further determine a fault power supply rail, wherein the fault power supply rail is the first power supply rail that remains low.

4. The chip debug system of claim 3, wherein, When it is determined that the power-on fails, the platform debugging controller is configured to control the Xth input of the selector to be connected to the output of the selector to obtain the level state of the Xth power supply rail of the target development board; if the Xth power supply rail is high, the platform debugging controller is configured to control the selector to be connected from the X+1th input to the N-1th input to the output of the selector, so as to determine the faulty power supply rail; if the Xth power supply rail is low, the platform debugging controller is configured to control the selector to be connected from the X-1th input to the 2nd input to the output of the selector, so as to determine the faulty power supply rail, wherein X is the quotient of N divided by 2.

5. The chip debug system of claim 1, wherein, The second UART serial port of the platform debugging controller is connected to the chip control unit of the chip under test. After the 1st power supply rail of the target development board jumps to high, the platform debugging controller is configured to monitor the state of the chip control unit to determine whether the chip control unit is successfully started, and if the chip control unit is successfully started, to determine whether the chip control unit is loaded. When the chip control unit is successfully started and loaded, it is determined that the chip control unit passes the debugging.

6. The chip debug system of claim 1, wherein, The third UART serial port of the platform debugging controller is connected to the power supply distribution unit of the chip under test. After the 1st power supply rail of the target development board jumps to high, the platform debugging controller is configured to monitor the state of the power supply distribution unit to determine whether the power supply distribution unit is successfully started, and if the power supply distribution unit is successfully started, to determine whether the power supply distribution unit is loaded. When the power supply distribution unit is successfully started and loaded, it is determined that the power supply distribution unit passes the debugging.

7. The chip debug system of claim 1, wherein, The fourth UART serial port of the platform debugging controller is connected to the target processor of the chip under test. The host computer is further configured to send a second type of log request to the platform debugging controller after the chip under test is successfully started, wherein the second type of log request comprises a second type of target event identifier. The platform debugging controller is configured to send the second type of log request to the target processor and feed back the second type of target log fed back by the target processor to the host computer. The host computer is configured to perform debugging analysis on the target processor according to the second type of target log to determine whether the target processor passes the debugging.

8. The chip debugging system of claim 1, wherein The target development board is further configured to adjust an over-temperature identifier bit to an over-temperature protection state when it is detected that the chip temperature of the chip under test is higher than a target temperature. The platform debugging controller is configured to monitor the over-temperature identifier bit of the target development board to determine whether the over-temperature protection is triggered.

9. A method of debugging a chip, characterized by, The method is applied to the chip debugging system of any one of claims 1-8, and the method comprises: The platform debugging controller monitors the state of the central processor after it is determined that the chip under test is successfully powered on, and feeds back to the host computer that the chip under test is successfully started after it is determined that the central processor is successfully started and the operating system is loaded. The host computer sends a first type of log request to the platform debugging controller after the to-be-tested chip is successfully started, wherein the first type of log request comprises a first type of target event identifier; The platform debugging controller sends the first type of log request to the central processor and feeds back a first type of target log fed back by the central processor to the host computer; The host computer performs debugging analysis on the central processor according to the first type of target log and determines whether the central processor passes the debugging.

10. A method of debugging a chip, characterized by, The platform debugging controller applied to the chip debugging system in any one of claims 1-8, the method comprises: The platform debugging controller monitors the power rail state of the target development board, determines that the to-be-tested chip is powered on successfully, monitors the state of the central processor, determines that the central processor is successfully started and completes operating system loading, and feeds back to the host computer that the to-be-tested chip is successfully started; The platform debugging controller sends the first type of log request transmitted by the host computer to the central processor and feeds back a first type of target log fed back by the central processor to the host computer, so that the host computer performs debugging analysis on the central processor according to the first type of target log and determines whether the central processor passes the debugging, wherein the first type of log request comprises a first type of target event identifier.

Images