A multi-channel parallel-based solid state disk data prefetching method
By employing a multi-channel parallel architecture and intelligent prefetching algorithm, the problems of uneven channel load and coarse prefetching granularity in SSDs are solved, achieving efficient data prefetching and improving SSD IOPS and bandwidth performance.
Patent Information
- Application Number
- CN202511445870.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-11
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2045-10-11
AI Technical Summary
Existing SSD multi-channel parallel architectures suffer from issues such as unbalanced channel load, coarse prefetch granularity, and lack of cross-channel coordination, resulting in significant IOPS loss in mixed load scenarios and sequential read/write bandwidth failing to break through theoretical bottlenecks.
Employing a multi-channel parallel architecture and intelligent prefetching algorithm, the load monitoring module collects channel parameters in real time, dynamically adjusts the prefetching granularity, prefetches data across channels in segments, and optimizes task allocation using a cross-channel scheduling arbiter. Combined with hardware and firmware co-design, it achieves channel load balancing and collaborative data transmission.
It significantly improves the prefetch hit rate and bandwidth utilization in mixed load scenarios, reduces the load difference between channels, meets low latency requirements, and increases random read IOPS and sequential read/write bandwidth.
Smart Images
Figure CN120929021B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of solid state disks, in particular to a solid state disk data prefetching method based on multi-channel parallelism. BACKGROUND
[0002] In the multi-channel parallel architecture of SSD, such as supporting multiple NAND channels, the existing data prefetching technology has the following core problems:
[0003] 1. Channel load imbalance: the traditional prefetching algorithm does not consider the real-time load difference between channels, resulting in the concentration of prefetching data in a few busy channels, and low prefetching data hit rate;
[0004] 2. Coarse-grained prefetching: LBA (Logical Block Address) is used as the unit of prefetching, which cannot adapt to random access scenarios, and the utilization rate of prefetching data is insufficient;
[0005] 3. Lack of cross-channel coordination: the prefetching operation is limited to the current channel, and the bandwidth resources of the idle channels are not utilized, and the overall bandwidth utilization rate needs to be improved.
[0006] The existing solution causes significant IOPS loss of SSD in mixed load scenarios, and the sequential read-write bandwidth cannot break through the theoretical value bottleneck. SUMMARY
[0007] To overcome the shortcomings of the prior art, the present application provides a solid state disk data prefetching method based on multi-channel parallelism, which improves data access efficiency through multi-channel parallel architecture and intelligent prefetching algorithm, and hardware-firmware collaborative design, suitable for enterprise-level high-performance SSD and storage arrays.
[0008] To achieve the above purpose, a solid state disk data prefetching method based on multi-channel parallelism is designed, including the following steps:
[0009] The hardware architecture step of multi-channel load sensing; including:
[0010] A1, a separate load monitoring module is deployed for each NAND channel, which collects parameters of each NAND channel in real time and calculates the load index of each channel;
[0011] A2, a hardware priority encoder is used to convert the channel load index into a priority code;
[0012] A3, the priority code is transmitted to the cross-channel scheduling arbitrator, and a dynamic weight distribution algorithm is used;
[0013] The step of setting an intelligent prefetching strategy engine at the firmware layer; including:
[0014] B1, dynamic prefetch granularity adjustment algorithm: dynamically adjust the prefetch unit size according to the host access mode; use the sliding window algorithm to calculate the address continuity rate in real time, and dynamically adjust the prefetch strategy;
[0015] B2, cross-channel data fragment prefetching: divide the target prefetch data into multiple sub-blocks, assign them to different idle channels for parallel reading; the sub-block address is mapped to the channel with the lowest load through a hash function; each channel independently performs sub-block reading, and reorganizes the data in the main control cache after completion;
[0016] The prefetch data cache management step comprises:
[0017] C1, channel-specific prefetch cache: divide the main control cache into sub-caches equal to the number of channels, and each sub-cache only stores the prefetch data of the corresponding channel to avoid cross-channel cache pollution;
[0018] C2, prefetch data validity verification: when the host initiates a read request, first query all channel sub-caches; if the data exists in any sub-cache, select the channel with the lowest load through the cross-channel arbitrator to return the data; if not, trigger multi-channel cooperative prefetching.
[0019] In step A1, the load monitoring module collects the channel queue depth, data transmission rate, and waiting cycle number in real time, including:
[0020] Queue depth counter, which counts the number of pending commands in the NAND channel command queue in real time;
[0021] Transmission rate sensor, which measures the data transmission volume per unit time;
[0022] Waiting cycle timer, which records the channel idle waiting time;
[0023] Data register, which temporarily stores raw data;
[0024] Load index generator, which uses a normalized weighted summation algorithm to generate a load index based on the parameter information collected by the load monitoring module through a combination of logic circuits to complete parameter normalization, weighted summation, and result quantization processing.
[0025] The hardware priority encoder and the cross-channel scheduling arbitrator are further provided with:
[0026] Load index register: stores the latest load index of each channel, supports simultaneous read and write operations;
[0027] AXI bus interface: transmits data to the cross-channel scheduling arbitrator through the AXI bus.
[0028] In the step A3, the cross-channel scheduling arbitrator adopts a dynamic weight distribution algorithm, including: a low-load channel is given a high weight, and a prefetch task is preferentially distributed; a high-load channel enters a throttle mode, and a prefetch request rate is limited.
[0029] In the step A3, the cross-channel scheduling arbitrator includes:
[0030] A load index input unit receives a priority-encoded load index, supports parallel input of all channels of a solid state disk, and supports parallel input of all channels of a solid state disk.
[0031] A weight calculation unit calculates the weight of each channel.
[0032] An arbitration decision engine makes a decision logic to select a free channel with the highest weight, and adopts a polling mechanism in multi-channel concurrency.
[0033] A throttle controller controls the request rate through a token bucket algorithm, and guarantees that the maximum prefetch bandwidth occupancy is less than or equal to 30%.
[0034] A prefetch task distributor uniformly distributes tasks to free channels.
[0035] In the step B1, the size of the prefetch unit is dynamically adjusted according to the host access mode, including: a larger prefetch unit and a prefetch depth are used in sequential access; and the prefetch unit and the prefetch depth are reduced in random access, and invalid prefetch is reduced.
[0036] In the step B1, the size of the prefetch unit is configured through a register, and the firmware automatically switches according to a continuity rate; a sliding window address continuity rate is calculated using C language, the window contains a plurality of LBAs, and a threshold value is set for continuous address determination.
[0037] In the step B2, a hash function is used in the fragmentation algorithm to map the LBA to a channel ID; sub-block reorganization is realized by a hardware description language in the main control DDR cache, and multi-channel data parallel reception and reorganization are supported.
[0038] In the step B2, sub-block level error checking is supported, and a single sub-block error does not affect the transmission of other sub-blocks.
[0039] In the step C1, a least recently used (LRU) strategy is used for the sub-cache to improve the prefetch data hit rate. Compared with the prior art, the present application has the following technical effects:
[0040] 1. The prefetch efficiency is significantly improved, the prefetch hit rate is improved in a mixed load scenario, the random read IOPS is significantly improved, the sequential read and write bandwidth is close to the theoretical value, and the traditional scheme is obviously improved.
[0041] 2. Channel load balancing optimization, significant reduction in inter-channel load difference, significant improvement in idle channel utilization, and significant improvement in multi-channel parallel efficiency; throttling mode narrows the delay fluctuation of busy channels, meeting low delay requirements.
[0042] 3. Ensure flexibility and reliability, dynamically adjust the pre-fetch granularity to different application scenarios to reduce random access delay; sub-block level transmission and error checking ensure the effectiveness of pre-fetch data, and the data reorganization delay is controlled within a reasonable range. BRIEF DESCRIPTION OF DRAWINGS
[0043] Figure 1 The hardware architecture diagram of the present application.
[0044] Figure 2 The schematic diagram of the load monitoring module of the present application.
[0045] Figure 3 The schematic diagram of the cross-channel scheduling arbitrator of the present application.
[0046] Figure 4 The flowchart of the present application in use. DETAILED DESCRIPTION
[0047] The present application will be further described below according to the drawings.
[0048] As shown in Figure 1 The solid state disk data pre-fetching method based on multi-channel parallel in the embodiment includes the following steps:
[0049] Multi-channel load-aware hardware architecture steps; including:
[0050] A1, deploy an independent load monitoring module for each NAND channel, collect parameters of each NAND channel in real time, and calculate the load index of each channel;
[0051] A2, use a hardware priority encoder to convert the load index of each channel into a priority code;
[0052] A3, the priority code is transmitted to a cross-channel scheduling arbitrator, which supports multi-channel parallel scheduling and uses a dynamic weight distribution algorithm to ensure that the pre-fetch tasks are evenly distributed to idle channels;
[0053] The steps of setting an intelligent pre-fetch strategy engine at the firmware layer; including:
[0054] B1, dynamic pre-fetch granularity adjustment algorithm: dynamically adjust the pre-fetch unit size according to the host access mode; use a sliding window algorithm to calculate the address continuity rate in real time and dynamically adjust the pre-fetch strategy;
[0055] B2, cross-channel data slice prefetching: the target prefetch data is divided into multiple sub-blocks, which are assigned to different idle channels for parallel reading; the sub-block addresses are mapped to the channel with the lowest load through a hash function; each channel independently performs sub-block reading, and after completion, the data is recombined in the master cache;
[0056] a prefetch data cache management step; comprising:
[0057] C1, channel-specific prefetch cache: the master cache is divided into sub-caches equal to the number of channels, each sub-cache only stores the prefetch data of the corresponding channel, avoiding cross-channel cache pollution;
[0058] C2, prefetch data validity verification: when the host initiates a read request, first query all channel sub-caches; if the data exists in any sub-cache, select the channel with the lowest load through the cross-channel arbitrator to return the data; if not, trigger multi-channel cooperative prefetching, the prefetching bandwidth does not exceed 30% of the total bandwidth, ensuring that it does not affect real-time IO.
[0059] In step A1, the load monitoring module collects the channel queue depth, data transmission rate, and waiting cycle number in real time, including:
[0060] Queue depth counter, which counts the number of pending commands in the NAND channel command queue in real time; in this embodiment, a 32-bit up counter is used.
[0061] Transmission rate sensor, which measures the data transmission volume per unit time; in this embodiment, a clock cycle counter + data transmission volume register is used.
[0062] Waiting cycle timer, which records the channel idle waiting time; in this embodiment, a high-precision timer with a resolution of 10 ns is used.
[0063] Data register, which temporarily stores raw data, and a synchronous latching mechanism ensures data consistency. In this embodiment, a 32-bit register is used.
[0064] Load index generator, which uses a normalized weighted summation algorithm, based on the parameter information collected by the load monitoring module, to complete parameter normalization, weighted summation, and result quantization processing through a combination of logic circuits, finally outputting a load index of 0-255; in specific use, the combination of logic circuits includes an adder and a comparator. The larger the output load index value, the higher the channel load and the busier it is, ensuring that the calculation result can directly reflect the real-time busy degree of the channel, and adapt to subsequent priority encoding and arbitration scheduling.
[0065] Between the hardware priority encoder and the cross-channel scheduling arbitrator, there is also:
[0066] Load index register: stores the latest load index of each channel, supporting simultaneous read and write operations;
[0067] AXI bus interface: transmit data to cross-channel scheduling arbitrator through AXI bus.
[0068] In specific use, the hardware priority encoder selects an encoder supporting high-frequency update, and in the embodiment, an encoder with 10us / time update is selected.
[0069] In step A3, the cross-channel scheduling arbitrator adopts a dynamic weight distribution algorithm, including: a low-load channel is given a high weight, and a prefetch task is preferentially distributed; a high-load channel enters a throttling mode, and a prefetch request rate is limited.
[0070] In step A3, the cross-channel scheduling arbitrator includes:
[0071] A load index input unit receives a priority-encoded load index, supports parallel input of all channels of a solid state disk, and supports parallel input of all channels of a solid state disk;
[0072] A weight calculation unit calculates the weight of each channel;
[0073] An arbitration decision engine, the decision logic is to select the idle channel with the highest weight, and a polling mechanism is used when multiple channels are concurrent;
[0074] A throttling controller: controls the request rate through a token bucket algorithm, and ensures that the maximum prefetch bandwidth occupancy is ≤30%;
[0075] A prefetch task distributor: evenly distributes tasks to idle channels.
[0076] In the cross-channel scheduling arbitrator, a plurality of configuration registers are also set to temporarily store data.
[0077] The cross-channel scheduling arbitrator realizes dynamic weight distribution based on FPGA, the weight register is updated at a high frequency, the arbitration logic uses a priority encoder IP core, and supports multi-channel concurrent processing.
[0078] In step B1, the prefetch unit size is dynamically adjusted according to the host access mode, including: a larger prefetch unit and prefetch depth are used when sequentially accessing; and the prefetch unit and prefetch depth are reduced when randomly accessing, and invalid prefetch is reduced.
[0079] In step B1, the prefetch unit size is configured through a register, and the firmware automatically switches according to the continuity rate; a sliding window address continuity rate is calculated using C language, the window contains a plurality of LBAs, and a threshold value is set for continuous address determination.
[0080] In step B2, the fragmentation algorithm uses a hash function to map the LBA to a channel ID; sub-block reorganization is realized through a hardware description language in the main control DDR cache, and supports multi-channel data parallel reception and reorganization.
[0081] In step B2, sub-block level error checking is supported, and a single sub-block error does not affect the transmission of other sub-blocks.
[0082] In step C1, a least recently used (LRU) strategy is used for sub-cache, to improve the hit rate of pre-fetch data.
[0083] As shown in the specific example of the present application, the following steps are included: Figure 4
[0084] Load data collection: NAND channel queue depth and transmission rate are collected every 10 microseconds, and address continuity rate is calculated every 1 millisecond, with a sliding window containing the last 1000 LBA accesses.
[0085] Access mode determination: if the continuity rate is greater than 80%, the sequential access strategy is triggered, the pre-fetch unit (PU) is set to 128 KB, and the pre-fetch depth is 8 levels; if the continuity rate is less than 30%, the random access strategy is triggered, the PU is reduced to 4 KB, and the pre-fetch depth is 2 levels; in the intermediate interval, the current PU size is maintained, and the pre-fetch depth is dynamically adjusted.
[0086] Cross-channel fragment pre-fetching: the target PU data is divided into 16 KB sub-blocks, with 128 KB PUs divided into 8 blocks and 4 KB PUs not divided; the sub-blocks are mapped to the 3 channels with the lowest load by using a MurmurHash3 hash function, and then read in parallel and recombined in the main control cache.
[0087] Strategy feedback optimization: the sliding window size and continuity rate threshold are adjusted according to the real-time calculated pre-fetch hit rate, forming a closed-loop optimization.
[0088] To verify the effectiveness of the method in this embodiment, performance tests are conducted, including pre-fetch hit rate, channel load balancing, and delay stability tests. The test scenario is set to generate a mixed load of 70% random read + 30% sequential write load with a block size of 4 KB. In the pre-fetch hit rate test, the hit rate of the present application is 85.2%, and that of the traditional scheme is 71.5%, with an increase of 18%. In the channel load balancing test, a protocol analyzer is used to monitor the queue depth of each channel, and the standard deviation between channels is significantly reduced in the present application, and the load balancing degree is significantly improved. In the delay stability test, a burst of traffic is injected into the busy channel, and the delay fluctuation range of the present application is significantly narrowed, meeting the QoS requirements of related protocols.
[0089] The core components of the application include a plurality of channel load sensing modules integrated in the master chip, a cross-channel scheduling arbitrator, an intelligent prefetch strategy engine and a prefetch data cache management system, which work together through hardware and firmware to provide a basic support for efficient data prefetching. In the load monitoring path, the load sensor of each NAND channel, i.e. the queue depth counter, the transmission rate sensor and the waiting period timer, collects data in real time, generates a load index of 0-255 through a hardware priority encoder, and transmits it to the arbitrator through the AXI bus. In the prefetch task allocation, the arbitrator dynamically allocates the prefetch task according to the load index, the low-load channel (load index < 64) is given priority to obtain the task, and the high-load channel (≥ 128) enters the throttle mode, and the task is distributed to the NAND channel array through the cross-channel data bus. In the cache management, the channel-specific sub-cache is one-to-one mapped with the corresponding NAND channel, the prefetch data is stored in the sub-cache after being screened by the arbitrator, and the host read request is responded through the sub-cache of the channel with the lowest load.
[0090] Through dynamic load monitoring, cross-channel prefetch scheduling and fine-grained data fragmentation technology, the application realizes the balanced allocation of prefetch data, on-demand granularity adjustment and cross-channel collaborative transmission, significantly improving the prefetch hit rate and bandwidth utilization of multi-channel SSD.
Claims
1. A data prefetching method for solid-state drives based on multi-channel parallel processing, characterized in that: Includes the following steps: The hardware architecture steps for multi-channel load awareness include: A1 deploys an independent load monitoring module for each NAND channel to collect parameters of each NAND channel in real time and calculate the load index of each channel. A2 uses a hardware priority encoder to convert the load index of each channel into priority code; A3, priority encoding is transmitted to the cross-channel scheduling arbitrator, using a dynamic weight allocation algorithm; The steps for configuring the intelligent prefetch strategy engine at the firmware layer include: B1, Dynamic prefetch granularity adjustment algorithm: dynamically adjusts the prefetch unit size according to the host access mode; uses a sliding window algorithm to calculate the address continuity rate in real time and dynamically adjust the prefetch strategy; B2, cross-channel data fragmentation prefetching: The target prefetched data is divided into multiple sub-blocks and allocated to different idle channels for parallel reading; the sub-block address is mapped to the channel with the lowest load through a hash function; each channel independently executes sub-block reading, and the data is reassembled in the main control cache after completion; Prefetch data cache management steps; including: C1, Channel-specific prefetch cache: The main control cache is divided into sub-caches equal to the number of channels. Each sub-cache stores only the prefetch data of the corresponding channel, avoiding cross-channel cache pollution; C2, Prefetch data validity verification: When the host initiates a read request, it first queries all channel sub-caches; if the data exists in any sub-cache, it selects the channel with the lowest load through the cross-channel arbitrator to return the data; if it does not exist, it triggers multi-channel collaborative prefetching.
2. The solid-state drive data prefetching method based on multi-channel parallel processing according to claim 1, characterized in that: In step A1, the load monitoring module collects channel queue depth, data transmission rate, and waiting cycle count in real time, and includes the following built-in features: Queue depth counter, which counts the number of pending commands in the NAND channel command queue in real time; Transmission rate sensor, which measures the amount of data transmitted per unit time; Waiting period timer, records the channel idle waiting time; Data registers are used to temporarily store raw data. The load index generator uses a normalized weighted summation algorithm. Based on the parameter information collected by the load monitoring module, it completes parameter normalization, weighted summation, and result quantization through combinational logic circuits, and finally outputs the load index.
3. The solid-state drive data prefetching method based on multi-channel parallel processing according to claim 1, characterized in that: The hardware priority encoder and the cross-channel scheduling arbitrator are further provided with: Load Index Register: Stores the latest load index for each channel and supports simultaneous read and write operations; AXI Bus Interface: Transmits data to the cross-channel scheduling arbitrator via the AXI bus.
4. The solid-state drive data prefetching method based on multi-channel parallel processing according to claim 1, characterized in that: In step A3, the cross-channel scheduling arbitrator adopts a dynamic weight allocation algorithm, including: assigning high weights to low-load channels and prioritizing the allocation of prefetch tasks; and putting high-load channels into throttling mode to limit the prefetch request rate.
5. The solid-state drive data prefetching method based on multi-channel parallel processing according to claim 1, characterized in that: In step A3, the cross-channel scheduling arbitrator includes: The load index input unit receives the priority-encoded load index and supports parallel input from all channels of the solid-state drive. The weight calculation unit calculates the weight of each channel. The arbitration decision engine selects the idle channel with the highest weight, and uses a polling mechanism when multiple channels are concurrent. Throttling controller: Controls the request rate using the token bucket algorithm to ensure that the maximum prefetch bandwidth usage is ≤30%; Prefetch Task Distributor: Distributes tasks evenly across idle channels.
6. The solid-state drive data prefetching method based on multi-channel parallel processing according to claim 1, characterized in that: In step B1, the size of the prefetch cell is configured through a register and automatically switched by the firmware based on the continuity rate; the sliding window address continuity rate calculation is implemented using C language, the window contains several LBAs, and a threshold is set for continuous address determination.
7. A data prefetching method for solid-state drives based on multi-channel parallel processing according to claim 1, characterized in that: In step B2, the sharding algorithm uses a hash function to map LBAs to channel IDs; sub-block reassembly is implemented in the main controller DDR cache using a hardware description language, supporting parallel reception and reassembly of multi-channel data.
8. A data prefetching method for solid-state drives based on multi-channel parallel processing according to claim 1, characterized in that: In step B2, sub-block level error checking is supported, and an error in a single sub-block does not affect the transmission of other sub-blocks.
9. A data prefetching method for solid-state drives based on multi-channel parallel processing according to claim 1, characterized in that: In step C1, the sub-cache adopts the Least Recently Used (LRU) strategy to improve the prefetch data hit rate.
Citation Information
Patent Citations
Multi-channel transmission management system based on GPGPU chip
CN116841714A
Fifth generation (5G) new radio channel equalization
WO2021207429A1