Task migration method, electronic device, storage medium, and program product

By dynamically adjusting the load weight of processor and hardware interaction, dynamic balancing of multi-core computing resources is achieved, solving the problem of processor core overload in multi-core solid-state drives, and improving task processing efficiency and overall solid-state drive performance.

CN120929225BActive Publication Date: 2025-12-16INSPUR SUZHOU INTELLIGENT TECH CO LTD
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Patent Information

Application Number
CN202511463132.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-10-14
Publication Date
2025-12-16
Estimated Expiration
2045-10-14

AI Technical Summary

Technical Problem

In multi-core solid-state drives, static task allocation strategies can overload processor cores, resulting in lower processor efficiency in handling tasks.

Method used

By acquiring the first parameters of the task on the processor and the second parameters of the interaction with the hardware, the weights of the first load and the second load are dynamically determined, the third load of the processor reflecting the real-time state of the system is calculated, and the tasks in the high-load processor are migrated.

Benefits of technology

This effectively avoids the problem of uneven load among processors caused by the static task allocation strategy's inability to respond to load changes, improves the efficiency of processors in processing tasks, and enhances the overall performance of solid-state drives.

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Abstract

The application discloses a task migration method, an electronic device, a storage medium and a program product, relates to the technical field of computers, and comprises the following steps: dynamically adjusting the weights of a first load and a second load based on the average utilization rate of a processor core and the response time length of hardware interaction, calculating a third load of the processor reflecting the real-time state of the system, and then migrating tasks in a high-load processor. Therefore, the inter-processor load imbalance problem caused by the static task allocation strategy failing to respond to runtime load changes can be effectively avoided, the technical problem of the parallel processing capability of a multi-core architecture being restricted due to the overload of part of the cores and the low efficiency of the processor in processing tasks being affected is solved, the technical effect of dynamically optimizing task allocation according to the real-time load of the system is achieved, and the processing efficiency of the processor is improved.
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Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a task migration method, electronic device, storage medium, and program product. Background Technology

[0002] In multi-core solid-state drives (SSDs), parallel processing can be achieved by distributing tasks among multiple processor cores.

[0003] In related technologies, a static allocation strategy is typically used for task allocation, where different types of tasks are fixedly assigned to specific processor cores for execution. However, in this process, as the number of tasks allocated to a processor core continuously increases, that core may become overloaded, leading to lower processor efficiency in processing tasks. Summary of the Invention

[0004] This application provides a task migration method, electronic device, storage medium, and program product to at least address the problem of low processor efficiency in task processing in related technologies.

[0005] This application provides a task migration method, including:

[0006] When processing multiple tasks, obtain the first parameters associated with multiple tasks and multiple processors, and the second parameters associated with multiple hardware interactions;

[0007] Based on each first parameter, the first load of each task on each processor is determined, and based on each second parameter, the second load of each task on each hardware is determined.

[0008] Obtain the average utilization of multiple processors and the response time of each task interacting with multiple hardware components;

[0009] Based on average utilization and response time, determine the first weight of multiple first loads corresponding to each processor and the second weight of multiple second loads corresponding to each hardware.

[0010] The third load of each processor is determined based on multiple first loads, first weights, multiple second loads, second weights, and preset weights for each task.

[0011] Based on the third load of each processor, the tasks in the target processor are migrated, where the third load of the target processor is greater than or equal to the first threshold.

[0012] This application also provides a task migration apparatus, comprising: a first acquisition module, a first determination module, a second acquisition module, a second determination module, a third determination module, and a migration module, wherein,

[0013] The first acquisition module is used to acquire first parameters associated with multiple tasks and multiple processors, and second parameters associated with multiple hardware interactions during multiple task processing.

[0014] The first determining module is used to determine the first load of each task on each processor based on each first parameter, and to determine the second load of each task on each hardware based on each second parameter.

[0015] The second acquisition module is used to acquire the average utilization of multiple processors and the response time of each task interacting with multiple hardware components;

[0016] The second determining module is used to determine the first weight of multiple first loads corresponding to each processor and the second weight of multiple second loads corresponding to each hardware based on the average utilization and response time.

[0017] The third determination module is used to determine the third load of each processor based on multiple first loads, first weights, multiple second loads, second weights, and preset weights of each task corresponding to each processor.

[0018] The migration module is used to migrate tasks in the target processor based on the third load of each processor, wherein the third load of the target processor is greater than or equal to a first threshold.

[0019] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described task migration methods when executing the computer program.

[0020] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described task migration methods.

[0021] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described task migration methods.

[0022] The task migration method, electronic device, storage medium, and program product provided in this application can dynamically adjust the weights of the first and second loads based on the average utilization of the processor cores and the response time of hardware interactions, and calculate the third load of the processor that reflects the real-time state of the system, thereby migrating tasks in high-load processors. Therefore, it can effectively avoid the problem of uneven load between processors caused by static task allocation strategies failing to respond to changes in runtime load, and solve the technical problem that the parallel processing capability of multi-core architecture is restricted by the overload of some cores, affecting the low efficiency of processor task processing. It achieves the technical effect of dynamically optimizing task allocation according to the real-time load of the system, improving processor processing efficiency, and improving the overall performance of SSD. Attached Figure Description

[0023] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the system architecture provided for an embodiment of this application;

[0025] Figure 2 A flowchart illustrating the task migration method provided in this application embodiment;

[0026] Figure 3 A schematic diagram illustrating a method for determining a first weight and a second weight provided in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram illustrating a method for migrating tasks in a target processor, provided in an embodiment of this application.

[0028] Figure 5 This is a schematic diagram of the structure of a task migration device provided in an embodiment of this application;

[0029] Figure 6 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, other embodiments obtained by those of ordinary skill in the art without creative effort are all within the protection scope of this application.

[0031] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0032] First, let me explain the terms used in this application.

[0033] Solid State Drives (SSDs): SSDs are data storage devices used in computer systems. Their core function is to provide persistent data storage and high-speed access services for operating systems and applications. With SSDs, the system can permanently save and quickly read / write data. Internally, an intelligent manager efficiently allocates and maintains the storage location, integrity, and lifecycle of data, ensuring data storage reliability and access efficiency. Due to their fully electronic operation, SSDs have significant advantages in data read / write speeds, shock resistance, and operating noise control, effectively improving the overall responsiveness and user experience of computer systems.

[0034] In related technologies, a static allocation strategy is typically used for task allocation, where different types of tasks are fixedly assigned to specific processor cores for execution. However, in this process, as the number of tasks allocated to a processor core continuously increases, that core may become overloaded, leading to lower processor efficiency in processing tasks.

[0035] To address the aforementioned issues, in this embodiment, when task migration is required, the system acquires first operating parameters of multiple tasks on the processor and second operating parameters related to hardware interaction. Based on the processor's average utilization and the hardware interaction response time, the weights of the first and second loads are dynamically determined. A third load reflecting the real-time system state is then calculated, and tasks in target processors with a third load greater than or equal to a first threshold are migrated according to this third load. This dynamic perception of the real-time load status of the system's processor and hardware allows for automatic adjustment of task allocation strategies, effectively avoiding uneven load distribution among processor cores caused by static task allocation strategies failing to respond to runtime load changes. This achieves dynamic balancing and efficient utilization of multi-core computing resources, improving both processor task processing efficiency and overall SSD performance.

[0036] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] This section describes the specific application environment architecture or hardware architecture that the task migration method depends on. (References) Figure 1 , Figure 1 This is a schematic diagram of the system architecture provided for an embodiment of this application. Please refer to [link / reference]. Figure 1 This includes electronic devices and terminal devices. Electronic devices can be any device with on-device computing capabilities, such as servers and terminal devices. Electronic devices may include solid-state drives (SSDs). Communication is possible between terminal devices and electronic devices. Terminal devices can send tasks to be run to electronic devices, which can then run the received tasks via the SSD and process ongoing tasks, completing task migration. Notably, the electronic device and the terminal device can be the same device, meaning it can acquire tasks in progress and migrate running tasks.

[0038] Figure 2 This is a flowchart illustrating the task migration method provided in an embodiment of this application, as shown below. Figure 2 As shown, embodiments of this application provide a task migration method, which is described in detail below:

[0039] S201. When processing multiple tasks, obtain the first parameters associated with multiple tasks and multiple processors, and the second parameters associated with multiple hardware interactions.

[0040] The execution subject of this application embodiment can be an electronic device or a task migration device installed in an electronic device. The task migration device can be implemented by software or by a combination of software and hardware.

[0041] A task refers to a task performed during operation. For example, tasks can include I / O front-end tasks, I / O back-end tasks, management tasks, log management tasks, mapping table management tasks, and error correction tasks.

[0042] Among them, I / O front-end tasks refer to receiving I / O requests sent by the host, I / O back-end tasks refer to writing the received I / O requests to the corresponding locations in the SSD's flash memory and reading data from the SSD's flash memory, management tasks refer to managing the SSD's operating parameters, log management tasks refer to recording information about write, erase, and other operations during the process, mapping table management tasks refer to managing the mapping relationship between the physical address and virtual address of data writing, and error correction tasks refer to detecting and correcting data errors in the flash memory to ensure data integrity.

[0043] The processor is used to execute the running logic and control instructions for tasks. In this embodiment, the processor refers to multiple processor cores integrated inside the solid-state drive controller.

[0044] Hardware is used to provide physical functional support during task execution. In this embodiment, hardware refers to the physical components in the solid-state drive that interact with task execution. For example, hardware may include flash memory.

[0045] The first parameter is used to indicate the resource usage of the task on the processor. In the embodiments of this application, the first parameter refers to the execution time of each task on the processor per unit time.

[0046] The second parameter is used to indicate the interaction between the task and the hardware. In the embodiments of this application, the second parameter refers to the time each task waits for a hardware response per unit of time.

[0047] In some embodiments, the electronic device can record the execution status of each task and the hardware interaction status in real time within a preset time period using an initialized counter and timer. Specifically, the electronic device can collect the first start time and the first end time of each task execution on the processor within a unit time, and collect the second start time and the second end time of each task interaction with the hardware within a unit time. Based on the first start time and the first end time, a first parameter is determined, and based on the second start time and the second end time, a second parameter is determined.

[0048] Here, the first start time refers to the start time of the task running on the processor, the first end time refers to the end time of the task running on the processor, the second start time refers to the sending time when the task accesses the hardware, and the second end time refers to the receiving time when the task receives the completion message from the hardware.

[0049] For example, for the i-th task, the electronic device can collect the first start time of the i-th task's execution on the j-th processor within a unit of time. and the first end moment And the second starting moment of the i-th task accessing the k-th hardware within a unit of time. Second End Time Based on the unit time t, the first parameter at time t+1 can be obtained. and the second parameter at time t+1 When starting to process multiple tasks, the first and second parameters can be initialized, i.e. and All are 0.

[0050] In some embodiments, the electronic device can collect the number of times each task is executed on each processor per unit time, and the number of times each task interacts with the hardware per unit time. For example, at time t within a unit time, the number of times the i-th task is executed on the j-th processor is... If the i-th task is executed again at time t+1, then the number of times the i-th task is executed on the j-th processor at time t+1 is... At time t within a unit of time, the number of interactions between the i-th task and the k-th hardware is . If, at time t+1, the i-th task interacts with the hardware again, then the number of times the i-th task interacts with the k-th hardware at time t+1 is: .

[0051] S202. Based on each first parameter, determine the first load of each task on each processor, and based on each second parameter, determine the second load of each task on each hardware.

[0052] The first load is used to indicate the resource consumption of a task on the processor. In other words, the first load refers to the load on processor resources caused by the task during its execution.

[0053] The second load is used to indicate the degree of interaction between the task and the hardware. In other words, the second load refers to the load on hardware resources during the interaction between the task and the hardware.

[0054] In some embodiments, the electronic device may determine the first load of each task on each processor based on each first parameter and the second load of each task on each hardware based on each second parameter, in the following manner: determining a first duration, the first duration being used to indicate the data acquisition duration; determining the ratio of each first parameter to the first duration as the first load of each task on each processor; and determining the ratio of each second parameter to the first duration as the second load of each task on each hardware.

[0055] The first duration refers to a pre-set collection period, such as 30 seconds. This means that the electronic device can continuously collect task data for multiple first durations within a preset time period and determine the first and second parameters for each first duration.

[0056] In some embodiments, during the first duration Within this context, regarding the execution status of the i-th task on the j-th processor, its first parameter can be... The first load can be For the interaction between the i-th task and the k-th hardware, its second parameter can be... The second load can be For example, if the first duration is 10ms, and the first parameter of the first task on the second processor is 3ms, then the first load is 0.3. If the second parameter of the task interacting with the first hardware is 5ms, then the second load is 0.5.

[0057] S203, obtain the average utilization of multiple processors and the response time of each task interacting with multiple hardware components.

[0058] Average utilization rate refers to the average resource usage ratio of the processor within the first time period.

[0059] Response time refers to the time from when a task sends an access request to when it receives the hardware's response information within the first time period.

[0060] In some embodiments, for any given processor, the electronic device can obtain the runtime occupancy of multiple tasks on the processor within a first duration, i.e., a first parameter, and determine the total runtime occupancy of the processor based on the first parameter of each task. The ratio of the total runtime occupancy to the first duration is then determined as the utilization rate of the processor. For example, if the runtime occupancy of multiple tasks on the processor is 1ms, 1ms, and 2ms respectively, and the first duration is 5ms, then the utilization rate of the processor is 0.8.

[0061] In some embodiments, the electronic device may determine the utilization rate and the total number of processors, and determine the average utilization rate as the ratio of the sum of the utilization rates to the total number. For example, if the utilization rates of the processors are 0.7, 0.6 and 0.8 respectively, the average utilization rate is 0.7.

[0062] S204. Based on average utilization and response time, determine the first weight of multiple first loads corresponding to each processor and the second weight of multiple second loads corresponding to each hardware.

[0063] The first weight is used to indicate the degree of influence of multiple first loads on the total processor load. For example, the larger the first weight, the greater the influence of the multiple first loads corresponding to each processor on the total processor load; the smaller the first weight, the smaller the influence of the multiple first loads corresponding to each processor on the total processor load.

[0064] The second weight is used to indicate the degree of influence of multiple second loads on the total processor load. For example, the larger the second weight, the greater the influence of the multiple second loads corresponding to each hardware on the total processor load; the smaller the second weight, the smaller the influence of the multiple second loads corresponding to each hardware on the total processor load.

[0065] For example, if the first weight of multiple first loads is greater than the second weight of multiple second loads, the electronic device can determine that, in the current state, the influence of multiple first loads corresponding to each processor on the total load of the processor is greater than the influence of multiple second loads corresponding to each hardware on the total load of the processor.

[0066] In some embodiments, the electronic device may determine a first weight of a plurality of first loads corresponding to each processor and a second weight of a plurality of second loads corresponding to each hardware based on average utilization and response time, by: determining a first initial weight of a plurality of loads corresponding to each processor and a second initial weight of a plurality of second loads corresponding to each hardware; and processing the first initial weight and the second initial weight based on average utilization and response time to obtain the first weight and the second weight.

[0067] The first initial weight is used to indicate the initial impact of multiple first loads on the total processor load.

[0068] The second initial weight is used to indicate the initial impact of multiple second loads on the total processor load.

[0069] In some embodiments, the electronic device may determine a first initial weight and a second initial weight based on the processor's operating state. For example, if the processor's operating state is significantly affected by multiple first loads, the first initial weight is greater than the second initial weight; if the processor's operating state is significantly affected by multiple second loads, the second initial weight is greater than the first initial weight.

[0070] In some embodiments, the electronic device can determine a first initial weight and a second initial weight based on preset rules. The preset rules refer to pre-defined weight configuration rules. For example, the preset rules can be determined based on the configuration parameters of the solid-state drive. The electronic device can determine the first initial weight and the second initial weight through the configuration parameters of the processor and hardware.

[0071] For example, if the number of processors is small but the number of hardware channels is large, the second initial weight is set to be greater than the first initial weight (e.g., the first initial weight is 0.4 and the second initial weight is 0.6); if the number of processors is large but the number of hardware channels is small, the first initial weight is set to be greater than the second initial weight (e.g., the first initial weight is 0.6 and the second initial weight is 0.4).

[0072] In some embodiments, the electronic device may determine a first initial weight for a plurality of loads corresponding to each processor and a second initial weight for a plurality of second loads corresponding to each piece of hardware based on the following implementation: determining a load type, which includes a processor load type and a hardware load type; when the load type is a processor load type, determining a first initial weight and a second initial weight associated with the processor load type, wherein the first initial weight is greater than the second initial weight; when the load type is a hardware load type, determining a first initial weight and a second initial weight associated with the hardware load type, wherein the first initial weight is less than the second initial weight.

[0073] The load type is used to indicate the category corresponding to the total processor load.

[0074] Processor load type indicates the load category corresponding to a task that is using a high amount of processor resources.

[0075] Hardware load type indicates the load category corresponding to a high proportion of hardware calls by a task.

[0076] In some embodiments, the electronic device can determine the load type based on the task processing type. That is, if the task processing type is an I / O intensive task, it means that the processor load is slightly higher than the hardware load, and the first initial weight is slightly greater than the second initial weight (for example, the first initial weight is 0.6 and the second initial weight is 0.4). If the task processing type is a compute intensive task, it means that the processor load is significantly higher than the hardware load, and the first initial weight is significantly greater than the second initial weight (for example, the first initial weight is 0.8 and the second initial weight is 0.2). If the task processing type is an I / O task, that is, in this case only the hardware is called to process the task, it means that the processor load is significantly lower than the hardware load, and the first initial weight is significantly less than the second initial weight (for example, the first initial weight is 0.3 and the second initial weight is 0.7).

[0077] In some embodiments, the electronic device may process a first initial weight and a second initial weight based on average utilization and response time to obtain a first weight and a second weight, based on the following implementation: determining a second threshold corresponding to average utilization and a third threshold corresponding to response time; processing the first initial weight and the second initial weight based on average utilization, the second threshold, response time and the third threshold to obtain a first weight and a second weight.

[0078] The second threshold is used to determine whether the average utilization rate exceeds the preset range.

[0079] The third threshold is used to determine whether the response time exceeds the preset range.

[0080] In some embodiments, the electronic device may determine a second threshold based on the average utilization of the processor during the historical acquisition period, for example, by determining the average of each average utilization as the second threshold. Furthermore, the electronic device may determine a third threshold based on the response time of hardware interactions during the historical acquisition period, for example, by determining the upper limit of the response time when the hardware is working normally as the third threshold.

[0081] In some embodiments, the electronic device can process the first initial weight and the second initial weight by the relationship between the average utilization rate and the second threshold, and the relationship between the response time and the third threshold, to obtain the first weight and the second weight.

[0082] In some embodiments, the electronic device can be based on the total number of times the task is run within a first duration. The first and second initial weights are processed; for example, if the total number of times the task runs within the first duration is... If the weight continues to increase, then based on the current state, the first initial weight needs to be continuously increased while the second initial weight continuously decreases. This applies if the total number of task runs within the first time period... If the weight continues to decrease, then the first initial weight needs to be continuously decreased and the second initial weight needs to be continuously increased based on the current state.

[0083] S205. Based on the multiple first loads, first weights, multiple second loads, second weights, and preset weights of each task corresponding to each processor, determine the third load of each processor.

[0084] The third load indicator is used to indicate the total load on the processor.

[0085] In some embodiments, the electronic device can determine the third load of each processor by combining the load of each processor and the load of each hardware interaction with the weight of each processor's influence on the total load and the weight of each hardware interaction's influence on the total load.

[0086] In some embodiments, the electronic device may determine the third load of each processor based on the following implementation: multiple first loads, a first weight, multiple second loads, a second weight, and a preset weight of each task corresponding to each processor; for any processor; multiply the first load corresponding to the processor by the first weight to obtain a first value; sum the multiple second loads to obtain a second value, and multiply the second value by the second weight to obtain a third value; determine the third load of the processor based on the first value, the third value, and the preset weight.

[0087] In some embodiments, the first load corresponding to the j-th processor is The first weight is The first value is The second load corresponding to the kth hardware is Summing multiple second loads yields the third value. The second weight is Then the third value is .

[0088] In some embodiments, the electronic device may determine the third load of the processor based on a first value, a third value, and a preset weight, by: determining a first number of tasks in the processor; summing the first value and the third value for any one task in the processor to obtain a fourth value; and performing a weighted summation of multiple fourth values ​​and preset weights for each task based on the first number to obtain the third load of the processor.

[0089] Preset weights refer to the pre-defined importance coefficients of tasks.

[0090] The first quantity refers to the total number of tasks in the processor.

[0091] In some embodiments, the electronic device may determine the preset weight of each task based on the priority of the task. For example, the higher the priority of the task, the greater the corresponding preset weight, and the lower the priority of the task, the smaller the corresponding preset weight.

[0092] In some embodiments, the electronic device can determine the priority of tasks based on the type of task. For example, the priority order of each task can be set as: I / O front-end task > I / O back-end task > management task > log management task > mapping table management task > error correction task.

[0093] In some embodiments, for the i-th task, the first and third values ​​can be summed, and the fourth value is... This represents the impact of the i-th task on the total processor load, with each task having a preset weight. The preset weights for each task are: By performing a weighted summation of multiple fourth values ​​and the preset weights of each task, the third load for the j-th processor is calculated. , representing the degree of impact of m tasks on the total load of the processor, where, That is, the third load can be represented as: .

[0094] In some embodiments, if the processor capability of the current processor is the primary issue, a first weight can be set. Larger, for example, the first weight A value of 0.7-0.9 is acceptable; if the current hardware interaction capability is the primary issue, the first weight can be set. Smaller, for example, the first weight You can take a value between 0.1 and 0.3.

[0095] S206. Based on the third load of each processor, migrate the tasks in the target processor.

[0096] Among them, the third load of the target processor is greater than or equal to the first threshold.

[0097] The target processor refers to the processor with a high workload.

[0098] The first threshold is used to determine whether the processor's load exceeds the normal range. For example, if the processor's third load is greater than or equal to the first threshold, the processor is identified as the target processor. If the processor's third load is less than the first threshold, there is no target processor in this acquisition period, and task migration is not required.

[0099] exist Figure 2 In the illustrated embodiment, when task migration is required, the system acquires first operating parameters of multiple tasks on the processor and second operating parameters of hardware interaction. Based on the average utilization of the processor and the response time of hardware interaction, the weights of the first and second loads are dynamically determined. A third load reflecting the real-time state of the system is then calculated, and tasks in target processors with a third load greater than or equal to a first threshold are migrated according to this third load. This allows for dynamic sensing of the real-time load status of the system's processors and hardware, enabling automatic adjustment of task allocation strategies. This effectively avoids the problem of uneven load distribution among processors caused by static task allocation strategies failing to respond to runtime load changes. It achieves dynamic balancing and efficient utilization of multi-core computing resources, significantly enhancing the processor's adaptability to complex workloads while improving task processing efficiency. Furthermore, by optimizing the allocation of background tasks such as garbage collection, it reduces flash memory writes introduced by garbage collection, lowers the write amplification factor, and thus extends the lifespan of the SSD.

[0100] Based on any of the above embodiments, the method by which the electronic device processes the first initial weight and the second initial weight based on the average utilization rate, the second threshold, the response time and the third threshold to obtain the first weight and the second weight will be described in detail.

[0101] Figure 3 This is a schematic diagram illustrating a method for determining a first weight and a second weight, provided in an embodiment of this application. Please refer to... Figure 3 ,include:

[0102] S301. Determine the adjustment step size.

[0103] The adjustment step size refers to the smallest unit of change in the weight adjustment process. For example, the adjustment step size can be set to 0.05.

[0104] S302. When the average utilization rate is greater than or equal to the second threshold and the response time is less than the third threshold, the first initial weight is increased by at least one step and the second initial weight is decreased by at least one step to obtain the first weight and the second weight.

[0105] In some embodiments, when the average utilization rate is greater than or equal to the second threshold, it indicates that the first load of the current processor has a greater impact on the third load, and when the response time is less than the third threshold, it indicates that the second load of the current hardware interaction has a smaller impact on the third load. In this case, one step can be added to the first initial weight and one step can be deducted from the second initial weight. If, after the above processing, the average utilization rate is still greater than or equal to the second threshold and the response time is less than the third threshold, two steps can be added to the first initial weight and two steps can be deducted from the second initial weight, and so on, until the average utilization rate and response time meet the threshold requirements.

[0106] For example, if the average utilization of each processor is 0.9, the second threshold is 0.8, the response time is 10ms, the third threshold is 10s, the adjustment step size is 0.05, the first initial weight is 0.6, and the second initial weight is 0.4, where the average utilization is greater than the second threshold and the response time is less than the third threshold, then the first weight is 0.65 and the second weight is 0.35. If the average utilization still does not meet the threshold after adjustment, then the first weight is 0.7 and the second weight is 0.3, and so on, until the average utilization is less than 0.8.

[0107] S303. When the average utilization rate is less than the second threshold and the response time is greater than or equal to the third threshold, the first initial weight is reduced by at least one step and the second initial weight is increased by at least one step to obtain the first weight and the second weight.

[0108] In some embodiments, when the average utilization is less than the second threshold, it indicates that the first load of the current processor has a relatively small impact on the third load, and when the response time is greater than or equal to the third threshold, it indicates that the second load of the current hardware interaction has a relatively large impact on the third load. In this case, the first initial weight can be reduced by one step, and the second initial weight can be increased by one step. If, after the above processing, the average utilization is still greater than or equal to the second threshold, and the response time is less than the third threshold, the first initial weight can be reduced by two steps, and the second initial weight can be increased by two steps, and so on, until the average utilization and response time meet the threshold requirements.

[0109] For example, if the average utilization of each processor is 0.6, the second threshold is 0.8, the response time is 1 minute, the third threshold is 10 seconds, the adjustment step size is 0.05, the first initial weight is 0.6, and the second initial weight is 0.4, where the average utilization is less than the second threshold and the response time is greater than the third threshold, then the first weight is 0.55 and the second weight is 0.45. If the response time after adjustment still does not meet the threshold, then the first weight is 0.5 and the second weight is 0.5, and so on, until the response time is less than 10 ms.

[0110] S304. When the average utilization rate is greater than or equal to the second threshold and the response time is greater than or equal to the third threshold, or when the average utilization rate is less than the second threshold and the response time is less than the third threshold, the first initial weight is determined as the first weight and the second initial weight is determined as the second weight.

[0111] In some embodiments, if the average utilization rate is greater than or equal to a second threshold and the response time is greater than or equal to a third threshold, it indicates that the processor is under high load, with high computational pressure and high hardware latency. In this case, both the first and second loads significantly impact performance, and arbitrarily adjusting the weight ratios (e.g., increasing the first weight or increasing the second weight) may lead to instability. Therefore, setting the first initial weight as the first weight and the second initial weight as the second weight can avoid introducing additional fluctuations due to weight adjustments.

[0112] In some embodiments, if the average utilization is less than the second threshold and the response time is less than the third threshold, it indicates that the processor is in a light and balanced state, and there are no obvious problems in the interaction between the processor and the hardware. Therefore, there is no need to change the load judgment strategy by adjusting the weights. Determining the first initial weight as the first weight and the second initial weight as the second weight can effectively maintain the current good load balance.

[0113] exist Figure 3 In the illustrated embodiment, since the numerical allocation of the first weight and the second weight can be dynamically adjusted based on the comparison results of the processor's average utilization and the hardware response time threshold, the first weight is increased in compute-intensive scenarios, the second weight is increased in I / O-intensive scenarios, and the original weight configuration is maintained when the load state does not change significantly, the problem of load judgment deviation caused by the inability of fixed weight strategy to adapt to dynamic workload can be effectively avoided. This solves the technical problem that the rigid load indicator measurement standard affects the accuracy of multi-core task allocation. While ensuring the real-time performance of load judgment, the adaptability and accuracy of task migration decision-making are significantly improved, thereby achieving overall optimization of the solid-state drive's performance in changing business scenarios.

[0114] Based on any of the above embodiments, the method by which the electronic device migrates tasks in the target processor based on the third load of each processor in the above processing method will be described in detail.

[0115] Figure 4 This is a schematic diagram illustrating a method for migrating tasks in a target processor, as provided in an embodiment of this application. Please refer to... Figure 4 ,include:

[0116] S401. Based on the first threshold, determine the target processor among multiple processors.

[0117] In some embodiments, the electronic device can determine a first threshold based on the third load of each processor. Specifically, the electronic device can sort the third load of each processor after the end of each acquisition cycle (first duration). After calculating the average load, the electronic device can identify the processor whose third load exceeds the average load by a certain range as the target processor. For example, the processor whose third load exceeds the average load by 120% can be identified as the target processor.

[0118] For example, if there are 4 processors, namely processor A, processor B, processor C and processor D, after one acquisition cycle, the third load of processor A is 0.5, the third load of processor B is 0.6, the third load of processor C is 0.7 and the third load of processor D is 0.9, that is, the average load is 0.675. Among them, the third load of processor D exceeds 120% of the average load (0.9>0.81), then processor D is identified as the target processor.

[0119] S402. In the target processor, determine the target task to be migrated.

[0120] The target task is used to indicate the task to be migrated.

[0121] In some embodiments, the electronic device may determine the target task to be migrated in the target processor based on the following implementation: obtaining the priority among multiple tasks in the target processor and the degree of dependence of each task on the target processor; and determining the target task among multiple tasks in the target processor based on the priority and the degree of dependence.

[0122] Dependency refers to the strength of a task's dependence on the target processor. For example, tasks with a low degree of dependence on the target processor may be log management tasks, mapping table management tasks, etc.

[0123] For example, if the priority order of each task is: I / O front-end task > I / O back-end task > management task > log management task > mapping table management task > error correction task, and the current processor includes I / O front-end task, I / O back-end task, management task, log management task and mapping table management task, then tasks with lower priority and weaker dependencies can be selected first. For example, log management task and mapping table management task can be identified as target tasks and migrated from the target processor, while tasks with higher priority and close interaction with the front-end, such as I / O front-end task, need not be migrated for the time being.

[0124] In some embodiments, the electronic device may migrate the target task based on the following implementation: determining the processor receiving the task among a plurality of processors based on the third load of each processor and the target task, wherein the third load of the processor receiving the task is less than or equal to a fourth threshold; and migrating the target task to the processor receiving the task.

[0125] In some embodiments, the electronic device may determine a fourth threshold based on the third load of each processor. Specifically, after calculating the average load, the electronic device may determine the processors whose third load is lower than the average load by a certain range as the processors to accept the task. For example, the processors whose third load is lower than 80% of the average load may be determined as the processors to accept the task.

[0126] For example, if there are 4 processors, namely processor A, processor B, processor C and processor D, after one acquisition cycle, the third load of processor A is 0.3, the third load of processor B is 0.5, the third load of processor C is 0.7 and the third load of processor D is 0.9, that is, the average load is 0.6. Among them, the third load of processor A is less than 80% of the average load (0.3 < 0.48), then processor A is determined to be the processor receiving the task.

[0127] In some embodiments, the electronic device may determine the processor for receiving the task from among multiple processors based on the third load of each processor and the target task, in the following manner: processors with a third load less than or equal to a fourth threshold are identified as candidate processors; the matching degree between each candidate processor and the target task is determined; and the candidate processor with the highest matching degree is identified as the processor for receiving the task.

[0128] Candidate processors are used to indicate the third processor whose load is below a certain range of the average load.

[0129] For example, if there are 4 processors, namely processor A, processor B, processor C and processor D, after one acquisition cycle, the third load of processor A is 0.3, the third load of processor B is 0.4, the third load of processor C is 0.7 and the third load of processor D is 0.9, that is, the average load is 0.575. Among them, the third load of processor A and processor B is less than 80% (0.46) of the average load, then processor A and processor B are identified as candidate processors.

[0130] Matching degree is used to indicate the degree of matching between the target task and each task in the current candidate processor. In other words, it can determine the compatibility between the target task and each task in the candidate processor based on the type of the target task. For example, I / O front-end tasks should not appear twice in the same processor. This can effectively avoid assigning tasks that frequently access the same hardware to the same candidate processor, thereby reducing the impact of resource contention.

[0131] S403. Migrate the target task.

[0132] In some embodiments, during task migration, electronic devices use inter-process communication (IPC) mechanisms to transfer task context and reallocate resources, ensuring data integrity and consistency during the migration process while minimizing migration time and reducing the impact on system performance. In this case, tasks that are currently being processed can continue to be processed in the source task, while new processes that have not yet been processed can be directly submitted to the target task.

[0133] In some embodiments, after the task migration is completed, the load changes of each processor after migration are monitored in real time. If it is found that the load balancing effect does not meet expectations (for example, the third load of a processor is too high or too low than the first threshold), the above process is repeated for adjustment.

[0134] In some embodiments, during task migration, to further improve the processing efficiency and performance balance of the solid-state drive, a dynamic adjustment strategy can be adopted for the hardware. Specifically, the electronic device can monitor the secondary load and overall performance indicators of each hardware interaction in real time (e.g., the frequency of hardware access, average response time, etc.), and dynamically allocate hardware resources according to the hardware load and task requirements. For example, for hardware with a high secondary load, the frequency of access by lower priority tasks is limited, and the access requirements of higher priority tasks are prioritized. For hardware with a low secondary load, the number of times it is accessed by tasks can be appropriately increased to improve resource utilization. That is, through task priority management and hardware unit redundancy mechanism, the timely processing of high-priority tasks and the normal operation of the system in the event of hardware failure are ensured, thereby improving the overall stability and reliability.

[0135] In some embodiments, a redundancy mechanism for hardware units can be established. Specifically, when the second load of the hardware is too high or a failure occurs, a backup hardware capable of handling the relevant task can be identified among multiple hardware units, and the task can be automatically switched to the backup hardware for processing to ensure the normal operation and performance stability of the system.

[0136] In some embodiments, for hardware that supports parallel operation, the electronic device can decompose the task into multiple subtasks according to the characteristics of the task and the parallel processing capability of the hardware, and assign each subtask to different parallel channels of the hardware for processing, so as to improve the processing efficiency of the hardware.

[0137] In this embodiment, a method for calculating the processor's third load based on real-time monitoring of the first parameters of the task on the processor and the second parameters of the interaction with the hardware, particularly by introducing weights to balance the impact of processor load and hardware interaction load, and dynamically migrating and allocating tasks according to the processor's third load and task status, can avoid situations where some processors are overloaded while others are idle, fully utilize the parallel processing capabilities of the multi-core architecture, avoid task backlog, reduce system response latency, improve the real-time performance of task allocation, and thus improve the overall performance of the SSD. Furthermore, a method for dynamically allocating hardware resources, establishing redundancy mechanisms, and decomposing hardware units that support parallel operations into subtasks can be implemented based on hardware load and task requirements. In this way, by rationally allocating tasks to different processors and hardware, and through dynamic hardware usage strategies, contention for hardware resources between tasks can be reduced, and the utilization efficiency of hardware resources can be improved.

[0138] exist Figure 4 In the illustrated embodiment, since the migration target can be dynamically determined based on the overall load status of each processor, and the task to be migrated can be selected by analyzing the task priority and its dependence on the processor, and the optimal target processor can be dynamically selected based on the load threshold and task matching degree, the problem of processor resource contention and performance degradation caused by blind task migration can be effectively avoided. This solves the technical problem of affecting system stability and task execution efficiency due to unreasonable migration strategy. While ensuring the load balancing effect, the impact of the migration process on system performance is minimized, and the accuracy and reliability of task allocation under multi-core architecture are significantly improved.

[0139] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0140] Figure 5 This is a schematic diagram of a task migration device provided in an embodiment of this application. Figure 5 As shown, embodiments of this application also provide a task migration device 50, including: a first acquisition module 501, a first determination module 502, a second acquisition module 503, a second determination module 504, a third determination module 505, and a migration module 506, wherein,

[0141] The first acquisition module 501 is used to acquire first parameters associated with multiple tasks and multiple processors, and second parameters associated with multiple hardware interactions during multiple task processing.

[0142] The first determining module 502 is used to determine the first load of each task on each processor based on each first parameter, and to determine the second load of each task on each hardware based on each second parameter.

[0143] The second acquisition module 503 is used to acquire the average utilization of multiple processors and the response time of each task interacting with multiple hardware components.

[0144] The second determining module 504 is used to determine the first weight of multiple first loads corresponding to each processor and the second weight of multiple second loads corresponding to each hardware based on the average utilization and response time.

[0145] The third determining module 505 is used to determine the third load of each processor based on multiple first loads, first weights, multiple second loads, second weights and preset weights of each task corresponding to each processor.

[0146] Migration module 506 is used to migrate tasks in a target processor based on the third load of each processor, wherein the third load of the target processor is greater than or equal to a first threshold.

[0147] For a description of the features in the embodiment corresponding to the task migration device, please refer to the relevant description in the embodiment corresponding to the task migration method, which will not be repeated here.

[0148] In one possible implementation, the second determining module 504 is specifically used for:

[0149] Determine the first initial weights for multiple loads corresponding to each processor, and the second initial weights for multiple second loads corresponding to each piece of hardware;

[0150] Based on the average utilization rate and response time, the first initial weight and the second initial weight are processed to obtain the first weight and the second weight.

[0151] In one possible implementation, the second determining module 504 is specifically used for:

[0152] Determine the load type, which includes processor load type and hardware load type;

[0153] When the load type is processor load type, determine a first initial weight and a second initial weight associated with the processor load type, wherein the first initial weight is greater than the second initial weight;

[0154] When the load type is hardware load type, determine a first initial weight and a second initial weight associated with the hardware load type, wherein the first initial weight is less than the second initial weight.

[0155] In one possible implementation, the second determining module 504 is specifically used for:

[0156] Determine the second threshold corresponding to the average utilization rate and the third threshold corresponding to the response time;

[0157] Based on the average utilization rate, the second threshold, the response time, and the third threshold, the first initial weight and the second initial weight are processed to obtain the first weight and the second weight.

[0158] In one possible implementation, the second determining module 504 is specifically used for:

[0159] Determine the adjustment step size;

[0160] When the average utilization rate is greater than or equal to the second threshold and the response time is less than the third threshold, the first initial weight is increased by at least one step and the second initial weight is decreased by at least one step to obtain the first weight and the second weight.

[0161] When the average utilization rate is less than the second threshold and the response time is greater than or equal to the third threshold, the first initial weight is reduced by at least one step and the second initial weight is increased by at least one step to obtain the first weight and the second weight.

[0162] When the average utilization rate is greater than or equal to the second threshold and the response time is greater than or equal to the third threshold, or when the average utilization rate is less than the second threshold and the response time is less than the third threshold, the first initial weight is determined as the first weight and the second initial weight is determined as the second weight.

[0163] In one possible implementation, the third determining module 505 is specifically used for:

[0164] For any given processor;

[0165] Multiply the first load corresponding to the processor by the first weight to obtain the first value;

[0166] The second load is summed to obtain a second value, and then the second value is multiplied by the second weight to obtain a third value.

[0167] The third load of the processor is determined based on the first value, the third value, and the preset weight.

[0168] In one possible implementation, the third determining module 505 is specifically used for:

[0169] Determine the initial number of tasks in the processor;

[0170] For any task in the processor, sum the first and third values ​​to obtain the fourth value;

[0171] Based on the first quantity, multiple fourth values ​​and the preset weights of each task are weighted and summed to obtain the processor's third load.

[0172] In one possible implementation, the migration module 506 is specifically used for:

[0173] Based on the first threshold, the target processor is determined among multiple processors;

[0174] In the target processor, identify the target task to be migrated;

[0175] Migrate the target task.

[0176] In one possible implementation, the migration module 506 is specifically used for:

[0177] Obtain the priorities among multiple tasks in the target processor, as well as the degree of dependence of each task on the target processor;

[0178] Based on priority and dependency, the target task is determined among multiple tasks of the target processor.

[0179] In one possible implementation, the migration module 506 is specifically used for:

[0180] Based on the third load of each processor and the target task, among multiple processors, the processor receiving the task is determined, and the third load of the processor receiving the task is less than or equal to the fourth threshold.

[0181] The target task is moved to the processor that receives the task.

[0182] In one possible implementation, the migration module 506 is specifically used for:

[0183] Processors whose third load is less than or equal to the fourth threshold are identified as candidate processors;

[0184] Determine the matching degree between each candidate processor and the target task;

[0185] The candidate processor with the highest matching degree is selected as the processor to receive the task.

[0186] In one possible implementation, the first determining module 502 is specifically used for:

[0187] Determine the first duration, which indicates the duration of data collection;

[0188] The ratio of each first parameter to the first duration is determined as the first load of each task on each processor;

[0189] The ratio of each second parameter to the first duration is determined as the second load of each task on each hardware.

[0190] Figure 6 A schematic diagram of the structure of the electronic device provided in this application. Figure 6 As shown, the electronic device 60 provided in this embodiment includes at least one processor 601 and a memory 602. Optionally, the electronic device 60 further includes a communication component 603. The processor 601, memory 602, and communication component 603 are connected via a bus.

[0191] In a specific implementation, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to execute the above-described task migration method embodiment.

[0192] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0193] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0194] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0195] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0196] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described task migration method embodiments at runtime.

[0197] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0198] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the steps in any of the above-described task migration method embodiments.

[0199] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described task migration method embodiments.

[0200] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for specific applications, but such implementations should not be considered beyond the scope of this application.

[0201] The task migration method provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A task migration method, characterized in that, include: When processing multiple tasks, obtain the first parameters associated with multiple tasks and multiple processors, and the second parameters associated with multiple hardware interactions; Based on each first parameter, the first load of each task on each processor is determined, and based on each second parameter, the second load of each task on each hardware is determined. Obtain the average utilization of multiple processors and the response time of each task interacting with multiple hardware components; Based on the average utilization and the response time, determine the first weight of the multiple first loads corresponding to each processor and the second weight of the multiple second loads corresponding to each hardware; Based on the multiple first loads, first weights, multiple second loads, second weights, and preset weights of each task corresponding to each processor, the third load of each processor is determined; Based on the third load of each processor, the tasks in the target processor are migrated, wherein the third load of the target processor is greater than or equal to a first threshold. Based on the multiple first loads, first weights, multiple second loads, second weights, and preset weights of each task corresponding to each processor, the third load of each processor is determined, including: For any given processor; Multiply the first load corresponding to the processor by the first weight to obtain the first value; The plurality of second loads are summed to obtain a second value, and the second value is multiplied by the second weight to obtain a third value; Based on the first value, the third value, and the preset weight, the third load of the processor is determined.

2. The method according to claim 1, characterized in that, Based on the average utilization and the response time, determine the first weight of the multiple first loads corresponding to each processor and the second weight of the multiple second loads corresponding to each hardware, including: Determine the first initial weight of the multiple loads corresponding to each processor, and the second initial weight of the multiple second loads corresponding to each piece of hardware; Based on the average utilization rate and the response time, the first initial weight and the second initial weight are processed to obtain the first weight and the second weight.

3. The method according to claim 2, characterized in that, Determining the first initial weights of the multiple loads corresponding to each processor, and the second initial weights of the multiple second loads corresponding to each piece of hardware, includes: Determine the load type, which includes processor load type and hardware load type; When the load type is the processor load type, a first initial weight and a second initial weight are determined to be associated with the processor load type, wherein the first initial weight is greater than the second initial weight; When the load type is the hardware load type, a first initial weight and a second initial weight associated with the hardware load type are determined, wherein the first initial weight is less than the second initial weight.

4. The method according to claim 2, characterized in that, Based on the average utilization rate and the response time, the first initial weight and the second initial weight are processed to obtain the first weight and the second weight, including: Determine a second threshold corresponding to the average utilization rate and a third threshold corresponding to the response time; Based on the average utilization rate, the second threshold, the response time, and the third threshold, the first initial weight and the second initial weight are processed to obtain the first weight and the second weight.

5. The method according to claim 4, characterized in that, Based on the average utilization rate, the second threshold, the response time, and the third threshold, the first initial weight and the second initial weight are processed to obtain the first weight and the second weight, including: Determine the adjustment step size; When the average utilization rate is greater than or equal to the second threshold and the response time is less than the third threshold, the first initial weight is increased by at least one step and the second initial weight is decreased by at least one step to obtain the first weight and the second weight. When the average utilization rate is less than the second threshold and the response duration is greater than or equal to the third threshold, the first initial weight is reduced by at least one step and the second initial weight is increased by at least one step to obtain the first weight and the second weight. When the average utilization rate is greater than or equal to the second threshold and the response time is greater than or equal to the third threshold, or when the average utilization rate is less than the second threshold and the response time is less than the third threshold, the first initial weight is determined as the first weight, and the second initial weight is determined as the second weight.

6. The method according to claim 1, characterized in that, Based on the first value, the third value, and the preset weight, the third load of the processor is determined, including: Determine a first number of tasks in the processor; For any task in the processor, the first value and the third value are summed to obtain a fourth value; Based on the first quantity, the plurality of fourth values ​​and the preset weights of each task are weighted and summed to obtain the third load of the processor.

7. The method according to claim 1, characterized in that, Based on the third load of each processor, tasks in the target processor are migrated, including: Based on the first threshold, a target processor is determined among the plurality of processors; In the target processor, the target task to be migrated is determined; The target task is then migrated.

8. The method according to claim 7, characterized in that, In the target processor, the target task to be migrated is determined, including: Obtain the priorities among multiple tasks in the target processor, and the degree of dependence of each task on the target processor; Based on the priority and the degree of dependence, the target task is determined among multiple tasks of the target processor.

9. The method according to claim 7, characterized in that, The migration of the target task includes: Based on the third load of each processor and the target task, among the plurality of processors, a processor for receiving the task is determined, wherein the third load of the processor for receiving the task is less than or equal to a fourth threshold. The target task is migrated to the processor of the receiving task.

10. The method according to claim 9, characterized in that, Based on the third load of each processor and the target task, the processor that receives the task is determined among the plurality of processors, including: Processors whose third load is less than or equal to the fourth threshold are identified as candidate processors; Determine the matching degree between each candidate processor and the target task; The candidate processor with the highest matching degree is determined as the processor for the receiving task.

11. The method according to claim 1, characterized in that, Based on each first parameter, the first load of each task on each processor is determined; based on each second parameter, the second load of each task on each hardware is determined, including: A first duration is determined, which indicates the duration of data collection. The ratio of each first parameter to the first duration is determined as the first load of each task on each processor; The ratio of each second parameter to the first duration is determined as the second load of each task on each hardware.

12. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the task migration method as described in any one of claims 1 to 11 when executing the computer program.

Citation Information

Patent Citations

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