Extreme environment path planning method and system based on RISCV multi-core architecture

Abstract

The invention discloses an extreme environment path planning method and system based on an RISCV multi-core architecture, and relates to the technical field of path planning, and the method comprises the steps: carrying out the operation in a simulation environment based on an existing path planning algorithm, and obtaining key calculation features; performing comparison in different complexity scenes based on the key calculation features to obtain quantization results of the key calculation features; optimizing a standard RISCV instruction set by taking reduction of invalid instruction execution and core operation delay as a target based on the quantification result to obtain an optimized instruction set; constructing a final hybrid interconnection topological structure of a master core-slave core star type and a local mesh by taking reduction of redundant data transmission and cross-core synchronization overhead as a target based on a quantization result; and obtaining a target task, calling and executing a corresponding optimization instruction set on the final hybrid interconnection topological structure, and completing the path planning of the extreme environment. On the basis of improving the robot path planning efficiency, the power consumption is obviously reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of path planning, more particularly, to an extreme environment path planning method and system based on RISCV multi-core architecture. BACKGROUND

[0002] An extreme environment robot needs to complete diversified tasks such as terrain mapping, sample collection and equipment maintenance without human intervention, and autonomous path planning is a core link to ensure the safe and efficient movement of the robot. The link requires the robot to plan an optimal path from a starting point to a target point in real time according to the extreme environment terrain data obtained by a sensor, and needs to meet multiple constraint conditions such as obstacle avoidance, minimum energy consumption and shortest path. However, the extreme environment brings double challenges to the robot path planning: on the one hand, the terrain of the extreme environment is complex and uncertain, and the robot needs to run path search algorithms such as A* and Rapidly-exploring Random Trees (RRT) with high computational complexity. Such algorithms need to perform a large number of node expansions, distance calculations and cost evaluations when processing large-scale terrain data, which puts high requirements on the computing performance of the hardware platform. On the other hand, the extreme environment has no atmosphere, the day-night temperature difference is large, and the robot relies on limited solar power or nuclear battery power supply. Traditional high-power computing hardware not only cannot adapt to the extreme temperature environment, but also the continuous high energy consumption will seriously shorten the endurance time of the robot, restricting the continuous development of the exploration task.

[0003] The field of extreme environment robot path planning has formed a relatively rich algorithm system, and the application research of low-power RISCV architecture in deep space exploration has also gradually deepened, but the collaborative optimization research of the two still has obvious gaps: first, the optimization of existing path planning algorithms does not fully combine the characteristics of the hardware architecture, making it difficult to achieve efficient deployment on low-power hardware platforms; second, existing low-power RISCV architectures are mostly oriented towards general tasks or specific data processing tasks (such as image processing), and are not customized for the instruction call rules and data transmission characteristics of path planning algorithms, resulting in insufficient "algorithm-architecture" matching and failing to meet the efficient and low-power needs of extreme environment robot path planning.

[0004] Therefore, how to significantly reduce power consumption on the basis of improving the efficiency of robot path planning is a problem that needs to be solved by those skilled in the art. SUMMARY

[0005] In view of the above problems, the present application is proposed to provide an extreme environment path planning method and system based on RISCV multi-core architecture to overcome the above problems or at least partially solve the above problems, which significantly reduces power consumption on the basis of improving the efficiency of robot path planning.

[0006] In order to achieve the above object, the present application adopts the following technical solutions: In a first aspect, the embodiment of the present application provides an extreme environment path planning method based on RISCV multi-core architecture, comprising: Running an existing path planning algorithm in a simulation environment and obtaining key computing characteristics; Comparing the key computing characteristics in different complexity scenarios to obtain quantization results of the key computing characteristics; Optimizing the standard RISCV instruction set based on the quantization results to reduce invalid instruction execution and core operation delay as the target optimization standard to obtain an optimized instruction set; Based on the quantization results, a final hybrid interconnection topology structure of master-slave star + local mesh is constructed to reduce redundant data transmission and cross-core synchronization overhead; Obtaining a target task and calling the corresponding optimized instruction set on the final hybrid interconnection topology structure to complete the extreme environment path planning.

[0007] In one embodiment, the quantization results of the key computing characteristics include: The key computing characteristics include instruction call frequency, data transmission relationship, and parallel computing capability; Simulating different complexity terrain scenarios; Based on the existing path planning algorithm, the instruction call frequency final result, data transmission relationship final result, and parallel computing capability final result are obtained by taking the mean value after multiple simulation runs in the different complexity terrain scenarios according to the key computing characteristics; The corresponding quantization results are obtained based on the instruction call frequency final result, the data transmission relationship final result, and the parallel computing capability final result; The existing path planning algorithm includes a heuristic search-based path planning algorithm A* algorithm and a probability sampling-based path planning algorithm RRT algorithm.

[0008] In one embodiment, the quantization result acquisition method is: The instruction call frequency final result is the instruction execution proportion of arithmetic operation instructions, logical judgment instructions, data loading / storage instructions, branch instructions, and other instructions in the different complexity terrain scenarios; The instruction call frequency quantization result is obtained based on the instruction execution proportion; The data dependency relationship final result is the data dependency chain length and data dependency type proportion in the different complexity terrain scenarios; The data dependency relationship quantization result is obtained based on the data dependency chain length and the data dependency type proportion; The parallel computing potential final result is: different thread number speedup ratio, parallelizable subtask number, synchronization overhead ratio, and parallel efficiency in different complexity terrain scenes; The parallel computing potential quantization result is obtained based on the different thread number speedup ratio, the parallelizable subtask number, the synchronization overhead ratio, and the parallel efficiency.

[0009] In one embodiment, the instruction call frequency quantization result includes: The arithmetic operation instruction has the highest proportion in the RRT algorithm and the A* algorithm, the logical judgment instruction proportion increases with the increase of terrain scene complexity, the data load / storage instruction decreases with the increase of terrain scene complexity, and the other instruction has the lowest proportion as a redundant instruction. The data dependency quantization result includes: The data dependency of the RRT algorithm and the A* algorithm increases with the increase of terrain scene complexity, and the short dependency chain has the highest proportion. The data dependency of the RRT algorithm is lower than that of the A* algorithm. The control dependency of the A* algorithm is higher than that of the RRT algorithm. The parallel computing potential quantization result includes: The parallel potential of the RRT algorithm is higher than that of the A* algorithm. The parallel efficiency of the RRT algorithm and the A* algorithm decreases with the increase of terrain scene complexity. 4 threads are the optimal parallel scale.

[0010] In one embodiment, an optimized instruction set is obtained, specifically including: Based on the instruction call frequency quantization result, the standard RISCV instruction set is optimized: The redundant instructions irrelevant to the path planning algorithm are removed; For the arithmetic operation instruction and the data load / storage instruction, the hardware execution circuit is optimized: the ADD instruction uses a carry-select adder, the MUL instruction uses a Wallace tree multiplier, the data load / storage instruction optimizes the address generation logic, and supports continuous address data block access; For distance calculation type instructions, two special instructions for Manhattan distance calculation and Euclidean distance approximation calculation are set. For node sorting type instructions in the A* algorithm, a node priority sorting instruction is set, and the ascending order sorting is completed through a hardware sorting circuit, and the sorted node index is output.

[0011] In one embodiment, the final hybrid interconnection topology structure construction method is: Based on the data dependence quantization result, it is obtained that the A* algorithm has control dependence, the RRT algorithm has high parallel potential, and the cross-core data transmission of the two algorithms focuses on "master-core-slave task allocation and "slave-core-slave node information interaction, which are collectively used as first key information. Based on the first key information, an initial hybrid interconnection topology structure of master-core-star + local mesh is constructed. Based on the parallel computing potential quantization result, second key information that four slave cores achieve optimal speedup ratio is obtained. Based on the second key information, the initial hybrid interconnection topology structure is set to a 5-core structure of 1 master core + 4 slave cores, and the final hybrid interconnection topology structure is obtained.

[0012] In one embodiment, the final hybrid interconnection topology structure includes a global star interconnection layer and a local mesh interconnection layer. The global star interconnection layer is responsible for global data transmission between the master core and the slave core, the master core and the shared storage, and is connected by a bidirectional point-to-point link between the master core network interface and the four slave core network interfaces, forming a star structure; the master core is connected to the shared storage through a separate link, and the slave core needs to access the shared storage through the master core; The local mesh interconnection layer is responsible for local data interaction between the four slave cores, adopts a 2*2 mesh structure, and the four slave cores are respectively located at the four nodes of the mesh; each slave core is connected to the adjacent two slave cores through a network interface; the link between the slave cores adopts an asynchronous clock domain design; and each slave core network interface integrates a simple routing function to support local forwarding and cross-core transmission of data.

[0013] In one embodiment, it further includes a data transmission mechanism based on the final hybrid interconnection topology structure, which includes a layered transmission protocol and a dynamic link sleep mechanism. The data transmission mechanism includes a global transmission protocol and a local transmission protocol, both of which adopt a credit-based flow control mechanism. The global transmission protocol is used for high-bandwidth data transmission between the master core and the slave core, the master core and the shared storage, and adopts a "request-response" bidirectional transmission mode; the global link adopts a "data-driven wake-up" mechanism, and when there is no data transmission, the link is in a sleep state, the clock is closed, and the signal remains high impedance; when the master core or the slave core generates a data packet, the link clock and the interface circuit are activated through a wake-up signal, and after the data transmission is completed, the link reenters the sleep state within a preset clock period. The local transmission protocol is used for low-bandwidth data interaction between the slave cores, and adopts a "unicast-broadcast" hybrid transmission mode; an idle timeout sleep strategy is adopted, and when there is no data transmission for a continuous number of clock periods, the link clock is automatically closed and the link enters a sleep state; when a new data packet is generated, the link is quickly activated through a wake-up signal.

[0014] In one embodiment, further comprising: setting an energy consumption optimization strategy based on the final hybrid interconnection topology structure; The energy consumption optimization strategy comprises: a hardware circuit level optimization strategy and a runtime dynamic management strategy; The hardware circuit level optimization strategy comprises: Setting a low-power link driving circuit: the driving circuits of global and local links adopt CMOS open drain (OD) structure, instead of traditional push-pull structure; Setting a low-power network interface: a dynamic power consumption gate module is integrated into the core network interface, when the core is in an idle state, the data packet analysis and routing circuit inside the network interface is closed, only the wake-up detection circuit is retained; the master core network interface adopts a "clock gating" strategy, only the clock is activated during data packet transmission, and the clock is closed during idle time; The runtime dynamic management strategy comprises: Setting a link bandwidth dynamic adjustment mechanism: the master core dynamically adjusts the global link width through the DVFS instruction, and the local link allocates bandwidth on demand according to the data interaction frequency between the cores; Setting a slave core interconnection state dynamic switching mechanism: when the algorithm does not require data interaction between the cores, the master core sends an interconnection sleep instruction, closes the clock and driving circuit of the local mesh link, and only retains the global star link; when entering the need for core cooperation stage, the master core sends an interconnection wake-up instruction to reactivate the local mesh link.

[0015] In a second aspect, the embodiment of the present application provides an extreme environment path planning system based on a RISCV multi-core architecture, comprising: a key feature acquisition module, a quantization result acquisition module, an instruction set optimization module, a topology structure optimization module and a path planning module. The key feature acquisition module is configured to run an existing path planning algorithm in a simulation environment and acquire key computing features. The quantization result acquisition module is configured to compare the key computing features in different complexity scenarios to obtain quantization results of the key computing features. The instruction set optimization module is configured to optimize the RISCV instruction set based on the quantization results, with the target optimization standard being to reduce invalid instruction execution and core operation delay, to obtain an optimized instruction set. The topology structure optimization module is configured to construct a final hybrid interconnection topology structure of master core-slave core star+local mesh based on the quantization results, with the target being to reduce redundant data transmission and cross-core synchronization overhead. The path planning module is configured to acquire a target task and call the corresponding optimized instruction set on the hybrid interconnection topology structure to complete extreme environment path planning.

[0016] Compared with the prior art, the application provides an extreme environment path planning method and system based on a RISCV multi-core architecture, the computing characteristics of the extreme environment path planning algorithm are quantitatively analyzed, optimization is performed from two core levels of an instruction set and an interconnection topology, precise matching of path planning algorithm requirements and architecture capabilities is achieved, and the power consumption redundancy problem of a general architecture is effectively solved; the application sets special instructions and a hybrid interconnection topology that adapt to path planning core operations, adds special RISCV instructions for distance calculation, node sorting and other core operations of A* algorithm and RRT algorithm, reduces the number of instruction executions, adopts a hybrid interconnection topology combining a "master core-slave core" star type and a local mesh, optimizes a data transmission path, reduces cross-core data interaction energy consumption, and compared with a traditional architecture, the computing efficiency is improved while the power consumption is significantly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0018] Figure 1 A flowchart of the extreme environment path planning method based on the RISCV multi-core architecture provided in the embodiments of the present application.

[0019] Figure 2 A flowchart of the final hybrid interconnection topology construction method provided in the embodiments of the present application.

[0020] Figure 3 A structure schematic diagram of the extreme environment path planning system based on the RISCV multi-core architecture provided in the embodiments of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0022] The embodiments of the present application disclose an extreme environment path planning method based on a RISCV multi-core architecture, including the following steps, for the convenience of description, numbers S1-S5 are set, and the numbers are not used to limit the sequence of the steps of the present application: S1 runs in a simulation environment based on existing path planning algorithms and obtains key computing characteristics.

[0023] Further, the selected existing path planning algorithms of the present application include: path planning algorithm A* based on heuristic search and path planning algorithm RRT based on probability sampling; A* algorithm becomes the preferred choice under known terrain due to its optimal path guaranteeing capability; RRT algorithm is suitable for dynamic or partially unknown extreme environment scenarios due to its advantage of rapid exploration of unknown terrain.

[0024] Among them, A* algorithm can quickly find the shortest path that meets the constraint conditions in complex terrain by introducing heuristic function to balance search efficiency and path optimality, adapting to the dual demands of path safety and efficiency of extreme environment robots. RRT algorithm explores unknown terrain by randomly generating nodes, without traversing all grids, and has higher real-time performance in extreme environment with partially unknown or dynamic terrain, such as temporary rock obstacles. Further, the present application realizes simulation environment simulation and feature acquisition by building an experimental platform with terrain simulation, algorithm running and data acquisition functions. The platform adopts a hybrid architecture of "software simulation-hardware interface simulation", which can not only restore the influence of complex terrain in extreme environment on the algorithm, but also simulate the instruction execution environment of RISCV architecture, ensuring that the collected feature data match the hardware design requirements. The platform is divided into three layers: terrain simulation layer, algorithm running layer and feature acquisition layer, and the functions and interaction relationships of each layer are as follows: Terrain simulation layer: based on NASA's public extreme environment digital elevation model DEM data, such as 10m resolution elevation data obtained by lunar reconnaissance orbiter LRO, the data is preprocessed by Python's GDAL library to generate a grid map containing crater, rock, slope information, with a resolution of 0.5m x 0.5m, and support for custom obstacle distribution, such as adding rock obstacles with a diameter of 1-5m, to simulate extreme environment terrain scenarios with different complexity: simple scenario: obstacle ratio <10%; medium scenario: obstacle ratio 10%-30%; complex scenario: obstacle ratio >30%; Algorithm running layer: A*, RRT algorithms are implemented in C language to ensure consistent instruction calling logic with hardware implementation, integrated in Ubuntu 22.04 operating system environment, and the project is built and compiled by CMake; to simulate multi-core hardware environment, OpenMP parallel programming framework is introduced to support parallelization testing of key parts of the algorithm such as A* algorithm neighborhood node calculation and RRT algorithm random sampling, and to preliminarily evaluate the parallel computing potential; at the same time, a timestamp recording module is embedded in the algorithm code to calculate the time consumption ratio of each operation link; Feature collection layer: Through the cooperation of QEMU emulator and VTune Profiler, multi-dimensional feature data collection is realized. Instruction call frequency: Based on the QEMU emulator, an instruction execution environment is built. The RISCV executable file generated by compiling the algorithm running layer is loaded into the simulator. Through the tracking and debugging interface of QEMU, the instruction execution log is collected, including instruction type, instruction execution times, register read-write operation, etc. Through Python script, the execution times and proportion of various instructions are counted, and the execution frequency of arithmetic operation instructions (such as ADD, SUB, MUL), logical judgment instructions (such as BEQ, BNE), data loading / storage instructions (such as LW, SW), and branch instructions are focused on, to analyze the preference of the algorithm for instruction types.

[0025] Data dependency: Using the "Memory Access" analysis function of VTune Profiler, the memory access behavior during algorithm running is sampled to obtain the read-write address, access frequency and dependency of data; through the "Dependency Chain" analysis tool, the length of data dependency chain (i.e. how many previous operations a data needs to wait for before it can be used) and dependency type (data dependency, control dependency) are identified to quantify the degree of restriction of data dependency on parallel computing. Parallel computing potential: Based on the OpenMP framework, the key operation links of the algorithm are parallelized (such as the neighbor node cost calculation of A* algorithm and the multi-node sampling of RRT algorithm), and the execution time of the algorithm is tested under different thread numbers (1-8 threads) to calculate the speedup ratio (single-thread time / multi-thread time). Through self-defined script, the number of parallelizable subtasks (such as the number of independent sampling nodes generated by RRT algorithm in each iteration) and the synchronization overhead between subtasks (such as the time-consuming of data exchange between threads) are counted to evaluate the upper limit of the parallel computing potential of the algorithm.

[0026] Further, the key computing features include instruction call frequency, data transmission relationship and parallel computing capability.

[0027] S2 compares the key computing features in different complexity scenarios to obtain the quantitative results of the key computing features.

[0028] Further, the quantitative results of the key computing features include: Simulate to generate terrain scenarios of different complexity; Based on the existing path planning algorithm, according to the key computing features, the average value is taken after multiple simulation runs in terrain scenarios of different complexity to obtain the final results of instruction call frequency, data transmission relationship and parallel computing capability. Based on the instruction call frequency final result, the data transmission relationship final result and the parallel computing ability final result, corresponding quantitative results are obtained.

[0029] Further, in order to comprehensively obtain the key computing characteristics of A* algorithm and RRT algorithm, comparative experiments are carried out on the built simulation and characteristic analysis platform for three kinds of terrain complexity scenes (simple, medium and complex), three kinds of characteristic data of instruction call frequency, data dependency relationship and parallel computing potential are collected, and quantitative analysis is carried out, so as to provide data support for the customized design of RISCV multi-core architecture.

[0030] The application adopts the control variable method, keeps the algorithm input parameters (the distance between the starting point and the target point is set to 50m, the Manhattan distance is used for the heuristic function of A* algorithm, the step length of RRT algorithm is set to 1m, and the target threshold is set to 2m) consistent, only changes the terrain complexity, repeats the experiment 10 times for each scene, and takes the average value as the final result, so as to reduce the influence of random error on data.

[0031] Further, the quantitative result acquisition method is: The final result of instruction call frequency is: the instruction execution proportion of arithmetic operation instruction, logic judgment instruction, data loading / storage instruction, branch instruction and other instructions in different complexity terrain scenes; The instruction call frequency quantitative result is obtained based on the instruction execution proportion; The final result of data dependency relationship is: the data dependency chain length and the data dependency type proportion in different complexity terrain scenes; The data dependency relationship quantitative result is obtained based on the data dependency chain length and the data dependency type proportion; The final result of parallel computing potential is: the different thread number speedup ratio, the number of parallelizable subtasks, the synchronization overhead proportion and the parallel efficiency in different complexity terrain scenes; The parallel computing potential quantitative result is obtained based on the different thread number speedup ratio, the number of parallelizable subtasks, the synchronization overhead proportion and the parallel efficiency.

[0032] Further, the instruction call frequency quantitative result includes: The proportion of arithmetic operation instruction in RRT algorithm and A* algorithm is the highest, the proportion of logic judgment instruction increases with the increase of terrain scene complexity, the proportion of data loading / storage instruction decreases with the increase of terrain scene complexity, and the proportion of other instructions is the lowest, which is a redundant instruction; The data dependency relationship quantitative result includes: The data dependency of RRT algorithm and A* algorithm increases with the increase of terrain scene complexity, and the short dependency chain proportion is the highest; The data dependency of RRT algorithm is lower than that of A* algorithm; The A* algorithm control relies on higher than the RRT algorithm; The parallel computing potential results include: The parallel potential of the RRT algorithm is higher than that of the A* algorithm; The parallel efficiency of the RRT algorithm and the A* algorithm decreases with the increase of the complexity of the terrain scene; 4 threads are the optimal parallel scale.

[0033] Further, the instruction execution data of the two algorithms in different terrain scenes are collected by the QEMU simulator, and the execution times and proportions of the arithmetic operation instructions, logical judgment instructions, data loading / storage instructions, branch instructions and other instructions are calculated as the final results of the instruction call frequency. The instruction execution proportion results of the A* algorithm in different terrain scenes are shown in Table 1: Table 1 Instruction execution proportion of A* algorithm in different terrain scenes (%)

[0034] The instruction execution proportion results of the RRT algorithm in different terrain scenes are shown in Table 2: Table 2 Instruction execution proportion of RRT algorithm in different terrain scenes (%)

[0035] Based on the instruction execution times and proportions in Table 1 and Table 2, the instruction call frequency quantization results are obtained: The arithmetic operation instruction proportion in the RRT algorithm and the A* algorithm is the highest: the average proportion of arithmetic operation instructions of the A algorithm and the RRT algorithm is 41.6% and 46.9% respectively, and increases significantly with the increase of the complexity of the terrain, because the more complex the terrain is, the more distance calculation and cost evaluation operations the algorithm needs to perform, resulting in a significant increase in the call frequency of addition, multiplication and other arithmetic instructions; among them, the proportion of arithmetic instructions of the RRT algorithm is higher, mainly because the random sampling link needs to frequently calculate the distance between the sampling node and the node in the tree, which further verifies the necessity of designing special instructions for distance calculation.

[0036] The proportion of logical judgment instructions increases with the increase of the complexity of the terrain scene: the average proportion of logical judgment instructions of the A* algorithm is 28.4%, which increases by 5.5 percentage points in the complex scene compared with the simple scene; the average proportion of the RRT algorithm is 23.5%, which increases by 6.4 percentage points in the complex scene compared with the simple scene; logical judgment instructions are mainly used for obstacle detection (such as judging whether the node is located in the crater area) and node validity verification, the higher the complexity of the terrain is, the more the number of obstacles is, the more the number of judgments is, and the proportion of instructions increases accordingly.

[0037] Data data load / store instructions decrease with the complexity of the terrain scene: A algorithm data load / store instructions account for an average of 20.9%, down 2.8 percentage points in complex scenes compared to simple scenes; RRT algorithm accounts for an average of 17.3%, down 2.8 percentage points in complex scenes compared to simple scenes, because in complex scenes, the time-consuming proportion of algorithm operation links (such as node expansion, sampling) increases, the time-consuming proportion of data access links is relatively compressed, and the local data cache hit rate is improved (such as the open list data of A algorithm is accessed in cache), reducing memory load / store operations.

[0038] Other instructions account for the lowest proportion, as redundant instructions: other instructions in the two algorithms, such as complex floating point operations and privileged instructions, account for an average of only 1.1%-1.2%, and tend to be 0 as the complexity increases, indicating that a large number of general-purpose instructions in the standard instruction set are not used in path planning tasks, providing a clear direction for subsequent instruction set pruning.

[0039] Further, by collecting data dependencies of the two algorithms using VTune Profiler, the length of the data dependency chain and the proportion of data dependency types are counted as the final result of data dependency relationship, and the length of the data dependency chain of A* algorithm and RRT algorithm in different terrain scenes is shown in Table 3: Table 3 A* algorithm and RRT algorithm data dependency chain length statistics (unit: clock cycle)

[0040] The proportion of data dependency types of A* algorithm and RRT algorithm in different terrain scenes is shown in Table 4: Table 4 A* algorithm and RRT algorithm data dependency type proportion (%)

[0041] Based on the data dependency chain length and data dependency type proportion statistics in Table 3 and Table 4, the data dependency relationship quantization result is obtained: The data dependency of RRT algorithm and A* algorithm increases with the complexity of the terrain scene: the average dependency chain length of the two algorithms increases with the complexity of the terrain, and the A* algorithm increases by 50% in complex scenes compared to simple scenes, and the RRT algorithm increases by 42.1%, because in complex scenes, the algorithm needs to process more node data, and the relationship between data is more complex, resulting in longer dependency chain.

[0042] The proportion of short dependency chain of RRT algorithm and A* algorithm is the highest: the proportion of dependency chain length ≤3 cycles of the two algorithms is more than 60% (A* algorithm) -80% (RRT algorithm), indicating that the degree of restriction of data dependency on parallel computing is low, and most data can be completed in a short time, providing feasibility for multi-core parallel scheduling.

[0043] RRT algorithm data dependency is lower than A* algorithm: the average dependency chain length of RRT algorithm (1.9-2.7 cycles) is significantly shorter than that of A* algorithm (2.8-4.2 cycles), and the proportion of "no dependency" data (28.1%-38.9%) is much higher than that of A algorithm (0.2%-9.3%). The reason is that the random sampling node generation, collision detection and other links of RRT algorithm have strong data independence, while the node expansion of A* algorithm needs to rely on the cost data of the previous node, forming strong data dependency. A* algorithm control dependency is higher than RRT algorithm: the control dependency proportion of A* algorithm (32.5%-35.1%) is significantly higher than that of RRT algorithm (18.3%-23.7%). Because A* algorithm needs to frequently perform branch judgment (such as judging whether the node is the target point or not, whether it is in the open list), while RRT algorithm has less branch operation (such as whether the sampling is successful), the control dependency is weaker.

[0044] Further, based on the OpenMP framework, the speedup ratios of the two algorithms under different terrain scenarios and different thread numbers are tested, and the number of parallelizable subtasks, the synchronization overhead proportion and the parallel efficiency are used as the parallel computing potential results. The speedup ratio statistics of A* algorithm and RRT algorithm under different terrain scenarios and different thread numbers are shown in Table 5: Table 5 Speedup ratio of A* algorithm and RRT algorithm under different thread numbers

[0045] The number of parallelizable subtasks, the synchronization overhead proportion and the parallel efficiency statistics of A* algorithm and RRT algorithm under different terrain scenarios are shown in Table 6, wherein the parallel efficiency is equal to the ratio of actual speedup ratio and ideal speedup ratio: Table 6 Number of parallelizable subtasks, synchronization overhead proportion and parallel efficiency of A* algorithm and RRT algorithm

[0046] Based on the speedup ratio, the number of parallelizable subtasks, the synchronization overhead proportion and the parallel efficiency of different thread numbers obtained from the above Table 5 and Table 6, the parallel computing potential results include: The parallel potential of the RRT algorithm is higher than that of the A* algorithm: the 4-thread speedup ratio of the RRT algorithm (3.18-3.52) is significantly higher than that of the A* algorithm (2.51-2.95), the gap in the 8-thread speedup ratio is greater (5.25-6.18 vs 3.23-3.82), and the parallel efficiency (67.1%-78.5%) is higher than that of the A* algorithm (59.8%-71.2%). The core reason is that the random sampling and multi-node collision detection of the RRT algorithm can be independently executed in parallel, the number of parallel subtasks (28.7-41.6) is much larger than that of the A* algorithm (12.5-24.1), and the synchronization overhead (4.2%-7.3%) is lower.

[0047] The parallel efficiency of the RRT algorithm and the A* algorithm decreases with the increase of the complexity of the terrain scene: the parallel efficiency of both algorithms decreases with the increase of the complexity of the terrain, and the A* algorithm decreases by 11.4 percentage points in the complex scene compared to the simple scene, and the RRT algorithm decreases by 11.4 percentage points. Because in the complex scene, the number of parallel subtasks increases, the data interaction between subtasks (such as sharing of RRT algorithm sampling nodes) increases, the synchronization overhead increases, and the main core task scheduling pressure increases, resulting in a decrease in parallel efficiency.

[0048] 4 threads are the optimal parallel scale: the 4-thread speedup ratio of both algorithms is close to the ideal value, and the 8-thread speedup ratio improves slowly (e.g., the A* algorithm improves by only 0.27-0.87 from 4 threads to 8 threads). Because the competition for cache and bus resources between threads intensifies at 8 threads, and the synchronization overhead grows nonlinearly, it is shown that in the design of multi-core architecture, 4 slave cores are the optimal choice that balances parallel performance and energy consumption.

[0049] S3 optimizes the standard RISCV instruction set based on the quantization results to reduce invalid instruction execution and core operation delay as the optimization standard.

[0050] Further, the optimized instruction set includes: Optimize the standard RISCV instruction set based on the instruction call frequency quantization results: Eliminate redundant instructions unrelated to path planning algorithms; Optimize the hardware execution circuit for arithmetic operation instructions and data load / store instructions: use a carry-select adder for the ADD instruction, use a Wallace tree multiplier for the MUL instruction, optimize the address generation logic for data load / store instructions, and support continuous address data block access; For distance calculation instructions, set Manhattan distance calculation and Euclidean distance approximation calculation as two special instructions; For node sorting instructions in the A* algorithm, set a node priority sorting instruction, complete ascending sorting through a hardware sorting circuit, and output the sorted node index.

[0051] Further, the redundant instructions irrelevant to the path planning algorithm are pruned, including 64-bit integer division instructions DIV and REM, privilege mode instructions such as ECALL and EBREAK, floating point operation instructions, RVF extension, a total of 18 redundant instructions are pruned, the hardware area of the instruction decoding unit is reduced by 35%, and the energy consumption in the decoding stage is reduced.

[0052] Further, for the integer arithmetic instructions ADD and MUL and the data load / store instructions LW and SW frequently executed, the hardware execution circuit is optimized: the ADD instruction adopts a carry-select adder to reduce the critical path delay; the MUL instruction adopts a Wallace tree multiplier to compress the execution period from 3 cycles to 2 cycles; the LW / SW instruction optimizes the address generation logic, supports continuous address block access, reduces the number of address calculations when multiple data loads, and improves the data access efficiency.

[0053] Further, for the distance calculation operation accounting for more than 15% in the algorithm, Manhattan distance calculation MDIST and Euclidean distance approximation calculation EDIST are designed. The MDIST instruction can directly read two node coordinates (x1, y1, x2, y2), and parallelly calculate |x1-x2|+|y1-y2| through the hardware circuit, which compresses the operation of 4 ADD instructions and 2 ABS instructions into 1 instruction, and shortens the execution period from 5 cycles to 1 cycle; the EDIST instruction adopts an integer approximation algorithm (avoiding floating point operation), and calculates the Euclidean distance approximation value through the formula , the precision error is controlled within 5%, which meets the path planning precision requirement in extreme environment, and the execution period is only 2 cycles, which is 4 times more efficient than the software implementation.

[0054] For the high-frequency operation of the A* algorithm "open list" node priority sorting, the NSORT instruction is designed. The instruction supports reading the f (n) values of four nodes at a time and storing them in consecutive registers, and through the hardware sorting circuit, a two-by-two comparator is used to complete the ascending sorting and output the sorted node index, which compresses the sorting process of 8 comparison instructions and 4 exchange instructions in the software implementation into 1 instruction, and shortens the execution period from 12 cycles to 3 cycles, while avoiding frequent data load / store operations in the sorting process and reducing the memory access energy consumption.

[0055] Further, the customized instruction set follows the RISCV instruction encoding specification, adopts a fixed 32-bit instruction length (R-type and I-type encoding format), and allocates the special instruction encoding space in the RISCV custom extension opcode area (0x1C-0x1F) to avoid conflicts with the basic instructions. The MDIST instruction (Manhattan distance calculation) adopts the R-type encoding format. The EDIST instruction (Euclidean distance approximation calculation) adopts the R-type encoding format. NSORT instruction (node priority sorting): adopts I-type coding format.

[0056] Further, the special instruction execution flow is as follows: taking the MDIST instruction as an example, the execution flow is divided into four stages of instruction fetching, decoding, execution and write back, and the total time consumption is 1 clock cycle: The instruction cache (I-Cache) reads the 32-bit MDIST instruction according to the program counter (PC) address and transmits it to the instruction decoding unit in the instruction fetching stage; The decoding unit analyzes opcode (0x1C) and func3 (000) and identifies it as the MDIST instruction, and reads the node coordinate data in the rs1 and rs2 registers and transmits it to the special operation unit in the decoding stage; The absolute value circuit inside the special operation unit calculates |x1-x2| and |y1-y2| in the execution stage, and the addition circuit adds the two absolute value results to obtain the Manhattan distance value, which is temporarily stored in the operation unit output register; The distance value output by the operation unit is written into the rd register in the write back stage, and the instruction execution is completed. The execution flows of the EDIST and NSORT instructions are similar to MDIST, and the difference lies in that the special hardware circuit (approximate calculation circuit of EDIST and sorting comparison circuit of NSORT) is used in the execution stage, and the execution periods are 2 and 3, respectively. Both of them are implemented through pipeline design to realize parallel execution with basic instructions and avoid instruction blocking.

[0057] Further, in order to verify the energy consumption optimization effect of the optimized instruction set, based on the Synopsys Design Compiler tool, the instruction set hardware implementation is synthesized by using 40nm CMOS process, and the hardware area and energy consumption of the optimized instruction set and the standard RV64I instruction set are compared. 1000 times of node expansion is taken as the test scene, and the results are shown in Table 7: Table 7 Comparison of energy consumption of optimized instruction set and standard RV64I instruction set

[0058] The results show that the optimized instruction set of the application reduces the hardware area by 28.9% while reducing the energy consumption by 43.8% through cutting redundant instructions and special instruction hardware acceleration, and the instruction execution efficiency is improved by 78.8%, which fully verifies the double optimization effect of instruction set customization on low power consumption and high performance.

[0059] S4 constructs the final hybrid interconnection topology structure of master-slave star + local mesh based on the quantization results to reduce the redundant data transmission and cross-core synchronization overhead.

[0060] Further, asFigure 2 The final mixed interconnection topology construction method is shown as follows: Based on the data dependency relationship quantization result, it is obtained that the A* algorithm has control dependency, the RRT algorithm has high parallel potential, and the cross-core data transmission of the two algorithms is concentrated in the "master-core-slave core" task allocation and "slave core-slave core" node information interaction, which are collectively used as the first key information. Based on the first key information, an initial mixed interconnection topology of master-core-star + local mesh is constructed. Based on the parallel computing potential quantization result, the second key information that four slave cores achieve the optimal speedup ratio is obtained. Based on the second key information, the initial mixed interconnection topology is set to a 5-core structure of 1 master core + 4 slave cores, and the final mixed interconnection topology is obtained.

[0061] Further, the multi-core interconnection topology is a key factor affecting the parallel computing efficiency and energy consumption of the architecture, and the application adopts a "master-core-star + local mesh" mixed interconnection topology to replace the traditional full-connection mesh topology, which reduces invalid interconnection links and reduces the energy consumption of the interconnection network while ensuring the data transmission efficiency.

[0062] Further, the final mixed interconnection topology includes a global star interconnection layer and a local mesh interconnection layer. The global star interconnection layer is responsible for global data transmission between the master core and the slave core, the master core and the shared storage, and is connected by the master core network interface and the four slave core network interfaces through a bidirectional point-to-point link to form a star structure; the master core is connected to the shared storage through a separate link, and the slave core needs to access the shared storage through the master core; The local mesh interconnection layer is responsible for local data interaction between the four slave cores, adopts a 2x2 mesh structure, and the four slave cores are respectively located at the four nodes of the mesh; each slave core is connected to the adjacent two slave cores through a network interface; the link between the slave cores adopts an asynchronous clock domain design; and each slave core network interface integrates a simple routing function to support local forwarding and cross-core transmission of data.

[0063] Further, the global star interconnection layer link is set as follows: a bidirectional point-to-point link is used between the master core and each slave core, the link width is 32 bits, matching the data bus width, the transmission rate is 1GHz, supporting burst transmission mode, transmitting four 32-bit data at a time, reducing the transmission times when the master core allocates task data (such as terrain grid, node initial parameter) to the slave core; The global star interconnection layer adopts shared storage connection: the main core is connected with shared storage (with a capacity of 256 KB, using low-power SRAM) through a separate 32-bit link, when the slave core needs to access the shared storage, the main core needs to be forwarded, that is, slave core - main core - shared storage, avoiding link redundancy caused by direct connection of the slave core to the shared storage, the frequency of the slave core accessing the shared storage is only 1 / 5 of the main core, and although the forwarding through the main core increases the delay by 1 cycle, 4 slave core-shared storage links can be reduced, and the hardware area and static energy consumption of the interconnection network are reduced.

[0064] Further, the link of the local mesh interconnection layer is set as: the link width between the slave cores is 16 bits (the data interaction amount between the slave cores is small, and the 16-bit width can meet the demand), the transmission rate is 800 MHz, and an asynchronous clock domain design is adopted to avoid conflict with the 1GHz clock of the global star interconnection layer and reduce clock synchronization energy consumption.

[0065] The local mesh interconnection layer adopts a routing node optimization: each slave core network interface integrates a simple routing function to replace an independent Router node, supports local forwarding and cross-core transmission of data, the routing decision adopts a "dimensional ordered routing" algorithm, first in the horizontal direction and then in the vertical direction, avoids data deadlock, and at the same time simplifies the routing logic and reduces the hardware complexity. Compared with the traditional 5-core full-connection mesh topology, the link number of the mixed interconnection topology of the application is reduced from 10 (full connection) to 8 (4 global star links + 4 local mesh links), and the link width is designed according to the difference in data transmission demand, so that the hardware area is greatly reduced, and the static energy consumption is greatly reduced.

[0066] S5 acquires a target task and calls an execution corresponding optimization instruction set on the final mixed interconnection topology structure to complete the path planning in an extreme environment.

[0067] Further, in order to further reduce the dynamic energy consumption of the interconnection network, based on the final mixed interconnection topology structure, a "layered transmission protocol + dynamic link sleep" data transmission mechanism is set, the protocol is divided into a global transmission protocol (main core - slave core, main core - shared storage) and a local transmission protocol (slave core - slave core), both of which adopt a credit-based flow control mechanism to avoid data loss and link congestion.

[0068] Further, the data transmission mechanism includes: a global transmission protocol and a local transmission protocol, both of which adopt a credit-based flow control mechanism. Global transmission protocol is used for high-bandwidth data transmission between master core and slave core, master core and shared storage, and adopts "request-response" bidirectional transmission mode. Global link adopts "data-driven wake-up" mechanism. When there is no data transmission, the link is in sleep state, the clock is closed, and the signal remains high impedance. When the master core or the slave core generates a data packet, the link clock and interface circuit are activated through the wake-up signal. After data transmission is completed, it reenters sleep state within a preset clock period. Local transmission protocol is used for low-bandwidth data interaction between slave cores, and adopts "unicast-broadcast" hybrid transmission mode. When there is no data transmission for a continuous number of clock periods, the link clock is automatically closed and enters sleep state. When a new data packet is generated, the link is quickly activated through the wake-up signal.

[0069] Further, the global transmission protocol data packet format is divided into request packet (Request) and response packet (Response): Request packet format: 64 bits in total, including 8-bit operation code (OP, such as task allocation, data reading, data writing), 8-bit slave core ID or L2 Cache bank ID, 32-bit address (Addr), and 16-bit data length (Len, unit: 32 bits); Response packet format: 64 bits in total, including 8-bit status code (Status, such as success, address error, data overflow), 8-bit master core ID, 32-bit address (corresponding to request packet), and 16-bit valid data or data length.

[0070] Further, in order to reduce energy consumption, the global link adopts "data-driven wake-up" mechanism. When there is no data transmission, the link is in sleep state (the clock is closed and the signal remains high impedance). When the master core or the slave core generates a data packet, the link clock and interface circuit are activated through the wake-up signal. After data transmission is completed, it reenters sleep state within 1 clock period, which can greatly reduce the dynamic energy consumption of the global link.

[0071] Further, the local transmission protocol data packet format is simplified to 32 bits, reducing the number of transmission bits to reduce energy consumption, and the specific structure is as follows: 32-bit data packet format: including 4-bit transmission type (Type, unicast = 0x01, broadcast = 0x02), 4-bit source slave core ID (0x01-0x04 corresponding to SC1-SC4), 4-bit destination slave core ID (unicast for specific slave core ID, broadcast for 0x0F), and 20-bit valid data (such as node coordinates (16 bits, 8 bits for x / y), collision detection result (1 bit, 0=no collision, 1=collision).

[0072] Further, the local transmission protocol supports two transmission processes: Unicast transmission process, for example, SC1 sends RRT node collision result to SC2: SC1 generates a data packet (Type=0x01, Source ID=0x01, Destination ID=0x02, Data=0x00001 (indicating that the node has no collision), and sends it to SC2-NI through the local mesh link; After SC2-NI receives the data packet, it parses the destination ID and transmission type, confirms the match, extracts the valid data, updates the local node information cache, and sends a 1-bit confirmation signal (high level=reception success) through the reverse link; After SC1-NI receives the confirmation signal, the unicast transmission is completed, and the entire process takes 3 clock cycles (1 cycle for sending, 1 cycle for receiving, and 1 cycle for confirmation); Broadcast transmission process, for example, SC3 broadcasts A* algorithm neighbor node coordinates to all slave cores: SC3 generates a data packet (Type=0x02, Source ID=0x03, Destination ID=0x0F, Data=0x12345 (x=0x12, y=0x34, node state=0x5)), and sends it to adjacent SC2 and SC4 through the local mesh link; After SC2-NI and SC4-NI receive the data packet, they need to forward the data packet to the slave core that is not directly connected (SC2 forwards to SC1, SC4 forwards to SC1) in addition to extracting data locally. During the forwarding process, no new data packet needs to be generated, only the source ID needs to be updated to the forwarding slave core ID; After all slave cores (SC1, SC2, SC4) receive the data packet, they send a confirmation signal to SC3. After SC3 receives all the confirmation signals, the broadcast transmission is completed, which takes 5 clock cycles, significantly improving the efficiency compared to traditional core-by-core unicast transmission.

[0073] Further, the local link also adopts a dynamic energy consumption optimization mechanism: in view of the intermittency of data interaction between slave cores, the data transmission interval between slave cores is 20 clock cycles on average, and an "idle timeout sleep" strategy is set: when there is no data transmission for 5 consecutive clock cycles, the link clock is automatically turned off and the link enters a sleep state; when a new data packet is generated, the link is quickly activated by a wake-up signal, and the wake-up delay is only 1 clock cycle. Simulation results show that this strategy can reduce the dynamic energy consumption of the local link by 38% without significantly increasing the transmission delay.

[0074] Further, in addition to the above topology structure and transmission protocol optimization, the present application further sets energy consumption optimization strategies for the interconnection topology from two dimensions of hardware circuit and runtime management: The energy consumption optimization strategy includes: hardware circuit level optimization strategy and runtime dynamic management strategy; The hardware circuit level optimization strategy includes: Low-power link driving circuit is set: the driving circuit of global and local links adopts CMOS open-drain (OD) structure, replacing the traditional push-pull structure to reduce static current consumption. When the OD structure keeps the signal at high level, it only provides current through the pull-up resistor, and the static current can be reduced from 5 μA of the push-pull structure to 0.8 μA. At the same time, the link transmission line adopts a combination of differential signal transmission (global link) and single-ended signal transmission (local link). The global link adopts differential signal due to high transmission rate (1 GHz), which has strong anti-interference ability. The local link adopts single-ended signal due to low transmission rate (800 MHz), which reduces the number of wires and capacitive load, and reduces dynamic energy consumption. Low-power network interface is set: a dynamic power consumption gating module is integrated in the slave network interface. When the slave core is in idle state, the data packet parsing and routing circuit inside the network interface is turned off, and only the wake-up detection circuit is retained. The master core network interface adopts a "clock gating" strategy, and only activates the clock during data packet transmission, and turns off the clock when idle, reducing the clock rollover energy consumption. The runtime dynamic management strategy includes: Link bandwidth dynamic adjustment mechanism is set: when the algorithm executes A* algorithm (stable data transmission, about 1.2 GB / s), the global link maintains 32-bit width, and the local link maintains 16-bit width. When the RRT algorithm is executed (data transmission fluctuates greatly, peak value 1.8 GB / s, valley value 0.5 GB / s), the master core dynamically adjusts the global link width through the DVFS instruction: expands to 64 bits (by connecting two 32-bit links) at peak, and reduces to 16 bits at valley. The local link switches between 16 bits and 8 bits according to the data interaction frequency between slave cores, realizing "on-demand allocation" bandwidth, and avoiding energy waste caused by bandwidth redundancy. Slave core interconnection state dynamic switching mechanism is set: when the algorithm does not require data interaction between slave cores, the master core sends an interconnection sleep instruction to turn off the clock and driving circuit of the local mesh link, and only the global star link is retained. When entering the slave core cooperation stage, the master core sends an interconnection wake-up instruction to reactivate the local mesh link, which can greatly reduce the invalid energy consumption of the local link.

[0075] Further, based on the Synopsys PrimePower tool (40 nm CMOS process, power supply voltage 1.2 V, temperature 25℃), an energy consumption simulation model of the hybrid interconnection topology is built. The energy consumption and performance of the traditional full-connection mesh topology and the optimized hybrid topology under A* algorithm and RRT algorithm are compared. The results are shown in Table 8: Table 8 Energy consumption and performance comparison before and after optimization of the final hybrid interconnection topology

[0076] The results show that the optimized final hybrid interconnection topology reduces the hardware area by 32.5%, reduces the static energy consumption by 28.6%, reduces the dynamic energy consumption by 48.2%, shortens the average transmission delay by 35.7%, and improves the data throughput by 31.3%, fully verifying the effectiveness of the topology structure, transmission protocol and energy consumption optimization strategy, and meeting the dual requirements of "low power consumption - high performance" of the interconnection network for the extreme environment path planning algorithm.

[0077] Example 2 Based on the FPGA verification platform and the standardized test scheme, the present embodiment carries out a comparative experiment of the RISCV multi-core architecture (hereinafter referred to as "customized architecture") and the general RISCV multi-core architecture (hereinafter referred to as "general architecture"). The experiment takes the extreme environment path planning core algorithm (A* algorithm, RRT algorithm) as the test load, collects the calculation delay and power consumption data of the two architectures in simple, medium and complex terrain scenes, and verifies the advantages of the customized architecture in efficiency and energy consumption through quantitative analysis. At the same time, combined with the architecture design details (such as special instructions, hybrid interconnection topology), the advantages are analyzed to provide data support for the engineering application of the customized architecture. To ensure the fairness and reliability of the experimental results, the basic hardware environment, software configuration and data preprocessing method of the experiment need to be clarified to eliminate the interference of test condition differences on the results. The core configurations of the customized architecture and the general architecture are shown in Table 9: Table 9 Comparison of core configurations of customized architecture and general architecture

[0078] The experimental test scene is divided into simple (obstacle ratio <10%), medium (obstacle ratio 10%-30%) and complex (obstacle ratio >30%) terrains. A* algorithm and RRT algorithm are executed 10 times in each scene, and the average value is taken as the final data.

[0079] To systematically verify whether the customized RISCV multi-core architecture meets the core requirements of the extreme environment path planning task, the experimental results are compared with the evaluation standards one by one to determine the compliance of each index. Combined with the key test data of A* algorithm and RRT algorithm in complex scenes, the compliance table of customized architecture and evaluation standards is formed, and the specific content is shown in Table 10: Table 10 Compliance table of customized architecture and evaluation standards

[0080] Based on the above table, the core indicators of the customized architecture meet or even exceed the evaluation standards, which are specifically shown as follows: Real-time compliance: In complex scenarios, the A* algorithm has a delay of 42.15 ms, which is 15.7% lower than the standard (≤50 ms), and the RRT algorithm has a delay of 68.74 ms, which is 14.1% lower than the standard (≤80 ms). Even in the most complex areas of extreme environmental terrain, the robot can still generate a path quickly to avoid the risk of movement caused by planning lag. Task robustness: The path planning success rate is 95%, which is 5 percentage points higher than the standard (≥90%), and only 0.5 times out of 10 tests had local path adjustment due to extreme terrain (dense and overlapping craters), and no complete planning failure occurred, verifying the stable operation of the architecture in complex environments. Energy consumption and parallel performance advantage: The A* algorithm has an energy efficiency ratio of 32.23 mJ / time in complex scenarios, which is 19.4% lower than the standard (≤40 mJ / time), and according to the robot's 1000 planning tasks per day in extreme environments, it can save energy by about 7.77 kJ. The average parallel speedup ratio is 3.5, which is 9.4% higher than the standard (≥3.2), close to the ideal speedup ratio of 4 cores, and the parallel efficiency is at the industry-leading level. In summary, the customized RISCV multi-core architecture meets the needs of extreme environment path planning tasks in real-time, robustness, energy consumption, and parallel performance, laying a solid performance foundation for subsequent engineering applications and verifying the scientificity and effectiveness of the "algorithm-architecture" deep collaboration design idea.

[0081] To further highlight the innovation and advantage of this research, the customized architecture is compared with related researches at home and abroad, such as ESA's "RISCV for Space" architecture and the "Space-RISCV" architecture of the Institute of Computing of the Chinese Academy of Sciences, in terms of key indicators in extreme environment path planning tasks. The results are shown in Table 11: Table 11 Performance comparison of customized architecture and existing research architecture (complex scenario A* algorithm)

[0082] From the comparison results, we can see that: Compared with single-core architecture: The customized architecture of the invention reduces the computing delay by 53%, the dynamic power consumption by 39.6%, and the energy efficiency ratio by 71.2% through multi-core parallelism and instruction set customization, fully demonstrating the advantages of multi-core parallelism and algorithm-architecture collaboration. Compared with general multi-core architecture: the customized architecture of the application is based on "Space-RISCV", further reduces the calculation delay by 32.3%, reduces the dynamic power consumption by 31.6%, reduces the energy efficiency ratio by 53.8%, and improves the parallel acceleration ratio by 10.3% through special instructions (MDIST / EDIST) and hybrid interconnection topology, which verifies the unique value of customized design in extreme environment path planning task, and fills the gap of "algorithm-architecture" cooperation in existing research. Embodiment 3 As Figure 3 shown, based on the same inventive concept, the application also provides an extreme environment path planning system based on RISCV multi-core architecture, which comprises a key feature acquisition module, a quantization result acquisition module, an instruction set optimization module, a topology structure optimization module and a path planning module. The key feature acquisition module is used to run the existing path planning algorithm in the simulation environment and acquire the key computing features; The quantization result acquisition module is used to compare the key computing features in different complexity scenarios to obtain the quantization results of the key computing features; The instruction set optimization module is used to optimize the standard RISCV instruction set based on the quantization results to reduce invalid instruction execution and core operation delay as the target optimization standard, and obtain the optimized instruction set; The topology structure optimization module is used to construct the final hybrid interconnection topology structure of master-slave star + local mesh based on the quantization results to reduce redundant data transmission and cross-core synchronization overhead as the target; The path planning module is used to acquire the target task and call the corresponding optimized instruction set on the hybrid interconnection topology structure to complete the extreme environment path planning.

[0083] Further, in this embodiment, the implementation method of each step corresponds to the function implementation process of the above system module one by one, which will not be repeated here.

[0084] Embodiment 4 Based on the same inventive concept, the application further provides an electronic device, which comprises a processor and a memory, and the memory stores instructions, characterized in that the instructions are loaded and executed by the processor to implement the extreme environment path planning method based on RISCV multi-core architecture as in Embodiment 1.

[0085] Based on the same inventive concept, the application further provides a computer device, which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete communication with each other through the communication bus; The memory is used to store computer programs; The processor is configured to execute the program stored in the memory, and implement the extreme environment path planning method based on the RISCV multi-core architecture in the embodiment 1.

[0086] The electronic device can include a processor, a communications interface, a memory and a communications bus, wherein the processor, the communications interface and the memory can communicate with each other through the communications bus. The processor can invoke the logic instructions in the memory to execute the extreme environment path planning method based on the RISCV multi-core architecture in the embodiment 1.

[0087] In addition, the logic instructions in the memory can be implemented in the form of a software function unit and sold or used as an independent product, which can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0088] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0089] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An extreme environment path planning method based on RISCV multi-core architecture, characterized in that, The application relates to a method for obtaining a quantization result of key computing characteristics. Based on existing path planning algorithms, key computing characteristics are obtained in a simulation environment; Based on the key computing characteristics, a comparison is made in different complexity scenarios to obtain the quantization result of the key computing characteristics; Based on the quantization result, the RISCV instruction set is optimized to reduce invalid instruction execution and core operation delay, and an optimized instruction set is obtained; Based on the quantization result, a final hybrid interconnection topology structure of a master-core-slave star + local mesh is constructed to reduce redundant data transmission and cross-core synchronization overhead; A target task is obtained and the corresponding optimized instruction set is called to execute on the final hybrid interconnection topology structure to complete extreme environment path planning.

2. The RISCV multi-core architecture based path planning method for extreme environment according to claim 1, wherein, The quantization result of the key computing characteristics includes: The key computing characteristics include instruction call frequency, data transmission relationship and parallel computing capability; Different complexity terrain scenarios are simulated; Based on the existing path planning algorithms, the instruction call frequency final result, the data transmission relationship final result and the parallel computing capability final result are obtained by taking the average of multiple simulation runs in the different complexity terrain scenarios according to the key computing characteristics; Based on the instruction call frequency final result, the data transmission relationship final result and the parallel computing capability final result, the corresponding quantization result is obtained; The existing path planning algorithms include the A* algorithm based on heuristic search and the RRT algorithm based on probability sampling.

3. The RISC-V multi-core architecture based path planning method for extreme environment according to claim 2, characterized in that, The quantization result obtaining method is: The instruction call frequency final result is the instruction execution proportion of arithmetic operation instructions, logical judgment instructions, data loading / storage instructions, branch instructions and other instructions in the different complexity terrain scenarios; Based on the instruction execution proportion, the instruction call frequency quantization result is obtained; The data dependency relationship final result is the data dependency chain length and the data dependency type proportion in the different complexity terrain scenarios; Based on the data dependency chain length and the data dependency type proportion, the data dependency relationship quantization result is obtained; The parallel computing potential final result is the different thread number speedup ratio, the number of parallelizable subtasks, the synchronization overhead proportion and the parallel efficiency in the different complexity terrain scenarios; Based on the different thread number speedup ratio, the number of parallelizable subtasks, the synchronization overhead proportion and the parallel efficiency, the parallel computing potential quantization result is obtained.

4. The RISC-V multi-core architecture based extreme environment path planning method according to claim 3, characterized in that, The instruction call frequency quantization result includes: In the RRT algorithm and the A* algorithm, the arithmetic operation instruction proportion is the highest, the logical judgment instruction proportion increases with the increase of the complexity of the terrain scenario, the data loading / storage instruction proportion decreases with the increase of the complexity of the terrain scenario, and the other instruction proportion is the lowest and is a redundant instruction; The data dependency relationship quantization result includes: The data dependency of the RRT algorithm and the A* algorithm increases with the increase of the complexity of the terrain scenario, and the short dependency chain proportion is the highest; The data dependency of the RRT algorithm is lower than that of the A* algorithm; The control dependency of the A* algorithm is higher than that of the RRT algorithm; The parallel computing potential result includes: The parallel potential of the RRT algorithm is higher than that of the A* algorithm; The parallel efficiency of the RRT algorithm and the A* algorithm decreases with the increase of the complexity of the terrain scene; 4 threads are the optimal parallel scale.

5. The RISC-V multi-core architecture based extreme environment path planning method according to claim 4, characterized in that, An optimized instruction set is obtained, specifically including: Based on the instruction call frequency quantization result, the standard RISCV instruction set is optimized: The redundant instructions irrelevant to the path planning algorithm are removed; For the arithmetic operation instructions and the data load / storage instructions, the hardware execution circuit is optimized: the ADD instruction adopts a carry-select adder, the MUL instruction adopts a Wallace tree multiplier, the data load / storage instruction optimizes the address generation logic, and supports continuous address data block access; For the distance calculation type instructions, two special instructions for Manhattan distance calculation and Euclidean distance approximation calculation are set; For the node sorting type instructions in the A* algorithm, a node priority sorting instruction is set, and the ascending order sorting is completed through a hardware sorting circuit, and the sorted node index is output.

6. The RISC-V multi-core architecture based extreme environment path planning method according to claim 5, characterized in that, The final hybrid interconnection topology construction method is: Based on the data dependency quantization result, it is obtained that the A* algorithm has control dependency, the RRT algorithm has high parallel potential, and the cross-core data transmission of the two algorithms is focused on "master-core-slave task allocation and "slave-core-slave node information interaction, which are collectively used as the first key information; Based on the first key information, an initial hybrid interconnection topology structure of master-core-star+local mesh is constructed; Based on the parallel computing potential quantization result, the second key information that 4 slave cores achieve the optimal speedup ratio is obtained; Based on the second key information, the initial hybrid interconnection topology structure is set to a 5-core structure of 1 master core+4 slave cores, and the final hybrid interconnection topology structure is obtained.

7. The RISC-V multi-core architecture based extreme environment path planning method according to claim 6, characterized in that, The final hybrid interconnection topology structure includes a global star interconnection layer and a local mesh interconnection layer; The global star interconnection layer is responsible for global data transmission between the master core and the slave core, the master core and the shared storage, and is connected by a bidirectional point-to-point link between the master core network interface and the four slave core network interfaces, forming a star structure; the master core is connected to the shared storage through a separate link, and the slave core needs to access the shared storage through the master core; The local mesh interconnection layer is responsible for local data interaction between the four slave cores, adopts a 2*2 mesh structure, and the four slave cores are located at the four nodes of the mesh, each slave core is connected to the adjacent two slave cores through a network interface; the inter-core link adopts an asynchronous clock domain design; each slave core network interface integrates a simple routing function, supporting local forwarding and cross-core transmission of data.

8. The RISC-V multi-core architecture based path planning method for extreme environment according to claim 7, characterized in that, Further including: Based on the final hybrid interconnection topology structure, a data transmission mechanism including a hierarchical transmission protocol and dynamic link dormancy is set; The data transmission mechanism includes a global transmission protocol and a local transmission protocol, both of which adopt a credit-based flow control mechanism; The global transmission protocol is used for high-bandwidth data transmission between the master core and the slave core, the master core and the shared storage, and adopts a "request-response" bidirectional transmission mode; the global link adopts a "data-driven wake-up" mechanism, and when there is no data transmission, the link is in a sleep state, the clock is closed, and the signal remains high impedance; when the master core or the slave core generates a data packet, the link clock and the interface circuit are activated through a wake-up signal, and after the data transmission is completed, the link reenters the sleep state within a preset clock period; The local transmission protocol is used for low-bandwidth data interaction between the slave cores, and adopts a "unicast-broadcast" hybrid transmission mode; when there is no data transmission for a continuous number of clock periods, the link clock is automatically closed and the link enters a sleep state; when a new data packet is generated, the link is quickly activated through a wake-up signal.

9. The RISC-V multi-core architecture based extreme environment path planning method according to claim 8, characterized in that, Further comprising: An energy consumption optimization strategy is set based on the final hybrid interconnection topology structure; The energy consumption optimization strategy comprises a hardware circuit level optimization strategy and a runtime dynamic management strategy; The hardware circuit level optimization strategy comprises: A low-power link driving circuit is set: the driving circuits of the global and local links adopt a CMOS drain open circuit OD structure, instead of a traditional push-pull structure; A low-power network interface is set: a dynamic power consumption gate module is integrated into the slave core network interface, and when the slave core is in an idle state, the data packet analysis and routing circuit inside the network interface is closed, and only the wake-up detection circuit is retained; the master core network interface adopts a "clock gating" strategy, and only the clock is activated during data packet transmission, and the clock is closed when idle; The runtime dynamic management strategy comprises: A link bandwidth dynamic adjustment mechanism is set: the master core dynamically adjusts the global link width through a DVFS instruction, and the local link implements on-demand bandwidth allocation according to the data interaction frequency between the slave cores; A slave core interconnection state dynamic switching mechanism is set: when the algorithm does not require data interaction between the slave cores, the master core sends an interconnection sleep instruction to close the clock and driving circuit of the local mesh link, and only the global star link is retained; when entering a slave core cooperation stage, the master core sends an interconnection wake-up instruction to reactivate the local mesh link.

10. An extreme environment path planning system based on RISCV multicore architecture for performing the method of extreme environment path planning based on RISCV multicore architecture according to any one of claims 1-9, characterized in that, Comprise: A key feature acquisition module, a quantization result acquisition module, an instruction set optimization module, a topology structure optimization module and a path planning module; The key feature acquisition module is configured to run an existing path planning algorithm in a simulation environment and acquire key computing features; The quantization result acquisition module is configured to compare in different complexity scenarios based on the key computing features to obtain quantization results of the key computing features; The instruction set optimization module is configured to optimize an RISCV instruction set based on the quantization results, with the optimization standard being to reduce invalid instruction execution and core operation delay, to obtain an optimized instruction set; The topology structure optimization module is configured to construct a final hybrid interconnection topology structure of a master core-slave core star + local mesh based on the quantization results, with the target being to reduce redundant data transmission and cross-core synchronization overhead; The path planning module is configured to acquire a target task and call the corresponding optimized instruction set on the hybrid interconnection topology structure to complete extreme environment path planning.

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