Chip testing method and device, computer equipment and storage medium

Abstract

The invention discloses a chip testing method and device, computer equipment and a storage medium, and relates to the technical field of data processing, and the method comprises the steps: obtaining the coding information of each to-be-tested module in a plurality of to-be-tested modules corresponding to a to-be-tested chip in a target scene; based on the coding information and association information between the to-be-tested modules, coding the to-be-tested modules to obtain an initial population; updating the initial population based on the fitness score of each primary individual in the initial population to obtain a target population; generating test excitation according to the constraint information of the target population on the original test platform, and obtaining a current test result of the to-be-tested chip based on the test excitation; and if the current test result and the original test result of the test excitation on the original test platform conform to expectations, generating problem positioning information of the to-be-tested chip in the target test scene. The problem of low problem positioning efficiency during chip simulation testing is solved, and the technical effect of improving the problem positioning efficiency is achieved.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and specifically to a chip testing method, apparatus, computer equipment, and storage medium. Background Technology

[0002] In chip verification, functional testing of a chip requires testing on multiple platforms, such as simulation based on simulation tools or virtual machines, and hardware simulation based on specific hardware testing platforms. Simulation can be written and generate relevant simulation test stimuli according to test requirements.

[0003] In simulation, due to limitations in related servers and simulation resources, simulating complex scenarios usually takes a long time, resulting in low simulation efficiency. At the same time, the simulation test cases of the simulation platform depend on the code written by simulation engineers. Due to the different skill levels of engineers, the simulation scenarios that the test stimuli they write can cover also vary.

[0004] In the hardware testing platform, the verification scenarios are all real-world application scenarios, which eliminates the problem of incomplete coverage of verification scenarios due to differences in the experience of verification engineers. However, since the chips under test are all in a fully packaged state, the signals that engineers can capture are very limited. Therefore, debugging methods frequently used in simulation, such as signal tracing, are difficult to apply on the hardware simulation platform, thus affecting the efficiency of engineers in locating problems. At the same time, after engineers locate the initial problem, they need to write test stimuli on the simulation platform for further simulation verification, which greatly reduces the efficiency of problem location and directly affects the chip deployment speed. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a chip testing method, apparatus, computer equipment, and storage medium to solve the problem that low problem localization efficiency directly affects the chip deployment speed during chip simulation testing.

[0006] In a first aspect, embodiments of the present invention provide a chip testing method, the method comprising:

[0007] Obtain the encoding information of each module under test in the target scenario among the multiple modules under test of the chip under test;

[0008] Based on the encoded information and the correlation information between the modules to be tested, the modules to be tested are encoded to obtain the initial population;

[0009] The initial population is updated based on the fitness scores of each first-generation individual in the initial population to obtain the target population;

[0010] Test stimuli are generated based on the constraint information of the target population on the original test platform, and the current test results of the chip under test are obtained based on the test stimuli.

[0011] If the current test results and the test stimulus both meet the expectations of the original test results on the original test platform, then problem location information of the chip under test in the target test scenario will be generated.

[0012] The chip testing method provided in this invention efficiently locates problems by encoding and evaluating the fitness of multiple modules under test in a target scenario, avoiding the efficiency reduction caused by signal capture limitations and test stimulus programming in hardware testing platforms. Furthermore, by utilizing the evolutionary strategies of the initial and target populations, the generation of test stimuli is ensured to be more comprehensive and accurate, improving the efficiency of problem location and thus accelerating chip deployment. Simultaneously, by combining the constraint information of the original testing platform, the accuracy and reliability of the test results are further guaranteed.

[0013] In one possible implementation, the encoding information of each module under test (DUT) among multiple DUT modules corresponding to the chip under test in the target scenario is obtained, including:

[0014] Analyze the testing requirements of the chip under test in the target scenario;

[0015] Based on the testing requirements, multiple modules to be tested for the chip under test were identified.

[0016] Based on the encoding stimuli of relevant elements in the module under test, the encoding information of each module under test is determined.

[0017] In one possible implementation, the modules under test are encoded based on the encoded information and the association information between the modules under test to obtain an initial population, including:

[0018] Obtain the relationship information between the modules under test;

[0019] Based on the correlation information, related modules under test from multiple modules under test are integrated to obtain integrated modules under test and unintegrated modules under test;

[0020] The integrated and unintegrated modules under test are encoded based on the encoded information to obtain the initial population.

[0021] In one possible implementation, the initial population is updated based on the fitness scores of each first-generation individual in the initial population to obtain the target population, including:

[0022] Obtain the resource utilization rate and coverage of the target scenario for each initial individual's corresponding test plan;

[0023] The fitness score of each initial individual is calculated based on resource utilization and coverage.

[0024] The first-generation individuals with fitness scores greater than or equal to the score threshold are used as the parent individuals, and crossover and mutation operations are performed on the parent individuals to generate new offspring individuals.

[0025] The target population is obtained by updating the initial population with the first-generation individuals whose fitness scores are less than the score threshold based on the offspring individuals.

[0026] In one possible implementation, test stimuli are generated based on the constraint information of the target population on the original test platform, and the current test results of the chip under test are obtained based on the test stimuli, including:

[0027] Obtain the test plan corresponding to the target individual in the target population, and adjust the test plan according to the constraint information of the original test platform to obtain the test incentive that meets the requirements of the original test platform;

[0028] Test stimuli are applied to the chip under test, and the response data of the chip under test under the test stimuli are collected;

[0029] The chip under test is evaluated based on the response data to obtain the current test results.

[0030] In one possible implementation, if the current test results and the original test results of the test stimulus on the original test platform both meet expectations, then problem location information of the chip under test in the target test scenario is generated, including:

[0031] Compare the current test results with the target test results of the original test platform;

[0032] If the current test result is the same as the target test result, the converted test stimulus will be tested on the original test platform to obtain the original test result;

[0033] If the original test results are the same as the target test results, then based on the test stimulus and the response data of the chip under test, the problem of the chip under test in the target test scenario is analyzed, and problem location information is generated.

[0034] In one possible implementation, the above method further includes:

[0035] If the current test results and test incentives do not meet expectations in the original test results on the original test platform, then update the scoring threshold;

[0036] The fitness scores of each initial generation individual are recalculated based on the updated scoring threshold. Initial generation individuals with fitness scores higher than the updated scoring threshold are selected and crossover and mutation operations are performed to generate a new target population.

[0037] Secondly, embodiments of the present invention provide a chip testing apparatus, comprising:

[0038] The acquisition module is used to acquire the encoding information of each module under test among multiple modules under test corresponding to the chip under test in the target scenario;

[0039] The encoding module is used to encode the modules under test based on the encoding information and the correlation information between the modules under test, so as to obtain the initial population.

[0040] The update module is used to update the initial population based on the fitness scores of each first-generation individual in the initial population, so as to obtain the target population.

[0041] The excitation module is used to generate test excitations based on the constraint information of the target population on the original test platform, and to obtain the current test results of the chip under test based on the test excitations.

[0042] The testing module is used to generate problem location information for the chip under test in the target test scenario if the current test results and the test stimuli both meet the expectations of the original test results on the original test platform.

[0043] The chip testing apparatus provided in this invention can efficiently locate problems by encoding and evaluating the fitness of multiple modules under test in a target scenario, avoiding the efficiency reduction caused by signal capture limitations and test stimulus programming in hardware testing platforms. Furthermore, by utilizing the evolutionary strategies of the initial and target populations, the generation of test stimuli is ensured to be more comprehensive and accurate, improving the efficiency of problem location and thus accelerating chip deployment. Simultaneously, by combining the constraint information of the original testing platform, the accuracy and reliability of the test results are further guaranteed.

[0044] Thirdly, embodiments of the present invention provide a computer device, including: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the method described in the first aspect or any corresponding embodiment thereof.

[0045] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer instructions that cause a computer to perform the method described in the first aspect or any of its corresponding embodiments. Attached Figure Description

[0046] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0047] Figure 1 This is a schematic flowchart of a chip testing method provided according to an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of population update in the chip testing method provided according to an embodiment of the present invention;

[0049] Figure 3 This is a data flow diagram of a chip testing method provided according to an embodiment of the present invention;

[0050] Figure 4 This is a flowchart illustrating another chip testing method provided according to an embodiment of the present invention;

[0051] Figure 5 This is a structural block diagram of a chip testing apparatus according to an embodiment of the present invention;

[0052] Figure 6 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0054] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0055] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] This embodiment provides a chip testing method. Figure 1 This is a flowchart of a chip testing method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0057] Step 110: Obtain the encoding information of each module under test in the multiple modules under test corresponding to the chip under test in the target scenario.

[0058] The target scenario is preset based on the application environment of the chip under test. The target scenario can reflect the working status and performance requirements of the chip under test in actual applications.

[0059] In one possible implementation, when obtaining the encoding information of each module under test (DUT) among multiple DUTs corresponding to the chip under test in the target scenario, the testing requirements of the chip under test in the target scenario can be analyzed first. Based on the testing requirements, multiple DUTs of the chip under test are determined. Based on the encoding stimuli of relevant elements in the DUTs, the encoding information of each DUT is determined. The relevant elements include input ports, output ports, and DUT nodes in the DUTs; the encoding stimuli of input ports and output ports include platform identifiers, stimuli sequences, and relevant constraints; the encoding stimuli of DUT nodes include stimuli sequences, relevant constraints, and target coverage points.

[0060] As an example, suppose the target scenario is an image processing chip application in an autonomous driving system, where the testing requirements include ensuring high frame rate processing and low power consumption performance. In this scenario, after analyzing the testing requirements, several modules under test (DUT) of the chip are identified, including the image sensor interface module, the image processing engine module, and the output display control module. Based on the testing requirements, the relevant elements of the image sensor interface module are as follows: the input port's coded stimulus includes the platform identifier "ADAS-ImgSen", the stimulus sequence is a simulated image data stream (e.g., resolution 1920x1080@30fps), and related constraints such as a maximum input latency not exceeding 5ms; the output port's coded stimulus includes the platform identifier "ADAS-Proc", the stimulus sequence is the processed image frames, and related constraints such as a power consumption threshold below 100mW; the DUT's coded stimulus includes the stimulus sequence such as a boundary condition test sequence, related constraints such as a coverage target of 98%, and target coverage points such as key nodes in the pixel processing path. Similarly, for the image processing engine module, the input port's encoding stimulus includes the platform identifier "ADAS-ProcIn", the stimulus sequence is noise injection data, and related constraints such as processing error less than 1%; the output port's encoding stimulus includes the platform identifier "ADAS-Disp", the stimulus sequence is the optimized image output, and related constraints such as frame rate stability; the node under test's encoding stimulus includes the stimulus sequence such as parallel processing test, related constraints such as timing constraints, and target coverage points such as the algorithm's core logic points. For the output display control module, the input port's encoding stimulus is based on the platform identifier "ADAS-DispIn", the stimulus sequence is the display drive signal, and related constraints such as synchronization error range; the output port's encoding stimulus corresponds to the platform identifier "ADAS-Screen", the stimulus sequence is the final display output, and related constraints such as color accuracy; the node under test's encoding stimulus includes the stimulus sequence such as the refresh rate test sequence, and related constraints such as coverage point targets and target coverage point signal output stability nodes.

[0061] The chip testing method provided in this invention, by analyzing testing requirements, can accurately identify the key performance indicators of the chip under test in practical applications, thereby significantly improving the targeting and efficiency of testing and reducing redundant testing steps. By using coded stimuli based on relevant elements in the module under test, the generated coded information for each module under test is ensured to be more accurate and complete, helping to comprehensively cover potential fault points of the chip under different operating states.

[0062] Step 120: Based on the encoding information and the correlation information between the modules to be tested, the modules to be tested are encoded to obtain the initial population.

[0063] The correlation information between modules under test (DUTs) includes their logical connections, data transmission paths, and dependencies. Obtaining these correlations ensures accurate simulation of the chip's actual operating environment during testing, enabling more effective detection of potential performance issues or fault points. Furthermore, the accuracy and completeness of this correlation information are crucial for improving testing efficiency, reducing test iterations due to misjudgments or omissions, and accelerating chip development and deployment. In addition, the correlation information can be obtained based on iteration resource constraints and historical data stored in a database.

[0064] In one possible implementation, the modules to be tested are encoded based on the encoding information and the association information between the modules to be tested. When obtaining the initial population, the association information between the modules to be tested can be obtained first. Based on the association information, the related modules to be tested in multiple modules to be tested are integrated to obtain integrated modules to be tested and unintegrated modules to be tested. Based on the encoding information, the integrated modules to be tested and unintegrated modules to be tested are encoded to obtain the initial population.

[0065] Specifically, when acquiring the correlation information between modules under test (DUTs), the logical connections, data transmission paths, and interdependencies between modules can be extracted by parsing the interface definitions and signal transmission paths in the chip design file. Based on this correlation information, DUTs with highly coupled or frequently interacting data are grouped and integrated to form integrated DUTs, simulating collaborative operations in real-world scenarios. Simultaneously, unintegrated DUTs are identified and retained; these modules are highly independent or have minimal interaction. Then, based on the encoding information, corresponding encoding sequences are generated for each integrated and unintegrated DUT, ensuring that the encoding covers potential fault points under different operating conditions. Finally, all encoding sequences are combined into an initial population to facilitate subsequent test optimization and iteration. Furthermore, integrating related modules reduces redundant operations during testing, improves testing efficiency, and maintains accurate simulation of the overall chip behavior.

[0066] Step 130: Update the initial population based on the fitness scores of each first-generation individual in the initial population to obtain the target population.

[0067] As shown above, the initial population is updated based on the fitness scores of each first-generation individual in the initial population, so that selection, crossover and mutation operations can be performed according to the fitness scores to eliminate low-scoring first-generation individuals and introduce new variants, thereby generating the target population.

[0068] In one possible implementation, please refer to Figure 2To obtain the target population, the initial population is updated based on the fitness scores of each first-generation individual. This is achieved by first obtaining the resource utilization rate and coverage of the target scenario for each first-generation individual in the corresponding test scheme. The fitness score of each first-generation individual is then calculated based on the resource utilization rate and coverage. First-generation individuals with fitness scores greater than or equal to the score threshold are designated as parent individuals, and crossover and mutation operations are performed on these parent individuals to generate new offspring individuals. Finally, the first-generation individuals in the initial population with fitness scores less than the score threshold are updated based on the offspring individuals to obtain the target population.

[0069] The fitness value directly affects the determination of whether the current first-generation individual is a potential root cause of the problem. Therefore, a dynamically adjustable fitness function can be constructed based on resource utilization and coverage. That is, the fitness function calculates the fitness of different first-generation individuals based on the assumptions about the first-generation individuals and simulation results, thereby determining whether the current first-generation individual is a potential root cause of the problem. Specifically, this includes:

[0070] By detecting the coverage rate in each iteration, it is determined whether the current population's coverage scenario meets the requirements, thus guiding the next genetic operation; the formula for calculating the coverage rate is:

[0071]

[0072] Among them, S c (x) represents the coverage rate; N represents the total number of coverage points; P(C k |G x ) is used to represent the corresponding initial individual (test module, combined test module) x, for the coverage point C. k The activation probability of the first-generation individual is such that if the activation probability of the first-generation individual for the coverage point is high, then the first-generation individual is more likely to be the root cause of the problem, and vice versa; H(C k ) is used to represent the coverage point C k The rarity of the coverage point is low when the number of times the coverage point is activated is large, meaning it is not scarce. Therefore, the value of the corresponding denominator becomes smaller, and the overall value of the function increases, indicating that the current first-generation individual contributes more to the root cause of the problem, and vice versa. k It is used to represent the association weight between different first-generation individuals. For example, the weight coefficient of the critical path among first-generation individuals is larger, and the weight coefficient of the regular path is smaller; α is used to represent the coverage point contribution rate adjustment coefficient.

[0073] Resource utilization rate: Under the condition of ensuring coverage, the resource utilization rate is the degree of consumption of simulation time, memory, and other resources during constraint testing. The formula for resource utilization rate is:

[0074]

[0075] C r (x) is used to represent resource utilization rate; R x R is used to represent the resource consumption value of the current first-generation individual; max The threshold for allowed resource consumption is used to represent the fitness level. If the current resource consumption value is less than or equal to the threshold, the fitness gradually decreases with increasing resource consumption, thus encouraging the algorithm to search in the low resource consumption region. If the current resource consumption value is greater than the threshold, the fitness will increase sharply according to the characteristics of the exponential function. δ represents the fitness adjustment coefficient; λ1 is the first resource occupancy weight; λ2 is the resource occupancy offset; and λ3 is the second resource occupancy weight.

[0076] Fitness function: Used to score the fitness of the current first-generation individual x. The specific formula is as follows:

[0077]

[0078] Where γ is the resource consumption adjustment coefficient. If a certain first-generation individual contributes less to the coverage, the fitness score V(x) will decrease accordingly. At the same time, if the first-generation individual consumes more resources than the threshold, the fitness score will increase sharply.

[0079] Furthermore, although the fitness of different initial individuals can be scored and calculated, allowing for some dynamic adjustment of the initial individuals and test stimuli, thus introducing a degree of randomness into the iterative process, the adjustment of the initial individuals relies too heavily on simulation results and fitness scores. This dependence can lead to low iteration efficiency and difficulty in expanding the solution space, potentially causing the iteration process to get stuck in local optima. Expanding the solution space by increasing the number of iterations is limited by computational resources and time costs, making unlimited expansion difficult. Therefore, using initial individuals with fitness scores greater than or equal to the scoring threshold as parent individuals, and performing crossover and mutation operations on these parent individuals to generate new child individuals, expands the possible solution space, avoids getting stuck in local optima, and controls the probability of crossover and mutation operations to prevent convergence difficulties due to an excessively large solution space.

[0080] The core function of crossover is that the generated individuals can integrate the advantageous characteristics of their parents, such as efficient stimulus sequences and relatively low resource consumption. During genetic iteration, different parent individuals may each possess one or more advantageous characteristics. Therefore, crossover allows these advantageous characteristics to be combined to generate more advantageous offspring. Simultaneously, crossover enables the rapid propagation of advantageous genes from the parents throughout the population in each iteration, accelerating the algorithm's convergence speed. Furthermore, crossover can generate new combinations of initial-generation individuals in the current population, increasing the probability of finding the global optimum. The formula for crossover is:

[0081] Child=βParent1+(1-β)Parent2

[0082] Where β represents the crossover probability, and it can be dynamically adjusted using the following formula:

[0083]

[0084] Where t represents the current iteration number and T represents the total number of iterations, if V(x) continues to decrease after crossover, it means that the new first-generation individuals generated by the current crossover operation have not improved significantly. Therefore, it is necessary to reduce the probability of crossover of the new parent class in order to dynamically adjust the probability of crossover and avoid the inefficient iterative individuals generated by invalid crossover operations from affecting the overall iteration result.

[0085] While crossover can meet the need for generating new first-generation individuals to some extent, and dynamically adjusted mutation probabilities can avoid the negative impact of ineffective crossover on genetic iteration, the parent class in crossover is still generated based on the encoding method. Therefore, different encoding methods will still have different effects on the algorithm, introducing uncertainty into the entire genetic iteration process. Thus, in addition to crossover, mutation is introduced. The core objective of this operation is to introduce random perturbation to enhance and maintain population diversity. For example, using a Gaussian mutation method based on Gaussian distribution, the genes of the first-generation individuals are randomly modified. This utilizes the probability characteristics of Gaussian distribution to adjust relevant gene values, balancing local search and overall exploration, preventing the first-generation individuals in the population from becoming too homogeneous during genetic iteration. This ensures the solution space of the algorithm while allowing for refined local searches, ensuring the accuracy of the solution results.

[0086] Suppose that a certain gene value of the first generation individual (the first generation individual represents a more accurate hypothesis and configuration of the root cause, i.e., encoded information) is x. i The value obtained after Gaussian mutation is x. i ′ The formula for calculating this variation value is as follows:

[0087] x′ i =x i +Ν(0,σ)

[0088] Here, N(0,σ) is a normally distributed random function with a mean of 0 and a standard deviation of σ. The variation step size is controlled by the value of the standard deviation σ. When σ is small, it can produce subtle perturbations, while a larger σ value can expand the overall solution space and search range. Simultaneously, during the entire solution process, approximately 68% of the mutation values ​​are within (x±σ), and 95% are within (x±2σ). This makes the mutation more inclined to fine-tune near the current solution. When approaching the optimal solution, small-step mutation can accelerate convergence and improve the accuracy of the solution, making it suitable for local optimization. At the same time, the Gaussian distribution still has a probability of causing large jumps in mutation, preserving global exploration capabilities and preventing the algorithm from getting completely trapped in local optima.

[0089] Step 140: Generate test stimuli based on the constraint information of the target population on the original test platform, and obtain the current test results of the chip under test based on the test stimuli.

[0090] The constraint information from the original platform is used to define the generation boundaries of test stimuli, including voltage range, timing constraints, power consumption limits, and signal integrity requirements. This ensures that the stimulus signals operate safely within the chip's physical operating specifications, avoiding overdrive or violations, thereby improving test reliability and coverage. This constraint information can be mapped to specific stimulus parameters, such as pulse width, frequency, and amplitude, to generate effective test scenarios executable on the chip under test, supporting subsequent performance evaluation and fault detection.

[0091] In one possible implementation, when generating test stimuli based on the constraint information of the target population on the original test platform and obtaining the current test result of the chip under test based on the test stimuli, the test plan corresponding to the target individual in the target population can be obtained first, and the test plan can be adjusted according to the constraint information of the original test platform to obtain test stimuli that meet the requirements of the original test platform; the test stimuli are applied to the chip under test, and the response data of the chip under test under the test stimuli are collected; the chip under test is tested and evaluated based on the response data to obtain the current test result.

[0092] Specifically, after obtaining the test plan corresponding to the target individual, the constraint information of the original test platform needs to be parsed, including voltage range, timing constraints, power consumption limits, and signal integrity requirements. The parameters in the test plan are mapped to executable stimulus parameters, such as adjusting the pulse width to meet the minimum pulse width requirement, calibrating the frequency to adapt to clock cycle constraints, and setting the amplitude within a safe voltage threshold, thereby generating test stimuli that conform to physical operating specifications. Then, the test stimuli are applied to the chip under test (DUT) through the test interface, while data acquisition equipment monitors and collects the DUT's response data in real time, including output waveform timing, current and power consumption curves, and signal integrity indicators. Based on the collected response data, a preset evaluation method is applied for analysis, such as comparing the actual output with the expected output, detecting timing violations, voltage overshoot, or power consumption anomalies, and quantifying the failure rate and performance deviation. Finally, the current test results are generated for subsequent optimization iterations or fault diagnosis.

[0093] Step 150: If the current test results and the test stimulus both meet expectations on the original test platform, then generate the problem location information of the chip under test in the target test scenario.

[0094] As shown above, when the current test results and the original test results on the original test platform meet expectations, problem location information of the chip under test in the target test scenario is generated. This helps engineers quickly identify and correct potential defects in subsequent tests. At the same time, a fault database is established by combining historical data to improve the adaptability and diagnostic efficiency of the test plan.

[0095] In one possible implementation, if the current test result and the original test result of the test stimulus on the original test platform both meet expectations, then when generating the problem location information of the chip under test in the target test scenario, the current test result can be compared with the target test result of the original test platform; if the current test result is the same as the target test result, then the converted test stimulus is tested on the original test platform to obtain the original test result; if the original test result is also the same as the target test result, then based on the test stimulus and the response data of the chip under test, the problem of the chip under test in the target test scenario is analyzed, and problem location information is generated.

[0096] As an example, suppose the target test scenario is high-speed serial interface protocol verification, where the test stimulus includes a set of pseudo-random bit sequence (PRBS) patterns at a frequency of 5 GHz. The response data acquisition shows insufficient output eye diagram opening, specifically a rise time exceeding the specification limit by 10%. By comparing the actual waveform with a predefined reference model, the timing violation point is identified as being located at the edge of the data sampling window. Further analysis of the power consumption curve reveals an abnormal dynamic current peak. Combined with signal integrity indicators such as jitter distribution and signal-to-noise ratio, the fault incidence rate is quantified to be 2.5%, with a performance deviation of ±50 ps. Based on this, problem location information is generated, clearly indicating that the problem originates from phase mismatch in the clock recovery circuit, and it is recommended to optimize the PLL feedback loop parameters to correct the defect.

[0097] In one possible implementation, if the current test results and the original test results of the test stimulus on the original test platform both meet expectations, when generating problem location information for the chip under test in the target test scenario, the specific parameters of the test stimulus (such as frequency, voltage amplitude, and signal type) and the collected response data (including output waveform timing, current and power consumption curves, and signal integrity indicators) can be integrated first. A preset fault diagnosis model (e.g., based on a rule engine or machine learning classifier) ​​can then be used to extract features from the data and identify abnormal patterns, such as timing deviations, power consumption peaks, or signal distortion. Secondly, the abnormal data is matched against known defect types in the historical fault database to quantify the probability and scope of the problem. Finally, a structured problem location report is generated, including the problem type, location (e.g., specific module of the chip), root cause analysis suggestions, and optimization measures. The fault database is automatically updated to enhance the adaptability of subsequent tests.

[0098] Furthermore, if the current test results and the test stimuli meet expectations on the original test platform, relevant information from the iterative simulation can be collected and recorded, such as coding rules, iteration count, changes in the weight coefficients of genetic operations, and fitness calculation results in different iterative simulations. This data forms local data, which can help the initialization module form a more reasonable initial population before the iteration begins when problems are reproduced. Simultaneously, based on the collected results, the contribution of each test stimuli to coverage and resource utilization, trends, and high-contribution coding methods can be summarized, facilitating engineers' subsequent learning and experience accumulation. Additionally, test stimuli generated based on the constraint information of the target population on the original test platform can be reverse-engineered and tested on the original platform to ensure the accuracy of the current iteration results.

[0099] For a specific implementation method, please refer to Figure 3 ,include:

[0100] First, the encoding information of the modules and states of interest in the genetic iteration process is determined. Then, based on the encoding information and the local database, different population individuals are generated to obtain the initial population.

[0101] Secondly, based on the fitness calculation function, the fitness score of each individual in the initial generation in the initial population under different assumptions is calculated. Then, based on the fitness calculation results, corresponding genetic operations are performed to obtain the target population and optimize the iteration process.

[0102] Next, based on the constraints of the original test platform and the generated individual codes, the coding method is mapped to generate corresponding test stimuli and perform simulation; at the same time, after the iteration ends, the current test stimuli are reverse-transformed and retested on the original platform to ensure the accuracy of the current iteration results to the greatest extent.

[0103] Furthermore, based on the iteration results, a local database is established to store relevant iteration settings, providing data accumulation for subsequent problem localization and analysis; at the same time, results that engineers care about are also recorded for easy viewing.

[0104] Finally, the fitness score calculation and genetic operations are repeated, and the constraint information of the obtained target population and the original test platform are used to perform incentive mapping to obtain test incentives and perform simulations until the current simulation reaches the maximum number of iterations or reaches the set fitness threshold. Then, the test incentives of the target test platform (current test platform) are reverse-transformed and relevant tests are performed on the original test platform. If the test results meet or are close to expectations, the relevant results will be stored, such as storing the relevant data in a database, such as a fault database.

[0105] The chip testing method provided in this invention efficiently locates problems by encoding and evaluating the fitness of multiple modules under test in a target scenario, avoiding the efficiency reduction caused by signal capture limitations and test stimulus programming in hardware testing platforms. Furthermore, by utilizing the evolutionary strategies of the initial and target populations, the generation of test stimuli is ensured to be more comprehensive and accurate, improving the efficiency of problem location and thus accelerating chip deployment. Simultaneously, by combining the constraint information of the original testing platform, the accuracy and reliability of the test results are further guaranteed.

[0106] Figure 4 A flowchart of another embodiment of the chip testing method of the present invention is shown. Figure 4 As shown, the method includes the following steps:

[0107] Step 410: Obtain the encoding information of each module under test in the multiple modules under test corresponding to the chip under test in the target scenario.

[0108] Please see details Figure 1 Step 110 of the illustrated embodiment will not be described again here.

[0109] Step 420: Based on the encoding information and the correlation information between the modules to be tested, the modules to be tested are encoded to obtain the initial population.

[0110] Please see details Figure 1 Step 120 of the illustrated embodiment will not be described again here.

[0111] Step 430: Update the initial population based on the fitness scores of each first-generation individual in the initial population to obtain the target population.

[0112] Please see details Figure 1 Step 130 of the illustrated embodiment will not be described again here.

[0113] Step 440: Generate test stimuli based on the constraint information of the target population on the original test platform, and obtain the current test results of the chip under test based on the test stimuli.

[0114] Please see details Figure 1 Step 140 of the illustrated embodiment will not be described again here.

[0115] Step 450: If the current test results and the test incentives do not meet expectations in the original test results on the original test platform, then update the scoring threshold.

[0116] Specifically, if the current test results and test stimuli do not meet expectations on the original test platform, the scoring threshold can be quantitatively adjusted based on the fitness score distribution of individuals in the target population when updating the scoring threshold. For example, this can be done by calculating the mean μ and standard deviation of the fitness scores of individuals in the current population. Update the rating threshold to Where k is a preset adjustable coefficient. This can be achieved by dynamically adjusting the value of k or by directly using... The amplitude scaling threshold range allows the selection criteria for individual merits to adapt to the evolutionary state of the population during subsequent iterations, thereby more effectively guiding the population to converge in the direction that meets the testing requirements.

[0117] As an example, suppose that in a certain iteration cycle, the fitness score distribution of the target population shows a mean μ = 0.8 and a standard deviation of With a preset adjustable coefficient k = 1.5, the scoring threshold is updated to 0.8 ± 0.225, which is the range from 0.575 to 1.025. If the population diversity is high... The threshold range can be narrowed by dynamically reducing the adjustable coefficient k to 1.0, thus strengthening the selection of individuals with high fitness; conversely, if the population converges... Then k is increased to 2.0 to expand the exploration space. This quantitative adjustment allows the population update process in step 430 to more accurately eliminate inferior individuals while retaining potential optimization schemes, thereby ensuring that the test stimulus generated in step 440 is more in line with the chip's boundary constraints on the original test platform, improving the coverage and convergence efficiency of the test results.

[0118] In addition, if the current test results and test stimuli do not meet expectations in the original test results on the original test platform, the coding information of each module under test can be updated directly.

[0119] Step 460: Recalculate the fitness score of each first-generation individual based on the updated scoring threshold, select first-generation individuals with fitness scores higher than the updated scoring threshold, and perform crossover and mutation operations to generate a new target population.

[0120] Specifically, based on the updated scoring threshold, the fitness scores of each initial generation individual are recalculated. Initial generation individuals with fitness scores higher than the updated threshold are selected, and crossover and mutation operations are performed to generate a new target population. This can be achieved using crossover and mutation operations from a genetic algorithm, specifically single-point crossover and Gaussian mutation, to introduce random perturbations and maintain population diversity. The crossover operation randomly selects two parent individuals, exchanges some encoded information, and generates offspring individuals. This process ensures that the new target population retains high-fitness individuals while effectively exploring potential optimization schemes, thereby improving the efficiency of subsequent test stimulus generation and accelerating convergence to test results that satisfy chip boundary constraints.

[0121] The chip testing method provided in this invention introduces normally distributed random perturbations by applying crossover and mutation operations of a genetic algorithm to maintain population diversity and explore the optimization space. In the crossover operation, two parent individuals are randomly selected to exchange some coding information to generate offspring individuals, thereby ensuring that the new target population retains individuals with high fitness while effectively improving the efficiency of test stimulus generation and accelerating convergence to test results that meet chip boundary constraints, ultimately achieving an efficient and robust chip testing scheme.

[0122] Figure 5 A schematic diagram of an embodiment of a chip testing apparatus according to the present invention is shown. Figure 5 As shown, the device includes:

[0123] The acquisition module 510 is used to acquire the encoding information of each module under test among multiple modules under test corresponding to the chip under test in the target scenario;

[0124] Encoding module 520 is used to encode the module under test based on the encoding information and the correlation information between the modules under test to obtain the initial population.

[0125] The update module 530 is used to update the initial population based on the fitness scores of each first-generation individual in the initial population to obtain the target population.

[0126] The excitation module 540 is used to generate test excitations based on the constraint information of the target population on the original test platform, and to obtain the current test results of the chip under test based on the test excitations.

[0127] The test module 550 is used to generate problem location information of the chip under test in the target test scenario if the current test results and the test stimuli both meet the expectations of the original test results on the original test platform.

[0128] In one possible implementation, the acquisition module 510 includes:

[0129] The requirements analysis unit is used to analyze the test requirements of the chip under test in the target scenario.

[0130] The test-pending unit is used to determine multiple test modules of the chip under test based on test requirements.

[0131] The module coding unit is used to determine the coding information of each module under test based on the coding stimuli of relevant elements in the module under test.

[0132] In one possible implementation, the encoding module 520 includes:

[0133] The information acquisition unit is used to acquire the correlation information between the modules under test.

[0134] The module integration unit is used to integrate related modules from multiple modules under test based on association information, resulting in integrated modules under test and unintegrated modules under test;

[0135] The population acquisition unit is used to encode the integrated and unintegrated modules in the test module based on the encoding information to obtain the initial population.

[0136] In one possible implementation, the update module 530 includes:

[0137] The data acquisition unit is used to acquire the resource utilization rate and coverage rate of the target scenario for each initial individual's corresponding test plan.

[0138] The fitness scoring unit is used to calculate the fitness score of each initial individual based on resource utilization and coverage.

[0139] Genetic manipulation unit, used to take the first generation individuals with fitness scores greater than or equal to the score threshold as the parent individuals, and to perform crossover and mutation operations on the parent individuals to generate new offspring individuals;

[0140] The population update unit is used to update the initial population of individuals whose fitness scores are less than the score threshold based on offspring individuals, thereby obtaining the target population.

[0141] In one possible implementation, the excitation module 540 includes:

[0142] The test incentive unit is used to obtain the test plan corresponding to the target individual in the target population, and adjust the test plan according to the constraint information of the original test platform to obtain the test incentive that meets the requirements of the original test platform.

[0143] The data acquisition unit is used to apply test stimuli to the chip under test and acquire the response data of the chip under test under the test stimuli.

[0144] The test evaluation unit is used to perform test evaluation on the chip under test based on the response data and obtain the current test results.

[0145] In one possible implementation, the test module 550 includes:

[0146] The result comparison unit is used to compare the current test result with the target test result of the original test platform.

[0147] The incentive testing unit is used to test the transformed test incentive on the original testing platform to obtain the original test result if the current test result is the same as the target test result.

[0148] The problem localization unit is used to analyze the problem of the chip under test in the target test scenario based on the test stimulus and the response data of the chip under test, and generate problem localization information if the original test results are the same as the target test results.

[0149] In one possible implementation, the test module 550 further includes:

[0150] The scoring update unit is used to update the scoring threshold if the current test results and test incentives do not meet expectations on the original test platform.

[0151] The population generation unit is used to recalculate the fitness score of each initial generation individual based on the updated score threshold, select initial generation individuals with fitness scores higher than the updated score threshold, and perform crossover and mutation operations to generate a new target population.

[0152] The chip testing apparatus provided in this invention can efficiently locate problems by encoding and evaluating the fitness of multiple modules under test in a target scenario, avoiding the efficiency reduction caused by signal capture limitations and test stimulus programming in hardware testing platforms. Furthermore, by utilizing the evolutionary strategies of the initial and target populations, the generation of test stimuli is ensured to be more comprehensive and accurate, improving the efficiency of problem location and thus accelerating chip deployment. Simultaneously, by combining the constraint information of the original testing platform, the accuracy and reliability of the test results are further guaranteed.

[0153] For a description of the features in the embodiments corresponding to the chip testing apparatus of this application, please refer to the relevant descriptions in the embodiments corresponding to the chip testing method, which will not be repeated here.

[0154] Embodiments of this application also provide a computer device, such as... Figure 6 As shown, it includes a memory 610 and a processor 620. The memory 610 stores a computer program, and the processor 620 is configured to run the computer program to perform the steps in any of the chip testing method embodiments described above.

[0155] The computer device also includes a communication interface 630 for communicating with other devices or communication networks.

[0156] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the chip testing method embodiments described above when running.

[0157] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0158] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the chip testing method embodiments described above.

[0159] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the chip testing method embodiments described above.

[0160] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for various specific applications, but such implementations should not be considered beyond the scope of this application.

[0161] The foregoing has provided a detailed description of a chip testing method, apparatus, computer device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A chip testing method, characterized in that, Applied to a target testing platform, the method includes: Obtain the encoding information of each module under test in the target scenario among the multiple modules under test of the chip under test; Based on the encoding information and the association information between the modules under test, the modules under test are encoded to obtain an initial population; The initial population is updated based on the fitness scores of each first-generation individual in the initial population to obtain the target population; Test stimuli are generated based on the constraint information of the target population on the original test platform, and the current test results of the chip under test are obtained based on the test stimuli. If the current test result and the test stimulus both meet expectations on the original test platform, then problem location information of the chip under test in the target test scenario is generated.

2. The method according to claim 1, characterized in that, The acquisition of the encoding information of each module under test in the multiple modules under test corresponding to the chip under test in the target scenario includes: Analyze the testing requirements of the chip under test in the target scenario; Based on the aforementioned testing requirements, multiple modules to be tested for the chip under test are identified. Based on the encoding stimuli of relevant elements in the module under test, the encoding information of each module under test is determined.

3. The method according to claim 1, characterized in that, The process of encoding the modules under test based on the encoded information and the association information between the modules under test to obtain an initial population includes: Obtain the association information between the modules under test; Based on the association information, related modules under test from multiple modules under test are integrated to obtain integrated modules under test and unintegrated modules under test; Based on the encoding information, the integrated and unintegrated modules under test in the module under test are encoded to obtain the initial population.

4. The method according to claim 1, characterized in that, The process of updating the initial population based on the fitness scores of each first-generation individual in the initial population to obtain the target population includes: Obtain the resource utilization rate and coverage rate of the target scene for each of the initial individual test schemes; The fitness score of each of the first-generation individuals is calculated based on the resource utilization rate and the coverage rate. The first-generation individuals with fitness scores greater than or equal to the score threshold are used as parent individuals, and crossover and mutation operations are performed on the parent individuals to generate new offspring individuals. The target population is obtained by updating the initial population of individuals whose fitness scores are less than a threshold based on the offspring individuals.

5. The method according to claim 1, characterized in that, The step of generating test stimuli based on the constraint information of the target population on the original test platform, and obtaining the current test result of the chip under test based on the test stimuli, includes: Obtain the test plan corresponding to the target individual in the target population, and adjust the test plan according to the constraint information of the original test platform to obtain test incentives that meet the requirements of the original test platform; The test stimulus is applied to the chip under test, and the response data of the chip under test under the test stimulus is collected. The chip under test is tested and evaluated based on the response data to obtain the current test result.

6. The method according to claim 1, characterized in that, If the current test result and the test stimulus both meet expectations on the original test platform, then problem location information of the chip under test in the target test scenario is generated, including: The current test results are compared with the target test results of the original test platform; If the current test result is the same as the target test result, the transformed test stimulus will be tested on the original test platform to obtain the original test result; If the original test result is the same as the target test result, then based on the test stimulus and the response data of the chip under test, the problem of the chip under test in the target test scenario is analyzed, and the problem location information is generated.

7. The method according to claim 1, characterized in that, The method further includes: If the current test result and the test incentive do not meet expectations on the original test platform, then update the scoring threshold; The fitness scores of each of the first-generation individuals are recalculated based on the updated scoring threshold. First-generation individuals with fitness scores higher than the updated scoring threshold are selected and crossover mutation operations are performed to generate a new target population.

8. A chip testing device, characterized in that, include: The acquisition module is used to acquire the encoding information of each module under test among multiple modules under test corresponding to the chip under test in the target scenario; An encoding module is used to encode the module under test based on the encoding information and the association information between the modules under test to obtain an initial population; An update module is used to update the initial population based on the fitness scores of each first-generation individual in the initial population to obtain the target population. The incentive module is used to generate test incentives based on the constraint information of the target population on the original test platform, and to obtain the current test results of the chip under test based on the test incentives. The testing module is used to generate problem location information of the chip under test in the target testing scenario if the current test result and the original test result of the test stimulus on the original test platform both meet expectations.

9. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the method of any one of claims 1 to 7.

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