Data transmission method and device based on PCIe speed reduction bridge, equipment and storage medium

Abstract

The application relates to a data transmission method and device based on a PCIe speed reduction bridge, equipment and a storage medium, which are applied to the PCIe circuit verification field and include the following steps: initializing a speed reduction bridge module, so that a first PCIe link and a second PCIe link enter a normal operation state and an activated state; a control verification platform end generates to-be-transmitted data, and the to-be-transmitted data is transmitted to a simulation terminal module; the simulation terminal module analyzes the to-be-transmitted data, generates a data link layer package and a transaction layer data package, and performs data checking on the data link layer package and the transaction layer data package respectively; valid data passing the checking is stored in a preset data storage module; the valid data stored in the data storage module is transmitted to a full-speed terminal module and then to an upper computer end. The application has the technical effects that the PCIe link two-end speed mismatch data transmission problem is solved, and the cost of board verification is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of PCIe circuit verification, and in particular to a data transmission method and device based on a PCIe speed reduction bridge, equipment and a storage medium. BACKGROUND

[0002] PCI (Peripheral Component Interconnect, Peripheral Component Interconnect) bus is a parallel, synchronous and high-speed computer local bus standard. With the growth of graphics processing, high-speed storage and other needs, the traditional parallel PCI bus has gradually become a bottleneck in terms of bandwidth, scalability, signal integrity and other aspects. Therefore, as a high-speed serial computer expansion bus standard, PCIe replaces the early PCI parallel bus standard and has a wide development prospect in the field of computers and communications. However, the PCIe protocol is constantly updated and iterated, and the transmission rate is getting faster and faster, which makes the development and verification of the PCIe protocol more and more difficult, especially the development and verification of Gen5 and above rates. PCIe Gen5, the fifth generation of PCIe, has a transmission rate of up to 32GT / s (Giga Transfers per second).

[0003] At present, for 32GT / s PCIe, the code amount of some large chip designs is large and complex, and it runs slowly in the software simulation environment, which cannot simulate the actual working rate of PCIe Gen5, resulting in that the PIPE interface (Physical Interface for PCI Express, PCI Express physical interface) rate of the prototype verification platform does not match the physical layer rate, and the PCIe root complex (Root Complex, RC) and PCIe endpoint device (Endpoint, EP) cannot be directly connected for on-board verification. SUMMARY

[0004] In order to help solve the problem that the large chip design runs slowly in the software simulation environment, cannot simulate the actual working rate of PCIe Gen5, resulting in that the PIPE interface rate of the prototype verification platform does not match the physical layer rate, and the PCIe root complex and PCIe endpoint device cannot be directly connected, the present application provides a data transmission method and device based on a PCIe speed reduction bridge, equipment and a storage medium.

[0005] In a first aspect, the application provides a data transmission method based on a PCIe reduced speed bridge, which adopts the following technical scheme: the method is applied to a data transmission system based on a PCIe reduced speed bridge, the system comprises a verification platform end, a host computer end and a reduced speed bridge module, the reduced speed bridge module comprises a full speed terminal module and an emulation terminal module, the emulation terminal module and the verification platform end comprise a first PCIe link, and the full speed terminal module and the host computer end comprise a second PCIe link; the method comprises:

[0006] initializing the reduced speed bridge module to enable the first PCIe link and the second PCIe link to enter a normal operating state and an activated state;

[0007] controlling the verification platform end to generate to-be-transmitted data and transmit the to-be-transmitted data to the emulation terminal module;

[0008] controlling the emulation terminal module to perform data analysis on the to-be-transmitted data and generate a data link layer packet and a transaction layer data packet;

[0009] controlling the emulation terminal module to perform data verification on the data link layer packet and the transaction layer data packet respectively, and storing valid data corresponding to the data link layer packet and the transaction layer data packet that pass the verification to a preset data storage module;

[0010] transmitting the valid data stored in the data storage module to the full speed terminal module and to the host computer end through a preset PCIe physical layer module.

[0011] In a specific implementation, the emulation terminal module comprises a first flow control module, and the full speed terminal module comprises a second flow control module; the initialization of the reduced speed bridge module to enable the first PCIe link and the second PCIe link to enter a normal operating state and an activated state comprises:

[0012] controlling the emulation terminal module and the full speed terminal module to perform link training on the first PCIe link and the second PCIe link respectively, so that the first PCIe link and the second PCIe link enter a normal operating state;

[0013] controlling the first flow control module and the second flow control module to interact, and determining whether the buffer capacity of the host computer end is greater than a preset value according to the information of the interaction;

[0014] if the buffer capacity of the host computer end is greater than the preset value, controlling the first PCIe link and the second PCIe link to enter an activated state.

[0015] In one specific implementation, after the control of the verification platform end generates the data to be transmitted, and transmits the data to be transmitted to the simulation terminal module, it further includes:

[0016] controlling the simulation terminal module to perform descrambling processing on the data to be transmitted, and generating descrambled transmission data;

[0017] The control of the simulation terminal module on the data to be transmitted includes:

[0018] controlling the simulation terminal module to perform data analysis on the descrambled transmission data.

[0019] In one specific implementation, the transaction layer data packet includes transaction layer data body, transaction layer CRC data and sequence code, and the data link layer packet includes link layer CRC data;

[0020] The control of the simulation terminal module on the data link layer packet and the transaction layer data packet respectively includes:

[0021] controlling the simulation terminal module to perform verification on the transaction layer CRC data and the sequence code, and retaining the transaction layer data body corresponding to the transaction layer data packet that passes the verification;

[0022] controlling the simulation terminal module to perform verification on the link layer CRC data, and retaining the update flow control storage unit credit data corresponding to the data link layer packet that passes the verification;

[0023] setting the transaction layer data body and the update flow control storage unit credit data as valid data, and storing the valid data to a preset data storage module;

[0024] wherein, the update flow control storage unit credit data is generated by the simulation terminal module according to the data link layer packet that passes the verification.

[0025] In one specific implementation, the retaining of the transaction layer data body corresponding to the transaction layer data packet that passes the verification includes:

[0026] if the transaction layer CRC data and the sequence code are correct, controlling the simulation terminal module to perform positive acknowledgement, generating a positive acknowledgement value, and retaining the transaction layer data body corresponding to the transaction layer data packet that passes the verification;

[0027] if the transaction layer CRC data and the sequence code are incorrect, controlling the simulation terminal module to perform negative acknowledgement, and generating a negative acknowledgement value;

[0028] feedback the positive acknowledgement value or the negative acknowledgement value to the verification platform end.

[0029] In one specific implementation, the verification platform end includes a first PIPE serial and conversion module, and the data transmission system of the PCIe reduced speed bridge includes a second PIPE serial and conversion module.

[0030] The module of transmitting the data to be transmitted to the emulation terminal includes:

[0031] The module of transmitting the data to be transmitted to the first PIPE serial and conversion module and generating first converted data includes:

[0032] The module of transmitting the first converted data to the second PIPE serial and conversion module and generating second converted data includes:

[0033] The module of transmitting the second converted data to the emulation terminal includes:

[0034] The module of controlling the emulation terminal to perform data analysis on the data to be transmitted includes:

[0035] The module of controlling the emulation terminal to perform data analysis on the second converted data includes:

[0036] In one specific implementation, the module of transmitting the valid data stored in the data storage module to the full-speed terminal and transmitting the valid data to the host computer end through a preset PCIe physical layer module includes:

[0037] The module of transmitting the valid data in the data storage module to the full-speed terminal and reorganizing the valid data according to the data format requirement of the host computer end and generating reorganized data includes:

[0038] The module of scrambling the reorganized data according to a preset scrambling mode and generating reorganized scrambled data includes:

[0039] The module of transmitting the reorganized scrambled data to the host computer end through a preset PCIe physical layer module includes:

[0040] In a second aspect, the application provides a data transmission device based on a PCIe reduced speed bridge, which adopts the following technical solution: the device is applied to a data transmission system based on a PCIe reduced speed bridge, the system includes a verification platform end, a host computer end and a reduced speed bridge module, the reduced speed bridge module includes a full-speed terminal and an emulation terminal, the emulation terminal and the verification platform end are connected through a first PCIe link, and the full-speed terminal and the host computer end are connected through a second PCIe link; the device includes:

[0041] The system initialization module is configured to initialize the speed reduction bridge module, so that the first PCIe link and the second PCIe link enter a normal operation state and an active state.

[0042] The data generation module is configured to control the verification platform end to generate to-be-transmitted data, and transmit the to-be-transmitted data to the simulation terminal module.

[0043] The data analysis module is configured to control the simulation terminal module to perform data analysis on the to-be-transmitted data, and generate a data link layer packet and a transaction layer data packet.

[0044] The data storage module is configured to control the simulation terminal module to perform data verification on the data link layer packet and the transaction layer data packet respectively, and store valid data corresponding to the data link layer packet and the transaction layer data packet that pass the verification to a preset data storage module.

[0045] The data transmission module is configured to transmit the valid data stored in the data storage module to a full-speed terminal module, and transmit the valid data to an upper computer end through a preset PCIe physical layer module.

[0046] In a third aspect, the present application provides a computer device, which adopts the following technical solution: comprising a memory and a processor, the memory stores a computer program capable of being loaded and executed by the processor to perform any of the above data transmission methods based on the PCIe speed reduction bridge.

[0047] In a fourth aspect, the present application provides a computer readable storage medium, which adopts the following technical solution: storing a computer program capable of being loaded and executed by the processor to perform any of the above data transmission methods based on the PCIe speed reduction bridge.

[0048] In summary, the present application has the following beneficial technical effects:

[0049] Through the design of the speed reduction bridge, that is, through the design of the full-speed terminal module and the simulation terminal module, efficient and accurate transmission of data between the verification platform and the commercial PC end can be achieved under the condition of unmatched speed, the PCIe root complex (PCIe RC) and the PCIe endpoint device (PCIe EP) can be directly connected through the speed reduction bridge, and the board verification can be achieved. At the same time, through the design of the speed reduction bridge, the use of expensive third-party verification systems can be avoided, thereby reducing the verification cost. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 is a flowchart of the data transmission method based on the PCIe speed reduction bridge in the embodiments of the present application;

[0051] Figure 2is a framework diagram of a data transmission system based on a PCIe speed reduction bridge in embodiments of the present application;

[0052] Figure 3 is a schematic diagram of a data transmission device based on a PCIe speed reduction bridge in embodiments of the present application;

[0053] Figure 4 is a schematic diagram for embodying a computer device in embodiments of the present application.

[0054] Reference signs: 301, system initialization module; 302, data generation module; 303, data analysis module; 304, data storage module; 305, data transmission module. DETAILED DESCRIPTION

[0055] The following will be described in detail in combination with Figures 1-4 The present application is further described in detail.

[0056] Embodiments of the present application disclose a data transmission method based on a PCIe speed reduction bridge. The data transmission method can solve the situation that the rates of two ends of a PCIe link do not match, and can avoid using an expensive third-party verification system, thereby reducing verification cost.

[0057] The PCI (Peripheral Component Interconnect, Peripheral Component Interconnect) bus is a parallel, synchronous, high-speed computer local bus standard. With the growth of the demand for graphics processing, high-speed storage, etc., the traditional parallel PCI bus has gradually become a bottleneck in terms of bandwidth, scalability, signal integrity, etc. Therefore, as a high-speed serial computer expansion bus standard, PCIe replaces the early PCI parallel bus standard and has a wide development prospect in the field of computers and communications. However, the PCIe protocol is constantly updated and iterated, and the transmission rate is getting faster and faster, which makes the development and verification of the PCIe protocol more and more difficult, especially the development and verification of Gen5 and above rates. PCIe Gen5, i.e., the fifth generation of PCIe, has a transmission rate of 32 GT / s (Giga Transfers per second).

[0058] Currently, for PCIe of 32GT / s, the code amount of some large chip designs is huge and complex, and it runs slowly in a software simulation environment, cannot simulate the actual working rate of PCIe Gen5, causes the rate of the prototype verification platform PIPE interface (Physical Interface for PCI Express, PCI Express physical interface) to be unmatched with the rate of the physical layer, the PCIe root complex (Root Complex, RC) and the PCIe endpoint device (Endpoint, EP) cannot be directly connected, and on-board verification is performed. There are independent third-party on-board verification systems on the market that can directly perform on-board verification. However, the existing systems are generally expensive, which increases the verification cost of the company. Therefore, in order to help solve the problem of rate mismatch at both ends of the link and reduce the verification cost, the application provides a data transmission method based on a PCIe speed reduction bridge.

[0059] Reference Figure 1 The method comprises the following steps:

[0060] S10, the speed reduction bridge module is initialized to make the first PCIe link and the second PCIe link enter a normal operating state and enter an active state.

[0061] Specifically, the data transmission method based on the PCIe speed reduction bridge is applied to a data transmission system based on the PCIe speed reduction bridge. The system includes a verification platform end, a host computer end, and a speed reduction bridge logic platform part. The verification platform end generally includes a DUT (device under test). The host computer end can be a commercial PC, a PCIe endpoint device (PCIe EP), and the like. The PCIe EP can be a graphics card, a network card, and the like. The speed reduction bridge logic platform part mainly includes a speed reduction bridge module, which includes a full-speed terminal module, a simulation terminal module, and a data storage module. The full-speed terminal module is connected with the host computer end, such as a commercial PC, and the like. The two are connected by a PCIe link, which is the real rate of PCIe. The simulation terminal module and the verification platform end are also connected by a PCIe link. The PCIe link between the two is not the real rate of PCIe, but the simulation rate, which is generally much smaller than the real rate of PCIe.

[0062] Generally, the PCIe link and the data link in the speed reduction bridge module need to enter a normal working state before normal data transmission can be performed. Therefore, before data transmission, the speed reduction bridge module needs to be initialized to make the PCIe link enter a normal working state. Specifically, the simulation terminal module includes a first flow control module and a first link training module, and the full-speed terminal module includes a second flow control module and a second link training module.

[0063] Firstly, the simulation terminal module and the full-speed terminal module are controlled to perform link training on the first PCIe link and the second PCIe link respectively, so that the first PCIe link and the second PCIe link enter a normal operation state; the specific execution manner can be that the link training module in the simulation terminal module and the link training module in the full-speed terminal module perform training on the corresponding first PCIe link and second PCIe link respectively, so that the two PCIe links enter a normal operation state, that is, the LTSSM (link training state) of the two PCIe links enters an L0 state (the L0 state is also a normal operation state).

[0064] After that, the first flow control module and the second flow control module are controlled to interact, and whether the buffer capacity of the host computer end is greater than a preset value is judged according to the information of the interaction. The full-speed terminal module and the simulation terminal module of the speed-reduced bridge module are provided with flow control modules (Flow Control modules), and the flow control modules ensure reliable data transmission between the sending end and the receiving end through a credit mechanism to prevent overflow of the receiving buffer. During initialization, the initial synchronization of the credit value is completed through the InitFC1 (receiving end sending credit capacity) and InitFC2 (sending end confirmation) DLLP packets, and a basis is established for data transmission. If the buffer capacity of the host computer end (that is, the data receiving end) is greater than the preset value, that is, the buffer capacity of the receiving end can receive the data this time, the PCIe links on both sides enter an active state and can perform subsequent data transmission.

[0065] S20, the verification platform end is controlled to generate to-be-transmitted data, and the to-be-transmitted data is transmitted to the simulation terminal module.

[0066] Specifically, after the two PCIe links enter a normal operation state (L0 state) and enter an active state, a normal data transmission process can be started. During data transmission, the verification platform end (such as a DUT) is first controlled to generate a to-be-transmitted data, and the to-be-transmitted data is transmitted to the simulation terminal module part in the speed-reduced bridge logic platform, and the data is processed accordingly before being transmitted to the host computer end.

[0067] S30, the simulation terminal module is controlled to perform data analysis on the to-be-transmitted data, and generate a data link layer packet and a transaction layer data packet.

[0068] Specifically, the originally generated data is a comprehensive data containing multiple functions or multiple types of data. The built-in analysis module is used to analyze and process the original data to be transmitted, and the original data to be transmitted is analyzed into different parts for different processing to ensure that the data subject to be transmitted can be efficiently and accurately transmitted to the data receiving end. After data analysis and processing, the data link layer package (DLLP package) and the transaction layer data package (TLP package) are generated. The TLP package data is generated by the transaction layer and is used to carry the actual data, i.e., the subject of the data to be transmitted. The DLLP package data is generated by the data link layer and is mainly used for data link management, etc., and will manage flow control, etc.

[0069] S40, the control emulation terminal module respectively analyzes the data link layer package and the transaction layer data package, and stores the valid data corresponding to the data link layer package and the transaction layer data package that passes the data check to the preset data storage module.

[0070] Specifically, the transaction layer data package and the data link layer package obtained after analysis are subjected to data check to ensure that the data has been transmitted and received in the emulation terminal module, and to check whether the data transmission is mis-transmitted or missed, etc., to ensure the accuracy of the data transmission while ensuring the efficient transmission of the data. The corresponding valid data in the DLLP package and the TLP package that passes the check is stored in the preset data storage module.

[0071] S50, the valid data stored in the data storage module is transmitted to the full-speed terminal module and transmitted to the host computer end through the preset PCIe physical layer module.

[0072] Specifically, the data to be transmitted is stored in the data storage module after being processed by the data processing inside the emulation terminal module. After the data to be transmitted stored in the storage module is transmitted to the full-speed terminal module for processing, it is transmitted to the host computer end, such as a commercial PC end, through the PCIe physical layer module, thereby realizing the complete data transmission process.

[0073] Specifically, the valid data in the data storage module is first transmitted to the full-speed terminal module, and is reorganized by the built-in packet assembly module in the full-speed terminal module according to the data format requirement of the host computer end, and reorganized data is generated. Then, the reorganized data is scrambled according to a preset scrambling manner, and reorganized scrambled data is generated. Considering that the communication link will be in an idle state for a long time when the system does not transmit data, which will cause the entire link to be unstable and susceptible to interference, the scrambling processing makes it possible to have interference data transmission when the system does not transmit data, and at this time, the entire link can reduce the possibility of being interfered. In addition, the scrambling processing can improve the anti-interference ability of the data, reduce the burst error probability, improve the overall fault tolerance, and improve the channel adaptability and transmission robustness. Finally, the reorganized scrambled data is transmitted to the host computer end through the preset PCIe physical layer module. The PCIe physical layer module, also known as the PCIe PHY module, is a physical layer integrated circuit in the PCIe interface, which can convert the received PCIE physical layer data into a PIPE interface, and convert the PIPE interface data to be sent into serial data through the module.

[0074] It should be noted that the data transmission based on the PCIe link is bidirectional. After the data is generated at the DUT end and transmitted to the commercial PC end through the speed reduction bridge, the commercial PC end will also correspondingly return a data, realizing mutual transmission of data. Similarly, the host computer end can also generate new data and transmit it to the DUT end through the same data transmission manner. For example, after the commercial PC end generates data, the data is transmitted to the full-speed terminal module through the PCIe PHY module. The full-speed terminal module processes and verifies the data, and stores the data that passes the verification in the data storage module. Then, the data in the data storage module is transmitted to the simulation terminal module. The built-in packet assembly module in the simulation terminal module reorganizes the received data according to the data format requirement of the DUT end, and then sends the data to the DUT end after scrambling processing. After the DUT end receives the data, it returns a data to the commercial PC end, realizing mutual transmission of data.

[0075] In the scheme of the present application, through the design of the speed reduction bridge, that is, through the design of the full-speed terminal module and the simulation terminal module, efficient and accurate transmission of data between the verification platform and the commercial PC end can be realized under the condition of speed mismatch, and the PCIe root complex (PCIe RC) and the PCIe endpoint device (PCIe EP) can be directly connected through the speed reduction bridge, realizing on-board verification. At the same time, through the design of the speed reduction bridge, the use of expensive third-party verification systems can be avoided, thereby reducing the verification cost.

[0076] In one embodiment, considering that the scrambled data will affect the accuracy of the data, therefore, after generating the to-be-transmitted data at the control verification platform end and transmitting the to-be-transmitted data to the simulation terminal module, the following steps can also be performed:

[0077] The control simulation terminal module performs descrambling processing on the to-be-transmitted data and generates descrambled transmission data. The control simulation terminal module performs data analysis on the descrambled transmission data.

[0078] In the scheme of the present application, considering that the data link does not transmit data, that is, empty transmission will reduce the stability of the entire communication link and affect the accuracy of data transmission, therefore, the data is usually scrambled before transmission, so that the entire link can reduce the possibility of being disturbed and improve the channel adaptability and transmission robustness. Therefore, before the data is checked and processed during data transmission, the data needs to be descrambled first to avoid the influence of the interference data added in advance on the accuracy of the real transmission data.

[0079] In one embodiment, the transaction layer data packet includes transaction layer data body, transaction layer CRC data and sequence code, the data link layer packet includes update flow control storage unit credit data and link layer CRC data; the control simulation terminal module respectively performs data checking on the data link layer packet and the transaction layer data packet, and stores the valid data corresponding to the data link layer packet and the transaction layer data packet that pass the checking to the preset data storage module.

[0080] Firstly, the control simulation terminal module checks the transaction layer CRC data and the sequence code, and retains the transaction layer data body corresponding to the transaction layer data packet that passes the checking. Specifically, the simulation terminal module is internally provided with a TLP checking module (TLP Error Check module), which checks the TLP sequence code (Seq_Num) and the CRC check code of the TLP packet. If the transaction layer CRC data and the sequence code are checked correctly, the control simulation terminal module performs positive acknowledgement, generates a positive acknowledgement value, and retains the transaction layer data body corresponding to the transaction layer data packet that passes the checking, which is the data without the header, the tail and the CRC check. If the transaction layer CRC data and the sequence code are not checked correctly, the control simulation terminal module performs negative acknowledgement and generates a negative acknowledgement value; the positive acknowledgement value or the negative acknowledgement value is fed back to the verification platform end.

[0081] The sequence code check is to check whether the data transmission is correct and whether the data transmission is in the preset data sequence. If the data transmission is correct, an ACK response is sent. If there is a missing transmission, the check module will send a NAK response. CRC data check (Cyclic Redundancy Check) is an algorithm for generating a short fixed bit check code based on network data packets or computer files. It is mainly used to detect or check errors that may occur after data transmission or storage. If the CRC data after data transmission is consistent with the CRC data calculated before data transmission, the data is correct, and an ACK response is generated. If the two CRC data are inconsistent, there may be a problem in the data transmission process, and a NAK response is sent, and the problematic data is discarded.

[0082] The response is an ACK / NAK response. When the data check is passed, an ACK response is sent (positive response), and an ACK response value is generated. When the data check fails, a NAK response is sent (negative response), and a NAK response value is generated. The ACK / NAK response module is provided in the simulation terminal module. According to the ACK response value or the NAK response value, the corresponding response data packet is generated and transmitted to the DUT end. Considering that data processing and transmission require a certain amount of time during data transmission, the system may mistakenly think that the data transmission is incorrect or that no data has been received, and thus a warning process is performed. Through the response mechanism, a flag can be given to the data sending end to indicate that the data has been transmitted, avoiding system errors and improving data transmission efficiency.

[0083] Then, the simulation terminal module checks the link layer CRC data and retains the update flow control storage unit credit data corresponding to the data link layer packet that passes the check. The CRC data check of the DLLP packet is the same as that of the TLP packet. If the CRC data check fails, the corresponding DLLP packet is discarded. If the CRC check passes, the DLLP packet data is transmitted to the flow control module built-in the simulation terminal module. The flow control module generates update flow control storage unit credit data (UpdateFC) according to the retained DLLP packet. Finally, the transaction layer data body and the update flow control storage unit credit data are set as valid data, and the valid data is stored in the preset data storage module.

[0084] In the scheme, the accuracy of data transmission is ensured by checking and responding mechanism, and the accuracy of data transmission is verified by sequence code and CRC check during data transmission. In addition, the ACK response or NAK response is transmitted to the data sending end through the setting of the response mechanism to inform the data transmission state, so as to avoid system error caused by long time non-response of the system.

[0085] In one embodiment, the verification platform end includes a first PIPE string and conversion module, and the data transmission system of the PCIe speed reduction bridge includes a second PIPE string and conversion module; the mode of transmitting the to-be-transmitted data to the emulation terminal module can be specifically implemented as:

[0086] First, the to-be-transmitted data is transmitted to the first PIPE string and conversion module, and the first conversion data is generated; then, the first conversion data is transmitted to the second PIPE string and conversion module, and the second conversion data is generated; and then the second conversion data is transmitted to the emulation terminal module. The control emulation terminal module performs data analysis on the to-be-transmitted data, including: controlling the emulation terminal module to perform data analysis on the second conversion data.

[0087] The PIPE string and conversion module in the scheme is mainly used to solve the problem that the number of PIPE data parallel transmission data lines is huge, it is difficult to achieve consistent delay, and the wiring is complex. The parallel sending end of the PIPE string and conversion module on the speed reduction bridge logic platform is connected to the sending end of the PIPE data of the speed reduction bridge module, the parallel receiving end of the PIPE string and conversion module on the speed reduction bridge logic platform is connected to the receiving end of the PIPE data of the speed reduction bridge module, the serial sending end of the PIPE string and conversion module on the speed reduction bridge logic platform is connected to the serial receiving end of the PIPE string and conversion module on the verification platform, and the serial receiving end of the PIPE string and conversion module on the speed reduction bridge logic platform is connected to the serial sending end of the PIPE string and conversion module on the verification platform.

[0088] Reference Figure 2, a complete system framework diagram based on the PCIe speed reduction bridge of the present application. The system includes three parts, including a verification platform, a speed reduction bridge logic platform and a commercial PC / endpoint device. The verification platform mainly includes a DUT and a first PIPE serial-parallel conversion module. The parallel sending end of the PIPE serial-parallel conversion module on the verification platform receives the sending part of the DUT PIPE data, the parallel receiving end of the PIPE serial-parallel conversion module on the verification platform receives the receiving part of the DUT PIPE data, the serial sending end of the PIPE serial-parallel conversion module on the verification platform receives the serial receiving end of the PIPE serial-parallel conversion module on the speed reduction bridge logic platform, and the serial receiving end of the PIPE serial-parallel conversion module on the verification platform receives the serial sending end of the PIPE serial-parallel conversion module on the speed reduction bridge logic platform. The DUT is a PCIe module to be verified, and the DUT working mode can be PCIe Ep (Endpoint, PCIe endpoint device) or PCIe RC (Root Complex, PCIe root complex). The DUT supports any combination of Gen1-Gen5 (speed 2.5GT / s-32GT / s) and 1Lane-16Lane (1 channel-16 channel).

[0089] The speed reduction bridge logic platform mainly includes a speed reduction bridge module, a second PIPE serial-parallel conversion module, a mode configuration module, a PCIe PHY module and a PCIe hardware device. The PCIe hardware device is mainly responsible for the PCIE physical interface between the commercial PC / endpoint device and the PCIE PHY module. The PCIE PHY module converts the received PCIE physical layer data into a PIPE interface, and converts the PIPE interface data to be sent into serial data through the module. The mode configuration module is mainly used to configure the speed reduction bridge related parameters. When the DUT is Ep, the speed reduction bridge working mode is configured as Ep; when the DUT is RC, the working mode is configured as RC; the speed reduction bridge SimSpeed part PCIE mode, working speed and PCIE Lane channel number are configured. The PIPE serial-parallel conversion module and the PIPE serial-parallel conversion module in the verification platform have the same function, which aims to solve the problem that the number of PIPE data parallel transmission data lines is huge, it is difficult to achieve consistent delay, and the wiring is complex.

[0090] The speed reduction bridge module includes a simulation terminal module (Simspeed), a full-speed terminal module (Fullspeed) and a data storage module. The data storage module is mainly used for storing data to be transmitted. The simulation terminal module and the full-speed terminal module have the same internal structure, and are internally provided with a link training module, a descrambling module, a scrambling module, a data analysis module, a TLP checking module, a DLLP checking module, an ACK / NAK response module, a flow control module and a packet assembly module. Before data transmission starts, the link training modules of the full-speed terminal and the simulation terminal will train the respective PCIe links, so that the PCIe links on both sides enter a normal operating state (L0 state). Then, the control flow control modules on both sides exchange information, send and receive InitFC packets, and judge the buffer capacity of the data receiving end. When the buffer capacity can receive data, the state is jumped to make the PCIe links on both sides enter an active state and can normally transmit data.

[0091] After initialization and state jumping are completed, the PCIe link can normally transmit data. The data sending end can be the DUT end or the commercial PC end, and then generates data to be transmitted. If the data sending end is the DUT end, the data to be transmitted is transmitted to the simulation terminal module through twice PIPE serial-parallel conversion module data conversion; if the data sending end is the commercial PC end, the data to be transmitted is transmitted to the full-speed terminal module through the PCIe hardware and the PCIe PHY module. Then, the data to be transmitted is first descrambled, and then transmitted to the data analysis module for data analysis to obtain a TLP packet (transaction layer data packet) and a DLLP packet (data link layer packet). The TLP checking module checks the sequence code and CRC data of the TLP packet, and generates an ACK response and a NAK response accordingly, and feeds back the ACK response value or the NAK response value to the data sending end. The data body of the TLP packet that passes the check is stored in the data storage module after the header, the tail and the CRC check data are removed. The DLLP checking module checks the CRC data of the DLLP packet. If the data passes the check, the data is transmitted to the flow control module, the flow control module updates and generates an update flow control storage unit credit data (UpdateFC), and the UpdateFC is also stored in the data storage module. If the check fails, the corresponding DLLP packet is discarded.

[0092] Afterwards, the data in the data storage module is transmitted to the side corresponding to the data receiving end. For example, if the data sending end is the DUT end, the data is processed in the Simspeed side, and then the data in the storage module is transmitted to the Fullspeed side. If the data sending end is the commercial PC end, the data is processed in the Fullspeed side, and then the data in the storage module is transmitted to the Simspeed side. The built-in packet assembling module reassembles the data according to the requirements of the data receiving end, and then transmits the data to the data receiving end after scrambling processing. After receiving a data, the data receiving end will simultaneously return a data to the data sending end, so as to realize the mutual transmission of data.

[0093] The commercial PC / PCIE Endpoint device is used for data transmission with the DUT to be verified. When the DUT to be verified is an Endpoint, the commercial PC transmits data with the DUT through the speed reduction bridge module, and the PCIE supported by the commercial PC meets Gen1x1Lane; when the DUT to be verified is a Root Complex, the PCIE Endpoint device transmits data with the DUT through the speed reduction bridge module, and the PCIE Endpoint device can be a graphics card, a network card, etc., and the PCIE supported by the PCIE Endpoint device meets Gen1x1Lane.

[0094] Figure 1 The flowchart of the data transmission method based on the PCIe speed reduction bridge in one embodiment is shown. It should be understood that, although the steps in the flowchart are displayed in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows; unless explicitly stated in this article, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences; and Figure 1 at least part of the steps in the flowchart can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with other steps or sub-steps or stages of other steps. Figure 1

[0095] Based on the above method, the embodiment of the application further discloses a data transmission device based on a PCIe speed reduction bridge.

[0096] Referring to Figure 3 , the device includes the following modules:

[0097] The system initialization module 301 is configured to initialize the speed reduction bridge module, so that the first PCIe link and the second PCIe link enter a normal operating state and an active state.​

[0098] The data generation module 302 is configured to control the verification platform end to generate to-be-transmitted data, and transmit the to-be-transmitted data to the simulation terminal module.

[0099] The data analysis module 303 is configured to control the simulation terminal module to perform data analysis on the to-be-transmitted data, and generate a data link layer packet and a transaction layer data packet.

[0100] The data storage module 304 is configured to control the simulation terminal module to perform data verification on the data link layer packet and the transaction layer data packet respectively, and store valid data corresponding to the data link layer packet and the transaction layer data packet that pass the verification to a preset data storage module.

[0101] The data transmission module 305 is configured to transmit the valid data stored in the data storage module to the full-speed terminal module, and transmit the valid data to the host computer end through a preset PCIe physical layer module.

[0102] In an embodiment, the system initialization module 301 is specifically configured to control the simulation terminal module and the full-speed terminal module to perform link training on the first PCIe link and the second PCIe link respectively, so that the first PCIe link and the second PCIe link enter a normal operating state; control the first flow control module and the second flow control module to interact, and determine whether the buffer capacity of the host computer end is greater than a preset value according to the information of the interaction; if the buffer capacity of the host computer end is greater than the preset value, control the first PCIe link and the second PCIe link to enter an activated state.

[0103] In an embodiment, the data generation module 302 is further configured to control the simulation terminal module to perform descrambling processing on the to-be-transmitted data, and generate descrambled transmission data; and control the simulation terminal module to perform data analysis on the to-be-transmitted data includes: control the simulation terminal module to perform data analysis on the descrambled transmission data.

[0104] In an embodiment, the data storage module 304 is specifically configured to control the simulation terminal module to perform verification on transaction layer CRC data and sequence codes, and retain a transaction layer data body corresponding to a transaction layer data packet that passes the verification; control the simulation terminal module to perform verification on link layer CRC data, and retain updated flow control storage unit credit data corresponding to a data link layer packet that passes the verification; set the transaction layer data body and the updated flow control storage unit credit data as valid data, and store the valid data to a preset data storage module; wherein the updated flow control storage unit credit data is generated by the simulation terminal module according to the data link layer packet that passes the verification and is retained.

[0105] In one embodiment, the data storage module 304 is specifically configured to control the emulation terminal module to perform positive acknowledgement if the transaction layer CRC data and the sequence code pass the check, generate a positive acknowledgement value, and reserve the transaction layer data subject corresponding to the transaction layer data packet that passes the check; control the emulation terminal module to perform negative acknowledgement if the transaction layer CRC data and the sequence code do not pass the check, and generate a negative acknowledgement value; and feed back the positive acknowledgement value or the negative acknowledgement value to the verification platform end.

[0106] In one embodiment, the data generation module 302 is specifically configured to transmit the to-be-transmitted data to the first PIPE string and conversion module, and generate first conversion data; transmit the first conversion data to the second PIPE string and conversion module, and generate second conversion data; transmit the second conversion data to the emulation terminal module; and control the emulation terminal module to perform data analysis on the to-be-transmitted data, including controlling the emulation terminal module to perform data analysis on the second conversion data.

[0107] In one embodiment, the data transmission module 305 is specifically configured to transmit the valid data in the data storage module to the full-speed terminal module, reorganize the data according to the data format requirement of the host computer end, and generate reorganized data; scramble the reorganized data according to a preset scrambling mode, and generate scrambled reorganized data; and transmit the scrambled reorganized data to the host computer end through the preset PCIe physical layer module.

[0108] The PCIe speed reduction bridge-based data transmission device provided in the embodiments of the present application can be applied to the PCIe speed reduction bridge-based data transmission method provided in the above-described embodiments, and the related details are referred to the above-described method embodiments, which are similar in implementation principle and technical effects, and will not be described herein again.

[0109] It should be noted that the PCIe speed reduction bridge-based data transmission device provided in the embodiments of the present application is only exemplified by the division of the above-described functional modules / functional units during data transmission, and in actual application, the above-described functions can be completed by different functional modules / functional units according to needs, that is, the internal structure of the PCIe speed reduction bridge-based data transmission device is divided into different functional modules / functional units to complete all or part of the above-described functions. In addition, the implementation manner of the PCIe speed reduction bridge-based data transmission method provided in the above-described method embodiments belongs to the same concept as the implementation manner of the PCIe speed reduction bridge-based data transmission device provided in the present embodiment, and the specific implementation process of the PCIe speed reduction bridge-based data transmission device provided in the present embodiment is described in detail in the above-described method embodiments, which will not be described herein again.

[0110] The embodiments of the present application also disclose a computer device.

[0111] Specifically, as shown in FIG. 6, the computer device comprises a PCIe speed reduction bridge-based data transmission device 600. Figure 4As shown, the computer device can be a desktop computer, a notebook computer, a palm computer, a cloud server, and the like. The computer device can include, but is not limited to, a processor and a memory. The processor and the memory can be connected through a bus or other means. The processor can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processing units (GPU), embedded neural-network processing units (NPU) or other dedicated deep learning co-processors, discrete gate or transistor logic devices, discrete hardware components, or combinations thereof.

[0112] The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs and modules, such as program instructions / modules corresponding to the methods in the above embodiments. The processor executes various functions and data processing of the processor by running the non-transitory software programs, instructions and modules stored in the memory, that is, implements the methods in the above method embodiments. The memory can include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application required by a function; the data storage area can store data created by the processor and the like. In addition, the memory can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory remotely arranged with respect to the processor, and these remote memories can be connected to the processor through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0113] The embodiments of the present application also disclose a computer-readable storage medium.

[0114] Specifically, the computer readable storage medium is configured to store a computer program, and the computer program is configured to be executed by the processor to implement the method in the above method embodiments. Those skilled in the art can understand that all or part of the processes in the above method embodiments of the present application can be completed by a computer program to instruct related hardware, and the program can be stored in a computer readable storage medium. When the program is executed, the program can include the processes of the above method embodiments. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc. The storage medium can also include a combination of the above types of memories.

[0115] The specific embodiments are only an explanation of the present application, and are not a limitation of the present application. Those skilled in the art can make modifications to the embodiments without creative contributions, according to the needs after reading the specification, and as long as the modifications are within the scope of the claims of the present application, they are protected by the patent law.

Claims

1. A data transmission method based on a PCIe speed reduction bridge, characterized in that: The method is applied to a data transmission system based on a PCIe speed-reduction bridge. The system includes a verification platform, a host computer, and a speed-reduction bridge module. The speed-reduction bridge module includes a full-speed terminal module and a simulation terminal module. A first PCIe link connects the simulation terminal module to the verification platform, and a second PCIe link connects the full-speed terminal module to the host computer. The method includes: The speed reduction bridge module is initialized to enable the first PCIe link and the second PCIe link to enter normal operation and activation state. The verification platform is controlled to generate data to be transmitted and then transmit the data to the simulation terminal module. The simulation terminal module is controlled to parse the data to be transmitted and generate data link layer packets and transaction layer data packets. The simulation terminal module is controlled to perform data verification on the data link layer packet and the transaction layer data packet respectively, and the valid data corresponding to the verified data link layer packet and transaction layer data packet is stored in the preset data storage module; The valid data stored in the data storage module is transmitted to the full-speed terminal module, and then transmitted to the host computer through the preset PCIe physical layer module; The simulation terminal module includes a first flow control module, and the full-speed terminal module includes a second flow control module; the initialization of the speed reduction bridge module to enable the first PCIe link and the second PCIe link to enter normal operation and activation includes: The simulation terminal module and the full-speed terminal module are controlled to perform link training on the first PCIe link and the second PCIe link respectively, so that the first PCIe link and the second PCIe link enter the normal operation state. The system controls the interaction between the first flow control module and the second flow control module, and determines whether the buffer capacity of the host computer is greater than a preset value based on the information exchanged. If the buffer capacity of the host computer is greater than a preset value, the first PCIe link and the second PCIe link are controlled to enter the active state.

2. The PCIe reduced-rate bridge based data transfer method of claim 1, wherein: After the verification platform generates the data to be transmitted and transmits the data to the simulation terminal module, the method further includes: The simulation terminal module is controlled to descramble the data to be transmitted and generate descrambled transmission data; The process of controlling the simulation terminal module to parse the data to be transmitted includes: The simulation terminal module is controlled to parse the descrambled transmission data.

3. The PCIe reduced-rate bridge based data transfer method of claim 1, wherein: The transaction layer data packet includes a transaction layer data body, transaction layer CRC data, and a sequence code; the data link layer packet includes link layer CRC data. The step of controlling the simulation terminal module to perform data verification on the data link layer packets and the transaction layer packets respectively, and storing the valid data corresponding to the verified data link layer packets and transaction layer packets into a preset data storage module includes: The simulation terminal module is controlled to verify the transaction layer CRC data and the sequence code, and retain the transaction layer data body corresponding to the transaction layer data packet that passes the verification; The simulation terminal module is controlled to verify the CRC data of the link layer and retain the credit data of the updated flow control storage unit corresponding to the data link layer packet that passes the verification. The transaction layer data body and the updated flow control storage unit credit data are set as valid data, and the valid data is stored in a preset data storage module; The updated flow control storage unit credit data is generated by the simulation terminal module based on the verified and retained data link layer packets.

4. The PCIe reduced-rate bridge based data transfer method of claim 3, wherein: The transaction layer data body corresponding to the retained transaction layer data packet that passed the verification includes: If the transaction layer CRC data and the sequence code are verified correctly, the simulation terminal module is controlled to give a positive response, generate a positive response value, and retain the transaction layer data body corresponding to the transaction layer data packet that has passed the verification. If the transaction layer CRC data and the sequence code are incorrect, the simulation terminal module is controlled to issue a negative response and generate a negative response value. The positive response value or the negative response value is fed back to the verification platform.

5. The PCIe reduced-rate bridge based data transfer method of claim 1, wherein: The verification platform includes a first PIPE serial-to-parallel conversion module, and the data transmission system of the PCIe speed-down bridge includes a second PIPE serial-to-parallel conversion module. The step of transmitting the data to be transmitted to the simulation terminal module includes: The data to be transmitted is transmitted to the first PIPE serial-to-parallel conversion module, and first converted data is generated; The first converted data is transmitted to the second PIPE serial-to-parallel conversion module, and the second converted data is generated. The second conversion data is transmitted to the simulation terminal module; The process of controlling the simulation terminal module to parse the data to be transmitted includes: The simulation terminal module is controlled to parse the second conversion data.

6. The PCIe reduced-rate bridge based data transfer method of claim 1, wherein: The step of transmitting the valid data stored in the data storage module to the full-speed terminal module, and then transmitting it to the host computer through the preset PCIe physical layer module includes: The valid data in the data storage module is transmitted to the full-speed terminal module, and reassembled according to the data format requirements of the host computer to generate reassembled data. The recombined data is scrambled according to a preset scrambling method, and recombined scrambled data is generated; The recombined scrambling data is transmitted to the host computer via a preset PCIe physical layer module.

7. A data transmission device based on a PCIe speed-reduction bridge, characterized in that: The device is applied to a data transmission system based on a PCIe speed-reduction bridge. The system includes a verification platform, a host computer, and a speed-reduction bridge module. The speed-reduction bridge module includes a full-speed terminal module and a simulation terminal module. A first PCIe link is included between the simulation terminal module and the verification platform, and a second PCIe link is included between the full-speed terminal module and the host computer. The device includes: The system initialization module (301) is used to initialize the speed reduction bridge module so that the first PCIe link and the second PCIe link enter the normal operation state and the activation state. The data generation module (302) is used to control the verification platform to generate data to be transmitted and transmit the data to be transmitted to the simulation terminal module; The data parsing module (303) is used to control the simulation terminal module to parse the data to be transmitted and generate data link layer packets and transaction layer data packets; The data storage module (304) is used to control the simulation terminal module to perform data verification on the data link layer packet and the transaction layer data packet respectively, and to store the valid data corresponding to the verified data link layer packet and transaction layer data packet into the preset data storage module; The data transmission module (305) is used to transmit the valid data stored in the data storage module to the full-speed terminal module, and transmit it to the host computer through the preset PCIe physical layer module; The simulation terminal module includes a first flow control module, and the full-speed terminal module includes a second flow control module. The system initialization module 301 is specifically used to control the simulation terminal module and the full-speed terminal module to perform link training on the first PCIe link and the second PCIe link respectively, so that the first PCIe link and the second PCIe link enter the normal operation state; control the first flow control module to interact with the second flow control module, and determine whether the buffer capacity of the host computer is greater than a preset value based on the interaction information; if the buffer capacity of the host computer is greater than the preset value, then control the first PCIe link and the second PCIe link to enter the activation state.

8. A computer device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer program is stored that can be loaded by a processor and executed as described in any one of claims 1 to 6.

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