Data transmission control circuit and method thereof, memory

Abstract

The present disclosure provides a data transmission control circuit and a method thereof and a memory, and relates to the technical field of data transmission. The circuit comprises a data grouping circuit, a transmission control circuit and a data analysis circuit. The data grouping circuit divides current transmission data into a to-be-transmitted data group when the current transmission data on a parallel data bus is different from last transmission data, and determines a first to-be-transmitted data group and a second to-be-transmitted data group in the to-be-transmitted data group. The transmission control circuit performs flip processing on the data of the identification bit in the first to-be-transmitted data group to obtain first identification data, and transmits the first identification data to a receiving end. The first data corresponding to the second to-be-transmitted data group is transmitted to the receiving end. The data analysis circuit analyzes the received data to obtain the current transmission data, thereby saving the power consumption of the parallel data bus.

Description

Technical Field

[0001] This disclosure relates to the field of data transmission technology, and in particular to a data transmission control circuit, a data transmission control method, and a memory. Background Technology

[0002] In the field of chip design, power consumption is a key factor affecting chip performance. Data in memory such as dynamic random access memory is transferred through the data bus during read and write operations, and the power consumption generated in this process should not be underestimated.

[0003] In related technologies, the fourth-generation interface standard DDR4 introduced the Data Bus Inversion (DBI) function. However, when multiple sets of data are transmitted on the bus, a large amount of data needs to be inverted on the bus, and the power consumption remains high. Summary of the Invention

[0004] This disclosure provides a data transmission control circuit and method, and a memory, which at least to some extent overcomes the problem of high power consumption in bus data transmission provided in related technologies.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a data transmission control circuit is provided, applied to an n-bit parallel data bus having a transmitting end and a receiving end. The transmitting end includes a data packetization circuit and a transmission control circuit, the data packetization circuit and the transmission control circuit being connected. The receiving end is provided with a data parsing circuit. The data packetization circuit is configured to, in response to a current transmitted data on the n-bit parallel data bus being different from the previous transmitted data, divide the current transmitted data into m groups to be transmitted, and determine a first data groups to be transmitted and ma second data groups to be transmitted from the m groups, where m, n, and a are positive integers, and all data relative to the previous transmitted data need to be transmitted. The flipped data group is identified as the first data group to be transmitted, and the data group that has not been completely flipped relative to the previous transmitted data is identified as the second data group to be transmitted; the transmission control circuit is used to flip the identifier data in the a first data groups to be transmitted to obtain first identifier data, and transmit the first identifier data to the receiving end; transmit the first data corresponding to the ma second data groups to be transmitted to the receiving end; the data parsing circuit is used to flip the previous transmitted data corresponding to the a first data groups to be transmitted according to the first identifier data to obtain second data; and obtain the current transmitted data according to the first data and the second data.

[0007] In one embodiment of this disclosure, the data packet circuit includes a first flip-flop and m first comparators, each first comparator corresponding to a data group to be transmitted. The input of the first flip-flop is used to input the current transmitted data, the enable input of the first flip-flop is used to input a latch enable signal, and the output of the first flip-flop is used to output the previous transmitted data when the latch enable signal is valid. One input of each first comparator is connected to the output of the first flip-flop and is used to input the previous transmitted data corresponding to the data group to be transmitted. The other input of each first comparator is used to input the current transmitted data corresponding to the data group to be transmitted. The output of each first comparator is used to output a packet identification signal for the data group to be transmitted. When the packet identification signal is in a first state, the data group to be transmitted is identified as a first data group to be transmitted; when the packet identification signal is in a second state, the data group to be transmitted is identified as a second data group to be transmitted.

[0008] In one embodiment of this disclosure, the data packet circuit further includes an AND gate group and a first tri-state gate; wherein, the input terminal of the AND gate group is connected to the output terminals of m first comparators respectively, and the output terminal of the AND gate group is used to output a first control signal, the first control signal being used to characterize whether the current transmitted data has been completely flipped relative to the previous transmitted data; the input terminal of the first tri-state gate is connected to the output terminal of the AND gate group, the first tri-state gate is controlled by a first enable signal, and the output terminal of the first tri-state gate is used to output the first control signal when the first enable signal is in a first state.

[0009] In one embodiment of this disclosure, the circuit includes m transmission control circuits, each corresponding to a data group to be transmitted; each transmission control circuit includes a first signal generation circuit, a first data transmission control circuit, a second signal generation circuit, and a second data transmission control circuit; wherein, the first signal generation circuit is used to generate a second control signal based on a first enable signal, a second enable signal, a first control signal, and the group identifier signal; the first data transmission control circuit is used to process the identifier bit data in the data group to be transmitted according to the second control signal and transmit it to the receiving end; the second signal generation circuit is used to generate a third control signal based on the group identifier signal and the second enable signal; the second data transmission control circuit is used to determine whether to transmit the non-identifier bit data in the data group to be transmitted to the receiving end according to the third control signal, wherein the non-identifier bit data is the data bit corresponding to each data line other than the identifier bit in the data group to be transmitted.

[0010] In one embodiment of this disclosure, the first signal generation circuit includes: a first selector, one input terminal of which is used to input the second enable signal, and another input terminal of which is used to input the first enable signal, the first selector being controlled by the packet identification signal; and a first NOR gate, one input terminal of which is connected to the output terminal of the first selector via a first inverter, the other input terminal of which is used to input the first control signal, and the output terminal of which is connected to the first data transmission control circuit to provide the second control signal to the first data transmission control circuit.

[0011] In one embodiment of this disclosure, the first data transmission control circuit includes: a second selector, the second selector being controlled by the packet identification signal, one input terminal of the second selector being used to input the identification bit data in the data group to be transmitted, and the other input terminal of the second selector being connected to the output terminal of a second inverter, the input terminal of the second inverter being used to input the identification bit data in the data group to be transmitted; and a second tri-state gate, the input terminal of the second tri-state gate being connected to the output terminal of the second selector, the second tri-state gate being controlled by the second control signal, and the output terminal of the second tri-state gate being used to output the identification bit data in the data group to be transmitted.

[0012] In one embodiment of this disclosure, the second signal generation circuit includes: a third inverter, the input of which is used to input the group identification signal; a first AND gate, one input of which is connected to the output of the third inverter, the other input of which is used to input the second enable signal, and the output of which is connected to the second data transmission control circuit to provide the third control signal to the second data transmission control circuit; the second data transmission control circuit includes: a third tri-state gate, the input of which is used to input non-identifier bit data in the data group to be transmitted, and the third tri-state gate is controlled by the third control signal to determine whether to send the non-identifier bit data in the data group to be transmitted.

[0013] In one embodiment of this disclosure, the receiving end includes m data parsing circuits. Each data parsing circuit is used to parse the data of a corresponding data group to be transmitted. Each data parsing circuit includes a signal parsing circuit and a data processing circuit. The signal parsing circuit is used to receive the data corresponding to the identifier bit in the data group to be transmitted, and generate a fourth control signal based on a first enable signal, the identifier bit data in the data group to be transmitted, and the identifier bit data of the previous transmitted data. The data processing circuit is controlled by the fourth control signal, and obtains the data corresponding to the data group to be transmitted based on the received data corresponding to the data group to be transmitted and the previous transmitted data corresponding to the data group to be transmitted.

[0014] In one embodiment of this disclosure, the signal parsing circuit includes: a second flip-flop, the input of which is used to receive identifier bit data in the data group to be transmitted, and the enable terminal of which is used to input a first enable signal; a second comparator, one input of which is connected to the output of the second flip-flop, and the other input of which is used to input identifier bit data related to the previously transmitted data; and a third flip-flop, the input of which is connected to the output of the second comparator, the enable terminal of which is used to input a delay signal of the first enable signal, and the output of which is connected to the data processing circuit to provide a fourth control signal to the data processing circuit.

[0015] In one embodiment of this disclosure, the data processing circuit includes: a fourth flip-flop, the input of which is used to receive data corresponding to the data group to be transmitted, and the enable terminal of which is used to receive a second enable signal; a third selector, one input of which is connected to the output of the fourth flip-flop, and the other input of which is input via a fourth inverter to the previously transmitted data corresponding to the data group to be transmitted, and the third selector is controlled by a fourth control signal; and a fifth flip-flop, the input of which is connected to the output of the third selector, the enable terminal of which is used to input a delay signal of the second enable signal, and the output of which is used to output data corresponding to the data group to be transmitted.

[0016] In one embodiment of this disclosure, the receiving end further includes a sixth flip-flop, one input of which receives a first control signal, and the other input of which receives a first enable signal. The output of the sixth flip-flop generates a fourth control signal, which is used to instruct the receiving end to perform a flip-flop process on the previously transmitted data to obtain the currently transmitted data.

[0017] In one embodiment of this disclosure, the circuit further includes an enable control circuit, wherein the data grouping circuit is used to determine whether the current transmitted data is the same as the previous transmitted data based on the data changes in the previous transmitted data and the current transmitted data on the n-bit parallel data bus; the enable control circuit is used to control the enable terminal to be turned off when the current transmitted data and the previous transmitted data on the n-bit parallel data bus are the same; the data parsing circuit detects that the enable terminal is in a turned-off state and uses the previous transmitted data as the current output data; the enable control circuit is used to control the enable terminal to be turned on when the current transmitted data and the previous transmitted data on the n-bit parallel data bus are different.

[0018] According to another aspect of this disclosure, a data transmission method is also provided, applied to an n-bit parallel data bus having a transmitting end and a receiving end, comprising: the transmitting end, in response to the current transmitted data on the n-bit parallel data bus being different from the previous transmitted data, dividing the current transmitted data into m groups of data to be transmitted, and determining a first data groups to be transmitted and ma second data groups to be transmitted among the m groups of data to be transmitted, wherein m, n, and a are positive integers, and the data groups that need to be completely flipped relative to the previous transmitted data are determined as the first data groups to be transmitted, and the data groups that are not completely flipped relative to the previous transmitted data are determined as the second data groups to be transmitted; the transmitting end flips the identifier bit data in the a first data groups to be transmitted to obtain first identifier data, and transmits the first identifier data to the receiving end; transmits the first data corresponding to the ma second data groups to the receiving end; the receiving end flips the previous transmitted data corresponding to the a first data groups to be transmitted according to the first identifier data to obtain second data; and obtains the current transmitted data according to the first data and the second data.

[0019] According to another aspect of this disclosure, a memory is also provided, including the data transmission control circuitry described in any embodiment of this disclosure.

[0020] In embodiments of this disclosure, the circuit is applied to an n-bit parallel data bus having a transmitting end and a receiving end. The transmitting end includes a data packetization circuit and a transmission control circuit, which are connected together. The receiving end is provided with a data parsing circuit. The data packetization circuit is used to divide the current transmitted data into m data groups to be transmitted in response to the current transmitted data being different from the previous transmitted data on the n-bit parallel data bus, and to determine a first data group to be transmitted and ma second data groups to be transmitted from the m data groups to be transmitted, where m, n, and a are positive integers. Data groups that need to be completely flipped relative to the previous transmitted data are identified. The data groups to be transmitted are designated as the first data groups to be transmitted, and the data groups that have not been completely flipped relative to the data transmitted in the previous transmission are designated as the second data groups to be transmitted. The transmission control circuit is used to flip the flag bit data in the a first data groups to be transmitted to obtain the first flag data, and transmit the first flag data to the receiving end; transmit the first data corresponding to the ma second data groups to be transmitted to the receiving end; the data parsing circuit is used to flip the previous transmission data corresponding to the a first data groups to be transmitted according to the first flag data to obtain the second data; and obtain the current transmission data according to the first data and the second data, thereby saving power consumption of the parallel data bus.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0023] Figure 1 This diagram illustrates the structure of a data transmission control circuit according to an embodiment of the present disclosure.

[0024] Figure 2 This diagram illustrates the structure of a data packet circuit provided in an embodiment of the present disclosure.

[0025] Figure 3 This diagram illustrates the structure of another data packet circuit provided in an embodiment of the present disclosure.

[0026] Figure 4 This diagram illustrates the structure of a transmission control circuit provided in an embodiment of the present disclosure.

[0027] Figure 5 A schematic diagram of another transmission control circuit provided in an embodiment of this disclosure is shown.

[0028] Figure 6 This diagram illustrates the principle of data transmission from the transmitting end according to an embodiment of the present disclosure.

[0029] Figure 7 A timing diagram of the transmitting end provided in an embodiment of this disclosure is shown.

[0030] Figure 8 This diagram illustrates the structure of a data parsing circuit provided in an embodiment of the present disclosure.

[0031] Figure 9 A schematic diagram of another data parsing circuit provided in an embodiment of this disclosure is shown.

[0032] Figure 10 This diagram illustrates the principle of the receiving end parsing data provided in an embodiment of this disclosure.

[0033] Figure 11 A timing diagram of the receiving end provided in an embodiment of this disclosure is shown.

[0034] Figure 12 This diagram illustrates another principle of transmitting data from a transmitter according to an embodiment of the present disclosure.

[0035] Figure 13 A flowchart of a data transmission method provided in an embodiment of this disclosure is shown.

[0036] Figure 14 A flowchart of another data transmission method provided by an embodiment of this disclosure is shown.

[0037] Figure 15 A flowchart of another data transmission method provided in an embodiment of this disclosure is shown.

[0038] The reference numerals in the attached figures are explained as follows: 100, transmitting end; 110, data packetization circuit; 111, AND gate group; 120, transmission control circuit; 121, first signal generation circuit; 122, first data transmission circuit; 123, second signal generation circuit; 124, second data transmission circuit; 200, receiving end; 210, data parsing circuit; 211, signal parsing circuit; 212, data processing circuit. Detailed Implementation

[0039] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0040] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly stated.

[0041] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0042] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0043] In chip design, power consumption is a major factor affecting chip performance. Memory such as Dynamic Random Access Memory (DRAM) typically includes memory arrays for storing data, data input / output pads, and related timing control circuitry. DRAM power consumption during normal operation includes, but is not limited to, static power consumption, dynamic power consumption, and bus power consumption. Static power consumption refers to the power consumed by DRAM even when there are no data read / write operations to ensure the stability of parameters such as voltage and temperature. Dynamic power consumption refers to the power consumed by DRAM during read / write operations, which is related to the cycle, frequency, and amount of data involved in the read / write operation. Bus power consumption refers to the power consumption generated during data transmission.

[0044] Within a memory chip, data transmission from the data input / output pads to the storage array often requires long metal lines. Bus power consumption is related to the data transmission distance and the amount of data.

[0045] Double Data Rate (DDR) synchronous dynamic random access memory transmits data twice within a clock cycle, enabling it to transmit data once on the rise and once on the fall of the clock.

[0046] For example, in the fourth-generation DRAM interface standard DDR4, the parallel data bus is 64-bit. Data is transmitted through the parallel data bus during the read and write process, and the resulting power consumption is not to be underestimated.

[0047] In related technologies, Data Bus Inversion (DBI) is introduced in DDR4 to reduce bus power consumption. This involves detecting the number of high and low voltage levels on the parallel data bus during a single data transmission. When the number of low voltage levels exceeds the number of high voltage levels, DBI is enabled, inverting all data on the parallel data bus to ensure that the number of high voltage levels is greater than the number of low voltage levels, thus reducing bus power consumption. When the number of high voltage levels exceeds the number of low voltage levels, data transmission proceeds normally. However, even with DBI, DDR4's bus power consumption remains relatively high, necessitating the design of a technology to further reduce bus power consumption during data transmission.

[0048] To at least partially solve the aforementioned technical problems, the data transmission control circuit provided in this disclosure is applied to an n-bit parallel data bus having a transmitting end 100 and a receiving end 200. The transmitting end 100 includes a data packetization circuit 110 and a transmission control circuit 120, which are connected. The receiving end 200 is provided with a data parsing circuit 210. The data packetization circuit 110 is used to divide the current transmitted data into m data groups to be transmitted in response to the current transmitted data on the n-bit parallel data bus being different from the previous transmitted data, and to determine a first data group to be transmitted and ma second data groups to be transmitted among the m data groups to be transmitted, where m, n, and a are positive integers relative to the previous data group. The data group that needs to be completely flipped in the next transmission is determined as the first data group to be transmitted, and the data group that has not been completely flipped relative to the previous transmission is determined as the second data group to be transmitted. The transmission control circuit 120 is used to flip the identifier bit data in a first data group to be transmitted to obtain first identifier data, and transmit the first identifier data to the receiving end 200; transmit the first data corresponding to ma second data groups to be transmitted to the receiving end 200; the data parsing circuit 210 is used to flip the previous transmission data corresponding to a first data group to be transmitted according to the first identifier data to obtain second data; and obtain the current transmission data according to the first data and the second data, thereby saving power consumption of the parallel data bus. This is specifically illustrated through the following embodiment:

[0049] Figure 1This diagram illustrates the structure of a data transmission control circuit according to an embodiment of the present disclosure. Figure 1 As shown, the data transmission control circuit in this embodiment is applied to an n-bit parallel data bus having a transmitting end 100 and a receiving end 200. The transmitting end 100 includes a data packetization circuit 110 and a transmission control circuit 120, which are connected. The receiving end 200 is provided with a data parsing circuit 210. The data packetization circuit 110 is used to divide the current transmitted data into m groups to be transmitted in response to a difference between the current transmitted data and the previous transmitted data on the n-bit parallel data bus, and to determine a first data group to be transmitted and ma second data groups to be transmitted from the m groups, where m, n, and a are positive integers relative to... The data group that needed to be completely flipped in the previous transmission is identified as the first data group to be transmitted, and the data group that was not completely flipped relative to the previous transmission is identified as the second data group to be transmitted. The transmission control circuit 120 is used to flip the identifier data in a first data group to be transmitted to obtain first identifier data, and transmit the first identifier data to the receiving end 200; transmit the first data corresponding to a second data group to be transmitted to the receiving end 200; the data parsing circuit 210 is used to flip the previous transmission data corresponding to a first data group to be transmitted according to the first identifier data to obtain second data; and obtain the current transmission data according to the first data and the second data.

[0050] The transmitter 100 and receiver 200 can be located inside the DRAM. For example, the transmitter 100 can be a global input / output line (GIO), and the receiver 200 can be data input / output pads (DQpads). It should be noted that this disclosure is not limited to DRAM scenarios, but can also be applied to other scenarios that use parallel data buses for data transmission. During data transmission, the greater the power consumption, the more significant the power reduction through the solution disclosed in this disclosure.

[0051] Continue to refer to Figure 1 The transmitting end 100 includes a data packetization circuit 110 and a transmission control circuit 120, which are connected. The data packetization circuit 110 is used to group the n-bit parallel data bus based on the current transmission data and the previous transmission data to obtain multiple data groups to be transmitted. The transmission control circuit 120 is used to process the grouped data groups to be transmitted and transmit the data corresponding to each data group to the receiving end 200. The receiving end 200 is provided with a data parsing circuit 210, which is used to receive the data sent by the transmitting end 100 and parse the data to obtain the current transmission data.

[0052] The data grouping circuit 110 can respond to the current transmission data on the n-bit parallel data bus being different from the previous transmission data by dividing the current transmission data into m data groups to be transmitted, and determining a first data group to be transmitted and ma second data groups to be transmitted among the m data groups to be transmitted.

[0053] The number of bits n in the parallel data bus can be determined according to the actual situation. For example, DDR4 is a 64-bit parallel data bus, i.e., n = 64. The currently transmitted data is the data to be transmitted from the sending end 100 to the receiving end 200 during this transmission process; the previous transmitted data is the data that was transmitted from the sending end 100 to the receiving end 200 before the current transmitted data was transmitted. Both the current transmitted data and the previous transmitted data are n bits.

[0054] The current transmitted data differs from the previous transmitted data in that at least one data bit in the current transmitted data and the previous transmitted data are different. For example, if the previous transmitted data contained "Bus"... <1> The data is logic 1, and the Bus is currently transmitting data. <1> If the data is logic 0, then it is determined that the current transmitted data is different from the previous transmitted data.

[0055] The current transmitted data differs from the previous transmitted data in several ways. This can mean that all n data bits in the current transmitted data are different from those in the previous transmitted data, or it can mean that only some data bits in the current transmitted data are different from those in the previous transmitted data. If all n data bits in the current transmitted data are the same as those in the previous transmitted data, then the current transmitted data is considered to be the same as the previous transmitted data, meaning that the data transmitted in two consecutive transmissions is identical.

[0056] The number of data bits in each data group to be transmitted is i = n / m, meaning that the n bits of current data to be transmitted are divided into m data groups of width i to be transmitted. Current transmitted data: Data <n-1:0>The first data group to be transmitted can be represented as D0.<i-1,0> The second data group to be transmitted can be represented as D1<2i-1,i>, and the m-th data group to be transmitted can be represented as Dm.<n-1,i(m-1)> .

[0057] The number m of the aforementioned data groups to be transmitted can be determined according to the actual situation. The transmitting end 100 and the receiving end 200 exchange information through a protocol, which is not limited in this disclosure. For example, if a 64-bit parallel data bus is divided into 8 data groups to be transmitted, then each data group to be transmitted includes 8 data bits.

[0058] In a dataset of m data groups to be transmitted, there are 'a' first data groups and 'ma' second data groups, where 'a' and 'ma' are both positive integers greater than or equal to 0. This means that when the current transmitted data differs from the previous transmitted data, none of the m data groups need to be completely reversed compared to the previous transmission. In this case, all m data groups are not completely reversed compared to the previous transmission, resulting in 0 first data groups and 'm' second data groups. Conversely, if all m data groups need to be completely reversed compared to the previous transmission, none of them need to be completely reversed, again resulting in 'm' first data groups and 0 second data groups.

[0059] It should be noted that the aforementioned data group that needs to be completely flipped relative to the previous transmission refers to the i data bits in the data group to be transmitted, which can all transition from the logic high level of the previous transmission to the logic low level of the current transmission, or all transition from the logic low level of the previous transmission to the logic high level of the current transmission. The aforementioned data group that is completely flipped relative to the previous transmission refers to a data group to be transmitted where the number of data bits that need to be flipped is less than the total number of data bits i in the data group to be transmitted.

[0060] The transmission control circuit 120 can be used to flip the flag bit data in a first data group to be transmitted to obtain first flag data, and transmit the first flag data to the receiving end 200. Thus, data transmission is achieved by flipping all the flag bits in the data group to be transmitted, which greatly reduces the power consumption of the bus.

[0061] In one feasible implementation, the identifier bit data in the first data group to be transmitted can be a specific data bit in the first data group to be transmitted.

[0062] For example, the aforementioned identifier bit can be the first bit of the first data group to be transmitted. For instance, when the n-bit parallel data bus is divided into m data groups to be transmitted, the first data bit of each of the m data groups can be used. <0> Data ...Data<(m-1)i> is used as a flag bit.

[0063] For example, the aforementioned flag bit can also be the last bit in the first data group to be transmitted. For instance, the last data bit (Data) of m data groups to be transmitted can be used. <i-1>、Data<2i-1>……Data <n>As an identifier.

[0064] It should be noted that the number of identifier bits in the first data group to be transmitted can be one or more. Preferably, the identifier bit of the first data group to be transmitted is the first data bit of each data group, but this disclosure does not make a specific limitation in this regard. The identifier bit of the data group to be transmitted is only valid when data is transmitted in the first data group to be transmitted. In the second data group to be transmitted, the identifier bit transmits the data corresponding to that data bit.

[0065] The aforementioned first identifier data is obtained by inverting the previous transmitted data corresponding to the identifier bit of the first data group to be transmitted.

[0066] It should be noted that the data corresponding to the first data group to be transmitted to the receiving end 200 is only the first identifier data obtained by inverting the identifier bits of the first data group to be transmitted. The number of bits of each first identifier data is the same as the number of bits of the identifier bits of the first data group to be transmitted, for example, 1 bit. The first data transmitted to the receiving end 200 is the data normally transmitted by the second data group to be transmitted. The first data corresponding to each second data group to be transmitted is i bits.

[0067] In one embodiment, the sending end 100 can use delayed transmission of the second data, transmitting the first identification data first and then the second data. The delay duration can be one time period or multiple time periods, depending on actual needs. The sending end 100 transmits the first identification data within a first time period T0 and transmits the second data within a second time period T1.

[0068] The data parsing circuit 210 can reverse the previous transmitted data corresponding to the a first data groups to be transmitted based on the first identification data to obtain the second data; and obtain the current transmitted data based on the first data and the second data.

[0069] The data parsing circuit 210 of the receiving end 200 can determine the data of the first data group to be transmitted that needs to be completely flipped relative to the previous data in the current transmitted data based on the position and quantity of the first identifier data. It then inverts all the previous transmitted data corresponding to the first data group to be transmitted corresponding to the first identifier data to obtain the second data, which is the data of the first data group to be transmitted this time.

[0070] After obtaining the first data and the second data, the data parsing circuit 210 can combine the first data and the second data according to the order of the n-bit parallel data bus to obtain the currently transmitted data, that is, to obtain the complete bus data.

[0071] In this embodiment of the disclosure, the data transmission control circuit is applied to an n-bit parallel data bus having a transmitting end 100 and a receiving end 200. The transmitting end 100 includes a data packetization circuit 110 and a transmission control circuit 120, which are connected. The receiving end 200 is provided with a data parsing circuit 210. The data packetization circuit 110 is used to divide the current transmitted data into m data groups to be transmitted in response to a difference between the current transmitted data and the previous transmitted data on the n-bit parallel data bus. It also determines a first data group to be transmitted and ma second data groups to be transmitted from the m data groups, where m, n, and a are positive integers. Data groups that need to be completely flipped relative to the previous transmitted data are determined as first data groups to be transmitted. Data groups whose data was not completely flipped in the previous transmission are identified as the second data groups to be transmitted. The transmission control circuit 120 is used to flip the identifier data in a first data groups to be transmitted to obtain first identifier data, and transmit the first identifier data to the receiving end 200; transmit the first data corresponding to a second data groups to be transmitted to the receiving end 200; the data parsing circuit 210 is used to flip the previous transmission data corresponding to a first data groups to be transmitted according to the first identifier data to obtain second data; and obtain the current transmission data according to the first data and the second data. When the data is transmitted between the sending end 100 and the receiving end 200, only the first identifier data and the second data are transmitted, thereby reducing the power consumption of data transmission. Without increasing the chip area and cost, the power consumption of bus transmission is greatly reduced.

[0072] In one embodiment, the data grouping circuit 110 is used to determine whether the current transmitted data and the previous transmitted data are the same based on the data changes in the previous transmitted data and the current transmitted data on the n-bit parallel data bus. The determination result may include the two transmitted data being completely identical, the current transmitted data needing to be completely flipped relative to the previous transmitted data (the case of being completely different), and the current transmitted data needing to be partially flipped relative to the previous transmitted data (the case of being partially different).

[0073] In this disclosure, different processing methods can be applied to the three scenarios described above. For example, if the current transmitted data needs to be partially flipped relative to the previous transmitted data, the processing method described in the above embodiments can be implemented to achieve partial real data transmission through grouping, thereby reducing bus power consumption. If the two transmitted data are completely identical, the receiving end 200 can use the previous transmitted data as the current transmitted data, thus eliminating the need for the n-bit parallel data bus to transmit data. If the two transmitted data are completely different, the receiving end 200 can invert the previous transmitted data to obtain the current transmitted data, thereby requiring only the transmission of the flag bit data on the n-bit parallel data bus, which also reduces bus power consumption.

[0074] The specific implementation of the above three scenarios for the data grouping circuit 110 is described in detail below.

[0075] Figure 2 A schematic diagram of the structure of the data packet circuit 110 provided in an embodiment of this disclosure is shown. Figure 2 As shown, in one embodiment, the data packet circuit 110 includes a first flip-flop DFF1 and m first comparators Comp, such as... Figure 2 In the first comparator, Comp0 to Comp(m-1) are used. Compj is the (j+1)th first comparator, where j = {0, 1, ..., m-1}. Each first comparator Compj corresponds to one data group to be transmitted. The number of first comparators is determined by the number of data groups to be transmitted, and this disclosure does not impose a specific limitation on this. The following explanation uses the first comparator Compj as an example.

[0076] The input of the first trigger DFF1 is used to input the current transmission data Data. <n-1:0>The enable input of the first flip-flop DFF1 is the latch enable signal Latch_en, and the output of the first flip-flop DFF1 is used to output the last transmitted data Data_0 when the latch enable signal Latch_en is valid. <n-1:0>。Data_0 <n-1:0>This refers to the data that was latched by the latch during the previous transmission.

[0077] One input of each first comparator Compj is connected to the output of the first flip-flop DFF1, and is used to input the previous transmitted data corresponding to the data group to be transmitted. The other input of each first comparator Compj is used to input the current transmitted data corresponding to the data group to be transmitted. The output of each first comparator Compj is used to output the group identifier signal flag_gj of the data group to be transmitted. When the group identifier signal flag_gj is in the first state, the data group to be transmitted is determined as the first data group to be transmitted. When the group identifier signal flag_gj is in the second state, the data group to be transmitted is determined as the second data group to be transmitted.

[0078] In one embodiment, the first state can be a first voltage level, such as a logic high level, and the second state can be a second voltage level, such as a logic low level. It should be noted that the first state can also be a second voltage level, i.e., a logic low level, and the second state can also be a first voltage level, i.e., a logic high level; this disclosure does not specifically limit this.

[0079] In this disclosure, the first state being a logic high level and the second state being a logic low level are used as examples for illustration.

[0080] Continue to refer to Figure 2 An n-bit parallel data bus is divided into m groups of data to be transmitted. The first comparators corresponding to each group of data to be transmitted are Comp0 to Comp(m-1). When the latch enable signal Latch_en is valid, the first flip-flop DFF1 outputs the data from the last transmission, Data_0. <n-1:0>The first comparator Comp0 corresponding to the first data group to be transmitted is input to the current data Data<(i-1):0> and the previous data Data_0<(i-1):0>, and outputs the group identifier signal flag_g0 for the first data group to be transmitted; the first comparator Comp1 corresponding to the second data group to be transmitted is input to the current data Data<2i-1:i> and the previous data Data_0<(2i-1):i>, and outputs the group identifier signal flag_g1 for the second data group to be transmitted; the first comparator Comp(j-1) corresponding to the j-th data group to be transmitted is input to the current data Data<(i-1):0> and the previous data Data_0<(i-1):0>, and outputs the group identifier signal flag_g1 for the second data group to be transmitted;<ji-1:i(j-1)> The data is combined with the previously transmitted data Data_0<(ji-1):i(j-1)>, and the packet identifier signal flag_g(j-1) of the j-th data group to be transmitted is output. This process continues until the first comparator Comp(m-1) corresponding to the m-th data group to be transmitted receives the current data Data<(n-1):i(m-1)> and the previously transmitted data Data_0<(n-1):i(m-1)> respectively, and outputs the packet identifier signal flag_g(m-1) of the m-th data group to be transmitted. At this point, the data grouping is completed.

[0081] In this disclosure, when the packet identifier signal flag_g(j-1) is 1, it indicates that the current transmitted data of the j-th data group to be transmitted needs to be completely flipped relative to the previous transmitted data, that is, the j-th data group to be transmitted is determined to be the first data group to be transmitted; when the packet identifier signal flag_g(j-1) is 0, it indicates that the current transmitted data of the j-th data group to be transmitted does not need to be completely flipped relative to the previous transmitted data, that is, the j-th data group to be transmitted is determined to be the second data group to be transmitted.

[0082] In one embodiment, the trigger in this disclosure can be a bistable trigger, and the comparator can be any circuit, module, etc. that can compare the magnitudes of two voltages or currents; this disclosure does not impose any specific limitations on this.

[0083] In this embodiment, by setting a first flip-flop DFF1 and m comparators (Comp0 to Comp(m-1)), data grouping of an n-bit parallel data bus can be realized, thereby determining the data changes between the current transmitted data and the previous transmitted data, and then determining the corresponding data processing method based on the data changes, thereby achieving the purpose of reducing bus power consumption. This circuit is simple and easier to implement.

[0084] Figure 3 A schematic diagram of another data packet circuit 110 provided in an embodiment of this disclosure is shown. Figure 2 Based on the previous embodiment, by adding AND gate group 111 and tri-state gates, a comprehensive judgment is made on two adjacent data transmissions on an n-bit parallel data bus to determine when all data needs to be flipped. Figure 3 As shown, in one embodiment, the data packet circuit 110 further includes an AND gate group 111 and a first tri-state gate PORT1; wherein, the input terminal of the AND gate group 111 is connected to the output terminals of m first comparators Comp0 to Comp(m-1), and the output terminal of the AND gate group 111 is used to output a first control signal flag_all, which is used to characterize the currently transmitted data Data. <n-1:0>Compared to the previous data transmission Data_0 <n-1:0>Whether to flip all; the input of the first tri-state gate PORT1 is connected to the output of the AND gate group 111. The first tri-state gate PORT1 is controlled by the first enable signal Case0_en. The output of the first tri-state gate PORT1 is used to output the first control signal flag_all when the first enable signal Case0_en is in the first state.

[0085] In one embodiment, the AND gate group 111 may include multiple AND gates. The outputs of the first comparators Comp0 and Comp1 can be connected to the input of one AND gate, the outputs of the first comparators Comp2 and Comp3 can be connected to the input of another AND gate, the outputs of the two AND gates can be connected to the input of the next-level AND gate, and so on, until all the group identification signals output by the first comparators are input to the AND gate group 111 to obtain the first control signal flag_all. It should be noted that the number of AND gates can be determined according to actual needs, and this disclosure does not impose a specific limitation on it.

[0086] Data transmission is achieved through a delay between the latch enable signal Latch_en and the first enable signal Case_en.

[0087] In one feasible implementation, when the first control signal flag_all is in the first state, it indicates that the current transmitted data needs to be completely flipped compared to the previous transmitted data, so that the receiving end 200 can invert the previous transmitted data according to the first control signal flag_all to obtain the current transmitted data. When the first control signal flag_all is in the second state, it indicates that the current transmitted data does not need to be completely flipped compared to the previous transmitted data, and group transmission judgment is required. When the first enable signal Case0_en is in the first state, the first tri-state gate PORT1 outputs the first control signal flag_all; when the first enable signal Case0_en is in the second state, the first tri-state gate PORT1 is in a high-impedance state and has no output.

[0088] In this embodiment of the disclosure, the grouping of the n-bit parallel data bus and the determination of three cases can be realized by AND gate group 111 and the first tri-state gate POTR1, so as to reduce bus power consumption.

[0089] Figure 4 This diagram illustrates the structure of a transmission control circuit 120 provided in an embodiment of the present disclosure. Figure 4 As shown, in one embodiment, the data transmission control circuit includes m transmission control circuits 120, each corresponding to a data group to be transmitted. Each transmission control circuit 120 is used to control the transmission of flag bit data and non-flag bit data in the data group to be transmitted. Non-flag bit data refers to the data bits corresponding to other data lines besides the flag bit in each data group to be transmitted. For example, for the data group Data<(i-1):0> to be transmitted, the flag bit is Data. <0> The non-flag bit is Data<(i-1):1>.

[0090] Each transmission control circuit 120 includes a first signal generation circuit 121, a first data transmission control circuit 120, a second signal generation circuit 123, and a second data transmission control circuit 120. The first signal generation circuit 121 is used to generate a second control signal Sig1 based on a first enable signal Case0_en, a second enable signal Case1_en, a first control signal flag_all, and a packet identifier signal flag_gi. The first data transmission control circuit 120 is used to process the identifier bit data in the data group to be transmitted according to the second control signal Sig1 and transmit it to the receiving end 200. The second signal generation circuit 123 is used to generate a third control signal Sig2 based on the packet identifier signal flag_gi and the second enable signal Case1_en. The second data transmission control circuit 120 is used to determine whether to transmit the non-identifier bit data in the data group to be transmitted to the receiving end 200 based on the third control signal Sig2.

[0091] The first signal generation circuit 121 is used to generate a second control signal Sig1 to control the second signal generation circuit 123, so that the second signal generation circuit 121 outputs corresponding data under the control of the second control signal Sig1; the second signal generation circuit 123 is used to generate a third control signal Sig2 to control the second data transmission control circuit 120, so that the second data transmission control circuit 120 outputs corresponding data under the control of the third control signal Sig2.

[0092] In one embodiment, the first data transmission control circuit 120 is used to determine whether to flip the identifier bit data in the data group to be transmitted and transmit it to the receiving end 200 according to the second control signal Sig1; the second data transmission control circuit 120 is used to determine whether to transmit the non-identifier bit data in the data group to be transmitted to the receiving end 200 according to the third control signal Sig2.

[0093] In this embodiment of the disclosure, by processing and controlling the transmission of the flag bit data and non-flag bit data in each data group to be transmitted separately, the power consumption of the bus can be effectively reduced.

[0094] Figure 5 A schematic diagram of another transmission control circuit 120 provided in an embodiment of this disclosure is shown. Figure 5 The diagram shows the circuit diagram of the transmission control circuit 120 corresponding to the first data group to be transmitted, Group0. The circuit diagrams of the transmission control circuits 120 corresponding to the remaining m-2 data groups to be transmitted are the same as the circuit diagram of Group0. The principle of the transmission control circuit 120 of each data group to be transmitted is similar to that of Group0. The only difference is that the controlled signal of the selector is replaced with the group identification signal of the corresponding data group to be transmitted, and the identification bit data and non-identification bit data are replaced with the data corresponding to the corresponding data group to be transmitted. Here, Group0 is used as an example for explanation.

[0095] like Figure 5 As shown, in one embodiment, the first signal generation circuit 121 includes: a first selector MUX1, one input of which is used to input a second enable signal Case1_en, and the other input of which is used to input a first enable signal Case0_en, and the first selector MUX1 is controlled by a group identifier signal flag_g0; a first NOR gate NOR1, one input of which is connected to the output of the first selector MUX1 through a first inverter NOT1, and the other input of which is used to input a first control signal flag_all, and the output of the first NOR gate NOR1 is connected to a first data transmission control circuit 120 to provide a second control signal Sig1 to the first data transmission control circuit 120.

[0096] When the packet identifier signal flag_g0 is 0, meaning the first data group to be transmitted is the second data group to be transmitted, the first selector MUX1 outputs the value of the second enable signal Case1_en; when the packet identifier signal flag_g0 is 1, meaning the first data group to be transmitted is the first data group to be transmitted, the first selector MUX1 outputs the value of the first enable signal Case0_en.

[0097] The value output from the first selector MUX1 is inverted by the first inverter NOT1 and then input to the first NOR gate NOR1. After processing the above value and flag_all by the first NOR gate NOR1, the second control signal Sig1 is output.

[0098] When flag_all = 0 and flag_g0 = 1, if Case0_en is valid, the first selector MUX1 outputs a logic high level, which is converted to a logic low level after passing through the first inverter NOT1. At this time, both inputs of the first NOR gate NOR1 are logic low, and the output of the first NOR gate NOR1 is logic high (Sig1 = 1). When flag_all = 0 and flag_g0 = 0, if Case1_en is valid, the first selector MUX1 outputs a logic high level, which is converted to a logic low level after passing through the first inverter NOT1. At this time, both inputs of the first NOR gate NOR1 are logic low, and the output of the first NOR gate NOR1 outputs a logic high level (Sig1 = 1). When Case0_en and Case1_en are invalid, the second control signal Sig1 is 0.

[0099] Continue to refer to Figure 5 In one embodiment, the first data transmission control circuit 120 includes a second selector MUX2, which is controlled by a packet identifier signal flag_g0. One input of the second selector MUX2 is used to input the identifier bit data Data from the data group to be transmitted. <0> The other input of the second selector MUX2 is connected to the output of the second inverter NOT2. The input of the second inverter NOT2 is used to input the identifier data (Data) from the data group to be transmitted. <0> The second tri-state gate PORT2 has its input connected to the output of the second selector MUX2. PORT2 is controlled by the second control signal Sig1. Its output is used to output the identifier data BUS_tx from the data group to be transmitted. <0> .

[0100] When flag_all = 0 and flag_g0 = 1, the second selector MUX2 outputs Data. <0> After inverting the data, since the second control signal Sig1 = 1, the output terminal of the second tri-state gate PORT2 outputs the first identifier data BUS_tx. <0> Data is the identifier bit of the previous transmission. <0> The inverted data. When flag_all = 0 and flag_g0 = 0, the second selector MUX outputs Data. <0> Since the second control signal Sig1 = 1, the first identifier data BUS_tx is output from the output terminal of the second tri-state gate PORT2. <0> Directly output Data <0> The corresponding data.

[0101] In this embodiment of the disclosure, a second control signal Sig1 is generated by a first signal generation circuit 121, so that the second control signal Sig1 controls the first data transmission control circuit 120, thereby realizing the data transmission control of the identifier bit of the data group to be transmitted.

[0102] Continue to refer to Figure 5 In one embodiment, the second signal generation circuit 123 includes: a third inverter NOT3, the input of which is used to input a group identifier signal flag_g0; a first AND gate AND1, one input of which is connected to the output of the third inverter NOT3, the other input of which is used to input a second enable signal Case1_en, and the output of which is connected to the second data transmission control circuit 120 to provide a third control signal Sig2 to the second data transmission control circuit 120; the second data transmission control circuit 120 includes: a third tri-state gate PORT3, the input of which is used to input non-identifier bit data Data<(i-1):1> in the data group to be transmitted, and the third tri-state gate PORT3 is controlled by the third control signal Sig2 to determine whether to send the non-identifier bit data Data<(i-1):1> in the data group to be transmitted.

[0103] When the first data group to be transmitted, Group0, is the second data group to be transmitted, flag_g0 = 0, and after passing through the third inverter NOT3, it becomes a logic high level. When the second enable signal Case1_en is valid, both inputs of the first AND gate AND1 are at a logic high level. At this time, the output of the first AND gate AND1 outputs the third control signal Sig2 = 1.

[0104] When the third control signal Sig2 = 1, the third tri-state gate PORT3 directly outputs Data<(i-1):1> as the parallel data bus data BUS_tx<(i-1):1>.

[0105] Once the m data groups to be transmitted, Group0 to Group(m-1), have determined the data to be sent to the receiving end 200, the data of the n-bit parallel data bus can be obtained, denoted as BUS_tx<(n-1):0>.

[0106] In this embodiment of the disclosure, a third control signal Sig2 is generated by the second signal generation circuit 123. The third control signal Sig2 is used to control the transmission of non-identifier bit data in the second data group to be transmitted to the receiving end 200, so as to minimize the occupation of the parallel data bus and reduce the bus power consumption.

[0107] It should be noted that the n-bit parallel data bus can also connect multiple inverters connected in parallel to improve data transmission capability, reduce output blocking, and has a large load capacity.

[0108] Figure 6 This diagram illustrates the principle of data transmission by the transmitter 100 provided in an embodiment of this disclosure. Figure 6 As shown, the data on the n-bit parallel data bus is Data <n-1:0>The previous data transmission was data1, and the current data transmission is data2. The n-bit parallel data bus is divided into m data groups to be transmitted. Each data group contains n / m data items, denoted as D0. <n m-1:0>~Dm <n m-1:0>When the data group Dx is to be transmitted <n m-1:0>When the current transmitted data data2 needs to be completely reversed relative to the previous transmitted data data1, the data group to be transmitted is marked as Case0, and the flag0 bit of Case0 is inverted and transmitted to the receiving end 200. When the data group to be transmitted Dx <n m-1:0>If the current transmitted data data2 has not been fully flipped relative to the previous transmitted data data1, the data group to be transmitted is recorded as Case1, and the first data corresponding to the data group to be transmitted is directly transmitted to the receiving end 200.

[0109] Figure 7 A timing diagram of the transmitter 100 provided in an embodiment of this disclosure is shown. For example... Figure 7 As shown, during a certain time period, the first enable signal Case0_en is high, and the n-bit parallel data bus transmits the flag bit of Case0 and the first control signal flag_all to the receiving end 200; after a certain delay, the second enable signal Case1_en is high, and the n-bit parallel data bus transmits the first data of Case1 to the receiving end 200.

[0110] Figure 8 This diagram illustrates the structure of a data parsing circuit 210 provided in an embodiment of the present disclosure. Figure 8 As shown, in one embodiment, the data transmission control circuit provided in this disclosure includes m data parsing circuits 210. Each data parsing circuit 210 is used to parse the data of a corresponding group of data to be transmitted. Each group of data parsing circuits 210 includes a signal parsing circuit 211 and a data processing circuit 212. Figure 8 The circuit comprises m signal parsing circuits 211 and m data processing circuits 212. It should be noted that the parsing principles of the m data parsing circuits 210 are the same; the following explanation uses the parsing of the first data group to be transmitted, Group0, as an example.

[0111] Signal parsing circuit 211 is used to receive the identifier bit data Bus_tx in the data group to be transmitted. <0> And based on the first enable signal Case0_en and the identifier data Bus_tx in the data group to be transmitted <0> The identifier data Bus_rx from the last data transmission <0> The fourth control signal Sig3 is generated. The data processing circuit 212 is controlled by the fourth control signal Sig3. The data processing circuit 212 obtains the data Bus_rx<(i-1):0> corresponding to the data group to be transmitted based on the data Bus_tx<(i-1):0> corresponding to the received data group to be transmitted and the previous transmitted data Bus_rx<(i-1):0> corresponding to the data group to be transmitted.

[0112] After the m data processing circuits 212 output the corresponding data, n is obtained as the current transmission data BUS_rx<(n-1):0> of the parallel data bus.

[0113] Figure 9 A schematic diagram of another data parsing circuit 210 provided in an embodiment of this disclosure is shown. Figure 9 As shown, in one embodiment, the signal parsing circuit 211 includes a second flip-flop DFF2, the input of which is used to receive the identifier bit data Bus_tx in the data group to be transmitted. <0> The enable terminal of the second flip-flop DFF2 is used to input the first enable signal Case0_en; the second comparator Comp20 has one input terminal connected to the output terminal of the second flip-flop DFF2, and the other input terminal of the second comparator Comp20 is used to input the flag bit data Bus_rx of the previous data transmission. <0> The third flip-flop DFF3 has its input connected to the output of the second comparator Comp 20. The enable terminal of the third flip-flop DFF3 is used to input the delayed signal Case0_en_dly of the first enable signal. The output terminal of the third flip-flop DFF3 is connected to the data processing circuit 212 to provide the fourth control signal Sig3 to the data processing circuit 212.

[0114] In one embodiment, when Case0_en is valid, Bus_tx <0> The second comparator Comp 20 is input via the second flip-flop DFF2, and the second comparator Comp 20 compares Bus_tx. <0> and Bus_rx <0> When Case0_en is valid, if the two are inconsistent, the second comparator Comp 20 outputs a logic high level (1), that is, the flag bit of the data group to be transmitted is toggled, and the data group to be transmitted is determined to be the first data group to be transmitted. When Case0_en_dly is valid, the third flip-flop DFF3 outputs the fourth control signal Sig3 as a logic high level. When the two are consistent, the second comparator Comp 20 outputs a logic low level (0), and the data group to be transmitted is determined to be the second data group to be transmitted. When Case0_en_dly is valid, the third flip-flop DFF3 outputs the fourth control signal Sig3 as a logic low level.

[0115] Continue to refer to Figure 9 In one embodiment, the data processing circuit 212 includes: a fourth flip-flop DFF4, the input of which is used to receive data Bus_tx<(i-1):0> corresponding to the data group to be transmitted, and the enable terminal of the fourth flip-flop DFF3 is used to receive a second enable signal Case1_en; a third selector MUX3, one input of which is connected to the output of the fourth flip-flop DFF4, and the other input of which is input to the previous transmitted data Bus_rx<(i-1):0> corresponding to the data group to be transmitted via a fourth inverter NOT4, and the third selector MUX3 is controlled by a fourth control signal Sig3; and a fifth flip-flop DFF5, the input of which is connected to the output of the third selector MUX3, the enable terminal of which is used to input the delay signal Case1_en_dly of the second enable signal, and the output of which is used to output data Bus_rx<(i-1):0> corresponding to the data group to be transmitted.

[0116] In one embodiment, when Case1_en is valid, Bus_tx<(i-1):0> is input to the 0 input terminal of the third selector MUX3 via the fourth flip-flop DFF4, and Bus_rx<(i-1):0> is input to the 1 input terminal of the third selector MUX3 via the fourth inverter NOT4. When Sig3 = 1, the data group to be transmitted corresponding to the data processing circuit 212 is determined to be the first data group to be transmitted. The third selector MUX3 outputs the inverted data Bus_rx_pre<(i-1):0> to the fifth flip-flop DFF5. When Case1_en_dly is valid, the fifth flip-flop DFF5 outputs Bus_rx_pre<(i-1):0>, thus obtaining the second data Bus_rx<(i-1):0> corresponding to the data group to be transmitted.

[0117] When Sig3 = 0, the data group to be transmitted corresponding to the data processing circuit 212 is determined to be the second data group to be transmitted. The third selector MUX3 outputs the data Bus_tx<(i-1):0> to obtain Bus_rx_pre<(i-1):0>. When Case1_en_dly is valid, the fifth flip-flop DFF5 outputs Bus_rx_pre<(i-1):0> to obtain the first data Bus_rx<(i-1):0> corresponding to the second data group to be transmitted.

[0118] Continue to refer to Figure 9 In one embodiment, the receiver 200 further includes a sixth flip-flop DFF6, one input of which receives a first control signal flag_all, the other input of which receives a first enable signal Case0_en, and the output of which generates a fourth control signal Sig3.

[0119] When the first control signal flag_all = 1 and the first control signal Case0_en is valid, the sixth flip-flop DFF6 outputs the fourth control signal Sig3 = 1, so as to control the third selector MUX3 to output the inverted data of the previous transmission data Bus_rx<(i-1):0> according to the fourth control signal Sig3. The receiving end 200 combines the m data to obtain BUS_rx<(n-1):0>.

[0120] In this embodiment of the disclosure, the signal parsing circuit 211 and the data processing circuit 212 realize the parsing result of the identifier bit of the data group to be transmitted, and obtain the second data corresponding to the first data group to be transmitted and the first data corresponding to the second data group to be transmitted based on the parsing result. Then, the first data and the second data are combined to obtain the current transmission data, so that during the data transmission process, the first data group to be transmitted only flips the identifier bit, which greatly reduces the bus power consumption.

[0121] In one embodiment, the data transmission control circuit provided in this disclosure further includes an enable control circuit; wherein, the data grouping circuit 110 is used to determine whether the current transmission data is the same as the previous transmission data based on the data changes in the previous transmission data and the current transmission data on the n-bit parallel data bus; the enable control circuit is used to control the enable terminal to be turned off when the current transmission data and the previous transmission data on the n-bit parallel data bus are the same; the data parsing circuit 210 detects that the enable terminal is in a closed state and uses the previous transmission data as the current output data.

[0122] The enable control circuit is used to activate the enable terminal when the current transmitted data on the n-bit parallel data bus is different from the previous transmitted data. It should be noted that the implementation method of the data grouping circuit 110 in determining whether the current transmitted data is the same as the previous transmitted data is the same as the specific implementation method in the aforementioned embodiments, and will not be repeated here.

[0123] The enable control circuit can be a switching element connected in the circuit. When the current transmitted data is the same as the previous transmitted data, the switching element opens to close the enable terminal; when the current transmitted data is different from the previous transmitted data, the switching element closes to open the enable terminal.

[0124] The aforementioned enabling terminal is the enabling terminal of the transmitting terminal 100, used to control whether the transmitting terminal 100 sends data to the receiving terminal 200. When the enabling terminal is enabled, it can delay the input of latching enable signals, first enable signals, second enable signals, etc., thereby realizing the control of the transmitting terminal 100.

[0125] Figure 10 This diagram illustrates the principle of the receiver 200 parsing data according to an embodiment of this disclosure. Figure 10 As shown, for the data to be transmitted in Case0 and Case1, during time period T0, the first enable signal Case0_en is active high, and flag0 is used as a flag bit to transmit the first identifier data. The transmitting end 100 sends the data after inverting the flag bit flag0 of Case0 to the receiving end 200. The receiving end 200 inverts the previously transmitted data according to flag0 to obtain the second data data0. During time period T1, the first enable signal Case0_en is low, the second enable signal Case1_en is active high, the flag bit flag0 is invalid, and the transmitting end 100 directly sends the first data data1 corresponding to Case1 to the receiving end 200. The receiving end 200 combines the first data data1 and the second data data0 to obtain the current transmitted data data.

[0126] Figure 11 A timing diagram of the receiver 200 provided in an embodiment of this disclosure is shown. Figure 11 As shown, from the rising edge of the first enable signal Case0_en to the rising edge of the delay signal Case0_en_dly, the receiver 200 completes the flag bit Bus_rx. <0> The comparison between the new and old values ​​is performed. From the rising edge of the second enable signal Case1_en to the rising edge of the delayed signal Case1_en_dly, the receiver 200 keeps the old value unchanged to complete the comparison between the new and old values ​​of the non-flag bits. From the rising edge of Case0_en_dly to the rising edge of the delayed signal Case1_en_dly, the judgment and value retrieval of Bus_rx_pre<(n-1):0> have been completed, and the value on bus_rx is updated to obtain the current transmitted data.

[0127] Figure 12 This diagram illustrates another schematic of a transmitter 100 transmitting data according to an embodiment of this disclosure. Figure 12 As shown, when the current transmitted data D1 and the current transmitted data D2 are the same, the control disables the enable signal EN. After the receiver 200 detects that the enable signal EN is disabled, it directly uses the previous transmitted data D1 as the current transmitted data. When the current transmitted data D1 and the current transmitted data D2 are different, the enable signal EN is enabled, and group processing is performed.

[0128] It should be noted that the circuit structures of the data packet circuit 110, transmission control circuit 120, and data parsing circuit 210 described above are merely illustrative. The circuit structures of the data packet circuit 110, transmission control circuit 120, and data parsing circuit 210 in this embodiment of the present disclosure are not limited to the above-described manner. The aforementioned data packet circuit 110, transmission control circuit 120, and data parsing circuit 210 can be implemented individually or in combination with the solutions in the embodiments of the present disclosure, and the embodiments of the present disclosure do not impose any limitations on this.

[0129] Based on the same inventive concept, this disclosure also provides a data transmission method, as shown in the following embodiments. Since the principle by which this method solves the problem is similar to that of the circuit embodiments described above, the implementation of this method embodiment can refer to the implementation of the circuit embodiments described above, and repeated details will not be described again.

[0130] To facilitate a comprehensive understanding of the technical solutions provided by the embodiments of this disclosure, the data transmission method provided by the embodiments of this disclosure will be described below.

[0131] Figure 13 A flowchart illustrating a data transmission method provided in an embodiment of this disclosure is shown. Figure 13 As shown in the figure, this disclosure provides a data transmission method applied to an n-bit parallel data bus having a transmitting end and a receiving end. The method mainly includes the following steps:

[0132] S1302. When the transmitting end responds to the fact that the current transmitted data on the n-bit parallel data bus is different from the previous transmitted data, it divides the current transmitted data into m data groups to be transmitted, and determines a first data group to be transmitted and ma second data groups to be transmitted among the m data groups to be transmitted, where m, n, and a are positive integers. The data group that needs to be completely flipped relative to the previous transmitted data is determined as the first data group to be transmitted, and the data group that has not been completely flipped relative to the previous transmitted data is determined as the second data group to be transmitted.

[0133] S1304. The transmitting end flips the identifier data in a first data group to be transmitted to obtain first identifier data, and transmits the first identifier data to the receiving end; it also transmits the first data corresponding to ma second data groups to be transmitted to the receiving end.

[0134] S1306. The receiving end performs a flipping process on the previous transmitted data corresponding to the a first data groups to be transmitted according to the first identification data to obtain the second data; and obtains the current transmitted data according to the first data and the second data.

[0135] In one embodiment, the sending end delays the transmission of the second data, transmitting the first identification data first and then the second data.

[0136] In one embodiment, the identifier bit data in the first data group to be transmitted is a specific data bit in the first data group to be transmitted. For example, the identifier bit can be the first bit of the first data group to be transmitted. For instance, when the n-bit parallel data bus is divided into m data groups to be transmitted, the first data bit of each of the m data groups can be used as the identifier bit. <0> Data ...Data<(m-1)i> is used as a flag bit.

[0137] For example, the aforementioned flag bit can also be the last bit in the first data group to be transmitted. For instance, the last data bit (Data) of m data groups to be transmitted can be used. <i-1>、Data<2i-1>……Data <n>As an identifier.

[0138] It should be noted that the number of identifier bits in the first data group to be transmitted can be one or more. Preferably, the identifier bit of the first data group to be transmitted is the first data bit of each data group, but this disclosure does not make a specific limitation in this regard. The identifier bit of the data group to be transmitted is only valid when data is transmitted in the first data group to be transmitted. In the second data group to be transmitted, the identifier bit transmits the data corresponding to that data bit.

[0139] The aforementioned first identifier data is obtained by inverting the previous transmitted data corresponding to the identifier bit of the first data group to be transmitted.

[0140] It should be noted that the specific implementation of this control method embodiment is similar to the specific implementation of the aforementioned control circuit embodiment, and the similarities will not be repeated here.

[0141] In this embodiment, when the current transmitted data on the n-bit parallel data bus differs from the previous transmitted data, the transmitting end divides the current transmitted data into m groups of data to be transmitted, and determines a first data group and ma second data groups among the m groups of data to be transmitted, where m, n, and a are positive integers. The data group that needs to be completely flipped relative to the previous transmitted data is determined as the first data group of data to be transmitted, and the data group that has not been completely flipped relative to the previous transmitted data is determined as the second data group of data to be transmitted. The transmitting end flips the flag bit data in the a first data group of data to be transmitted to obtain first flag data, and transmits the first flag data to the receiving end. The transmitting end transmits the first data corresponding to the ma second data groups of data to be transmitted to the receiving end. The receiving end flips the previous transmitted data corresponding to the a first data groups of data to be transmitted according to the first flag data to obtain second data. The current transmitted data is obtained according to the first data and the second data, thereby reducing bus power consumption.

[0142] Figure 14 A flowchart illustrating another data transmission method provided in an embodiment of this disclosure is shown. Figure 14 As shown, in one embodiment, the method further includes:

[0143] S1402. The sending end responds to the requirement that the current transmitted data needs to be completely flipped relative to the previous transmitted data and generates the second identifier data of the identifier bits of the current transmitted data.

[0144] S1404. The receiving end receives the second identification data and flips the previous transmitted data according to the second identification data to obtain the current transmitted data.

[0145] In one embodiment, the identifier bit in the currently transmitted data is a specific data bit in the currently transmitted data.

[0146] It should be noted that the identifier bit in the currently transmitted data may be the same as or different from the identifier bit of the first data group to be transmitted; this disclosure does not limit this.

[0147] The number of bits in the identifier bits in the currently transmitted data can be determined according to actual needs, such as one or more bits.

[0148] For example, the first data bit of the first data group to be transmitted can be... <0> This is used as an identifier for the currently transmitted data to simplify the control logic.

[0149] When the current transmitted data needs to be completely flipped relative to the previous transmitted data, the second identifier data is obtained by inverting the identifier bits of the current transmitted data corresponding to the previous transmitted data. In this case, the number of bits of data transmitted on the n-bit parallel data bus is the same as the number of bits in the second identifier data, thus greatly reducing bus power consumption.

[0150] Figure 15 A flowchart illustrating yet another data transmission method provided in an embodiment of this disclosure is shown. Figure 15 As shown, in one embodiment, the method further includes:

[0151] S1502, The transmitting end responds to the fact that the current transmitted data on the n-bit parallel data bus is the same as the previous transmitted data, and controls the shutdown enable terminal;

[0152] S1504. The receiving end detects that the enable terminal is in the off state and uses the data transmitted last time as the current output data.

[0153] In one embodiment, the method further includes: in response to the fact that the current transmitted data on the n-bit parallel data bus is different from the previous transmitted data, the transmitting end controls the opening of the enable terminal and performs the step of dividing the current transmitted data into multiple groups of data to be transmitted.

[0154] This disclosure also provides a memory that includes the data transmission control circuit described in the above embodiments. The memory can include, but is not limited to, non-volatile memory, volatile memory, and novel non-volatile memory. Non-volatile memory mainly includes PROM (Programmable Read-Only Memory: EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory)), MROM / Mask ROM (Mask Mode Read-Only Memory), and Flash Memory (NAND Flash, NOR Flash), which retains stored data even after power loss. Volatile memory mainly includes DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), which does not retain data after power loss. Novel memory mainly includes FeRAM (Ferroelectric RAM), PCRAM (Phase Change RAM), ReRAM (Resistive Random Access Memory), and MRAM (Magnetic Random Access Memory), etc. Thus, combined with the above data transmission control circuit, data transmission power consumption is greatly reduced, improving the effectiveness and reliability of the memory.

[0155] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the claims. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0156] The above are merely preferred embodiments of the application examples and are not intended to limit the application examples. For those skilled in the art, the application examples can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the application examples should be included within the protection scope of the application examples.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A data transmission control circuit, characterized in that, This invention is applied to an n-bit parallel data bus having a transmitting end and a receiving end. The transmitting end includes a data packetization circuit and a transmission control circuit, which are connected together. The receiving end is equipped with a data parsing circuit. The data grouping circuit is used to divide the current transmitted data into m data groups to be transmitted in response to the current transmitted data being different from the previous transmitted data on the n-bit parallel data bus, and to determine a first data groups to be transmitted and ma second data groups to be transmitted among the m data groups to be transmitted, where m, n, and a are positive integers. Data groups that need to be completely flipped relative to the previous transmitted data are determined as the first data groups to be transmitted, and data groups that have not been completely flipped relative to the previous transmitted data are determined as the second data groups to be transmitted. The transmission control circuit is used to flip the identifier data in the a first data groups to be transmitted to obtain first identifier data, and transmit the first identifier data to the receiving end; transmit the first data corresponding to the ma second data groups to be transmitted to the receiving end; wherein, the data of the first data groups to be transmitted to the receiving end is the first identifier data. The data parsing circuit is used to perform a reversal process on the previous transmitted data corresponding to the a first data groups to be transmitted according to the first identification data to obtain the second data; and to obtain the current transmitted data according to the first data and the second data.

2. The circuit according to claim 1, characterized in that, The data packet circuit includes a first flip-flop and m first comparators, where each first comparator corresponds to one data packet to be transmitted. The input terminal of the first trigger is used to input the current transmitted data, the enable terminal of the first trigger is used to input a latch enable signal, and the output terminal of the first trigger is used to output the previous transmitted data when the latch enable signal is valid. One input of each of the first comparators is connected to the output of the first flip-flop, and is used to input the previous transmitted data corresponding to the data group to be transmitted. The other input of each of the first comparators is used to input the current transmitted data corresponding to the data group to be transmitted. The output of each of the first comparators is used to output the group identification signal of the data group to be transmitted. When the group identification signal is in a first state, the data group to be transmitted is determined as the first data group to be transmitted. When the group identification signal is in a second state, the data group to be transmitted is determined as the second data group to be transmitted.

3. The circuit according to claim 2, characterized in that, The data packet circuit also includes an AND gate group and a first tri-state gate; The input terminals of the AND gate group are respectively connected to the output terminals of m first comparators. The output terminal of the AND gate group is used to output a first control signal. The first control signal is used to characterize whether the current transmitted data has been completely flipped relative to the previous transmitted data. The input terminal of the first tri-state gate is connected to the output terminal of the AND gate group. The first tri-state gate is controlled by a first enable signal. The output terminal of the first tri-state gate is used to output the first control signal when the first enable signal is in the first state.

4. The circuit according to claim 2, characterized in that, The circuit includes m transmission control circuits, one transmission control circuit corresponding to one data group to be transmitted; each transmission control circuit includes a first signal generation circuit, a first data transmission control circuit, a second signal generation circuit, and a second data transmission control circuit. The first signal generation circuit is used to generate a second control signal based on the first enable signal, the second enable signal, the first control signal, and the group identifier signal; The first data transmission control circuit is used to process the identifier bit data in the data group to be transmitted according to the second control signal and transmit it to the receiving end; The second signal generation circuit is used to generate a third control signal based on the group identification signal and the second enable signal; The second data transmission control circuit is used to determine whether to transmit the non-identifier bit data in the data group to be transmitted to the receiving end according to the third control signal, wherein the non-identifier bit data is the data bit corresponding to each data line other than the identifier bit in the data group to be transmitted.

5. The circuit according to claim 4, characterized in that, The first signal generation circuit includes: A first selector, one input terminal of which is used to input the second enable signal, and the other input terminal of which is used to input the first enable signal, and the first selector is controlled by the group identification signal; A first NOR gate, one input of which is connected to the output of the first selector via a first inverter, the other input of which is used to input the first control signal, and the output of which is connected to the first data transmission control circuit to provide the second control signal to the first data transmission control circuit.

6. The circuit according to claim 5, characterized in that, The first data transmission control circuit includes: The second selector is controlled by the group identification signal. One input of the second selector is used to input the identification bit data in the data group to be transmitted. The other input of the second selector is connected to the output of the second inverter. The input of the second inverter is used to input the identification bit data in the data group to be transmitted. The second tri-state gate has its input connected to the output of the second selector. The second tri-state gate is controlled by the second control signal, and its output is used to output the identifier bit data in the data group to be transmitted.

7. The circuit according to claim 4, characterized in that, The second signal generation circuit includes: The third inverter, the input of which is used to input the group identification signal; A first AND gate, one input of which is connected to the output of the third inverter, and the other input of which is used to input the second enable signal. The output of the first AND gate is connected to the second data transmission control circuit to provide the third control signal to the second data transmission control circuit. The second data transmission control circuit includes: The third tri-state gate has its input terminal used to input the non-identifier bit data in the data group to be transmitted. The third tri-state gate is controlled by the third control signal to determine whether to send the non-identifier bit data in the data group to be transmitted.

8. The circuit according to claim 1, characterized in that, The receiving end includes m data parsing circuits. Each data parsing circuit is used to parse the data of a corresponding group of data to be transmitted. Each group of data parsing circuits includes a signal parsing circuit and a data processing circuit. The signal parsing circuit is used to receive the identifier bit data in the data group to be transmitted, and generate a fourth control signal based on the first enable signal, the identifier bit data in the data group to be transmitted, and the identifier bit data of the previous transmitted data. The data processing circuit is controlled by the fourth control signal. The data processing circuit obtains the data corresponding to the data group to be transmitted based on the received data corresponding to the data group to be transmitted and the previous transmitted data corresponding to the data group to be transmitted.

9. The circuit according to claim 8, characterized in that, The signal analysis circuit includes: The second flip-flop has an input terminal for receiving the identifier bit data in the data group to be transmitted, and an enable terminal for inputting the first enable signal. The second comparator has one input connected to the output of the second flip-flop, and the other input is used to input the identifier bit data of the previous transmitted data. The third flip-flop has its input terminal connected to the output terminal of the second comparator, its enable terminal used to input a delayed signal of the first enable signal, and its output terminal connected to the data processing circuit to provide a fourth control signal to the data processing circuit.

10. The circuit according to claim 8, characterized in that, The data processing circuit includes: The fourth trigger, wherein the input terminal of the fourth trigger is used to receive the data corresponding to the data group to be transmitted, and the enable terminal of the fourth trigger is used to receive the second enable signal; The third selector has one input terminal connected to the output terminal of the fourth flip-flop, and the other input terminal of the third selector is connected to the previous transmission data corresponding to the data group to be transmitted via the fourth inverter. The third selector is controlled by the fourth control signal. The fifth flip-flop has its input connected to the output of the third selector. The enable terminal of the fifth flip-flop is used to input a delayed signal of the second enable signal, and the output terminal of the fifth flip-flop is used to output data corresponding to the data group to be transmitted.

11. The circuit according to claim 10, characterized in that, The receiving end further includes a sixth flip-flop, one input of which receives a first control signal, and the other input of which receives a first enable signal. The output of the sixth flip-flop generates a fourth control signal, which is used to instruct the receiving end to perform a flip-flop process on the previously transmitted data to obtain the current transmitted data.

12. The circuit according to any one of claims 1-11, characterized in that, The circuit also includes an enable control circuit. The data grouping circuit is used to determine whether the current transmitted data is the same as the previous transmitted data based on the data changes in the previous transmitted data and the current transmitted data on the n-bit parallel data bus. The enable control circuit is used to control the enable terminal to be turned off when the current transmitted data on the n-bit parallel data bus is the same as the previous transmitted data; the data parsing circuit detects that the enable terminal is in the off state and uses the previous transmitted data as the current output data. The enable control circuit is used to control the enable terminal to be turned on when the current transmitted data on the n-bit parallel data bus is different from the previous transmitted data.

13. A data transmission method, characterized in that, Applied to an n-bit parallel data bus with a transmitting end and a receiving end, including: When the transmitting end responds to the current transmission data on the n-bit parallel data bus being different from the previous transmission data, it divides the current transmission data into m groups of data to be transmitted, and determines a first data group and ma second data groups among the m groups of data to be transmitted, where m, n, and a are positive integers. The data group that needs to be completely flipped relative to the previous transmission data is determined as the first data group of data to be transmitted, and the data group that has not been completely flipped relative to the previous transmission data is determined as the second data group of data to be transmitted. The transmitting end flips the identifier data in the a first data groups to be transmitted to obtain first identifier data, and transmits the first identifier data to the receiving end; it also transmits the first data corresponding to the ma second data groups to be transmitted to the receiving end, wherein the data of the first data groups to be transmitted to the receiving end is the first identifier data. The receiving end performs a flipping process on the previous transmitted data corresponding to the a first data groups to be transmitted according to the first identification data to obtain the second data; and obtains the current transmitted data according to the first data and the second data.

14. The method according to claim 13, characterized in that, The sending end delays the transmission of the second data, transmitting the first identification data first and then the second data.

15. The method according to claim 13, characterized in that, The identifier bit data in the first data group to be transmitted is a specific data bit in the first data group to be transmitted.

16. The method according to claim 13, characterized in that, The method further includes: In response to the requirement that the current transmitted data needs to be completely flipped relative to the previous transmitted data, the transmitting end generates second identifier data for the identifier bits of the current transmitted data. The receiving end receives the second identification data, and performs a complete flip on the previous transmitted data based on the second identification data to obtain the current transmitted data.

17. The method according to claim 16, characterized in that, The identifier bit in the currently transmitted data is a specific data bit in the currently transmitted data.

18. The method according to claim 13, characterized in that, The method further includes: The transmitting end responds to the fact that the current transmitted data and the previous transmitted data on the n-bit parallel data bus are the same, and controls the enable terminal to be turned off. The receiving end detects that the enable terminal is in a closed state and uses the previously transmitted data as the current output data.

19. The method according to claim 18, characterized in that, The method further includes: In response to the fact that the current transmitted data on the n-bit parallel data bus is different from the previous transmitted data, the transmitting end controls the enable terminal to open and executes the step of dividing the current transmitted data into multiple groups of data to be transmitted.

20. A memory, characterized in that, Includes a data transmission control circuit as described in any one of claims 1-12, for storing and transmitting data on an n-bit parallel data bus.

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